A high electron mobility transistor with high withstand voltage capability

Abstract

The present application relates to a semiconductor power device, and more specifically, to a high-voltage high electron mobility transistor (HEMT). The high-voltage high electron mobility transistor comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, and a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate, which is insufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode is in electrical contact with the P-type nitride semiconductor layer, and both the source electrode and the drain electrode are in electrical contact with the two-dimensional electron gas.

Description

Technical Field

[0001] The present application relates to a semiconductor power device, and in particular to a high withstand voltage high electron mobility transistor (HEMT). Background Art

[0002] Group III nitride semiconductors are an important new type of semiconductor material, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Due to the advantages of direct band gap, wide bandgap, high breakdown electric field strength, etc., Group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics, and radio frequency devices.

[0003] An important device type of III-nitride semiconductors is the high electron mobility transistor (HEMT), which has great prospects in the field of power semiconductors. Due to the existence of spontaneous polarization and piezoelectric polarization effects, there is a strong polarized positive charge at the interface between GaN and AlGaN on the (0001) plane. The presence of these polarized positive charges will attract and lead to the generation of two-dimensional electron gas at the interface. These two-dimensional electron gases have a high carrier concentration and a high carrier mobility, and are the core components for making high electron mobility transistors (HEMTs).

[0004] Attached Figure 1 It is a common HEMT structure. The two-dimensional electron gas conducts current between the source and the drain. The gate electrode controls the switching of the device. It should be noted that in this structure, the source, drain, and gate electrodes are all located on the same side of the device. When the device is in the off state, the source and gate are both in a low voltage state (usually within ±20V), but the drain electrode may be at a voltage of tens to hundreds of volts or even thousands of volts. Such a high voltage applied to the device results in a very high electric field inside the device. On the other hand, the electric field distribution inside these devices is uneven, and the local electric field strength can far exceed the average electric field strength. These local high electric field strengths can approach or even exceed the breakdown electric field strength of the material used in the device, resulting in device breakdown, leakage or reliability problems. Therefore, preventing the occurrence of high-intensity local electric fields, or reducing the strength of the local electric field, is very critical to improving the overall performance and reliability of the device.

[0005] The electric field strength at the edge of the gate electrode (as shown in the figure) is often very high. Such a high electric field strength is near the gate stack, which is the weakest and core part of the device. It is easy to cause gate leakage, gate breakdown and low reliability problems at high electric fields, which require special attention. A common way to reduce the local electric field is to use a field plate structure. These field plate structures change the distribution of the electric field and can reduce the local excessive electric field. However, the field plate structure usually uses metal materials, and there is still the problem of tip discharge, and there are still local electric field spikes.

[0006] In addition, usually when the Al Ga N / Ga N heterojunction is prepared, a high-density two-dimensional electron gas conductive channel has been formed, which makes conventional Al Ga N / Ga N HEMT devices depletion-type (threshold voltage Vth<0), and a negative bias voltage needs to be applied to the gate to be in the off state. It is a normally on device. However, in the field of power switching devices, normally off devices are very much needed. GaN enhancement device technology has attracted great attention from researchers. After years of development, the methods for realizing enhancement devices mainly include thin barrier layers, grooved gates, and fluorine ion implantation under the gate. While improving the voltage resistance of the device, the present invention application can also partially or completely deplete the two-dimensional electron gas at the gate stack and realize an enhancement device through P-GaN layer doping modulation technology. Summary of the invention

[0007] The basic principle of the present invention is to introduce a P-type nitride semiconductor layer and adjust the electric field distribution through doping modulation technology to improve the device withstand voltage capability of the HEMT and realize an enhanced device.

[0008] The P-type nitride semiconductor layer is located below the two-dimensional electron gas and away from the gate, drain and other electrodes. If the barrier layer of the two-dimensional electron gas is vertical to the substrate, the P-type nitride semiconductor layer can also be located on the side of the barrier layer.

[0009] When the device is in the off state, the two-dimensional electron gas is depleted, leaving positive charges at the base of the channel. The holes in the P-type nitride semiconductor layer move under the action of the positive electric field of the drain, leaving negative charges on the base in some areas. These negative charges effectively offset the influence of the positive charges in the channel, reduce the intensity of the local high electric field, improve the electric field distribution, and improve the device performance and reliability.

[0010] On the one hand, the present application provides a HEMT with high withstand voltage capability, characterized in that it includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, a nucleation layer (devices with some substrate materials may not include it), and a substrate device structure; wherein the spatial distribution of the doping concentration of the P-nitride semiconductor layer is adjusted by epitaxially growing the P-type nitride semiconductor layer, the P-type nitride semiconductor layer is not sufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the drain electrode is in electrical contact with the two-dimensional electron gas. The P-type nitride semiconductor layer is at least partially located in the region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and under zero bias, except for the gate stack region, the channel two-dimensional electron gas concentration depleted by the P-type nitride semiconductor layer is less than 80% of the channel two-dimensional electron gas concentration when the P-type doping in the P-type nitride semiconductor layer is not included, that is, at least 20% of the two-dimensional electron gas is retained.

[0011] Furthermore, a low-doped or unintentionally doped nitride semiconductor layer may be inserted between the barrier layer and the P-type nitride semiconductor layer of the HEMT in the present application to reduce effects such as decreased electron mobility at the two-dimensional electron gas channel due to scattering of doped atoms.

[0012] Furthermore, the connection mode of the electrodes in the HEMT in the present application can be: the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas, and the independent body electrode is in electrical contact with the P-type nitride semiconductor layer. This is conducive to the independent control of the source potential and the working potential of the P-type nitride semiconductor layer, especially when the source potential is fixed at the 0 potential point, it can be independently controlled according to the working voltage or stable working voltage required to turn off the channel. This is also the first independent control mode proposed in the present application, which is conducive to the stable and efficient operation of the enhancement mode device.

[0013] Furthermore, in the present application, the portion where the body electrode of the HEMT contacts the P-type nitride semiconductor layer is a high doping concentration region, which is conducive to forming an ohmic contact.

[0014] Furthermore, in the present application, an insulating layer is provided on the substrate of the HEMT, a nucleation layer is formed at the opening of the insulating layer, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy; or a nucleation layer is grown on the substrate, an insulating layer is formed on the nucleation layer, the opening of the insulating layer exposes the nucleation layer, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy.

[0015] Under certain substrates (such as Al2O3 substrates) and process conditions, the nucleation layer can be selectively grown on the exposed substrate instead of on the insulating layer. However, when using a silicon substrate, AlN is usually required as the nucleation layer, and the selectivity of AlN is relatively poor. In this case, the AlN on the insulating layer can be etched / removed after the nucleation layer is grown. On the other hand, since the AlN grown on the insulating layer is a polycrystalline or amorphous structure, under appropriate growth conditions, the subsequent nitride semiconductor layer such as GaN cannot grow on such a polycrystalline AlN but only grows on the single crystal AlN nucleation layer at the substrate opening. In this case, there is no need to remove the AlN on the insulating layer and continue to selectively / laterally epitaxially grow the subsequent nitride semiconductor layer structure. Under certain growth conditions, such as in the presence of chlorine-based gases, the deposition of AlN on the insulating layer can be very little or no, and the nucleation growth mechanism of the subsequent nitride epitaxial layer cannot be formed on the insulating layer. That is, except for the growth in the nucleation zone, there is no obvious subsequent nitride growth in other areas. At this time, the step of removing the AlN on the insulating layer can be omitted and the subsequent growth can be directly performed. Alternatively, the nucleation layer can be produced first and then the insulating layer can be covered and part of the nucleation layer can be exposed.

[0016] Furthermore, in the present application, when the HEMT grows a P-type nitride semiconductor layer, the doping concentration of the P-type nitride semiconductor layer can be controllably changed during the selective / lateral epitaxial growth, and the P-type nitride semiconductor layer is lightly doped or undoped when the portion close to the preset drain electrode is selectively / laterally epitaxially grown. After the selective / lateral epitaxial growth, a portion of the upper surface nitride semiconductor layer is removed by a planarization or etching process, and then a barrier layer structure or a channel layer and a barrier layer structure are epitaxially formed.

[0017] Furthermore, in the present application, after growing the P-type nitride semiconductor layer, the HEMT grows a low-doped or undoped semiconductor layer to achieve an undoped channel layer on the upper surface of the P-type nitride semiconductor layer, so as to avoid adverse effects on the energy band of the channel layer and device operation.

[0018] Furthermore, in the present application, before growing the P-type nitride semiconductor layer, the HEMT forms a buffer layer above the nucleation layer, and the buffer layer can be a layer composed of a highly doped P-type nitride semiconductor material; after growing the P-type nitride semiconductor layer, a highly doped P-type nitride semiconductor layer region is formed above the nucleation layer to facilitate the formation of ohmic contact with the connected electrode.

[0019] Furthermore, the HEMT in the present application can adjust the doping concentration, so that when forming the P-type nitride semiconductor layer, the first region of the P-type nitride semiconductor layer, the first region of the strong P-type nitride semiconductor layer, and the second region of the P-type nitride semiconductor layer are formed in sequence, wherein the first region of the strong P-type nitride semiconductor layer is located below the gate electrode and can deplete the two-dimensional electron gas in the channel layer below the gate electrode by more than 95% under 0 bias.

[0020] Furthermore, the HEMT in the present application can adjust the doping concentration, so that when forming the P-type nitride semiconductor layer, the first region of the P-type nitride semiconductor layer, the first region of the strong P-type nitride semiconductor layer, and the second region of the P-type nitride semiconductor layer are formed in sequence, wherein the first region of the strong P-type nitride semiconductor layer is located between the source electrode and the gate electrode, and can deplete the two-dimensional electron gas in the channel layer below the gate electrode by more than 80% at 0 bias.

[0021] Furthermore, the HEMT in the present application can adjust the doping concentration to form a strong P-type nitride semiconductor layer first region first region, a P-type nitride semiconductor layer first region, a strong P-type nitride semiconductor layer first region second region, and a P-type nitride semiconductor layer second region in sequence when forming a P-type nitride semiconductor layer, wherein the strong P-type nitride semiconductor layer first region first region is located below the source electrode, the P-type nitride semiconductor layer first region is located below the source electrode, and the strong P-type nitride semiconductor layer first region second region is located below the gate and can deplete more than 95% of the two-dimensional electron gas in at least a portion of the channel layer below the gate electrode at zero bias.

[0022] Furthermore, in the present application, a precursor mixed atmosphere containing hydrogen and / or chlorine is used when the HEMT selectively / laterally epitaxially grows a P-type nitride semiconductor layer, and the amount of P-type dopant is controlled at different stages of epitaxial growth to control the concentration distribution of the growing P-type nitride semiconductor layer, so as to facilitate the adjustment of the electric field distribution.

[0023] Furthermore, in the present application, after forming the barrier layer, a gate insulating layer may be added under the gate electrode of the HEMT to reduce the off-state leakage current of the gate.

[0024] Furthermore, in the present application, after forming the barrier layer, the HEMT in-situ grows a SiNx passivation layer, that is, after the barrier layer is deposited, the epitaxial wafer is not taken out and the in-situ SiNx passivation layer is directly deposited in the same device. The SiNx passivation layer can effectively protect the surface of the barrier layer and has a very high quality, so that the barrier layer / SiNx interface obtained has fewer defect states. In addition to passivating the surface of the barrier layer, the in-situ SiNx layer can also be used as a gate dielectric layer at the gate stack, so that the in-situ grown SiNx layer has the dual functions of a dielectric layer under the gate and a surface passivation layer.

[0025] The P-type nitride semiconductor layer of the present application is formed by selective area / lateral epitaxy. The P-type doping concentration can be adjusted according to the proportion of the doped carrier gas atmosphere during the growth process. By adjusting the electric field distribution through P-type doping, high-quality P-type doping and spatial regulation of the two-dimensional electron gas can be obtained. The non-uniform distribution of P-type impurities (usually requiring a doping concentration of 2x10 18 cm -3 Above, the effective concentration after annealing activation is 2x10 17 cm -3 Only by doing so can the channel be turned off more effectively. A large number of unactivated doped atoms become electron scattering centers, reducing the channel current and affecting transconductance) and the significant carrier scattering effect it brings, as well as the carrier scattering and certain leakage channels caused by the irreversibility of some high-temperature annealing damage caused by ion implantation. Therefore, it is very beneficial to achieve high-quality P-type doping and hole distribution control. On the basis of our other patent applications, the present invention combines lateral / selective epitaxy technology with P-type doping electric field distribution technology, so that we can obtain high-quality P-type doping and its spatial regulation, improve the withstand voltage capability of HEMT, and realize enhanced devices through doping modulation. It avoids the problem that the source and drain electrodes of conventional HEMTs are only in electrical contact with the two-dimensional electron gas, cannot control and modulate the potential of the P-type nitride semiconductor layer, and cannot control the operation of the electron gas in each doping area differently, resulting in weak device performance and withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments of the present application are briefly introduced below. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without paying creative work.

[0027] Figure 1 A typical HEMT device structure provided as background technology;

[0028] Figure 2-Figure 5 The device structure of the HEMT provided in the embodiment of the present application;

[0029] Figure 6-Figure 10 An example diagram of the device structure formation process of the HEMT provided in the embodiment of the present application;

[0030] Figure 11-Figure 14 The device structure of the HEMT provided in the embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0032] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. "Up and down" etc. indicate a relative position relationship and do not mean that the two are directly adjacent.

[0033] In the high electron mobility transistor of the present application, the doping concentration of strong doping generally refers to a doping concentration of 2E18 / cm3 or more, and may even be as high as 5E19 / cm3 or higher. The doping concentration of light doping is generally below 2E18 / cm3, generally in the order of 2E17 / cm3. In HEMT, strong doping or light doping is relative and is related to the concentration of the two-dimensional electron gas at the interface of the channel layer / barrier layer.

[0034] Please see Figure 2 , Figure 2A high withstand voltage HEMT is provided in the embodiment of the present application. Its structure is to form a nucleation layer 202 on a substrate 201 (a nucleation layer may not be included in devices of some specific substrate materials), epitaxially form a P-type nitride semiconductor layer 203 on the nucleation layer 202, form a barrier layer 204 on the P-type nitride semiconductor layer 203, the P-type nitride semiconductor layer 203 and the barrier layer 204 are in contact with each other and form a heterojunction structure, form a two-dimensional electron gas at the interface, a source electrode 205 is electrically connected to the two-dimensional electron gas and the P-type nitride semiconductor layer 203, usually the source electrode 205 has a fixed potential, the drain electrode 206 is in contact with the two-dimensional electron gas, and the gate electrode 207 is located above the barrier layer. The P-type nitride semiconductor layer 203 is weakly P-type, and its hole concentration or P-type impurity concentration is low, and the two-dimensional electron gas located at the interface of the barrier layer 204 and the P-type nitride semiconductor layer 203 will not be seriously depleted, that is, there is a high concentration of two-dimensional electron gas at the interface of the P-type nitride semiconductor layer 203 and the barrier layer; when turned on, the HEMT is realized by controlling the different voltages of the gate and the drain. By selecting a suitable gate electrode material, it is also possible to deplete part or all of the two-dimensional electron gas at the gate stack to realize a normally-off device, and at the same time, maintain a high two-dimensional electron gas concentration in other regions to achieve good conduction characteristics. The P-type nitride semiconductor layer is at least partially located in the region between the source electrode and the gate electrode and the gate electrode and the drain electrode. Except for the gate stack region, the channel two-dimensional electron gas concentration depleted by the P-type nitride semiconductor layer is less than 80% of the channel two-dimensional electron gas concentration when the P-type nitride semiconductor layer is not present, that is, at least 20% of the two-dimensional electron gas is retained.

[0035] The basic requirement of the source electrode is to form an ohmic contact with the two-dimensional electron gas and the P-type nitride semiconductor layer 203. At this time, the source electrode portion in contact with the two-dimensional electron gas and the source electrode portion in contact with the P-type nitride semiconductor layer 203 can be the same material or different materials. The drain electrode usually has a higher voltage. If the drain electrode is in contact with the P-type nitride semiconductor layer, it will cause a large leakage during operation, resulting in unstable operation or even failure of the device. Therefore, in the device structure of the present application, the drain electrode is prevented from being electrically connected to the P-type nitride semiconductor layer, and the drain electrode is only inserted into the barrier layer to be electrically connected to the two-dimensional electron gas.

[0036] The gate electrode 207 is a Schottky contact to reduce off-state leakage current.

[0037] Figure 3Another high withstand voltage HEMT provided in the embodiment of the present application is structured as follows: a nucleation layer 302 is formed on a substrate 301, a P-type nitride semiconductor layer 303 is epitaxially formed on the nucleation layer 302, a low-doped or unintentionally doped nitride semiconductor layer 304 is formed on the P-type nitride semiconductor layer 303, a barrier layer 305 is formed on the low-doped or unintentionally doped nitride semiconductor layer 304, the low-doped or unintentionally doped nitride semiconductor layer 304 and the barrier layer 305 form a heterojunction structure, a two-dimensional electron gas is formed at the interface, a source electrode 306 is electrically connected to the two-dimensional electron gas and the P-type nitride semiconductor layer 303, usually the source electrode 306 has a fixed potential, the drain electrode 307 is in contact with the two-dimensional electron gas, and the gate electrode 308 is located above the barrier layer.

[0038] Since the doping in the P-type nitride semiconductor layer 303 will bring about a significant carrier scattering effect, when an unintentionally doped or low-doped channel layer 304 is formed between the barrier layer 305 and the P-type nitride semiconductor layer 304, the scattering experienced by the two-dimensional electron gas when flowing in the channel layer 304 can be greatly reduced.

[0039] The source electrode is connected to the P-type nitride semiconductor layer. Usually, the source electrode potential is fixed. The drain electrode is in contact with the two-dimensional electron gas above the channel layer and the channel layer. The gate electrode is located above the barrier layer. The P-type nitride semiconductor layer will not significantly deplete the two-dimensional electron gas in the channel except for the gate stack. When conducting, HEMT is achieved by controlling the different voltages of the gate and drain. By selecting a suitable gate electrode material, it is also possible to deplete part or all of the two-dimensional electron gas at the gate stack to realize a normally-off device, while maintaining a high two-dimensional electron gas concentration in other areas to achieve good conduction characteristics.

[0040] Figure 4 Another high withstand voltage HEMT provided in the embodiment of the present application is structured as follows: a nucleation layer 402 is formed on a substrate 401, a P-type nitride semiconductor layer 403 is epitaxially formed on the nucleation layer 402, a low-doped or unintentionally doped nitride semiconductor layer 404 is formed on the P-type nitride semiconductor layer 403 as a channel layer, a barrier layer 405 is formed on the low-doped or unintentionally doped nitride semiconductor layer 404, the low-doped or unintentionally doped nitride semiconductor layer 404 and the barrier layer 405 form a heterojunction structure, a two-dimensional electron gas is formed at the interface, a source electrode 407 and a drain electrode 408 are electrically connected to the two-dimensional electron gas above the channel layer 404, and a gate electrode 409 is located above the barrier layer and contacts the P-type nitride semiconductor layer through a body electrode 406. The body electrode controls the potential of the P-type nitride semiconductor layer, controls the source electrode, the drain electrode, and the gate electrode to achieve stable operation of the HEMT, and controls the potential of the independent body electrode 406 to achieve a fast shutdown operation of the HEMT.

[0041] Figure 5 Another high withstand voltage HEMT provided in the embodiment of the present application. Figure 3 The only difference is that the area in the corresponding P-type nitride semiconductor layer 503 connected to the source electrode 506 is strongly P-type doped to form a strongly P-type doped area 509, the gate electrode 508 is located on the barrier layer 505, the drain electrode 507 is electrically connected to the two-dimensional electron gas at the interface between the channel layer 504 and the barrier layer 505, and the source electrode forms a good ohmic contact with the strong P-type area formed by ion implantation or epitaxial growth in the P-type nitride semiconductor layer, thereby controlling the potential of the P-type nitride semiconductor layer. When turned on, the HEMT is realized by controlling the different voltage potentials of the gate and the drain, as well as the voltage potential of the P-type nitride semiconductor layer.

[0042] The strong P-type doping region 509 is formed in two ways:

[0043] After forming a nucleation layer 502 on the substrate 501 and growing a P-type nitride semiconductor layer 503, a strong P-type doped region 509 can be formed by ion implanting P-type impurities in a local area, which is conducive to forming an ohmic contact control with the P-type nitride semiconductor layer; or a doping modulation technique can be used to first form a strong P-type doped region 509 on the nucleation layer by selective area / lateral epitaxy, and then form a complete P-type nitride semiconductor layer 503, so as to improve the subsequent P-type ohmic contact quality and reduce the contact resistance. The P-type nitride semiconductor layer is lightly doped or undoped when the portion close to the preset drain electrode is grown by selective area / lateral epitaxy. After the P-type nitride semiconductor is grown, a layer of low-doped or undoped semiconductor layer is grown to achieve an undoped channel layer on the upper surface of the P-type nitride semiconductor layer. Alternatively, after selectively / laterally epitaxially growing a P-type nitride semiconductor, a portion of the upper surface nitride semiconductor layer may be removed by a planarization or etching process, and then a barrier layer structure or a channel layer and barrier layer structure may be epitaxially formed to prevent an inappropriate doping concentration from causing a change in a portion of the energy band structure at the channel, thereby affecting the two-dimensional electron gas concentration and the normal operation of the HEMT.

[0044] P-type impurities are ion-implanted into local areas of the P-type nitride semiconductor layer to form a strong P-type doping area. Such P-type doping impurities are not uniformly distributed in most cases. However, under certain distribution conditions, it can achieve better reduction of electric field peaks or be more conducive to achieving ohmic contact and other functions. Typical P-type doping impurities include P-type doping atoms such as magnesium and zinc.

[0045] The modulation of hole carrier concentration can also be achieved by reducing the activation degree of local P-type doping through local ion implantation of passivation impurities, thereby reducing the hole carrier concentration in some areas. This can also adjust the distribution of hole carriers and achieve the purpose of fine-tuning the electric field distribution. Typical passivation impurities include C, N, Ar, etc.

[0046] Figure 2-Figure 5 In addition to the basic structure of the represented embodiment, there may be other related settings, for example, a passivation layer, a cap layer, and various field plate structures, an additional electrode structure for controlling the uniformity of the channel electric field, etc. are provided above the barrier layer; there may be a gate dielectric layer, a P-GaN layer and other structural layers under the gate electrode; the settings of these related functional structures and the settings of the disclosed functional structures of other HEMTs are not excluded from the implementation methods of the present invention application.

[0047] Figure 2-Figure 5 The nucleation layer and epitaxial growth can be Figure 6-8 or other feasible ways.

[0048] like Figure 6 As shown, an insulating layer 602 is formed on a substrate 601, an opening area is formed through masking, etching and other processes, a nucleation layer 603 is epitaxially grown in the opening area, and a P-type nitride semiconductor layer 604 is grown on the nucleation layer by selective / lateral epitaxy as a channel layer.

[0049] like Figure 7 As shown, a nucleation layer 702 is epitaxially grown on a substrate 701, and then an insulating layer 703 is formed. The insulating layer is subjected to masking, etching and other processes to form an opening area 704 to expose the nucleation layer 702, and then a P-type nitride semiconductor layer is epitaxially grown on the nucleation layer in the opening area by selective area / lateral epitaxy.

[0050] like Figure 8 As shown, an insulating layer 802 is formed on a substrate 801, and an opening area is formed through masking, etching and other processes. A nucleation layer 803 is epitaxially grown in the opening area, and a buffer layer 804 is first formed on the nucleation layer 803 to improve the crystal quality. The buffer layer 804 can be a strongly P-type doped nitride semiconductor layer region, such as a strongly P-type doped strong P-GaN layer. The strong P-GaN layer can also be used as a strongly P-type doped region that forms a good ohmic contact with the electrode.

[0051] For silicon substrates, the nucleation layer is usually an AlN layer, which is beneficial to reduce the lattice mismatch between the substrate material and the III-group nitride semiconductor material layer and avoid the melt-back effect of the Ga source. When the P-type nitride semiconductor layer is selectively / laterally epitaxially grown on the nucleation layer or buffer layer, the gas mixture containing the precursor contains a hydrogen component, which is more conducive to the lateral growth of a P-type nitride semiconductor layer with good performance through selective epitaxial growth (SEG); at the same time, it is not desirable to nucleate on the insulating layer during selective / lateral epitaxial growth to avoid affecting the growth quality of the P-type nitride semiconductor layer. It is necessary to control the formation of nucleation cores on the insulating layer and the growth of low-quality nitride semiconductors during the growth process. In particular, a chlorine gas mixture can be used, and the etching effect of the Cl-containing atmosphere can be used to maintain a certain etching rate of the weak growth core on the insulating layer during the process, thereby controlling it to an extremely low level, while the Cl-containing atmosphere does not affect the etching rate of the high-speed growing nucleation upper layer selectively / laterally epitaxially grown P-type nitride semiconductor layer, that is, the selective etching effect of the Cl atmosphere is conducive to controlling the quality of the selectively / laterally epitaxially grown P-type nitride semiconductor layer. In the present application, a precursor mixed atmosphere containing hydrogen and / or chlorine is particularly used when selectively / laterally epitaxially growing the P-type nitride semiconductor layer.

[0052] In addition, different doping doses can be selectively used on the entire surface of the P-type nitride semiconductor layer according to the function to form different doping distributions of weak P-type, strong P-type or other adjustable P-type nitride semiconductor layers. The concentration distribution of the grown P-type nitride semiconductor layer on the entire surface can be controlled by controlling the amount of P-type dopant at different stages of epitaxial growth, so as to facilitate the adjustment of electric field distribution. By adjusting the electric field distribution technology, a high-quality P-type doped nitride semiconductor layer and its spatial adjustment can be obtained.

[0053] You can also Fig. 9 As shown, an insulating layer 902 is formed on a substrate 901, and an opening region is formed through masking, etching and other processes, a nucleation layer 903 is epitaxially grown at the opening region, and a P-type nitride semiconductor layer 905 is grown on the nucleation layer by selective / lateral epitaxy as a channel layer. After the P-type nitride semiconductor layer 905 is grown, a strong P-type doping region 904 can be formed by ion implantation of P-type impurities in a local region, which is conducive to forming an ohmic contact control with the P-type nitride semiconductor layer.

[0054] For example Fig.10As shown, an insulating layer 1002 is formed on a substrate 1001, and an opening area is formed through masking, etching and other processes. A nucleation layer 1003 is epitaxially grown at the opening area, and a P-type nitride semiconductor layer 1004 is grown on the nucleation layer by selective area / lateral epitaxy, and then other structures such as a channel layer 1005, a barrier layer 1006, and a passivation layer 1007 are formed in sequence. Since the doping concentration in the channel layer is very low or there is no intentional doping, the ion scattering during the transmission of the two-dimensional electron gas can be effectively reduced. The barrier layer 1006 is deposited, and then the in-situ SiN passivation layer 1007 is deposited in the same deposition equipment. That is, after the barrier layer 1006 is deposited, the epitaxial wafer is not taken out, and the in-situ SiN passivation layer 1007 is directly deposited in the same equipment. The SiN passivation layer can effectively protect the surface of the barrier layer 1006 and has a very high quality. The barrier layer / SiNx interface defect state obtained in this way is less. In addition to passivating the surface of the barrier layer, the in-situ SiNx layer can also be used as a gate dielectric layer at the gate stack by retaining only the SiNx layer in the preset gate electrode area through an etching process.

[0055] It should be noted that the P-type nitride semiconductor layer can be used as a channel layer to directly contact the barrier layer. However, since the doping in the P-type nitride semiconductor layer will bring about a significant carrier scattering effect, a better approach is to generate an unintentionally doped or low-doped channel layer between the barrier layer and the P-type nitride semiconductor layer. The scattering of the two-dimensional electron gas when flowing in the channel layer can be greatly reduced. Inserting a channel layer is a more preferred option but not a necessary option.

[0056] An insulating layer 1102, 1202 is formed on the substrate 1101, 1201, and an opening area is formed through masking, etching and other processes, and a nucleation layer 1103, 1203 is epitaxially grown in the opening area, and a strong P-type doping area 1110, 1211 is formed on the nucleation layer 1103, 1203 by selective area / lateral epitaxy, and then a P-type nitride semiconductor layer 1104, 1204 is epitaxially grown. After the P-type nitride semiconductor layer 1104, 1204 is grown, a strong P-type doping area 1110, 1211 can be formed by ion implantation of P-type impurities in a local area, which is conducive to the ohmic contact between the electrode and the P-type nitride semiconductor layer. A channel layer 1105, 1205 is formed above the P-type nitride semiconductor layers 1104, 1204, and a barrier layer 1106, 1206 is further formed, and then a source electrode 1107, 1207, a gate electrode 1109, 1209, and a drain electrode 1108, 1208 are formed. The drain electrodes 1108, 1208 are electrically contacted with the two-dimensional electron gas above the channel layers 1105, 1205, and in the embodiment shown in Figure 12, a body electrode 1210, etc. are also included.

[0057] exist Fig.11In the illustrated embodiment, the source electrode 1107 is connected to the strong P-type doping region 1110 in the P-type nitride semiconductor layer through the two-dimensional electron gas, the drain electrode 1108 is in contact with the two-dimensional electron gas above the channel layer 1105, and the gate electrode 1109 is located above the barrier layer 1106. In this device structure, the potential of the source electrode 1107 is usually fixed at 0V, and the normally off and on operation of the HEMT is achieved by controlling the different voltages of the gate and the drain.

[0058] exist Fig.12 In the illustrated embodiment, the source electrode 1207 and the drain electrode 1208 are in contact with the two-dimensional electron gas above the channel layer 1205, and the gate electrode 1209 is located above the barrier layer 1206. The body electrode 1210 forms a good ohmic contact with the semiconductor layer of the strong P-type doping region 1211 in the P-type nitride semiconductor layer 1204, thereby controlling the potential of the P-type nitride semiconductor layer 1204 independently. When the normally-off and normally-on operation is performed, the HEMT is realized by controlling the different voltage potentials of the gate electrode, the source electrode and the drain electrode, and the voltage potential of the P-type nitride semiconductor layer 1204. By independently controlling the potential of the body electrode 406, the fast shutdown operation of the HEMT can be achieved.

[0059] exist Fig.13 and Fig.14 In the illustrated embodiment, each functional layer is exemplary.

[0060] An insulating layer 1302, 1402 is formed on the substrate 1301, 1401, and an opening area is formed through masking, etching and other processes. Nucleation layers 1303, 1403 are epitaxially grown in the opening area, and P-type nitride semiconductor layers 1304, 1404 are grown on the nucleation layers 1303, 1403 by selective / lateral epitaxy.

[0061] When epitaxially growing the P-type nitride semiconductor layers 1304 and 1404, the first region of the P-type nitride semiconductor layer (1304-1, 1404-1), the first region of the strong P-type nitride semiconductor layer (1304-2, 1404-2), and the second region of the P-type nitride semiconductor layer (1304-3, 1404-3) are formed in sequence through doping modulation technology, wherein the first region of the strong P-type nitride semiconductor layer (1304-2, 1404-2) is located below the gate electrode and can deplete the two-dimensional electron gas in the channel layer below the gate electrode 1410 by more than 95% under 0 bias.

[0062] Channel layers 1305 and 1405 and barrier layers 1306 and 1406 are formed in sequence above the P-type nitride semiconductor layers 1304 and 1404. Gate electrodes 1310 and 1410 are formed on the barrier layers 1306 and 1406. Drain electrodes 1309 and 1409 are disposed in the barrier layers and electrically connected to the two-dimensional electron gas. Fig.13 In the embodiment shown, after masking, etching and other processes, the source electrode 1308 penetrates the channel layer 1305 and forms an electrical contact with the first region (1304-1) of the P-type nitride semiconductor layer, and the potential of the P-type nitride semiconductor layer 1304 is controlled to be consistent with the source electrode, for example, it can be fixed at 0V, and the on and off of the enhanced HEMT can be controlled by only controlling the potential of the gate electrode 1310 and the drain electrode 1309. Fig.14 In the illustrated embodiment, after the P-type nitride semiconductor layer 1404 is grown, a strong P-type doping region 1404-4 can be formed by ion implantation of P-type impurities in a local area, and the source electrode 1408, after masking, etching and other processes, penetrates the channel layer 1405 and forms electrical contact with the strong P-type doping region 1404-4 of the P-type nitride semiconductor layer. The strong P-type doping region 1404-4 is conducive to the ohmic contact between the source electrode and the P-type nitride semiconductor layer, and reduces the on-resistance, which is conducive to the precise control of the potential of the P-type nitride semiconductor layer 1404. The potential of the P-type nitride semiconductor layer 1404 is controlled to be consistent with the source electrode, for example, it can be fixed at 0V, and the on and off of the enhanced HEMT can be controlled by only controlling the potential of the gate electrode 1410 and the drain electrode 1409.

[0063] for Figure 13-14 In the embodiment shown, at the end of the epitaxial growth of the second region (1304-3, 1404-3) of the P-type nitride semiconductor layer, that is, in the region close to the preset drain electrode, the doping concentration is low or undoped. This is to enhance the voltage resistance of the device while still having a good on-state current conduction capability. After the selective / lateral epitaxial growth is completed, a portion of the upper surface nitride semiconductor layer can be removed by a planarization or etching process, and then a barrier layer structure or a channel layer and a barrier layer structure can be formed by epitaxy. This is to prevent different concentrations of doping from having a negative impact on the device structure above the channel layer. A source electrode is arranged above the P-type nitride semiconductor layer corresponding to the opening area of ​​the nucleation layer, and the selective / lateral epitaxial growth radially expands with the source electrode projection surface area as the center, which is conducive to covering the entire surface with a high proportion on the entire substrate.

[0064] In addition, for Figure 13-14 In the embodiment shown, the potential control method of the P-type nitride semiconductor layer can be as follows Fig.12As shown, the source electrode and the drain electrode are only arranged in the barrier layer and electrically connected to the two-dimensional electron gas, while the body electrode is independently arranged to be electrically connected to the P-type nitride semiconductor layer region above the nucleation layer (when strongly doped, it is a strongly P-type doped region) to independently control the potential of the P-type nitride semiconductor layer.

[0065] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A high electron mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, and a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate, which is insufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas; The P-type nitride semiconductor layer is formed by selective area / lateral epitaxial growth; The P-type nitride semiconductor layer is lightly doped or undoped when the portion close to the preset drain electrode is selectively / laterally epitaxially grown, and the doping concentration of the lightly doped layer is below 2E18 / cm3; The P-type nitride semiconductor layer is at least partially located in a region between the source electrode and the gate electrode and between the gate electrode and the drain electrode; The P-type nitride semiconductor layer includes a strong P-type doping region and a P-type nitride semiconductor layer region, wherein the strong P-type doping region is located below the gate electrode and / or the source electrode.

2. The transistor according to claim 1, characterized in that The invention also includes a nucleation layer, which is located between the P-type nitride semiconductor layer and the substrate.

3. The transistor according to claim 1, characterized in that A low-doped or unintentionally doped nitride semiconductor layer is further included between the barrier layer and the P-type nitride semiconductor layer.

4. The transistor according to claim 1, characterized in that The doping concentration of the P-type nitride semiconductor layer can be controlled to change during the selective / lateral epitaxial growth, so as to form a modulation-doped P-type nitride semiconductor layer according to different regions.

5. The transistor according to claim 1, characterized in that After the selective / lateral epitaxial growth, a portion of the P-type nitride semiconductor layer in the height direction is removed by a planarization or etching process.

6. The transistor according to any one of claims 1 to 3, characterized in that: An insulating layer is provided on the substrate, an opening area is etched into the insulating layer, a nucleation layer is formed at the opening area, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy; or a nucleation layer is grown on the substrate, an insulating layer is formed on the nucleation layer, the opening of the insulating layer exposes the nucleation layer, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy.

7. The transistor according to claim 6, characterized in that Before growing the P-type nitride semiconductor layer, a buffer layer is formed on the nucleation layer, and the buffer layer is a layer composed of a highly doped P-type nitride semiconductor material.

8. The transistor according to any one of claims 1 to 3, characterized in that: Except for the gate stack region, at 0 bias, the channel two-dimensional electron gas concentration of the P-type nitride semiconductor layer depleted is less than 80% of the channel two-dimensional electron gas concentration when the P-type doping in the P-type nitride semiconductor layer is not present.

9. The transistor according to any one of claims 1 to 3, characterized in that: When forming the P-type nitride semiconductor layer, a first region of the P-type nitride semiconductor layer, a first region of the strong P-type nitride semiconductor layer, and a second region of the P-type nitride semiconductor layer are formed in sequence, wherein the first region of the P-type nitride semiconductor layer is located below the source electrode, the first region of the strong P-type nitride semiconductor layer is located below the gate electrode, and the second region of the P-type nitride semiconductor layer is located below the drain electrode, and the first region of the strong P-type nitride semiconductor layer depletes more than 95% of the two-dimensional electron gas in at least a portion of the channel layer below the gate electrode under 0 bias.

10. The transistor according to claim 1, characterized in that After forming the barrier layer, a SiNx passivation layer is grown in situ.

11. The transistor according to claim 1, characterized in that A gate insulating layer is added under the gate electrode to reduce the off-state leakage current of the gate.

12. The transistor according to claim 1, characterized in that The selective / lateral epitaxial growth of the nucleation layer adopts a precursor mixed atmosphere containing hydrogen and / or chlorine.

13. The transistor according to claim 1, characterized in that A precursor mixed atmosphere containing hydrogen and / or chlorine is used when selectively / laterally epitaxially growing a P-type nitride semiconductor layer.

14. A high electron mobility transistor, comprising a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer, and a substrate; the P-type nitride semiconductor layer is located between the barrier layer and the substrate, which is insufficient to significantly deplete the two-dimensional electron gas in the channel except for the gate stack, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas, and an independent body electrode is in electrical contact with the P-type nitride semiconductor layer, and the electrical contact region is a strongly P-type doped region; The P-type nitride semiconductor layer is lightly doped or undoped when the portion close to the preset drain electrode is selectively / laterally epitaxially grown, and the doping concentration of the lightly doped layer is below 2E18 / cm3; The P-type nitride semiconductor layer is at least partially located in a region between the source electrode and the gate electrode and between the gate electrode and the drain electrode; The P-type nitride semiconductor layer includes a strong P-type doping region and a P-type nitride semiconductor layer region, wherein the strong P-type doping region is located below the gate electrode and / or the source electrode.

15. The transistor according to claim 14, characterized in that The invention also includes a nucleation layer, which is located between the P-type nitride semiconductor layer and the substrate.

16. The transistor according to claim 14, characterized in that An insulating layer is provided on the substrate, an opening area is etched into the insulating layer, a nucleation layer is formed at the opening area, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy; or a nucleation layer is grown on the substrate, an insulating layer is formed on the nucleation layer, the opening of the insulating layer exposes the nucleation layer, and then an epitaxial layer structure including a P-type nitride semiconductor layer is grown by selective area / lateral epitaxy.

17. The transistor according to any one of claims 14 to 16, characterized in that The doping concentration of the P-type nitride semiconductor layer can be controlled to change during the selective / lateral epitaxial growth, so as to form a modulation-doped P-type nitride semiconductor layer according to different regions.

18. The transistor according to any one of claims 14 to 16, characterized in that After the P-type nitride semiconductor layer is grown, a low-doped or undoped semiconductor layer is grown to achieve an undoped channel layer on the upper surface of the P-type nitride semiconductor layer.

19. The transistor according to any one of claims 14 to 16, characterized in that After the selective / lateral epitaxial growth, a portion of the upper surface nitride semiconductor layer is removed by a planarization or etching process, and then a barrier layer structure or a channel layer and barrier layer structure is formed by epitaxy.

20. The transistor according to any one of claims 14 to 16, characterized in that When forming the P-type nitride semiconductor layer, a first region of the P-type nitride semiconductor layer, a first region of the strong P-type nitride semiconductor layer, and a second region of the P-type nitride semiconductor layer are formed in sequence, wherein the first region of the P-type nitride semiconductor layer is located below the body electrode, the first region of the strong P-type nitride semiconductor layer is located below the gate electrode, and the second region of the P-type nitride semiconductor layer is located below the drain electrode, and the first region of the strong P-type nitride semiconductor layer depletes more than 95% of the two-dimensional electron gas in at least a portion of the channel layer below the gate electrode under 0 bias.

21. The transistor according to claim 20, characterized in that When forming a P-type nitride semiconductor layer, after the first region of the P-type nitride semiconductor layer, the first region of the strong P-type nitride semiconductor layer, and the second region of the P-type nitride semiconductor layer are formed in sequence, ion implantation is performed in the region where the first region of the P-type nitride semiconductor layer is connected to the body electrode to form a strong P-type doped region, the body electrode is connected to the strong P-type doped region to form an ohmic contact, the first region of the strong P-type nitride semiconductor layer is located below the gate electrode, the second region of the P-type nitride semiconductor layer is located below the drain electrode, and the first region of the strong P-type nitride semiconductor layer depletes more than 95% of the two-dimensional electron gas in at least a portion of the channel layer below the gate electrode under zero bias.

22. The transistor according to any one of claims 14 to 16, characterized in that Before growing the P-type nitride semiconductor layer, a buffer layer is formed on the nucleation layer, and the buffer layer is a layer composed of a highly doped P-type nitride semiconductor material.

23. The transistor according to any one of claims 14 to 16, characterized in that After the P-type nitride semiconductor layer is grown, a highly doped P-type nitride semiconductor layer region is formed above the nucleation layer to facilitate the formation of an ohmic contact with a connected electrode.

24. The transistor according to claim 14, characterized in that After forming the barrier layer, a SiNx passivation layer is grown in situ.

25. The transistor according to claim 14, characterized in that A gate insulating layer is added under the gate electrode to reduce the off-state leakage current of the gate.

26. The transistor according to claim 14, characterized in that The selective / lateral epitaxial growth of the nucleation layer adopts a precursor mixed atmosphere containing hydrogen and / or chlorine.

27. The transistor according to claim 14, characterized in that A precursor mixed atmosphere containing hydrogen and / or chlorine is used when selectively / laterally epitaxially growing a P-type nitride semiconductor layer.

28. The transistor according to claim 14, characterized in that Except for the gate stack region, at 0 bias, the channel two-dimensional electron gas concentration of the P-type nitride semiconductor layer depleted is less than 80% of the channel two-dimensional electron gas concentration when the P-type doping in the P-type nitride semiconductor layer is not present.

29. A method for preparing a high electron mobility transistor as claimed in claim 1 or claim 14, characterized in that: A P-type nitride semiconductor layer is grown on the nucleation layer by selective / lateral epitaxy. The doping concentration of the P-type nitride semiconductor layer can be controllably changed during the selective / lateral epitaxial growth. A modulated doped P-type nitride semiconductor layer is formed in different regions, and then an electrode structure is formed, wherein the projection surface of the source electrode on the substrate partially overlaps with the projection surface of the nucleation layer on the substrate.

30. The method according to claim 29, characterized in that A precursor mixed atmosphere containing hydrogen and / or chlorine is used when selectively / laterally epitaxially growing a P-type nitride semiconductor layer.

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