Imaging system with tunable amplifier circuit

Abstract

An image sensor can include an array of image pixels. The array of image pixels can be coupled to column readout circuitry. A given image pixel can generate a low light signal and a high light signal for a given exposure. A column line can couple the given image pixel to readout circuitry having an amplifier circuit. The column line can be coupled to an auto-zero transistor for reading out the high light signal and a source follower stage for reading out the low light signal. The amplifier circuit can receive different common mode voltages depending on whether it is amplifying the low light signal or the high light signal. The gain and other operating parameters of the amplifier circuit can be adjusted based on whether the amplifier circuit is amplifying the low signal or the high signal. Separate amplifier circuits can be implemented for the low light signal and the high light signal if desired.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to imaging devices, and more particularly to readout circuitry in image sensors. BACKGROUND

[0002] Image sensors are often used in electronic devices such as mobile phones, cameras, and computers to capture images. In a typical arrangement, an image sensor includes an array of image pixels arranged in rows and columns of pixels. Circuitry can be coupled to each column of pixels to read out image signals from the image pixels.

[0003] Typically, each image pixel includes a photodiode to generate charge in response to incident light. Each image pixel can generate charge under varying light conditions, such as under relatively weak light conditions or under relatively strong light conditions. Thus, in some applications, it can be desirable for the image pixels to generate signals that are optimized for these varying light conditions, e.g., a weak light signal and a strong light signal. Additionally, the different characteristics between the weak light signal and the strong light signal, e.g., different types of dominant noise between the weak light signal and the strong light signal, can provide opportunities to more effectively adjust and configure the readout circuitry to read out each of these two signals.

[0004] Accordingly, it can be desirable to provide imaging systems with improved readout circuitry, e.g., to read out weak light signals with low read noise and higher stability accuracy, to read out strong light signals more quickly while reducing power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic diagram of an exemplary electronic device having an image sensor and processing circuitry for capturing images, in accordance with some embodiments.

[0006] Figure 2 is a schematic diagram of an exemplary pixel array and associated control and readout circuitry for controlling the pixel array and reading out image signals from the pixel array, in accordance with some embodiments.

[0007] Figure 3 is a circuit diagram of an exemplary image pixel that can be implemented across a pixel array, in accordance with some embodiments.

[0008] Figure 4 is a circuit diagram of an exemplary readout circuit coupled to an image pixel and having an adjustable amplifier circuit, in accordance with some embodiments.

[0009] Figure 5 is an exemplary timing diagram for operating a readout circuit, such as the readout circuit in Figure 4 and an image pixel, such as the image pixel in Figure 3 , in accordance with some embodiments.

[0010] Figure 6 is a circuit diagram of an exemplary readout circuit having separate amplifier circuits for different types of image signals, in accordance with some embodiments.

[0011] Figure 7 is an exemplary timing diagram for operating a readout circuit, such as the readout circuit in Figure 6 and an image pixel, such as the image pixel in Figure 3 DETAILED DESCRIPTION

[0012] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices can include image sensors that collect incident light to capture images. An image sensor can include an array of image pixels. Pixels in an image sensor can include a photosensitive element, such as a photodiode that converts incident light into an image signal. An image sensor can have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels). An image sensor can include control circuitry (such as circuitry for operating the image pixels) and a readout circuit for reading out image signals corresponding to charges generated by the photosensitive elements.

[0013] Figure 1 is a schematic diagram of an exemplary imaging system, such as an electronic device, that captures images using an image sensor. Figure 1 Electronic device 10 of FIG. 1 can be a portable electronic device, such as a camera, a cellular telephone, a tablet computer, a webcam, a camcorder, a video surveillance system, a motor vehicle imaging system, a video game system with imaging capability, an augmented reality and / or virtual reality system, a drone system (e.g., a drone), an industrial system, or any other desired imaging system or device that captures digital image data. Camera module 12 (sometimes referred to as an imaging module) can be used to convert incident light into digital image data. Camera module 12 can include one or more lenses 14 and one or more corresponding image sensors 16. Lenses 14 can include fixed lenses and / or adjustable lenses, and can include micro-lenses and other macro lenses formed on the imaging surface of image sensors 16. During an image capture operation, light from a scene can be focused by lenses 14 onto image sensors 16. Image sensors 16 can include circuitry for converting analog pixel image signals into corresponding digital image data that is provided to storage and processing circuitry 18. If desired, camera module 12 can be provided with an array of lenses 14 and an array of corresponding image sensors 16.

[0014] ​The storage and processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, a storage device such as random access memory and non-volatile memory, etc.) and may be implemented using components separate from and / or forming part of the camera module (e.g., circuitry forming part of an integrated circuit within a module including the image sensor 16 or associated with the image sensor 16). When the storage and processing circuitry 18 is included on an integrated circuit (e.g., a chip) different from the integrated circuit of the image sensor 16, the integrated circuit having the circuitry 18 may be vertically stacked or packaged relative to the integrated circuit having the image sensor 16. The processing circuitry 18 may be used to process and store image data captured by the camera module (e.g., using an image processing engine on the processing circuitry 18, using an imaging mode selection engine on the processing circuitry 18, etc.). The processed image data may be provided to external devices (e.g., a computer, an external display, or other devices) as needed using wired and / or wireless communication paths coupled to the processing circuitry 18.

[0015] like Figure 2 As shown, the image sensor 16 may include a pixel array 20 containing image sensor pixels 22 (sometimes referred to herein as image pixels or pixels) arranged in rows and columns, and control and processing circuitry 24. The array 20 may contain, for example, hundreds or thousands of rows and hundreds or thousands of columns of image sensor pixels 22. The control circuitry 24 may be coupled to row control circuitry 26 (sometimes referred to as row driver circuitry or row driver) and column readout circuitry 28 (sometimes referred to as column control circuitry, image readout circuitry, readout circuitry, processing circuitry, or column decoder circuitry). The row control circuitry 26 may receive row addresses from the control circuitry 24 and provide corresponding row control signals (such as reset control signals, anti-halo control signals, row selection control signals, charge transfer control signals, double conversion gain control signals, and readout control signals) to the pixels 22 via row control path 30. One or more wires (such as column lines 32) may be coupled to each column of pixels 22 in the array 20. The column lines 32 may be used to read out image signals from pixels 22 and to provide bias signals (e.g., bias current or bias voltage) to pixels 22. If necessary, during pixel readout operations, row control circuitry 26 can be used to select a pixel row in array 20, and the image signal generated by the image pixels 22 in that pixel row can be read along column line 32.

[0016] Column readout circuit 28 can receive image signals (e.g., analog pixel values ​​generated by pixel 22) via column lines 32. Column readout circuit 28 may include memory circuitry, amplifier circuitry or multiplier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, latching circuitry for selectively enabling or disabling column circuitry, or other circuitry coupled to one or more pixel columns in array 20 for operating pixel 22 and for reading image signals from pixel 22. The ADC circuitry in readout circuit 28 can convert the analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Column readout circuit 28 can provide digital pixel data for pixels in one or more pixel columns to control and processing circuitry 24 and / or processor 18. Figure 1 ).

[0017] If needed, each image pixel 22 may include more than one photosensitive area for generating charge in response to image light. The photosensitive areas within the image pixel 22 may be arranged in rows and columns on the array 20. The image array 20 may also be provided with a filter array having multiple (color) filtering elements (each corresponding to a corresponding pixel), which allows a single image sensor to sample light of different colors or different wavelength groups. For example, image sensor pixels such as the image pixels in array 20 may be provided with a color filter array having red, green, and blue filtering elements, which allows a single image sensor to sample red, green, and blue (RGB) light using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern.

[0018] In another suitable example, the green pixel in the Bayer pattern can be replaced with a broadband image pixel having a broadband color filter element (e.g., a transparent color filter element, a yellow color filter element, etc.). In yet another example, a green pixel in the Bayer pattern can be replaced with an IR image pixel formed under an infrared (IR) color filter element, and / or the remaining red, green, and blue image pixels can also be sensitive to IR light (e.g., formed under a filter element that allows IR light to pass through in addition to light of its corresponding color). These examples are merely illustrative; in general, filter elements of any desired color and / or wavelength and any desired pattern can be formed over any desired number of image pixels 22.

[0019] Image sensor 16 may include one or more image pixel arrays 20. The image pixels 22 may be formed in a semiconductor substrate using complementary metal-oxide-semiconductor (CMOS) technology, charge-coupled device (CCD) technology, or any other suitable photosensitive device technology. The image pixels 22 may be front-illuminated (FSI) image pixels or back-illuminated (BSI) image pixels. If desired, image sensor 16 may include an integrated circuit package or other structure in which multiple integrated circuit substrate layers or chips are stacked vertically relative to each other. In this case, one or more of circuits 24, 26, and 28 may be vertically stacked above or below the array 20 within image sensor 16. If desired, lines 32 and 30 may be formed in this case by vertical conductive via structures (e.g., through-silicon vias or TSVs) and / or horizontal interconnect lines.

[0020] Figure 3 This is a circuit diagram for an illustrative image pixel 22. For example... Figure 3 As shown, pixel 22 may include a photosensitive element, such as photodiode 40. Photodiode 40 may include a device for receiving a reference voltage V. SS The first terminal (e.g., the ground voltage provided by voltage terminal 38). Incident light can be collected by photodiode 40. Photodiode 40 can generate charge (e.g., electrons) in response to receiving incident photons. The amount of charge collected by photodiode 40 can depend on the intensity of the incident light and the exposure time (or accumulation time).

[0021] A positive power supply voltage V can be provided at voltage terminal 42. AA Before acquiring an image, (e.g., by asserting the control signal RST) the reset transistor 46 can be turned on to reset the charge storage region 48 (sometimes called the floating diffusion region) to voltage V. AA The voltage level stored in the floating diffusion region 48 can be read using the charge readout circuitry in pixel 22. The charge readout circuitry may include a source follower transistor 60 and a row select transistor 62. The charge stored in the charge storage region 48 may include the charge generated by the photodiode, the reset level charge (as opposed to voltage V), and other charges. AA (Associated) and / or other reference level charges (e.g., indicating dark current, parasitic light, etc.).

[0022] (For example, by connecting voltage terminal 42 to the second terminal of photodiode 40) photodiode 40 can be reset to the power supply voltage V. AAAfter photodiode 40 is reset, it can begin to accumulate photogenerated charge. Pixel 22 may include transfer transistor 58. (e.g., by activating a control signal TX) Transfer transistor 58 can be turned on to transfer charge from photodiode 40 to floating diffusion region 48. Floating diffusion region 48 may be a doped semiconductor region (e.g., a region doped in a silicon substrate by ion implantation, impurity diffusion, or other doping processes). Floating diffusion region 48 may have an associated charge storage capacity (e.g., as shown in the image). Figure 3 The coupling in is connected to a reference voltage (such as voltage V). SS The capacitance C of the capacitor. FD (As shown).

[0023] The row selection transistor 62 may have a gate terminal controlled by a row selection signal (i.e., signal RS). When the row selection signal is active, transistor 62 is turned on and corresponds to signal V. OUT (For example, an output signal whose amplitude is proportional to the amount of charge at the floating diffusion region 48) is transmitted to the pixel output path via the source follower transistor 60 and to the readout path (such as column line 68) (i.e., Figure 2 On line 32). When the floating diffusion region 48 stores the charge being read out by the photodiode, the corresponding signal V OUT This can be referred to as the image level signal. When the floating diffusion region 48 stores the reset level charge being read, the corresponding signal V... OUT This can be referred to as a reset level signal.

[0024] Having an image pixel array (such as Figure 3 The image sensor (pixels 22) can operate under varying lighting conditions (e.g., in relatively low light environments, in relatively bright light environments, in moderate light environments between low and bright light environments, etc.). In some applications (e.g., to provide high dynamic range images), it may be desirable to... Figure 3 Pixel 22 generates more than one image signal (e.g., two image signals) for each exposure time period.

[0025] Still referencing Figure 3 For example, pixel 22 may include a capacitor, such as a low (conversion) gain capacitor 52 (e.g., having a capacitance C). lcgCapacitor 52 may be configured to store overflow charge (e.g., a portion of the charge above a voltage threshold generated by photodiode 40, or excess charge generated under strong light conditions). Capacitor 52 may be coupled to floating diffusion region 48 via a transistor (such as dual-conversion gain transistor 50). Capacitor 52 may have terminals coupled to voltage terminals (such as voltage terminal 38 providing ground voltage) (or coupled to any other suitable voltage terminal). Transistor 50 may be activated to connect capacitor 52 to floating diffusion region 48, for example, by activating control signal DCG.

[0026] Specifically, capacitor 52 can be configured to extend the storage capacity of floating diffusion region 48. Pixel 22 can use (e.g., when capacitor 52 is disconnected from floating diffusion region 48) the charge stored at floating diffusion region 48 to generate a first signal (e.g., a weak light or high conversion gain signal, sometimes referred to herein as the S1 image signal), and can use (e.g., when capacitor 52 is connected to floating diffusion region 48) the charge stored at floating diffusion region 48 and capacitor 52 to generate a second signal (e.g., a strong light or low conversion gain signal, sometimes referred to herein as the S2 image signal).

[0027] Figure 3 The pixel configuration shown is merely illustrative. Figure 3 The type of pixel 22 in the middle is implemented as cross Figure 2 The arrangement of each pixel in the pixel 22 of array 20 is described herein as an example. Any suitable modifications to pixel 22 can be made to implement this if necessary. Figure 2 The pixel array 20 in the image. For example, pixel 22 may include multiple photodiodes (e.g., coupled to the same or different floating diffusion regions), anti-halo transistors or paths, multiple low-conversion-gain capacitors coupled to one or more floating diffusion regions via corresponding one or more gain control transistors, etc.

[0028] Generally speaking, pixel 22 can be...

[0029] In a typical image pixel array configuration, there are multiple rows and columns of pixels 22. A column readout path can be associated with each column of pixels 22 (e.g., each image pixel 22 in a column can be coupled to the column output path via an associated row selection transistor 62). A control signal RS can be activated to transmit the signal V from the selected image pixel. OUT Read the signal V onto the pixel readout path. OUT Provided to the readout circuit 28 ( Figure 2 ) and processing circuit 18 ( Figure 1 (For further processing)

[0030] Figure 4It is used in a pixel array (e.g., Figure 2 A circuit diagram illustrating an exemplary arrangement of a given pixel column in array 20) coupled to a readout circuit. For example... Figure 4 As shown, pixel column 102 may include pixels 22-1, 22-2, 22-3, etc. (for example, each having...) Figure 3 The configuration of pixel 22 in column 102). Each pixel in pixel 22 in column 102 may include a connection to a shared column line 68 (e.g., Figure 2 The corresponding row selection transistor is located at column line 32. Column line 68 can couple pixel 22 in column 102 to readout circuit 100. Readout circuit 100 can form Figure 2 This is part of the column readout circuit 28. For example, a corresponding individual readout circuit (similar to readout circuit 100) may be similarly coupled to other pixel columns in array 20 and may together form column readout circuit 28.

[0031] As mentioned above Figure 3 Each pixel can generate both strong and weak light signals. To more effectively perform readout operations on both strong and weak light signals, the image sensor may include adjustable readout circuitry, such as... Figure 4 The readout circuit 100 is described in detail below. Specifically, the low-light performance of an image sensor (e.g., obtaining a satisfactory low-light signal) emphasizes factors such as low readout chain (circuit) noise, good linearity, and low fixed-pattern noise, while the high-light performance of an image sensor (e.g., obtaining a satisfactory high-light signal) may not emphasize factors such as readout chain noise and stable accuracy, because input signal noise may be more dominant. Therefore, it may be desirable to relax the corresponding readout circuit parameters for high-light signals to improve sampling time and power consumption. Additionally, during the readout of the high-light image and reset level signal (e.g., by connecting the column lines to a reference voltage or ground voltage before readout to the column lines), it is advantageous to match the backflush effect of the pixel output on the floating diffusion region. The configuration of the readout circuit 100 having at least these desired properties is described in more detail below.

[0032] Specifically, the readout circuit 100 may include transistors 104 and 106 connected in series between column line 68 and voltage terminals, such as voltage terminal 38 providing voltage Vss (e.g., ground voltage). Transistor 104 may be used as a switch (e.g., by activating the control signal SFEN) to selectively connect column line 68 to transistor 106. Bias transistor 106 may be configured (e.g., by using the control signal SFBIAS) to generate a bias current, which helps drive the signal away from pixel 22 in column 102 during readout operations (e.g., for weak light signals).

[0033] The readout circuit 100 may include a transistor 108 coupled between column line 68 and a voltage terminal, such as voltage terminal 38 that provides a voltage Vss (e.g., ground voltage). Transistor 108 may be configured (e.g., by activating a control signal AZGND) to pull down the voltage of column line 68 to voltage Vss or any other reference voltage, such as a voltage higher than ground voltage.

[0034] The readout circuit 100 may include an amplifier circuit (e.g., an operational amplifier), such as amplifier circuit 110. Amplifier circuit 110 may include a first input terminal (e.g., an inverting terminal) and a second input terminal (e.g., a non-inverting terminal). The column line 68 providing the signal Vin may be coupled to the inverting terminal of amplifier circuit 110 via an input capacitor (e.g., capacitor 112 with capacitance Cs).

[0035] The non-inverting terminal of amplifier circuit 110 can receive one of two reference voltages, Vrefs1 and Vrefs2. Specifically, switch 114 (controlled by control signal S1) couples the reference voltage terminal 118, which provides voltage Vrefs1, to the non-inverting terminal of amplifier circuit 110. Switch 116 (controlled by control signal S2) couples the reference voltage terminal 120, which provides voltage Vrefs2, to the non-inverting terminal of amplifier circuit 110 along a separate path. For example, voltage Vrefs1 can be the lowest possible input common-mode voltage that can be received by amplifier 100, while voltage Vrefs2 can be greater than the reset level signal in the pixel output. Vrefs1 and Vrefs2 can be any other suitable value if desired.

[0036] Amplifier circuit 110 may include an output terminal that provides an amplifier output signal Vout. The output terminal of amplifier circuit 110 may be coupled to the inverting terminal of amplifier circuit 110 via an automatic zero-adjustment switch (such as switch 122 controlled by signal AZ). The output terminal of amplifier circuit 110 may also be coupled to the inverting terminal of amplifier circuit 110 via a feedback capacitor (such as feedback capacitor 124 having capacitance Cf) along a separate path (e.g., a second path parallel to the path along which switch 122 is coupled). The ratio of input capacitance Cs to feedback capacitance determines the gain (factor) G of amplifier circuit 110 and may be adjustable. For example, the gain may be relatively large (e.g., at least greater than one) for amplifying weak light signals, while the gain may be less than or equal to one for amplification.

[0037] Additionally, switch 126 can couple the output terminal of amplifier circuit 110 to voltage terminal 38 (e.g., to provide ground voltage) via capacitor 128 (e.g., a filter circuit). Switch 126 can be controlled by control signal S1 (e.g., the same signal received by switch 114). This band-limiting path can be used to reduce readout noise (e.g., for weak light signals).

[0038] The output terminals of amplifier circuit 110 can also be connected to a sample-and-hold circuit (e.g., a memory circuit for storing image level and reset level signals for strong and weak light signals). Specifically, a sampling switch (such as switch 130 controlled by signal SAMP) can connect the output terminals of amplifier circuit to a sampling circuit (such as sample-and-hold capacitor 132) (e.g., storing voltage Vsh at one terminal and receiving a reference voltage, such as ground voltage, at the other terminal).

[0039] The readout circuit 100 can be configured to operate in a first mode and a second mode (e.g., a low-light mode for reading out a low-light image level signal and a corresponding reset level signal, and a high-light mode for reading out a low-light image level signal and a corresponding reset level signal). Reference Figure 4 The transistor 108 in the transistor has a control signal AZGND that can be selectively activated during the strong light mode (e.g., before the column line 68 receives the strong light image level and reset level signals). The control signal SFEN can be deactivated throughout the strong light mode. These controls mitigate any memory effects on the column lines to match the backflow of the pixel output in during the readout of the strong light image and reset level signals, and reduce sampling time and power consumption during strong light mode operation.

[0040] In contrast, during low-light mode, the control signal AZGND can be disabled and the control signal SFEN can be enabled to provide greater stability and accuracy. In other words, during low-light mode, readout is performed using a source follower stage, and during high-light mode, readout is performed without a source follower stage. Any nonlinearities associated with performing readout without a source follower stage can be corrected using piecewise linearity correction in the digital domain (e.g., via downstream digital processing circuitry).

[0041] During low-light mode (e.g., for reading out low-light images and reset level signals), control signal S1 is active. During high-light mode (e.g., for reading out high-light images and reset level signals), control signal S2 is active. (See reference) Figure 4Reference voltage terminals 118 and 120, selectively connected to the non-inverting terminals of operational amplifier 110 via switches 114 and 116, can provide a relatively low common-mode voltage Vrefs1 to amplifier circuit 110 during low-light mode and a relatively high common-mode voltage Vrefs2 to amplifier circuit 110 during high-light mode. Each of the two common-mode voltages, Vrefs1 and Vrefs2, can be selected to optimize the performance of the corresponding signal in either low-light or high-light signal conditions.

[0042] refer to Figure 4 The switch 126 and capacitor 128 are configured such that control signal S1 is active during low-light mode. When configured in this manner (e.g., switch 126 is in the closed (i.e., conductive) state), the output signal Vout can be band-limited during low-light mode, thereby reducing readout noise in low-light signals. During high-light mode, control signal S2 can be disabled, and switch 126 can be in the open state to improve the speed of readout operations.

[0043] Figure 5 It is used to operate adjustable readout circuits (such as...) Figure 4 The readout circuit 100 is shown in an exemplary timing diagram for reading the image level and reset level signals for weak and strong light conditions. Specifically, the readout circuit can operate in weak light mode during a time period between time t1 and t2, and in strong light mode during a time period between time t2 and t3. Control circuitry (such as control circuits 24 and / or 26) Figure 2 )) can be configured to provide Figure 5 The control signal described herein (e.g., enabling and disabling the control signal).

[0044] like Figure 5 As shown, between time t1 and t2, the reset level signal and image level signal for weak light can be sampled. Specifically, the activation of control signals SAMP, A1 and A2, can selectively activate the sampling switch (e.g., Figure 4 Switch 130) corresponds to the amplifier output signal (e.g.,) that corresponds to the reset level signal at effective A1 and the image level signal at effective A2. Figure 4 The signal Vout of the amplifier circuit 110 in the middle is sampled.

[0045] During the time period between t1 and t2, control signal S1 can be activated (continuously) by activating D1 (e.g., to activate...). Figure 4 Switch 114 in the middle), thereby providing a first common-mode voltage of low-light mode to the amplifier circuit (e.g., to the switch ...). Figure 4 The amplifier circuit 110 in the middle provides the lowest possible common-mode voltage Vrefs1 and provides a bandwidth-limiting path (e.g., with...).Figure 4 (Connection of capacitor 128 in the middle). During the time period between t1 and t2, the control signal SFEN can be activated (continuously) by activating F1 (e.g., to activate). Figure 4 Transistor 104 in the middle), thereby providing bias current to the column line (e.g., connecting transistor 106 to Figure 4 (Column line 68 in the text). During the time period between t1 and t2, the control signal RS can be activated (continuously) by activating G1 (e.g., to...). Figure 4 Activated in the corresponding pixel 22 of column 102 (to which a readout operation is performed) Figure 3 Transistor 62 in the transistor, thereby enabling the pixel circuit (e.g., Figure 3 The source follower transistor 60 in the middle is connected to the corresponding column line.

[0046] Before performing a readout operation on the low-light reset level signal using activation A1 (e.g., before time t1), activation I' can be used to reset the floating diffusion region of the pixel from which the reset level signal is read out to the supply voltage. (e.g., using activations F1 and G1 for signals SFEN and RS, respectively). The reset level signal can be passed to the amplifier circuit as an input signal Vin. After time t1, control signal AZ can be activated via activation B1 to connect the amplifier circuit (e.g., Figure 4 The amplifier circuit 110 in the circuit contains the inverting terminal and the output terminal. At this time, the amplifier output signal Vout can be at a weak common-mode voltage (e.g., voltage Vrefs1). The amplifier output can be sampled using the active A1.

[0047] Then, the control signal TX can be activated via activation H to transfer the charge generated by the photodiode to the floating diffusion region (in the same pixel from which the reset level signal is read). (E.g., using activations F1 and G1) The weak light image level signal (e.g., the S1 image signal) can be passed to the amplifier circuit as the input signal Vin. At this time, the amplifier output signal Vout can be added to the sum of the product of the common-mode voltage Vrefs1 and the gain factor G with the associated or relative weak light image level signal Vshss1. Specifically, the gain factor G can be determined by the ratio of the amplifier input capacitance Cs to the amplifier feedback capacitance Cf, and the associated weak light image level signal Vshss1 can be determined by the difference between the absolute weak light image level signal (e.g., from ground voltage) and the absolute weak light reset level signal (e.g., from ground voltage). At this time, the amplifier output can be sampled using activation A2.

[0048] At time t2, the readout circuit can switch from low-light mode to high-light mode. Specifically, between time t2 and t3, the reset level signal and image level signal of the high-light signal can be sampled. Specifically, the activation of control signals SAMP A3 and A4 can selectively activate the sampling switch (e.g., Figure 4 Switch 130 in the middle) corresponds to the amplifier output signal (e.g., corresponding to the image level signal at effective A3 and the reset level signal at effective A4) Figure 4 The signal Vout of the amplifier circuit 110 in the middle is sampled.

[0049] During the time period between t2 and t3, control signal S2 can be activated (continuously) via activation E1 (e.g., to activate...). Figure 4 Switch 116 in the middle), thereby providing a second common-mode voltage of strong light mode to the amplifier circuit (e.g., to the switch ...). Figure 4 The amplifier circuit 110 provides a voltage Vrefs2 greater than the reset level voltage. Additionally, during the time period between t2 and t3, the control signal DCG can be activated (continuously) via activation J to connect the floating diffusion region at the pixel to the low-gain capacitor at the pixel (e.g., Figure 3 The capacitor 52 in the middle provides overflow charge stored in the low-gain capacitor for readout. In this way, the pixel can be configured to generate a low conversion gain image signal (e.g., a strong light image level signal).

[0050] After time t2, the control signal AZGND can be activated by activating C1 to connect the column line to ground voltage or a different reference voltage (e.g., connecting column line 68 to...). Figure 4 (Vss in the voltage). Although the control signal AZGND is active, the control signal RS may be inactive.

[0051] After time t2 (e.g., simultaneously with the activation of C1), control signal AZ can be activated via activation B2 to connect the amplifier circuit (e.g., Figure 4 The amplifier circuit 110 in the middle is connected to the inverting terminal and the output terminal. At this time, the amplifier output signal Vout can be at the common-mode voltage of the strong light (e.g., voltage Vrefs2). Then, the control signal RS can be activated by activating G2 to transmit the strong light image level signal to the column line (e.g., Figure 4 (Column line 86) and transmits to the amplifier circuit (e.g., Figure 4 The inverting terminal of the amplifier circuit 110 in the middle.

[0052] Therefore, the amplifier circuit can generate an amplifier output signal Vout based on the input high-intensity light image level signal. Specifically, the amplifier output signal Vout can be reduced from the common-mode voltage Vrefs2 to the difference between the common-mode voltage Vrefs2 and the product of the gain factor G and the absolute high-intensity light image level signal Vshss2 (e.g., from ground voltage), where the gain factor G is determined by the ratio of the amplifier input capacitance Cs to the amplifier feedback capacitance Cf. The gain factor G can be less than or equal to one in high-intensity light mode to avoid saturating the amplifier output. The amplifier output can be sampled using active A3.

[0053] After A3 is activated, the control signal AZGND can be reactivated by activating C2 to connect the column line to the ground voltage (e.g., connecting column line 68 to...). Figure 4 The voltage Vss in the circuit. Although the control signal AZGND is active, the control signal RS may be deactivated. In this case, the amplifier output signal Vout may again be at the common-mode voltage of strong light (e.g., voltage Vrefs2).

[0054] After A3 is activated (e.g., simultaneously with C2), the control signal RST can be activated via I to reset the floating diffusion region of the pixel to the supply voltage (e.g., Figure 3 The voltage V in AA Then, the control signal RS can be activated by activating G3 to transmit the strong light reset level signal to the column line (e.g., Figure 4 (Column line 86) and transmitted to the amplifier circuit (e.g., Figure 4 The inverting terminal of the amplifier circuit 110 in the middle.

[0055] Therefore, the amplifier circuit can generate the amplifier output signal Vout based on the input high-intensity light reset level signal. Specifically, the amplifier output signal Vout can be reduced from the common-mode voltage Vrefs2 to the difference between the common-mode voltage Vrefs2 and the product of the gain factor G and the absolute high-intensity light image level signal Vshrs2 (from the ground voltage), where the gain factor G is determined by the ratio of the amplifier input capacitance Cs to the amplifier feedback capacitance Cf. The amplifier output can be sampled using active A4.

[0056] Combination Figure 4 and Figure 5 The readout circuit and timing diagram for operating the readout circuit described are merely illustrative. Further details can be provided if needed. Figure 4 and Figure 5 Make any suitable modifications to the readout circuitry and timing diagram configuration. For example, Figure 6 This is a circuit diagram of an exemplary adjustable readout circuit with a separate amplifier circuit.

[0057] like Figure 6As shown, the readout circuit 200 may include components that can be connected to... Figure 4 The readout circuit 100 uses some of the same (or similar) components in a configuration identical to (or similar to) those in the circuit. To avoid unnecessary obfuscation... Figure 6 The implementation scheme omits further description of these similar elements and their similar configurations. As previously (e.g., in conjunction with...) Figure 4 Unless otherwise specified, these similar components may have similar functions, configurations, operating modes, etc.

[0058] Specifically, the readout circuit 200 may include two separate amplifier circuits 110-1 and 110-2. Figure 4 Amplifier circuit 110 amplifies both weak and strong light signals, while amplifier circuit 110-1 can be dedicated to weak light signals, and amplifier circuit 110-2 can be dedicated to strong light signals. Amplifier circuits 110-1 and 110-2 can be coupled to column line 68 via corresponding switches 140 and 142 controlled by control signals S1 and S2, respectively. Amplifier circuits 110-1 and 110-2 can be coupled to sample-and-hold circuit (e.g., sampling switches) via corresponding switches 144 and 146 controlled by control signals SAMPS1 and SAMPS2, respectively. When configured in a certain manner, a corresponding amplifier input signal Vin can be selectively provided to one amplifier line of amplifier circuit 110-1 or 110-2, and a corresponding amplifier output signal (e.g., signal Vouts1 or Vouts2) can be provided to the sample-and-hold circuit.

[0059] Each amplifier circuit in amplifier circuits 110-1 and 110-2 may have a corresponding input capacitor (e.g., capacitor 112-1 with capacitance Cs1 or capacitor 112-2 with capacitance Cs2), a corresponding auto-zeroing switch (e.g., switch 122-1 controlled by signal AZS1 or switch 122-2 controlled by signal AZS2), and a corresponding feedback capacitor (e.g., capacitor 124-1 with capacitance Cf1 or capacitor 124-2 with capacitance Cf2). Additionally, because of the bandwidth limitation for weak light signals (and strong light signals), switch 126 and capacitor 128 may be coupled to amplifier circuit 110-1 instead of amplifier circuit 110-2.

[0060] Each amplifier circuit in amplifier circuits 110-1 and 110-2 can receive a corresponding common-mode voltage at its non-inverting input terminal. In other words, the common-mode voltage Vrefs1 provided by terminal 118 can be provided to amplifier circuit 110-1, and the common-mode voltage Verfs2 provided by terminal 120 can be provided to amplifier circuit 110-2. Therefore, Figure 4The amplifier circuitry in the circuitry can advantageously avoid switching between different common-mode voltages.

[0061] Because separate amplifier circuits are provided, the parameters used to operate or configure the amplifier circuits can be optimized to amplify weak light signals (in the case of amplifier circuit 110-1) or weak light signals (in the case of amplifier circuit 110-2). Specifically, amplifier circuit 110-1 can be optimized for low noise and high bandwidth, while amplifier circuit 110-2 can be optimized for low power and high swing.

[0062] Figure 7 It is used to operate adjustable readout circuits (such as...) Figure 6 The readout circuit 200 is shown in an exemplary timing diagram for reading the image level and reset level signals for weak and strong light conditions. Specifically, the readout circuit can operate in weak light mode during a time period between time t1 and t2, and in strong light mode during a time period between time t2 and t3. Control circuitry (such as control circuits 24 and / or 26) Figure 2 )) can be configured to provide Figure 7 The control signal described herein (e.g., enabling and disabling the control signal).

[0063] like Figure 7 As shown, a timing diagram may include [data / ... Figure 5 Some of the same (or similar) activations and failures implemented in the same (or similar) manner in the timing diagram. To avoid unnecessary ambiguity. Figure 7 The implementation scheme omits a description of these similar elements. As previously described (e.g., in conjunction with...) Figure 5 Unless otherwise specified, these similar components may have similar functions, configurations, operating modes, etc.

[0064] In a dual amplifier circuit configuration (e.g., a dual operational amplifier configuration), the activation of the control signal SAMP for sampling the amplifier output can be combined with one of the control signals SAMPS1 and SAMPS2, depending on which amplifier circuit is providing the output. For example, during the low-light operation mode between time t1 and time t2, amplifier circuit 110-1 ( Figure 6 The control signal SAMPS1, which accesses the output of amplifier circuit 110-1, can be activated by activating K1 and K2, which occur simultaneously with activations A1 and A2, respectively. For example, during the high-light operation mode between time t2 and time t3, amplifier circuit 110-2 ( Figure 6 The control signal SAMPS2 that accesses the output of amplifier circuit 110-2 can be activated by activating L1 and L2, which occur simultaneously with activating A3 and A4, respectively.

[0065] Additionally, the automatic zeroing function for the amplifier's input and output terminals can be implemented separately in a dual amplifier circuit configuration. For example... Figure 7 As shown, when amplifier circuit 110-1 is active, control signal AZS1 can be activated by activation B1, and when amplifier circuit 110-2 is active, control signal AZS2 can be activated by activation B2.

[0066] The functionality and operation of a dual amplifier circuit configuration remain largely unchanged compared to those of a single amplifier circuit configuration. Although a dual amplifier circuit configuration requires additional space for implementation, it offers superior performance due to its more optimized amplifier circuitry and other features.

[0067] Combination Figure 6 and Figure 7 The readout circuit and timing diagram for operating the readout circuit described are merely illustrative. Further details can be provided if needed. Figure 6 and Figure 7 Make any appropriate modifications to the readout circuitry and timing diagram configuration.

[0068] Although the readout circuit (e.g., in) Figure 4 or Figure 6 The amplifier circuit multiplexing schemes are configured to read out and / or amplify strong and weak light signals, but these schemes are merely illustrative. These amplifier circuit multiplexing schemes can generally be applied to any suitable signal type if needed. If needed, these amplifier circuit multiplexing schemes (e.g., using two sets of operating modes or amplifier settings, or using multiple operating settings corresponding to multiple different signals) can be applied to two or more types of signals as described herein (e.g., strong light, medium light, weak light signals, four different types of signals, etc.).

[0069] Various implementation schemes of systems and methods for efficiently performing readout operations have been described.

[0070] For example, an image sensor may include an image sensor pixel array having image pixels. A readout circuit may be coupled to the image pixel via a pixel readout path. The readout circuit may include: an amplifier circuit having a first input terminal coupled to the pixel readout path and a second input terminal configured to receive a first common-mode voltage or a second common-mode voltage; a first transistor coupling the pixel readout path to a reference voltage terminal; a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current; a first switch coupling the second input terminal to a first voltage terminal providing the first common-mode voltage; a second switch coupling the second input terminal to a second voltage terminal providing the second common-mode voltage; and a sampling switch coupling the output terminal of the amplifier circuit to a sampling circuit (e.g., a sampling capacitor). The first input terminal can be coupled to the pixel readout path via an input capacitor, the first input terminal can be coupled to the output terminal along a first path via an auto-zero switch, the first input terminal can be coupled to the output terminal along a second path via a feedback capacitor, and the output terminal of the amplifier circuit can be coupled to an additional capacitor via an additional switch. The first switch and the additional switch can be configured to receive the same control signal.

[0071] If needed, the reference voltage terminal can be configured to provide a ground voltage. If needed, the reference voltage terminal can be configured to provide a voltage greater than the ground voltage.

[0072] For example, an image sensor may include: image pixels arranged in columns and rows; column readout circuitry having amplifier circuitry; and control circuitry. A given column of image pixels may be coupled to the amplifier circuitry via column lines, and the column readout circuitry may be configured to read out a weak light image signal from a given image pixel in the given column during a first operating mode, and to read out a strong light image signal from the given image pixel during a second operating mode. The control circuitry may be configured to control the readout circuitry to provide a first common-mode voltage to the amplifier circuitry during the first operating mode, and to provide a second common-mode voltage greater than the first common-mode voltage to the amplifier circuitry during the second operating mode. The column readout circuitry may include a first transistor coupled to the column lines to a reference voltage terminal, and the control circuitry may be configured to activate the first transistor during the second operating mode and deactivate the first transistor during the first operating mode. The column readout circuit may include a second transistor that couples the column line to a bias transistor, and the control circuit may be configured to activate the second transistor during the first operating mode and deactivate the second transistor during the second operating mode.

[0073] If desired, the amplifier circuit may include a non-inverting input terminal coupled via a first switch to a first voltage terminal providing the first common-mode voltage, and coupled via a second switch to a second voltage terminal providing the second common-mode voltage. The control circuit may be configured to control the readout circuit to provide the first common-mode voltage to the amplifier circuit by activating a first control signal received by the first switch, and is configured to control the readout circuit to provide the second common-mode voltage to the amplifier circuit by activating a second control signal received by the second switch. The column readout circuit may include a third switch coupling the output terminal of the amplifier circuit to a bandwidth capacitor, and the control circuit may be configured to close the third switch during a first operating mode and open the third switch during a second operating mode. The third switch may be configured to receive the first control signal.

[0074] For example, an image sensor may include: an image sensor pixel array having image pixels; and a readout circuit coupled to the image pixels via a pixel readout path. The readout circuit may include: a first amplifier circuit having a first input terminal coupled to the pixel readout path via a first switch and a second input terminal configured to receive a first common-mode voltage; a second amplifier circuit having a first input terminal coupled to the pixel readout path via a second switch and a second input terminal configured to receive a second common-mode voltage; a first transistor coupling the pixel readout path to a reference voltage terminal; a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current; a sampling circuit coupled to the output terminal of the first amplifier circuit via a third switch and to the output terminal of the second amplifier circuit via a fourth switch; and a fifth switch coupling the output terminal of the amplifier circuit to a bandwidth capacitor.

[0075] According to one embodiment, an image sensor may include: an image sensor pixel array having image pixels; and readout circuitry coupled to the image pixels via a pixel readout path. The readout circuitry may include: an amplifier circuit having a first input terminal coupled to the pixel readout path and a second input terminal configured to receive a first common-mode voltage or a second common-mode voltage; a first transistor coupling the pixel readout path to a reference voltage terminal; and a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current.

[0076] According to another embodiment, the readout circuit may include a first switch and a second switch, the first switch coupling the second input terminal to a first voltage terminal providing the first common-mode voltage, and the second switch coupling the second input terminal to a second voltage terminal providing the second common-mode voltage.

[0077] According to another embodiment, the readout circuit may include a sampling switch that couples the output terminal of the amplifier circuit to the sampling circuit.

[0078] According to another embodiment, the first input terminal may be coupled to the pixel readout path via an input capacitor, and the first input terminal may be coupled to the output terminal along the first path via an auto-zero switch.

[0079] According to another embodiment, the first input terminal may be coupled to the output terminal via a feedback capacitor along a second path.

[0080] According to another embodiment, the output terminal of the amplifier circuit can be coupled to an additional capacitor via an additional switch.

[0081] According to another embodiment, the first switch and the additional switch can be configured to receive the same control signal.

[0082] According to another embodiment, the reference voltage terminal can be configured to provide a ground voltage.

[0083] According to another embodiment, the reference voltage terminal can be configured to provide a voltage greater than the ground voltage.

[0084] According to one embodiment, an image sensor may include: image pixels arranged in columns and rows; and column readout circuitry having amplifier circuitry. A given column of image pixels may be coupled to the amplifier circuitry via column lines, and the column readout circuitry may be configured to read out a low-light image signal from a given image pixel in the given column during a first operating mode, and to read out a high-light image signal from the given image pixel during a second operating mode. The image sensor may include control circuitry configured to control the readout circuitry to provide a first common-mode voltage to the amplifier circuitry during the first operating mode, and to provide a second common-mode voltage greater than the first common-mode voltage to the amplifier circuitry during the second operating mode.

[0085] According to another embodiment, the column readout circuit may include a first transistor that couples the column line to a reference voltage terminal, and the control circuit may be configured to activate the first transistor during the second operating mode and deactivate the first transistor during the first operating mode.

[0086] According to another embodiment, the column readout circuit may include a second transistor that couples the column line to a bias transistor, and the control circuit may be configured to activate the second transistor during the first operating mode and deactivate the second transistor during the second operating mode.

[0087] According to another embodiment, the amplifier circuit may include a non-inverting input terminal coupled to a first voltage terminal providing the first common-mode voltage via a first switch, and coupled to a second voltage terminal providing the second common-mode voltage via a second switch.

[0088] According to another embodiment, the control circuit can be configured to control the readout circuit to provide the first common-mode voltage to the amplifier circuit by activating a first control signal received by the first switch, and can be configured to control the readout circuit to provide the second common-mode voltage to the amplifier circuit by activating a second control signal received by the second switch.

[0089] According to another embodiment, the column readout circuit may include a third switch that couples the output terminal of the amplifier circuit to a bandwidth capacitor, and the control circuit may be configured to close the third switch during the first operating mode and open the third switch during the second operating mode.

[0090] According to another implementation, the third switch can be configured to receive the first control signal.

[0091] According to one embodiment, an image sensor may include: an image sensor pixel array having image pixels; and readout circuitry coupled to the image pixels via a pixel readout path. The readout circuitry may include: a first amplifier circuit having a first input terminal coupled to the pixel readout path via a first switch and having a second input terminal configured to receive a first common-mode voltage; and a second amplifier circuit having a first input terminal coupled to the pixel readout path via a second switch and having a second input terminal configured to receive a second common-mode voltage.

[0092] According to another embodiment, the readout circuit may include a first transistor and a second transistor, the first transistor coupling the pixel readout path to a reference voltage terminal, and the second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current.

[0093] According to another embodiment, the readout circuit may include a sampling circuit that is coupled to the output terminal of the first amplifier circuit via a third switch and to the output terminal of the second amplifier circuit via a fourth switch.

[0094] According to another embodiment, the readout circuit may include a fifth switch that couples the output terminal of the amplifier circuit to a bandwidth capacitor.

[0095] The foregoing description is merely an illustrative representation of the principles of the present invention, and those skilled in the art can make various modifications without departing from the scope and essence of the invention. The above embodiments can be implemented individually or in any combination.

Claims

1. An image sensor comprising: an image sensor pixel array having image pixels; and a readout circuit coupled to the image pixels via a pixel readout path, wherein the readout circuit comprises: an amplifier circuit having a first input terminal coupled to the pixel readout path and a second input terminal configured to receive a first common mode voltage during a first operating mode and a second common mode voltage during a second operating mode; a first transistor coupling the pixel readout path to a reference voltage terminal, wherein the first transistor is configured to be activated for the second operating mode and deactivated for the first operating mode; and a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current.

2. The image sensor of claim 1, wherein the readout circuit comprises a first switch coupling the second input terminal to a first voltage terminal supplying the first common mode voltage and a second switch coupling the second input terminal to a second voltage terminal supplying the second common mode voltage.

3. The image sensor of claim 2, wherein the readout circuit comprises a sampling switch coupling an output terminal of the amplifier circuit to a sampling circuit, wherein the first input terminal is coupled to the pixel readout path via an input capacitor, wherein the first input terminal is coupled to the output terminal along a first path via an auto-zero switch, wherein the first input terminal is coupled to the output terminal along a second path via a feedback capacitor, wherein the output terminal of the amplifier circuit is coupled to an additional capacitor via an additional switch, and wherein the first switch and the additional switch are configured to receive a same control signal.

4. The image sensor of claim 1, wherein the reference voltage terminal is configured to supply a ground voltage.

5. The image sensor of claim 1, wherein the reference voltage terminal is configured to provide a voltage greater than a ground voltage.

6. An image sensor comprising: image pixels arranged in columns and rows; a column readout circuit having an amplifier circuit, wherein a given column of image pixels is coupled to the amplifier circuit via a column line, and the column readout circuit is configured to readout a low light image signal from a given image pixel in the given column during a first operating mode and to readout a high light image signal from the given image pixel during a second operating mode; and a control circuit configured to control the column readout circuit to provide a first common mode voltage for the amplifier circuit during the first operating mode and to provide a second common mode voltage for the amplifier circuit during the second operating mode, the second common mode voltage being greater than the first common mode voltage. wherein the column readout circuit includes a first transistor that couples the column line to a reference voltage terminal, and the control circuit is configured to activate the first transistor during the second operating mode and to deactivate the first transistor during the first operating mode.

7. The image sensor of claim 6, wherein the column readout circuit includes a second transistor that couples the column line to a bias transistor, and wherein the control circuit is configured to activate the second transistor during the first operating mode and to deactivate the second transistor during the second operating mode.

8. The image sensor of claim 6, wherein the amplifier circuit includes a non-inverting input terminal that is coupled to a first voltage terminal that supplies the first common mode voltage via a first switch and to a second voltage terminal that supplies the second common mode voltage via a second switch, wherein the control circuit is configured to control the column readout circuit to provide the first common mode voltage to the amplifier circuit by asserting a first control signal received by the first switch, and is configured to control the readout circuit to provide the second common mode voltage to the amplifier circuit by asserting a second control signal received by the second switch, wherein the column readout circuit includes a third switch that couples an output terminal of the amplifier circuit to a bandwidth capacitor, wherein the control circuit is configured to close the third switch during the first operating mode and to open the third switch during the second operating mode, and wherein the third switch is configured to receive the first control signal.

9. An image sensor, comprising: an image sensor pixel array having image pixels; and a readout circuit coupled to the image pixels via a pixel readout path, wherein the readout circuit includes: a first amplifier circuit having a first input terminal coupled to the pixel readout path via a first switch and having a second input terminal configured to receive a first common mode voltage during a first operating mode; and a second amplifier circuit having a first input terminal coupled to the pixel readout path via a second switch and having a second input terminal configured to receive a second common mode voltage greater than the first common mode voltage during a second operating mode; a first transistor that couples the pixel readout path to a reference voltage terminal, wherein the first transistor is configured to be activated for the second operating mode and to be deactivated for the first operating mode.

10. The image sensor of claim 9, wherein the readout circuit includes: a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current, wherein the readout circuit includes a sampling circuit coupled to an output terminal of the first amplifier circuit via a third switch and coupled to an output terminal of the second amplifier circuit via a fourth switch, and wherein the readout circuit includes a fifth switch coupling the output terminals of the amplifier circuits to a bandwidth capacitor.

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