Tagged memory operating at lower Vmin in fault tolerant systems

Abstract

Embodiments of the present disclosure relate to tagged memories operating at a lower Vmin in a fault-tolerant system. A memory management circuit device is arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. The memory management circuit device coupled to the plurality of memory cells marks a first set of the plurality of memory cells as low voltage cells and marks a second set of the plurality of memory cells as high voltage cells. Based on the marking, a power supply provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells.

Description

Technical Field

[0001] The present disclosure relates generally to memory arrays, such as memory arrays used in learning machines (eg, artificial neural networks (ANNs)). Background Art

[0002] It is well known that various computer vision, speech recognition, and signal processing applications benefit from the use of learning machines. As discussed in this disclosure, learning machines may fall under the technical names of machine learning, artificial intelligence, neural networks, probabilistic inference engines, accelerators, etc. Such machines are arranged to rapidly perform hundreds, thousands, and millions of concurrent operations. Conventional learning machines may deliver hundreds of trillions (10 trillion) of data per second. 12 ) floating-point computing capability.

[0003] Known computer vision, speech recognition, and signal processing applications benefit from the use of learning machines, such as deep convolutional neural networks (DCNNs). DCNNs are computer-based tools that process large amounts of data and adaptively "learn" by combining proximal related features within the data, making broad predictions about the data, and refining the predictions based on reliable conclusions and new combinations. DCNNs are arranged in multiple "layers," and make different types of predictions at each layer.

[0004] For example, if a plurality of two-dimensional pictures of faces are provided as input to a DCNN, the DCNN will learn various features of the face (such as edges, curves, angles, points, color contrast, light spots, dark spots, etc.). These one or more features are learned at one or more first layers in the DCNN. Then, in one or more second layers, the DCNN will learn various recognizable features of the face (such as eyes, eyebrows, forehead, hair, nose, mouth, cheeks, etc.); each feature can be distinguished from all features of other features. That is, the DCNN learns to recognize and distinguish eyes from eyebrows or any other facial features. In one or more third and subsequent layers, the DCNN learns the entire face and higher-order features, such as race, gender, age, emotional state, etc. In some cases, the DCNN is even taught to recognize the specific identity of a person. For example, a random image can be identified as a face, and the face can be identified as Person_A, Person_B, or some other identity.

[0005] In other examples, a DCNN may be provided with multiple pictures of animals, and the DCNN may be taught to identify lions, tigers, and bears; a DCNN may be provided with multiple pictures of cars, and the DCNN may be taught to identify and distinguish different types of vehicles; and many other DCNNs may be formed. DCNNs may be used to learn word patterns in sentences, identify music, analyze personal shopping patterns, play video games, create traffic routes, and DCNNs may also be used for many other learning-based tasks. Summary of the invention

[0006] The system can be summarized as including: a plurality of memory cells, which, in operation, store data; a memory management circuit device coupled to the plurality of memory cells, wherein in operation, the memory management circuit device marks a first set of the plurality of memory cells as being associated with a first operating mode and marks a second set of the plurality of memory cells as being associated with a second operating mode; and a power control circuit device coupled to the memory management circuit device and the plurality of memory cells, wherein in operation, the power control circuit device provides a first operating voltage to the first set of memory cells and provides a second operating voltage to the second set of memory cells based on the marking, wherein the first operating voltage is different from the second operating voltage.

[0007] The memory management circuitry may identify a first set of memory cells as memory cells having a statistical probability of error below a first threshold level at a first operating voltage. The first threshold level may correspond to one percent of bit cell sense amplifier marginal failures in a plurality of memory cells. The memory management circuitry may identify a second set of memory cells as memory cells having a statistical probability of error below a second threshold level at a second operating voltage, the second threshold level being lower than the first threshold level. In operation, the memory management circuitry may mark the first set of memory cells by storing a first value in a first memory associated with the first set of memory cells. In operation, the memory management circuitry may mark the memory cells by storing a table of memory cell addresses and corresponding markings.

[0008] The plurality of memory cells may be arranged as a plurality of cell rows intersecting a plurality of cell columns, and wherein the first set of memory cells comprises a subset of columns in the plurality of cell columns. In operation, the memory management circuitry may mark the first set of memory cells by storing a value in each column in the subset of columns. In operation, the memory management circuitry may mark the first set of memory cells by storing a value in a memory associated with the subset of the plurality of columns.

[0009] The plurality of memory cells may be arranged as a plurality of cell rows intersecting a plurality of cell columns, and wherein the first set of memory cells comprises a subset of rows in the plurality of cell rows. The memory management circuitry may mark the first set of memory cells by storing a value in each row in the subset of rows. The memory management circuitry may mark the first set of memory cells by storing a value in a memory associated with the subset of the plurality of rows.

[0010] The power control circuitry may include a low voltage power supply and a high voltage power supply. The system may include a voltage selection circuit, in operation, the voltage selection circuitry selects the low voltage power supply to provide a first operating voltage to the first set of memory cells based on the tag of the first set of memory cells, and selects the high voltage power supply to provide a second operating voltage to the second set of memory cells based on the tag of the second set of memory cells. In operation, the memory management circuitry may selectively implement error correction coding based on the tag value.

[0011] The method can be summarized as including: based on a statistical error rate associated with a first set of multiple memory cells, marking a first set of memory cells as associated with a first operating mode; based on a statistical error rate associated with a second set of multiple memory cells, marking a second set of memory cells as associated with a second operating mode; based on the marking, providing a first operating voltage to the first set of memory cells; and based on the marking, providing a second operating voltage to the second set of memory cells, wherein the second voltage is higher than the first voltage.

[0012] The method may include: providing a first operating voltage to a first set of memory cells for use by at least one first process based on a marking of a first set of a plurality of memory cells; and providing a second operating voltage to a second set of memory cells for use by at least one second process based on a marking of a second set of a plurality of memory cells. The method may include: receiving a request to modify a marking of a first set of memory cells; marking a first portion of the first set of memory cells as being associated with a first operating mode; and marking a second portion of the first set of memory cells as being associated with a second operating mode. The first set of memory cells may include a larger portion of the plurality of memory cells, and the second set of memory cells may include a smaller portion of the plurality of memory cells.

[0013] A non-transitory computer-readable medium having content that causes a processor to perform actions that can be summarized as including: determining a first set of a plurality of memory cells associated with a first operating mode based on a first statistical error rate; storing a first tag associated with the first set of memory cells; determining a second set of a plurality of memory cells associated with a second operating mode based on a second statistical error rate; storing a second tag associated with the second set of memory cells; selecting a first power supply to provide a first operating voltage to the first set of memory cells based on the first tag associated with the first set of memory cells; and selecting a second power supply to provide a second operating voltage to the second set of memory cells based on the second tag associated with the second set of memory cells, wherein the first operating voltage is above a minimum threshold and less than the second operating voltage. Selecting the first power supply to provide the first operating voltage to the first set of memory cells can include reducing the second operating voltage from the second power supply to the first operating voltage.

[0014] The system can be summarized as including: a plurality of memory cells, wherein in operation, the plurality of memory cells store data; a memory management circuit device coupled to the plurality of memory cells, wherein in operation, the memory management circuit device determines an operating voltage for a first set of memory cells in the plurality of memory cells based on an accuracy threshold, wherein the accuracy threshold corresponds to a statistical correlation between the operating voltage and the operating accuracy of the first set of memory cells; and a power control circuit device coupled to the memory management circuit device and the plurality of memory cells, wherein in operation, and based on the determined operating voltage, the power control circuit device provides a determined operating voltage to the first set of memory cells.

[0015] The operational accuracy of the first set of memory cells may be based on a system operational accuracy of an operation performed using at least data stored in the first set of memory cells. The operational accuracy of the first set of memory cells may be based on a statistical accuracy for a plurality of sense amplifier marginal failures in the first set of memory cells. In operation, the memory management circuitry may determine an operating voltage for the first set of memory cells based on the operational accuracy selected by a user. In operation, the power control circuitry may provide a second operating voltage to a second set of memory cells in the plurality of memory cells, wherein the determined operating voltage is different from the second operating voltage. In operation, the memory management circuitry may mark the first set of memory cells as being associated with a determined operating voltage by storing a first value in a first memory associated with the first set of memory cells.

[0016] In operation, the memory management circuit device can mark a first set of multiple memory cells as associated with a first operating mode and mark a second set of multiple memory cells as associated with a second operating mode; and wherein in operation, and based on the marking, the power control circuit device provides a first operating voltage to the first set of memory cells and provides a second operating voltage to the second set of memory cells, wherein the first operating voltage is different from the second operating voltage. The power control circuit device may include a low voltage power supply and a high voltage power supply. The system may include a voltage selection circuit, in operation, the voltage selection circuit selects the low voltage power supply to provide the first operating voltage to the first set of memory cells based on the marking of the first set of memory cells, and selects the high voltage power supply to provide the second operating voltage to the second set of memory cells based on the marking of the second set of memory cells.

[0017] The method can be summarized as including: initializing execution of a process using a plurality of memory cells to store data at a first operating voltage, the first operating voltage corresponding to a first operating accuracy of the process; detecting an event associated with the process; and in response to the detection of the event, modifying execution of the process to correspond to a second operating accuracy that is higher than the first operating accuracy. Execution of the modified process can include providing a second operating voltage that is higher than the first operating voltage to the plurality of memory cells. Execution of the modified process can include execution of a process using a second plurality of memory cells to store data at a second first operating voltage, the second first operating voltage corresponding to a second first operating accuracy of the process. The second operating voltage can be higher than the first operating voltage. Execution of the modified process can include initializing execution of a second process using a plurality of memories to store data at the first operating accuracy.

[0018] The method can be summarized as including: determining a first operating accuracy of a first plurality of memory cells, wherein in operation, the first plurality of memory cells store data; determining a second operating accuracy of a second plurality of memory cells, wherein in operation, the second plurality of memory cells store data, wherein the second operating accuracy is higher than the first operating accuracy; receiving a request to perform a computing operation; determining an operation type of the computing operation to be performed; performing the computing operation using the first plurality of memory cells in response to the first determined operation type; and performing the computing operation using the second plurality of memory cells in response to the second determined operation type. Performing the computing operation using the first plurality of memory cells may include providing a first operating voltage to the first plurality of memory cells, the first operating voltage being lower than a second operating voltage provided to the second plurality of memory cells. Performing the computing operation using the second plurality of memory cells may include providing the first operating voltage to the second plurality of memory cells, the first operating voltage being higher than the second operating voltage provided to the first plurality of memory cells.

[0019] The method may also include: wherein receiving a request to perform a computing operation includes: receiving a first request to perform a first computing operation of a first determined operating type; performing the first computing operation at a first operating voltage using a first plurality of memory cells; based on a result of the performance of the first computing operation, receiving a second request to perform a second computing operation of a second determined operating type; and performing the second computing operation at a second operating voltage higher than the first operating voltage using a second plurality of memory cells. Determining the operating type of the computing operation to be performed may include: identifying an acceptable operating accuracy of the result of performing the computing operation; in response to the acceptable operating accuracy being below a threshold, selecting the first determined operating type to use the first plurality of memory cells at the first operating voltage; and in response to the acceptable operating accuracy being above a threshold, selecting the second determined operating type to use the second plurality of memory cells at a second operating voltage higher than the first operating voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Non-limiting and non-exhaustive embodiments are described with reference to the following drawings, wherein the same reference numerals denote the same parts throughout the various figures unless otherwise indicated. The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes of the various elements are selected, enlarged, and positioned to improve the readability of the drawings. For ease of identification in the drawings, the specific shapes of the drawn elements have been selected. In addition, for ease of illustration, some elements known to those skilled in the art are not shown in the drawings. In the following, one or more embodiments are described with reference to the drawings, wherein:

[0021] Figure 1 is a functional block diagram of an embodiment of an electronic device or system having a processing core and a memory according to an embodiment;

[0022] Figure 2A-2B illustrates a use case context diagram of a memory array with labeled memory cells for low voltage memory cells and high voltage memory cells;

[0023] Figure 3A-3D illustrates additional use case context diagrams of memory arrays with labeled memory cells for low voltage memory cells and high voltage memory cells;

[0024] Figure 4 illustrates a logic flow diagram generally showing one embodiment of a process for marking a first set of memory cells as a low voltage and marking a second set of memory cells as a high voltage;

[0025] Figure 5illustrates a logic flow diagram generally showing another embodiment of a process for marking a memory cell as low voltage or high voltage based on a quality test of a memory array; and

[0026] Figure 6 A logic flow diagram is illustrated that generally shows one embodiment of a process for employing individual memory cells at different voltage levels based on the operating accuracy of the memory cells. DETAILED DESCRIPTION

[0027] The following description and attached Figure 1 Certain specific details are described together in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the disclosed embodiments can be practiced in various combinations without one or more of these specific details, or with other methods, components, devices, materials, etc. In other examples, well-known structures or components associated with the environment of the present disclosure, including but not limited to interfaces, power supplies, physical component layouts, etc., not shown or described in the computer memory environment, are used to avoid unnecessary confusion in the description of the embodiments. Additionally, the various embodiments can be methods, systems, or devices.

[0028] Throughout the specification, claims and drawings, unless the context otherwise indicates, the following terms have the meanings associated with this document. The term "herein" refers to the specification, claims and drawings associated with this application. The phrases "in one embodiment", "in another embodiment", "in various embodiments", "in some embodiments", "in other embodiments" and other variations thereof refer to one or more features, structures, functions, limitations or characteristics of the present disclosure, and are not limited to the same or different embodiments unless the context otherwise indicates. As used herein, the term "or" is an inclusive "or" operator and is equivalent to the phrases "A or B, or both", "A or B or C, or any combination thereof", and lists with other elements will be treated equally. Unless the context otherwise indicates, the term "based on" is not exclusive and allows for other features, functions, aspects or limitations based on undescribed ones. In addition, throughout the specification, the meanings of "a", "an" and "said" include singular and plural references.

[0029] The calculations performed by DCNN or other neural networks typically include repetitive calculations on large amounts of data. For example, many learning machines compare known information or kernels with unknown data or feature vectors, such as comparing known pixel groups with parts of an image. A common type of comparison is the dot product between the kernel and the feature vector. However, the size of the kernel, the size of the feature, and the depth tend to vary across different layers of the neural network. In some instances, dedicated computing units can be used to enable these operations to be performed on a varying data set.

[0030] Furthermore, memory arrays in integrated circuits may contain manufacturing defects that may render one or more cells of the memory array statistically inaccurate in storing data. Additionally, memory cells of the memory array may fail over time. Therefore, the memory array may contain spare cells in redundant rows, columns, or both, which may be used to replace failed rows or columns in the memory array.

[0031] Integrated circuits may be tested as part of a manufacturing process, or periodically after a manufacturing process, to identify faulty rows and columns of a memory array in the integrated circuit. For example, circuit devices and test routines such as probe testing, built-in self-test (BIST), etc. may be employed. Faulty rows, columns, or both may be identified using thresholds (e.g., the number of faulty cells in a row or column exceeds a threshold number), statistical analysis (e.g., the probability that an error correction technique (such as error correction coding) will fail to correct errors in a row or column that exceeds a threshold probability), etc., and various combinations thereof.

[0032] For example, various data patterns can be loaded into and read from the memory array, and the data read from the memory array can be analyzed to identify incorrect bit values. Information related to the occurrence of incorrect bit values ​​can be used to identify (based on statistical analysis) faulty rows and columns in the memory array.

[0033] If a row or column is identified as unusable, the memory array can be repaired by replacing the failed row or column with one of the spare rows or columns. Information identifying the failed rows or columns is stored so that those rows and columns are not used to store data. When the number of failed rows or columns is too high (e.g., exceeds a threshold number, or a statistical probability of chip failure), the integrated circuit including the memory array is determined to be unsuitable because it has too many unrepairable faults, and the integrated circuit is either discarded or may be completely reused (e.g., an integrated circuit designed to have a 6MB memory array can be reused as a 4MB memory array).

[0034] Figure 11 is a functional block diagram of an embodiment of an electronic device or system 100, the type of which may be applied to the embodiments to be described. The system 100 includes one or more processing cores or circuits 102. For example, the processing core 102 may include: one or more processors, state machines, microprocessors, programmable logic circuits, discrete circuit devices, logic gates, registers, etc., and various combinations thereof. The processing core may control the overall operation of the system 100, the application programs executed by the system 100, etc.

[0035] The system 100 includes one or more memories (such as one or more volatile and / or non-volatile memories) that can store, for example, all or part of instructions and data related to the control of the system 100, applications and operations executed by the system 100, etc. As shown, the system 100 includes one or more cache memories 104, one or more primary memories 106, and one or more secondary memories 108. One or more of the memories 104, 106, 108 include a memory array (see, for example, respectively). Figure 2A-2B The memory array 202 and the Figures 3A-3D ), where in operation, the memory arrays are shared by one or more processes executed by system 100.

[0036] The system 100 may include one or more sensors 120 (e.g., image sensors, audio sensors, accelerometers, pressure sensors, temperature sensors, etc.), one or more interfaces 130 (e.g., wireless communication interfaces, wired communication interfaces, etc.), one or more BIST circuits 140 and other circuits 150 (which may include antennas, power supplies, etc.), and a main bus system 170. The main bus system 170 may include one or more data, address, power, and / or control buses coupled to various components of the system 100. The system 100 may also include additional bus systems, such as: a bus system 162 that communicatively couples the cache memory 104 with the processing core 102; a bus system 164 that communicatively couples the cache memory 104 with the primary memory 106; a bus system 166 that communicatively couples the primary memory 106 and the processing core 102; and a bus system 168 that communicatively couples the primary memory 106 and the secondary memory 108.

[0037] Primary storage or memory 106 is typically working memory for system 100 (e.g., one or more memories on which processing core 102 operates), and may be typically volatile memory of limited size that stores code and data related to processes performed by system 100. For convenience, references herein to data stored in memory may also refer to code stored in memory. Secondary storage 108 may be typically non-volatile memory that stores instructions and data that may be retrieved and stored in main memory 106 when needed by system 100. Cache memory 104 may be a relatively fast memory compared to secondary storage 108, and may typically have a limited size, which may be larger than the size of primary storage 106.

[0038] Cache memory 104 temporarily stores code and data for later use by system 100. Instead of retrieving the required code or data from secondary memory 108 for storage in primary memory 106, system 100 may first check cache memory 104 to see if the data or code is already stored in cache memory 104. Cache memory 104 may significantly improve the performance of systems such as system 100 by reducing the time and other resources required to retrieve data and code used by system 100. When code and data used by system 100 are retrieved (e.g., from secondary memory 108), or when data or code is written (e.g., to primary memory 106 or to secondary memory 108), a copy of the data or code may be stored in cache memory 104 for later use by system 100. Various cache management routines may be employed to control the data stored in cache memory or memory 104.

[0039] System 100 also includes memory voltage management circuitry 160, wherein in operation, memory voltage management circuitry 160 employs one or more memory management routines to employ a first portion of memory 104, 106, or 108 in a low voltage mode and to employ a second portion of memory 104, 106, or 108 in a high voltage mode. In various embodiments, memory voltage management circuitry 160 marks or otherwise stores one or more indicators indicating which memory cells are operating in the low voltage mode and which memory cells are operating in the high voltage mode. Memory voltage management circuitry 160 may be alone or in combination with other processing circuitry (e.g., by processing core 102) to perform the routines and functions described herein, including respectively in Figure 4 and Figure 5The memory voltage management circuit device 160 can be one or more processors, state machines, microprocessors, programmable logic circuits, discrete circuit devices, logic gates, registers, etc. and various combinations thereof.

[0040] The use of the phrase "low voltage" or operating in a "low voltage mode" refers to a voltage provided to a memory cell that is less than a voltage provided to a memory cell provided with a "high voltage" or operating in a "high voltage mode". For example, a memory cell operating in a low voltage mode may be a memory cell associated with an execution process that is relatively more tolerant to an identified statistical number of errors caused by a bit cell sense amplifier marginal failure. Conversely, a memory cell operating in a high voltage mode may be a memory cell associated with a process that is relatively less tolerant to a bit cell sense amplifier marginal failure. The low voltage operating mode may be defined by a first selected or determined number of tolerances, and the high voltage operating mode may be defined by a second selected or determined number of tolerances. For example, for a memory cell operating in a low voltage mode, the voltage is maintained at a lower first level, which statistically results in errors of up to 1% in the value stored in or read from the low voltage memory cell. In contrast, for memory cells operating in the high voltage operating mode, the voltage is maintained at a higher second level, which statistically results in an error in the value stored in or read from the high voltage memory cell being less than 0.01%. In some embodiments, the low voltage mode may also be referred to as a "low power mode", and the high voltage mode may also be referred to as a "high power mode".

[0041] In various embodiments, the low voltage memory cells may include those memory cells that store kernel data, intermediate partial sums, or feature data associated with the learning or application of the artificial neural network system. Typically, the data stored by the low voltage memory cells may be data from which errors or contour data have been removed. For example, during the learning process, some blurry pixels or dead pixels in one image will be filtered out along with other images during the learning process. Therefore, errors in the memory cells due to low voltage will be similarly processed and removed. In contrast, the high voltage memory cells may include those memory cells that store configuration or layer sequence data for the learning or application of the artificial neural network system. For example, the data stored by the high voltage memory cells may be: data that may be static, data used as basic comparison information, or information for configuring one or more processing layers, information that is not further processed for error removal, host system processing, and the like.

[0042] Embodiments of system 100 may have Figure 1 More components than those shown in the figure may be present. Figure 1The components shown in the figure may be fewer than the components shown in the figure, the functions of the components may be combined in various ways, the functions of the components may be separated in various ways, etc., and various combinations thereof. For example, in some embodiments, in addition to or in place of the secondary memory 108 shown, the secondary memory may include a memory external to the system 100; in some embodiments, multiple layers of cache memory may be used; and so on.

[0043] Figure 2A-2B A use case background diagram of a memory array with labeled memory cells for low voltage memory cells and high voltage memory cells is illustrated. Figure 2A The system 200A in FIG. 1 includes a memory array 202, a voltage selection circuit 208, and a tag module 210. The system 200 also includes a low voltage power supply 204 and a high voltage power supply 206. The low voltage power supply 204 is configured to provide power to the memory cells of the memory array 202 at a first low voltage in operation, and the high voltage power supply 206 is configured to provide power to the memory cells of the memory array 202 at a high voltage portion in operation. The power supplied by the low voltage power supply is at a lower voltage than the power supplied by the high voltage power supply.

[0044] The memory array 202 includes a plurality of cells configured in a column-row arrangement, with a plurality of cell rows intersecting a plurality of cell columns. Each cell can be addressed via a particular column and a particular row. The number of cells in the memory array 202 can vary depending on the implementation, utilization, and system. The functions and components of each memory cell and the details for accessing a particular memory cell are known to those skilled in the art and are not described herein for the sake of brevity.

[0045] The marking module 210 stores data that identifies which memory cells in the memory array 202 are marked to operate in a low voltage mode and which memory cells in the memory array 202 are marked to operate in a high voltage mode. In some embodiments, the marking module 210 can be a memory or a database, or can access a memory or a database that stores such marking information. In the illustrated embodiment, the marking module 210 can store a mapping between a memory address 212 and a tag 214 of a memory cell in the memory array 202. In this example, the tag 214 can include a value of "yes", "yes" indicating that the corresponding mapped address 212 is in a low voltage mode; or can include a value of "no", "no" indicating that the corresponding mapped address 212 is in a high voltage mode. The "yes" and "no" values ​​can be represented in the marking module 210 by storing "1" and "0" or other such information. Although the marking module 210 shows a mapping between a single memory address 212 and a corresponding tag 214, the embodiment is not limited thereto. For example, a memory address can be such as in Figure 2B A range or group of memory addresses illustrated in FIG.

[0046] The voltage selection circuit 208 is configured to select the appropriate voltage to be delivered to the memory cells in the memory array 202 based on the mapping stored by the marking module 210 in operation. The voltage selection circuit 208 selects the low voltage power supply 204 to provide power to those memory cells marked as low voltage, and selects the high voltage power supply 206 to provide power to those memory cells marked as high voltage. In some embodiments, the voltage selection circuit 208 can be configured to select the appropriate voltage to be delivered to the memory cells in the memory array 202 based on the mapping stored by the marking module 210. Figure 1 Components or example embodiments of the memory voltage management circuit device 160 in are adopted.

[0047] exist Figure 2B The system 200B in is similar to that in Figure 2A 200A in which a memory array 202 and a tag module 222 are included. However, in this example, the tag module 222 stores data that identifies which groups of memory cells in the memory array 202 are marked as operating in a low voltage mode and which groups of memory cells in the memory array 202 are marked as operating in a high voltage mode. In the illustrated embodiment, the tag module 222 stores a mapping between memory address ranges 224 and tags 226 of memory cells in the memory array 202. The tags 226 may include a value of "yes", which indicates that the corresponding mapped address range 224 is in the low voltage mode; or may include a value of "no", which indicates that the corresponding mapped address range 224 is in the high voltage mode. In this example, each memory cell having an address within a particular memory address range 224 inherits the corresponding tag 226 value for that range 224.

[0048] Similar to Figure 2A The marking module 212 in the memory may be a memory or a database, or may access a memory or a database storing such marking information. Similarly, the marking values ​​"yes" and "no" may be represented in the marking module 222 by storing "1" and "0" or other such information. Although the marking module 222 illustrates a mapping between multiple memory addresses or regions 224 and corresponding markings 226, the embodiment is not limited thereto. For example, the memory address may be a single memory address, such as in Figure 2A As shown in the figure.

[0049] As in the above Figure 2A As described in , a voltage selection circuit can be used to select between a low voltage power supply and a high voltage power supply. Figure 2B The system 200B in the embodiment alternatively includes a high voltage power supply 206 and a voltage reduction circuit 220. The voltage reduction circuit 220 is configured to, in operation, identify which memory cells in the memory array 202 will operate in the low voltage mode and which memory cells in the memory array 202 will operate in the high voltage mode based on a mapping stored by a marking module 222. The voltage reduction circuit 220 provides the high voltage supplied by the high voltage power supply 206 to the high voltage mode memory cells, and reduces the voltage supplied by the high voltage power supply 206 to power the low power memory cells. In some embodiments, the voltage reduction circuit 220 can utilize a circuit device to gradually reduce the high voltage to a determined low voltage value. In some embodiments, the voltage reduction circuit 220 can be implemented by a circuit device in the embodiment. Figure 1 Components or example embodiments of the memory voltage management circuit device 160 in are adopted.

[0050] Figure 3A-3D Additional use case context diagrams of memory arrays with labeled memory cells are illustrated for low voltage memory cells and high voltage memory cells.

[0051] exist Figure 3AThe example 300A in includes a memory 330. The memory 330 is configured in a plurality of rows 332 and a plurality of columns 336a-336h (collectively referred to as 336). In this example, the memory 330 also includes a row 334 for storing tag values ​​for the corresponding columns 336a-336h. For example, columns 336a-336f have stored "low" values ​​in the corresponding rows 334 to indicate that the memory cells in columns 336a-336f are operating in a low voltage mode, and columns 336g-336h have stored "high" values ​​in the corresponding rows 334 to indicate that the memory cells in columns 336g-336h are operating in a high voltage mode. In some embodiments, the memory 330 may include additional circuit devices that provide similar circuitry to that in the example above based on the values ​​stored in the rows 334. Figure 2A The voltage selection circuit 208 in or Figure 2B The selection function or reduction function of the voltage reduction circuit 220 in FIG.

[0052] exist Figure 3B The example 300B in is similar to that in Figure 3A Example 300A in , but wherein multiple columns are marked together. Example 300B includes memory 340. Memory 340 is configured to be in multiple rows 342 and multiple columns 346a-346j (collectively referred to as 346). In this example, memory 340 also includes tag circuit devices 348a-348c (collectively referred to as 348) for storing tag values ​​for one or more columns 346a-346j. For example, tag circuit device 348a has stored a "low" value therein to indicate that the memory cells in columns 346a-346d operate in low voltage mode, tag circuit device 348b has stored a "low" value therein to indicate that the memory cells in columns 346e-346h operate in low voltage mode, and tag circuit device 348c has stored a "high" value therein to indicate that the memory cells in columns 346i-346j operate in high voltage mode. In some embodiments, memory 340 may include additional circuitry that provides similar functionality to that in row 334 based on the values ​​stored in row 334. Figure 2A The voltage selection circuit 208 in or Figure 2B The selection function or reduction function of the voltage reduction circuit 220 in FIG.

[0053] exist Figure 3C The example 300C in is similar to that in Figure 3A Example 300A in FIG. 1 , but in which the rows of memory cells are labeled. Figure 3CExample 300C in includes a memory 350. The memory 350 is configured in a plurality of rows 352a-352h (collectively referred to as 352) and a plurality of columns 356a-356h (collectively referred to as 356). In this example, the memory 350 also includes a column 358, which is used to store a tag value for the corresponding row 352a-352h. For example, rows 352a-352d have stored a "low" value in the corresponding column 358 to indicate that the memory cells in rows 352a-352d are operating in a low voltage mode, and rows 352e-352h have stored a "high" value in the corresponding column 358 to indicate that the memory cells in rows 352e-352h are operating in a high voltage mode. In some embodiments, the memory 350 may include additional circuit devices that provide similar circuitry to that in row 334 based on the values ​​stored in row 334. Figure 2A The voltage selection circuit 208 in or Figure 2B The selection function or reduction function of the voltage reduction circuit 220 in FIG.

[0054] exist Figure 3D The example 300D in is similar to the Figure 3C Example 300C in , but wherein multiple rows are marked together. Example 300D includes a memory 360. The memory 360 is configured in multiple rows 362a-362h (collectively referred to as 362) and multiple columns 366a-366h (collectively referred to as 366). In this example, the memory 360 also includes marking circuit devices 368a-368b (collectively referred to as 368) for storing marking values ​​for one or more rows 362a-362h. For example, the marking circuit device 368a has stored therein a "low" value to indicate that the memory cells in rows 362a-362d are operating in a low voltage mode, and the marking circuit device 368b has stored therein a "high" value to indicate that the memory cells in rows 362e-362h are operating in a high voltage mode. In some embodiments, the memory 360 may include additional circuit devices that provide similar circuitry to that in row 334 based on the values ​​stored in row 334. Figure 2A The voltage selection circuit 208 in or Figure 2B The selection function or reduction function of the voltage reduction circuit 220 in FIG.

[0055] although Figure 2A-2B and Figure 3A-3D The memory tags are described at the memory or circuit level, but the embodiments are not limited thereto. In other embodiments, software can be used to tag and manage the tags of memory cells based on the addresses of the memory cells using similar functions as described herein.

[0056] In addition, although the above examples discuss dynamically marking a specific memory cell or memory cell group as a low voltage or a high voltage, the embodiments are not limited thereto. For example, in some embodiments, a system may include two memory arrays, one of which operates at a low voltage and the other operates at a high voltage. In this type of system, there is no marking—instead, a static voltage is provided to the memory array so that one memory array operates at a voltage lower than the voltage of the other memory array. Both of these memory arrays can be parts of the same memory array, or they can be physically different. The low voltage memory array can have a specified low voltage power supply, which is separated from the high voltage power supply that provides power to the high voltage memory array. Alternatively, the low voltage memory array may include or be associated with an additional circuit device that gradually reduces the voltage, which gradually reduces or reduces the voltage provided by the high voltage power supply. In various embodiments, the memory array can operate under the same operating parameters, but is provided with different voltages. In this way, the low voltage memory cell can experience more errors than the high voltage memory cell. Because the data stored by the low voltage memory cell tolerates more errors, less voltage can be used to store data, thereby saving power by using a lower voltage.

[0057] In the context of embedded ANN systems, a large amount of on-chip memory of the ANN system may be required to store relatively fault-tolerant kernel data, intermediate sums, and feature data, and a smaller portion may be required to store configuration / layer sequence data with less fault tolerance. Similarly, the fault tolerance of the host system process may be lower. Therefore, marking the memory based on the fault tolerance of the memory at various operating voltage levels can promote a significant increase in the yield of the chip manufacturing process. In addition, the amount of memory required for redundancy can be reduced, because rows and columns that may have been conventionally designated as unavailable and replaced by redundant memory can be designated to operate at different voltage levels in different situations, thereby reducing the demand for redundant memory. The minimum operating voltage for an important part of the memory can also be reduced, thereby helping to reduce power usage, such as in mobile devices.

[0058] Now refer to Figure 4-Figure 6 To describe the operation of certain aspects of the present disclosure. As described herein, in various embodiments, respectively, Figure 4-Figure 6 The described processes 400, 500, and 600 may be implemented by one or more components or circuits associated with a memory computing element.

[0059] Figure 4A logic flow diagram is illustrated that generally illustrates one embodiment of a process 400 for marking a first set of memory cells as operating in a low voltage mode and marking a second set of memory cells as operating in a high voltage. Process 400 begins at block 402 after a start block, where a first set of memory cells is identified for use with one or more processes that are relatively more tolerant to errors. Relatively more tolerant processes are those that can operate within a defined threshold of reliability or accuracy when the number or percentage of incorrect memory bit values ​​is above a threshold.

[0060] Process 400 proceeds to block 404 where a second set of memory cells is identified for use with one or more processes that are relatively less tolerant to errors. Relatively less tolerant processes are those that operate within a defined threshold of reliability or accuracy when the number or percentage of incorrect stored bit values ​​is below a threshold.

[0061] As mentioned herein, a memory cell may be identified as being to utilize a more fault tolerant process, or a less fault tolerant process, based on the type of data to be stored in the memory cell.

[0062] In some embodiments, the tolerance flag is set by a user or administrator, or can be dynamically determined based on the current data processing being performed by the system. For example, during processing of the first layer in the artificial neural network, the administrator can set, or the system can determine, the amount of data that will be used to utilize a more tolerant process to be 60% of the total available memory. However, for the second layer in the artificial neural network, the administrator can set, or the system can determine, the amount of data that will be used to utilize a more tolerant process to be 90% of the total available memory.

[0063] Process 400 continues at block 406 where the first set of memory cells are marked as using a lower voltage. Next, process 400 proceeds to block 408 where the second set of memory cells are marked as using a higher voltage. In various embodiments, a database or a specific memory cell is updated based on the tolerance identification to store the corresponding marking value.

[0064] Next, process 400 continues at block 410 where a lower voltage is provided to a first set of memory cells. Process 400 proceeds to block 412 where a high voltage is provided to a second set of memory cells. In various embodiments, circuitry may be utilized to select or reduce power to a memory cell based on a tag of the cell. For example, a high voltage power supply may be selected to provide a high voltage to a second set of memory cells. Conversely, a low voltage power supply (or a reduced voltage from a high voltage power supply) may be selected to provide a low voltage to a first set of memory cells.

[0065] Process 400 continues at decision block 414 where a determination is made as to whether to dynamically reconfigure the memory cell flags. In various embodiments, this determination may be set or selected by an administrator, a user, or based on the type of process being executed by the system. For example, if an artificial neural network utilizes seven processing layers, each individual layer may tolerate a different number of errors. The memory cell flags may be dynamically reconfigured between different layers of processing.

[0066] As another example, during a first operation, a user may indicate that the artificial neural network is to operate at a first level of effectiveness (e.g., correctly identifying faces 40% of the time, or indicating that there is a 40% chance that an image contains a face). During this first operation, a greater amount of memory may be utilized in a low voltage mode. However, if during a second operation, the user indicates that the artificial neural network is to operate at a second, higher level of effectiveness (e.g., correctly identifying faces 80% of the time, or indicating that there is an 80% chance that an image contains a face), the flags may be reconfigured so that data is processed using a collection of memories in a high voltage mode. In this case, the system may tolerate more errors during the first operation than during the second operation.

[0067] One example implementation in which this functionality may be used is when first analyzing an image to determine the likelihood that the image contains a target feature (e.g., a face). For those images whose likelihood is above a selected threshold, those images may be reanalyzed to more accurately determine whether those images do contain the target feature. Thus, the majority of the memory may be used to analyze the images first in a low voltage mode, and the memory may be used in a high voltage mode to reprocess the images that meet the initial threshold.

[0068] In another example implementation, the voltage may be adjusted from a high voltage mode to a low voltage mode to reduce power consumption, which trades off reduced artificial neural network accuracy for extended battery life. In some embodiments, a built-in self-test may be run to determine how much the voltage may be reduced before the number of errors exceeds a threshold amount, or the neural network accuracy drops below a threshold amount.

[0069] If the memory cell is to be reconfigured, process 400 loops to block 402; otherwise process 400 terminates or otherwise returns to the calling process to perform other actions.

[0070] Figure 5 A logic flow diagram is illustrated that generally illustrates another embodiment of a process 500 for marking memory cells as operating at a low voltage or a high voltage based on a quality test of the memory array. After a start block, the process 500 begins at block 502 where a memory array is tested. During or after the manufacturing stage, various types of testing methods may be employed to test the memory, such as by testing a wafer containing multiple memory arrays to determine the number of errors caused by each memory array.

[0071] Process 500 proceeds to block 504 where the test results are analyzed. In various embodiments, the test results are analyzed to determine the number of errors generated by the entire memory array, or a portion of the memory array. The number of errors may be compared to one or more thresholds to classify the memory array. Statistical analysis may be performed. Testing may be performed at various operating voltage levels.

[0072] For example, if a memory array reaches a first threshold number of errors, the memory array may be classified as Grade_A. If a memory array does not reach the first threshold number of errors, but does reach a second threshold number of errors, the memory array may be classified as Grade_B. Any memory array that does not reach the second threshold may be classified as bad and discarded. A Grade_A memory array may be a memory array that may be used in a system or process that cannot tolerate errors, similar to data processed by high voltage memory cells. A Grade_B memory array may be a memory array that may be used in a system or process that can tolerate some errors, similar to data processed by low voltage memory cells.

[0073] The process 500 continues at decision block 506 where it is determined whether the memory array is satisfactory for a particular application. For example, if the application of the memory array is to store configuration data, then using the example above, the memory array must be classified as Grade_A. However, if the application of the memory array is to store kernel data, then the memory array may be classified as Grade_A or Grade_B. If the memory array is not satisfactory for the application, then the memory array may be discarded and the process 500 ends; otherwise, the process 500 flows to block 508.

[0074] At block 508, the low voltage values ​​of the memory array are qualified. In various embodiments, the memory array is qualified for a single low voltage or a set of low voltages Vmin using known techniques. For example, based on the analysis at 504, a voltage sufficient to provide a desired level of statistical accuracy may be selected. Voltage scaling or frequency scaling may also be performed.

[0075] Next, process 500 proceeds to block 510 where an operating mode of the memory array is determined. The operating mode may be based on the desired accuracy of the processing performed using the data stored in the memory array. For example, the first operating mode may be a low power state or a qualified state, and the second operating mode may be a high power state or a verified state. In this example, the neural network may process the image using most of the memory in a low voltage mode (first operating mode) to determine if there are events of interest in the image, such as the presence of a face. If the processing indicates that the image may have events of interest, the neural network may use the memory in a high voltage mode (second operating mode) to process those particular images. In this manner, the second processing confirms or verifies whether the image includes an event of interest.

[0076] Next, process 500 continues at block 512 where the memory is marked as low voltage or high voltage based on the operating mode. In some embodiments, the entire memory array can be marked as low voltage or high voltage based on the operating mode. In other embodiments, a first portion of the memory array is marked as low voltage and a second portion of the memory array is marked as high voltage. The marking can be performed as discussed herein.

[0077] Process 500 proceeds to block 514 where the memory is powered using the marked voltage during operation. In various embodiments, the low voltage supplied to the low voltage memory cell may be a voltage below the qualified low voltage value, but within a selected amount or threshold. The high voltage supplied to the high voltage memory cell is a voltage at or above the qualified low voltage value.

[0078] Process 500 continues to block 516 where it is determined whether the operating mode of the memory has been changed or updated. The operating mode may change from processing one set of data to processing another set of data (e.g., from one image to another), or to processing data in a different manner (e.g., from one neural network processing layer to another neural network processing layer). If the operating mode has been updated or changed, process 500 loops to block 512 to re-label the memory based on the updated operating mode; otherwise, process 500 terminates.

[0079] Although not illustrated, the qualified memory low voltage value may be requalified after a selected time period or a selected amount of utilization. If the memory low voltage value is to be requalified, the process 500 loops to block 508. In addition, as described above, individual memory arrays or portions of memory arrays may not be marked. Instead, depending on the qualified memory low voltage value determined at block 508 or the test results determined at block 504, a particular memory array may be used as a low voltage memory or as a high voltage memory. Again, in this type of system, there is no marking—rather, the voltage provided to the memory array is static, so that one memory array operates at a voltage lower than the operating voltage of another memory array. In another example, the memory array may be retested periodically or in response to a triggering event (e.g., a restart of the system). In this case, the method 500 may loop to block 502.

[0080] Embodiments of the foregoing processes and methods may be included in Figure 4-Figure 5 Additional actions not shown in the Figure 4-Figure 5 All actions shown in can be performed in various orders. Figure 4-Figure 5 The actions shown in , can be combined, and can be modified in various aspects. For example, in Figure 4 Process 400 in may omit act 414 so that memory marking is performed only once, process 400 may combine acts 402 and 404, process 400 may combine acts 406 and 408, process 400 may perform acts 410 and 412 in parallel, and so on.

[0081] In some embodiments, error correction coding (ECC) may be selectively implemented based on the tag value of the memory cell or region. For example, when the first region is used to store data for a first process, the first memory region that is marked as being associated with a more fault-tolerant process may be operated at a low voltage level with ECC coding, and when the second region is used to store data for the first process, the second memory region that is marked as being associated with a less fault-tolerant process may be operated at a high voltage level without ECC coding.

[0082] Although the embodiments described above are about the operation of the memory cell in the low voltage mode or in the high voltage mode, the embodiments are not limited thereto. Rather, in some embodiments, some memory cells or all memory cells can be operated in a dynamic voltage mode so that their operating voltage can be selected or modified based on a target or a selected accuracy threshold. The accuracy threshold corresponds to the statistical correlation between the operating voltage of the memory and the operating accuracy of the memory. In various embodiments, the operation of the memory at a lower operating voltage is statistically related to the lower operating accuracy of the memory (e.g., a higher number of faults and errors). On the contrary, the operation of the memory at a higher operating voltage is statistically related to the higher operating accuracy of the memory (e.g., a lower number of faults and errors). In this way, the accuracy of the system can be a trade-off for reducing the operating voltage of the memory (e.g., to reduce power consumption).

[0083] In some embodiments, the operational accuracy may be based on the system operational accuracy of operations performed using data stored in the memory. In at least one embodiment, the system operational accuracy may indicate a confidence value or probability threshold when performing certain operations in the artificial neural network. For example, an administrator may set, or the system may determine, that the artificial neural network unambiguously identifies an object with 70% confidence (e.g., there is at least a 70% probability that the image contains a face). In other embodiments, the operational accuracy may be based on a statistical accuracy for multiple sense amplifier marginal failures in a memory cell. For example, an administrator may set, or the system may determine, that the percentage (or number) of hard failures / errors of a memory bit cell or sense amplifier is less than one percent.

[0084] In various embodiments, in response to a user selection, in response to system operation (e.g., when entering a low power mode), or otherwise during operation, or some combination thereof, the dynamic voltage mode can be modified to change the operating voltage of the memory cells between different types of operations (e.g., when processing different layers in an artificial neural network). In some embodiments, a first set of memory cells can operate in a dynamic voltage mode, and a second set of memory cells can operate in a second voltage mode independent of the dynamic voltage mode.

[0085] Similar to the above, memory cells utilizing dynamic voltage modes may be marked. For example, a memory management circuit device (e.g., Figure 1The memory voltage management circuit device 160 in the memory cell can mark the first set of memory cells to be operated in the dynamic voltage mode with the associated operating voltage by storing a first value in a first memory associated with the first set of memory cells. In other embodiments, the memory management circuit device can mark the first set of multiple memory cells as being associated with a first operating mode (e.g., a dynamic operating mode) and mark the second set of multiple memory cells as being associated with a second operating mode. Based on the marking, the power control circuit device provides the first operating voltage to the first set of memory cells and provides the second operating voltage to the second set of memory cells. In some embodiments, the voltage selection circuit can select a low voltage power supply to provide the first operating voltage to the first set of memory cells based on the marking to the first set of memory cells, and select a high voltage power supply to provide the second operating voltage to the second set of memory cells based on the marking to the second set of memory cells.

[0086] Figure 6 A logic flow diagram is illustrated that generally illustrates one embodiment of a process for employing individual memory cells at different voltage levels based on the operational accuracy of the memory cells. After a start block, the process 600 begins at block 602 where a first operational accuracy of a first plurality of memory cells is determined. In some embodiments, the determination is made during a quality test of the memory. In other embodiments, the first plurality of memory cells may be marked with the first operational accuracy similar to that described above for marking memory cells for a lower operational voltage.

[0087] Process 600 proceeds to block 604 where a second operational accuracy of a second plurality of memory cells is determined. In various embodiments, block 604 employs the embodiments of block 602 to determine the operational accuracy, but with a different set of memory cells. In various embodiments, the second operational accuracy is higher than the first operational accuracy. An operational accuracy that is higher than another operational accuracy may be based on a statistical probability of fewer errors or failures in the memory, which may affect the accuracy of computing operations being performed using the memory. For example, a high operational accuracy may be that the memory performs with 0-.01% bit errors, while a low operational accuracy may be that the memory performs with 1% bit errors. In some cases, reducing the voltage of a first voltage at which 0-.01% bit errors occur to a second voltage at which 1% bit errors occur may save up to 30% of power.

[0088] In some embodiments, the first plurality of memory cells and the second plurality of memory cells are part of the same memory array. In other embodiments, the first plurality of memory cells and the second plurality of memory cells are part of separate memory arrays.

[0089] Process 600 continues at block 606 where a request to perform a computing operation is received. In various embodiments, the request is to perform some type of computing operation, such as host processing, a particular type of artificial neural network operation (e.g., different processing layers of the artificial neural network), a threshold accuracy for classification, a type of classification, etc. As a non-limiting example, a first request may be to perform a simple classification of an image (e.g., the image may contain a person) during an "always on" mode. As another example, a second request may be to perform a complex classification of an image (e.g., the image may contain an adult male) during an "awake" mode. Other types of requests to perform computing operations using the first memory or the second memory may also be received.

[0090] Next, process 600 proceeds to block 608 where an operational accuracy of the computing operation is determined. In some embodiments, an operational type of the computing operation is determined, and the operational type of the computing operation is associated with the operational accuracy. For example, using the example above, one operational type may be a simple classification, and another operational type may be a complex classification. A simple classification may be associated with a low operational accuracy, and a complex classification may be associated with a high operational accuracy.

[0091] Next, the process 600 continues at decision block 610, where it is determined whether the determined accuracy of the operation is above a threshold. In some embodiments, the threshold can be set by an administrator or user. In other embodiments, the threshold is set to a binary operation (e.g., if the computing operation is to perform a simple classification, the threshold is not satisfied; if the computing operation is to perform a complex classification, the threshold is satisfied). If the accuracy of the operation is above the threshold (or the type of operation is to utilize a higher accuracy memory), the process 600 flows to block 614; otherwise, the process 600 flows to block 612.

[0092] At block 612, a computing operation for the request is performed using the first plurality of memory cells. In some embodiments, the first plurality of memory cells operate at a lower operating voltage than the second plurality of memory cells. After block 612, process 600 continues at decision block 616.

[0093] If at decision block 610, the determined operational accuracy is above the threshold, process 600 flows from 610 to block 614. At block 614, the computing operation for the request is performed using the second plurality of memory cells. In some embodiments, the second plurality of memory cells operate at a higher operating voltage than the first plurality of memory cells.

[0094] Then, process 600 proceeds to decision block 616, where it is determined whether to change the accuracy of the operation based on the result of performing the calculation operation. In various embodiments, the first memory can be used at a lower operating voltage at block 612 to perform the calculation operation to perform a simple artificial neural network classification on the data set. If the result of the classification is a positive identification (e.g., a confidence level above a threshold, indicating a positive identification of the training object), the system can reanalyze the data set using a complex artificial neural network. In this example, the second memory will then be used at a higher operating voltage to perform the calculation operation.

[0095] If a change in operational accuracy is determined based on the computational results, process 600 returns to block 606 to receive a new or updated request to perform a computational operation; otherwise, process 600 terminates or otherwise returns to the calling process to perform other actions.

[0096] Although process 600 describes two memories being used for computing operations at two different operating accuracies, embodiments are not limited to the two memories being separate memories or different memories. Rather, in some embodiments, a single plurality of memory units are used for one or more processes or computing operations to be operated at different accuracies.

[0097] For example, in some embodiments, a process may be performed using multiple memory cells to store data at a first operating accuracy. During the process, an event may be detected that triggers a change in operating accuracy from the first operating accuracy to a second operating accuracy that is higher than the first operating accuracy. The process may continue to use the multiple memory cells, but be performed at the second, higher operating accuracy.

[0098] In some embodiments, a process may first be performed using a plurality of memory cells operating at a first operating voltage, which provides a first operating accuracy of the process. For example, the process may be to analyze an image for a person using a simple artificial neural network classifier. If the process detects a person (e.g., detects an event), the operating voltage of the plurality of memory cells may be increased to a second operating voltage that is higher than the first operating voltage. The process may then continue to process the image at a second operating accuracy that is higher than the first operating accuracy, which allows the process to be more accurate, or to perform a more complex artificial neural network classifier (e.g., to identify a specific person or face).

[0099] In other embodiments, other actions may be performed instead of increasing the voltage of the memory to increase the operating accuracy of the process. For example, the other actions may include: selecting other memory that operates at a higher voltage, selecting other memory with a higher operating accuracy, changing the neural network classifier or algorithm used, increasing the speed of the processor, initializing a separate process to be executed at a higher operating accuracy, etc.

[0100] Some embodiments may take the form of, or include, a computer program product. For example, according to one embodiment, a computer-readable medium including a computer program is provided, and the computer program is suitable for performing one or more of the above-mentioned methods or functions. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk (such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM)), a hard disk, a memory, a network, or a portable media item read by an appropriate drive or via an appropriate connection, including one or more bar codes or other related codes encoded to be stored on one or more such computer-readable media and read by an appropriate reader device.

[0101] In addition, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways, such as at least partially in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuit devices, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology and various combinations thereof.

[0102] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic system comprising: a plurality of memory cells, wherein the plurality of memory cells are arranged as a plurality of cell rows intersecting a plurality of cell columns, and in operation, the plurality of memory cells store data; memory management circuitry coupled to the plurality of memory cells, wherein in operation, the memory management circuitry marks a first set of the plurality of memory cells as being associated with a first operating mode and marks a second set of the plurality of memory cells as being associated with a second operating mode; as well as power control circuitry coupled to the memory management circuitry and the plurality of memory cells, wherein the power control circuitry is operable to provide a first operating voltage to a first set of the memory cells and a second operating voltage to a second set of the memory cells based on the tag, wherein the first operating voltage is different from the second operating voltage, wherein the first set of memory cells comprises: a subset of cells in a column of cells of the plurality of memory cells; a subset of a row of cells of the plurality of memory cells; or Both a subset of cells in columns of the plurality of memory cells and a subset of cells in rows of the plurality of memory cells. 2 . The electronic system of claim 1 , wherein the memory management circuitry identifies the first set of memory cells as memory cells having a statistical error probability below a first threshold level at the first operating voltage.

3. The electronic system of claim 2, wherein the first threshold level corresponds to one percent of bit cell sense amplifier marginal failures in the plurality of memory cells.

4. The electronic system of claim 2, wherein the memory management circuitry identifies the second set of memory cells as memory cells having a statistical error probability below a second threshold level at the second operating voltage, the second threshold level being lower than the first threshold level.

5. The electronic system of claim 1, wherein in operation, the memory management circuitry marks the first set of memory cells by storing a first value in a first memory associated with the first set of memory cells.

6. The electronic system of claim 1, wherein the first set of memory cells comprises a subset of columns in the plurality of memory cell columns.

7. The electronic system of claim 6, wherein in operation, the memory management circuitry marks the first set of memory cells by storing a value in each column of the subset of columns.

8. The electronic system of claim 6, wherein in operation, the memory management circuitry marks a first set of the memory cells by storing a value in memory associated with a subset of a plurality of the columns.

9. The electronic system of claim 1, wherein the first set of memory cells comprises a subset of rows in the plurality of memory cell rows.

10. The electronic system of claim 9, wherein the memory management circuitry marks the first set of memory cells by storing a value in each row in a subset of the rows.

11. The electronic system of claim 9, wherein the memory management circuitry marks the first set of memory cells by storing a value in memory associated with a subset of a plurality of the rows.

12. The electronic system of claim 6, wherein in operation, the memory management circuitry tags the memory cells by storing a table of memory cell addresses and corresponding tags.

13. The electronic system of claim 1, wherein the power control circuit arrangement comprises a low voltage power supply and a high voltage power supply.

14. The electronic system according to claim 13, comprising: A voltage selection circuit, in operation, the voltage selection circuit selects the low voltage power supply based on the marking of the first set of memory cells to provide the first operating voltage to the first set of memory cells, and selects the high voltage power supply based on the marking of the second set of memory cells to provide the second operating voltage to the second set of memory cells.

15. The electronic system of claim 1, wherein in operation, the memory management circuitry selectively implements error correction coding based on a flag value.

16. A method for a memory array, comprising: marking a first set of a plurality of memory cells as being associated with a first operating mode based on a statistical error rate associated with the first set of the plurality of memory cells, wherein the plurality of memory cells are arranged in a plurality of cell rows intersecting a plurality of cell columns; marking a second set of the plurality of memory cells as being associated with a second operating mode based on a statistical error rate associated with the second set of the plurality of memory cells; providing a first operating voltage to a first set of memory cells based on the flag; as well as providing a second operating voltage to a second set of memory cells based on the marking, wherein the second operating voltage is different from the first operating voltage and the first set of memory cells comprises: a subset of cells in a column of cells of the plurality of memory cells; a subset of a row of cells of the plurality of memory cells; or Both a subset of cells in columns of the plurality of memory cells and a subset of cells in rows of the plurality of memory cells.

17. The method according to claim 16, comprising: providing the first operating voltage to the first set of memory cells for use by at least one first process based on the markings of the first set of memory cells; and The second operating voltage is provided to the second set of memory cells for use by at least one second process based on the markings of the second set of memory cells.

18. The method according to claim 17, comprising: receiving a request to modify the markings of the first set of memory cells; marking a first portion of a first set of memory cells as being associated with the first mode of operation; as well as A second portion of the first set of memory cells is marked as being associated with the second mode of operation.

19. The method of claim 16, wherein the first set of memory cells comprises a larger portion of the plurality of memory cells and the second set of memory cells comprises a smaller portion of the plurality of memory cells.

20. A non-transitory computer-readable medium having content, the content causing a processor to perform actions comprising: determining, based on a first statistical error rate, a first set of the plurality of memory cells as being associated with a first operating mode; storing a first tag associated with a first set of memory cells; determining a second set of the plurality of memory cells as being associated with a second operating mode based on a second statistical error rate, wherein the plurality of memory cells are arranged as a plurality of cell rows intersecting a plurality of cell columns, and the first set of memory cells comprises: a subset of the cell columns of the plurality of memory cells; a subset of the cell rows of the plurality of memory cells; or both a subset of the cell columns of the plurality of memory cells and a subset of the cell rows of the plurality of memory cells; storing a second tag associated with a second set of the memory cells; selecting a first power supply to provide a first operating voltage to the first set of memory cells based on the first tag associated with the first set of memory cells; and Based on the second flag associated with a second set of the memory cells, a second power supply is selected to provide a second operating voltage to the second set of memory cells, wherein the first operating voltage is above a minimum threshold and less than the second operating voltage.

21. The non-transitory computer readable medium of claim 20, wherein selecting the first power supply to provide the first operating voltage to the first set of memory cells comprises: The second operating voltage from the second power supply is reduced to the first operating voltage.

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