Silicon carbide semiconductor device and method for manufacturing the same

Abstract

Provided are a silicon carbide semiconductor device and a method for manufacturing the same that can improve reliability and prevent cost increases. + The p-type region (21) is arranged directly below the trench (7) in a manner separate from the p-type base region (4) and faces the bottom surface of the trench (7) in the depth direction Z. The first p + The type region (21) is exposed at the bottom surface of the trench (7) and contacts the gate insulating film (8) at the bottom surface of the trench (7). + Type region (22) with the first p + The type area (21) and the groove (7) are separated and arranged between adjacent grooves (7) (table area). + The drain side end of the type region (22) is located at a position lower than the first p + The drain side end of the type region (21) is closer to the source side. + Type region (23) with the first p + The molded area (21) and the groove (7) are separated and arranged in the mesa area. + The molded area (23) is adjacent to the second p in the depth direction Z. + The molded areas (22) are opposite and adjacent to each other.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. Background Art

[0002] Conventionally, in trench-gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor having an insulating gate composed of a three-layer structure of metal-oxide film-semiconductor) composed of silicon carbide (SiC), it has been proposed to form each semiconductor region of the front element structure constituting the front side of the semiconductor substrate by combining epitaxial growth and ion implantation, thereby achieving a device with high withstand voltage and low on-resistance (for example, refer to the following patent documents 1 to 4).

[0003] In the following patent documents 1 to 4, by - Inside the drift region, closer to the n + The depth position of the type drain region forms a first p-type drain region opposite to the bottom surface of the trench in the depth direction. + type region and a second p-type base region that is opposite to and adjacent to the p-type base region in the depth direction. + type region, thereby preventing high electric fields from being applied to the bottom surface of the trench and achieving high withstand voltage and high reliability. + Type region and second p + The n-type impurity concentration in the JFET (Junction FET) region between the n-type regions is higher than that in the n-type regions. - The n-type impurity concentration in the drift region is reduced, thereby reducing the on-resistance.

[0004] In addition, by forming a p-type base region using an epitaxial layer with good crystallinity, the interface state density at the interface between the gate insulating film and SiC is reduced, thereby improving the carrier mobility of the channel (n-type inversion layer) and reducing the on-resistance. + The n-type region directly below (drain side) + type region, so that the first p + The n-type impurity concentration of the portion directly below the second p-type region is lower than that of the second p-type region. + By lowering the n-type impurity concentration in the portion immediately below the trench region, the breakdown voltage near the trench bottom surface is made higher than the breakdown voltage between trenches, thereby further improving reliability.

[0005] The cross-sectional structure of a conventional silicon carbide semiconductor device will be described. Figure 13 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Figure 13 Equivalent to the following patent document 4 Figure 1 . Figure 13The conventional silicon carbide semiconductor device 110 shown is in n - The interior of the drift region 102 has a structure that is closer to the n-type drift region than the bottom surface of the trench 107. + The first p-type drain region 101 has a depth of + Type region 121, the second p + Type region 122, and arranged in the second p + The n + A trench gate MOSFET is formed in the type region 123.

[0006] First p + The p-type region 121 is provided directly below the trench 107 (on the drain side) in a manner separated from the p-type base region 104 and faces the bottom surface of the trench 107 in the depth direction. + Type region 122 with the first p + The first p-type region 121 is provided between adjacent trenches 107 (a mesa region) in a manner separate from the trenches 107 and is opposed to and adjacent to the p-type base region 104 in the depth direction. + Type region 121, the second p + The drain-side end of the type region 122 is located at the same depth. + Type region 123 with the first p + The type region 121 is separated from the trench 107 and is arranged in the mesa region and is located in the depth direction from the second p + The molded areas 122 are opposite and adjacent to each other.

[0007] n + The type region 123 is located deeper than the first p + Type region 121, the second p + The first p-type region 122 is located closer to the drain side. + Type region 121, the second p + Type area 122 and n + The type region 123 is a diffusion region formed by ion implantation. + Type region 121, the second p + Type area 122 and n + The n-type region 123 has a function of relaxing the electric field applied to the bottom surface of the trench 107. Reference numeral 103 denotes an n-type region serving as a current spreading layer (CSL) that reduces diffusion resistance of carriers.

[0008] Reference numerals 104 to 106, 108, 109, and 111 are p-type base regions, n-type base regions, and + Type source region, p ++The gate electrode and the interlayer insulating film are shown in Figure 1. The reference numerals 112 and 113 are metal films constituting the source electrode, and the reference numeral 114 is a drain electrode. The reference numerals 131 to 133 are the n-type contact regions constituting the semiconductor substrate 130. + Type starting substrate, n - type epitaxial layer and p-type epitaxial layer, and respectively constitute n + Type drain region 101, n - type drift region 102 and a p-type base region 104 .

[0009] Next, a conventional method of manufacturing the silicon carbide semiconductor device 110 will be described. Figure 14 This is a flowchart showing an overview of a conventional method for manufacturing a silicon carbide semiconductor device. Figures 15-20 This is a cross-sectional view showing a state during the manufacturing process of a conventional silicon carbide semiconductor device. + The n-type drain region 101 + On the starting substrate 131, n - The n-type epitaxial layer 132 + Type drain region 101 to the first p + A portion 132a having a thickness up to the source-side end of the die region 121 is formed (step S101).

[0010] Next, in n - The surface of the epitaxial layer 132a is formed to be connected to the first p + Type region 121 and the second p + The first ion implantation mask 141 is formed by opening the portion corresponding to the formation area of ​​the p-type region 122 (step S102). Next, the first ion implantation mask 141 is used as a mask to perform the first ion implantation 142 of the p-type impurity (step S103). In the process of step S103, the first ion implantation mask 141 is used as a mask to perform the first ion implantation 142 of the p-type impurity (step S103). - The surface region of the epitaxial layer 132a selectively forms a first p + Type region 121 and as the second p + A portion of the p-type region 122 + Type area 122a ( Figure 15 ).

[0011] Next, a layer to be connected to n is formed on the first ion implantation mask 141. + The second ion implantation mask 143 is formed by opening the portion corresponding to the formation area of ​​the type region 123 (step S104). In the process of step S104, the first p-type ion implantation mask 141 used in the process of step S103 is formed to cover the first p-type ion implantation mask 141 exposed by the opening. +The second ion implantation mask 143 is formed in the n-type region 121. Next, the second ion implantation 144 of the n-type impurity is performed using the first ion implantation mask 141 and the second ion implantation mask 143 as masks (step S105).

[0012] In the process of step S105, - The surface area of ​​the epitaxial layer 132a is larger than the second p + The deep position of the type region 122 is so as to be aligned with the second p + The type region 122 is adjacent to form n + Type region 123. Since it is directly used to form the second p + The first ion implantation in the type region 122 is performed using the mask 141 for the second ion implantation 144, so that the n + The molded area 123 is formed with good positional accuracy on the second p + Directly below the mold area 122 ( Figure 16 ) Then, the first ion implantation mask 141 and the second ion implantation mask 143 are removed.

[0013] Next, a third ion implantation mask (not shown) is formed to open a portion corresponding to the formation region of the n-type region (hereinafter referred to as the n-type current diffusion region) 103 that will become the current diffusion layer (step S106). Next, the third ion implantation mask is used as a mask to perform the third ion implantation 145 of the n-type impurity (step S107). In the process of step S107, the first p + Type region 121 and the second p + An n-type region 103a ( Figure 17 ). Then, the third ion implantation mask is removed.

[0014] Next, deposit n - The first p-type epitaxial layer 132 + The remaining thickness portion 132b from the source side end of the p-type region 121 to the p-type base region 104 is processed (step S108). In the process of step S108, n - The epitaxial layer 132 becomes n + The predetermined thickness ( Figure 18 ). Next, in n - The surface of the epitaxial layer 132b is formed to be connected to the second p + A fourth ion implantation mask 146 is formed by opening a portion corresponding to the formation region of the die region 122 (step S109).

[0015] Next, the fourth ion implantation mask 146 is used as a mask to perform the fourth ion implantation 147 of the p-type impurity (step S110). In the process of step S110, a p-type impurity is selectively formed to penetrate the n-type impurity in the depth direction. - type epitaxial layer 132b and reaches the underlying p + The p-type region 122a + These adjacent p + The type regions 122a and 122b are connected to form a second p + Type area 122( Figure 19 ) Next, the fourth ion implantation mask 146 is removed.

[0016] Next, a fifth ion implantation mask (not shown) is formed with an opening corresponding to the formation region of the n-type current diffusion region 103 (step S111). Next, the fifth ion implantation mask is used as a mask to perform the fifth ion implantation of the n-type impurity (step S112: not shown). In the process of step S112, the adjacent second p + N-type regions 103b reaching the underlying n-type region 103a are formed between the n-type regions 122, and the n-type regions 103a and 103b adjacent in the depth direction are connected to form the n-type current diffusion region 103. Next, the fifth ion implantation mask is removed.

[0017] Next, in n - The surface of the p-type epitaxial layer 132b is deposited with a p-type epitaxial layer 133 which becomes the p-type base region 104 to form a semiconductor substrate (semiconductor wafer) 130 (step S113, Figure 20 ). Next, after forming (including heat treatment for impurity diffusion) the MOS gate structure, the metal films 112, 113 and / or the drain electrode 114 (refer to Figure 13 ) and other remaining parts (step S114), the conventional silicon carbide semiconductor device 110 is completed by singulating the semiconductor substrate 130 into individual chips.

[0018] Prior art literature

[0019] Patent Literature

[0020] Patent Document 1: International Publication No. 2017 / 064949

[0021] Patent Document 2: Japanese Patent Application Laid-Open No. 2017-139499

[0022] Patent Document 3: Japanese Patent No. 6115678

[0023] Patent Document 4: Japanese Patent Application Laid-Open No. 2018-019046 Summary of the Invention

[0024] Technical issues

[0025] In the above Figure 13 In the conventional silicon carbide semiconductor device 110 shown in FIG. 1 , by providing a second p + The n + The type region 123 is formed, thereby suppressing the occurrence of avalanche breakdown at the bottom surface of the trench 107 and improving reliability compared to the MOSFETs described in the above-mentioned patent documents 1 to 3. However, since it is necessary to increase the number of transistors for forming the n + The photolithography process of the ion implantation mask used in forming the die region 123 has problems such as characteristic variation due to positional deviation in alignment and cost increase due to increase in the number of steps.

[0026] An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the same that can improve reliability and prevent cost increases, in order to solve the above-mentioned problems of the prior art.

[0027] Technical Solution

[0028] To address the above-mentioned issues and achieve the objectives of the present invention, the silicon carbide semiconductor device of the present invention has the following features: A first semiconductor region of a first conductivity type is disposed within a semiconductor substrate composed of silicon carbide. A second semiconductor region of a second conductivity type is disposed between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of the first conductivity type is selectively disposed between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is disposed between the first and second semiconductor regions.

[0029] A trench penetrates the third semiconductor region and the second semiconductor region and reaches the fourth semiconductor region. A gate electrode is disposed within the trench via a gate insulating film. A fifth semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is disposed between the second main surface of the semiconductor substrate and the first semiconductor region. A first second conductivity type high concentration region is selectively disposed at a position closer to the second main surface than the bottom surface of the trench, spaced apart from the second semiconductor region, and facing the bottom surface of the trench in a depth direction. The impurity concentration of the first second conductivity type high concentration region is higher than the impurity concentration of the second semiconductor region.

[0030] A second second-conductivity-type high-concentration region is selectively provided in contact with the second semiconductor region, separated from the trench and the first second-conductivity-type high-concentration region. The second second-conductivity-type high-concentration region has a higher impurity concentration than the second semiconductor region. A first electrode is electrically connected to the second semiconductor region and the third semiconductor region. A second electrode is electrically connected to the fifth semiconductor region. An end portion of the second second-conductivity-type high-concentration region on the second principal surface is located closer to the first principal surface than an end portion of the first second-conductivity-type high-concentration region on the second principal surface.

[0031] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above-described invention, the impurity concentration of the first second-conductivity type high concentration region decreases as the impurity concentration is further away from the concentration peak position at which the impurity concentration reaches a maximum value toward the first main surface and the second main surface in the depth direction. An end portion of the second second-conductivity type high concentration region on the second main surface side is located closer to the first main surface than the concentration peak position of the first second-conductivity type high concentration region.

[0032] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, an end portion of the second second conductivity type high concentration region on the second main surface side has an arc shape convex toward the second main surface side.

[0033] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the silicon carbide semiconductor device further comprises: a first conductive type high concentration region, which is selectively arranged inside the fourth semiconductor region at a position closer to the second main surface in the depth direction than the second second conductive type high concentration region in a manner separate from the trench and the first second conductive type high concentration region, and is opposite to and in contact with the second second conductive type high concentration region, and has an impurity concentration higher than the impurity concentration of the first semiconductor region.

[0034] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the end of the second second conductive type high concentration region on the second main surface side is located closer to the first main surface side than the end of the first second conductive type high concentration region on the first main surface side.

[0035] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, an end portion of the second second conductivity type high concentration region on the second main surface side is a flat surface parallel to the second main surface.

[0036] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the distance from the end of the second main surface side of the second second conductive type high concentration region to the end of the second main surface side of the first second conductive type high concentration region is greater than the distance from the second semiconductor region to the end of the first main surface side of the first second conductive type high concentration region in the depth direction.

[0037] Furthermore, the silicon carbide semiconductor device of the present invention, in the above invention, is characterized in that a distance from the first second conductivity type high concentration region to the second second conductivity type high concentration region in a direction parallel to the first main surface is 1.1 μm or less.

[0038] Furthermore, to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device of the present invention has the following features: A first step is performed to deposit a first semiconductor layer of the first conductivity type composed of silicon carbide having an impurity concentration lower than that of the starting substrate on a starting substrate of the first conductivity type composed of silicon carbide. A second step is performed to selectively form a first second conductivity type high concentration region in the surface region of the first semiconductor layer by first ion implantation. A third step is performed to selectively form a first first conductivity type region in the surface region of the first semiconductor layer by second ion implantation, the first region being opposed to the first second conductivity type high concentration region in a direction parallel to the surface of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor layer. A fourth step is performed to deposit a second semiconductor layer of the first conductivity type composed of silicon carbide having an impurity concentration lower than that of the starting substrate on the first semiconductor layer. A fifth step is performed to form an ion implantation mask in the second semiconductor layer, the mask being opened in a portion opposing the first first conductivity type region in a depth direction.

[0039] A sixth step is performed, wherein a third ion implantation is performed using the ion implantation mask as a mask to selectively form a second second-conductivity-type high-concentration region in the surface region of the second semiconductor layer, separate from the first second-conductivity-type high-concentration region. A seventh step is performed to remove the ion implantation mask. An eighth step is performed, wherein a second first-conductivity-type region is selectively formed in the surface region of the second semiconductor layer by the fifth ion implantation, facing the second second-conductivity-type high-concentration region in a direction parallel to the surface of the second semiconductor layer, in contact with the first first-conductivity-type region in a depth direction, and having an impurity concentration higher than that of the second semiconductor layer. A ninth step is performed, wherein a third semiconductor layer of the second conductivity type composed of silicon carbide is deposited on the second semiconductor layer. A tenth step is performed, wherein an insulated gate structure is formed, comprising a trench penetrating the second semiconductor layer and reaching the first second-conductivity-type high-concentration region, and a gate electrode disposed within the trench via a gate insulating film. In the sixth step, the second second-conductivity-type high-concentration region is formed, with its lower end portion located shallower than the lower end portion of the first second-conductivity-type high-concentration region.

[0040] Furthermore, the method for manufacturing a silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, in the sixth step, the second second conductivity type high concentration region is formed, the lower end of which is located at a position shallower than the concentration peak position of the first second conductivity type high concentration region.

[0041] In addition, the manufacturing method of the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, after the fifth step and before the seventh step, it also includes: an eleventh step, using the ion injection mask as a mask to perform a fourth ion injection, and forming a first conductive type high concentration region at a position deeper than the second second conductive type high concentration region, which is adjacent to the second second conductive type high concentration region in the depth direction and has an impurity concentration higher than the impurity concentration of the first first conductive type region.

[0042] In addition, the manufacturing method of the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, in the eleventh step, the interface between the second second conductive type high concentration region and the first conductive type high concentration region is formed at a position shallower than the upper end portion of the first second conductive type high concentration region.

[0043] Furthermore, the method for manufacturing a silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the distance from the first second conductivity type high concentration region to the second second conductivity type high concentration region in a direction parallel to the surface of the second semiconductor layer is less than 1.1 μm.

[0044] According to the silicon carbide semiconductor device of the above invention, it is possible to ensure sufficient withstand voltage to the extent of meeting the predetermined rated voltage, reduce the on-resistance, and suppress the occurrence of avalanche breakdown at the bottom surface of the trench. In addition, according to the manufacturing method of the silicon carbide semiconductor device of the above invention, the process for forming the first conductive type high concentration region directly below the second second conductive type high concentration region can be omitted. Alternatively, the photolithography process for forming the ion implantation mask used for forming the first conductive type high concentration region directly below the second second conductive type high concentration region can be omitted. Therefore, the number of processes can be reduced. When forming the first conductive type high concentration region, characteristic deviations caused by positional deviations of the alignment can be prevented.

[0045] Technical Effects

[0046] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, there are effects of being able to improve reliability and prevent cost increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0048] Figure 2 It will Figure 1 A cross-sectional view showing an enlarged portion of the diagram.

[0049] Figure 3 This is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0050] Figure 4 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0051] Figure 5 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0052] Figure 6 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0053] Figure 7 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0054] Figure 8 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0055] Figure 9 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0056] Figure 10 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment.

[0057] Figure 11 It will Figure 10 A cross-sectional view showing an enlarged portion of the diagram.

[0058] Figure 12 3 is a characteristic diagram showing the relationship between the JFET width, the breakdown voltage, and the on-resistance in the embodiment.

[0059] Figure 13 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0060] Figure 14 This is a flowchart showing an overview of a conventional method for manufacturing a silicon carbide semiconductor device.

[0061] Figure 15 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0062] Figure 16 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0063] Figure 17 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0064] Figure 18 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0065] Figure 19 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0066] Figure 20 This is a cross-sectional view showing a state of a conventional silicon carbide semiconductor device during manufacturing.

[0067] Explanation of symbols

[0068] 1:n + Type Drain Region

[0069] 2:n - Drift zone

[0070] 3: n-type current diffusion region

[0071] 3a, 3b: n-type region

[0072] 4: p-type base region

[0073] 5:n + Type source region

[0074] 6: p ++ Type contact area

[0075] 7: Grooves

[0076] 8: Gate insulating film

[0077] 9: Gate electrode

[0078] 10, 10': Silicon carbide semiconductor devices

[0079] 11: Interlayer insulation film

[0080] 12: Ohmic electrode

[0081] 13: Source electrode

[0082] 14: Drain electrode

[0083] 21: p just below the groove + Type region (first p + Type area)

[0084] 21a: First p + The depth position of the concentration peak in the type area

[0085] 22, 22': p in the table area + Type region (second p + Type area)

[0086] 22a: Second p + The depth position of the concentration peak in the type area

[0087] 23: Second p + n just below the type area + Type area

[0088] 30: Semiconductor substrate

[0089] 31:n + Type starting substrate

[0090] 32, 32a, 32b: n - Epitaxial layer

[0091] 33: p-type epitaxial layer

[0092] 41, 44: Mask for ion implantation

[0093] 42, 43, 45, 46: Ion implantation

[0094] d1, d1': from the second p + The depth of the drain-side end of the type region to the first p + The distance from the drain side end of the region to the depth position

[0095] d2: JFET width

[0096] d3: from the second p + n just below the type area + The depth of the drain-side end of the type region to the first p + The distance from the drain side end of the region to the depth position

[0097] t: In the formation of the second p + n deposited in the type zone - The thickness of the epitaxial layer

[0098] w1: width of the groove

[0099] w11: first p + Width of the mold area

[0100] w12: second p + Width of the mold area

[0101] w13: second p + n just below the type area + Width of the mold area

[0102] X: first direction parallel to the front surface of the semiconductor substrate

[0103] Y: a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction

[0104] Z: Depth direction DETAILED DESCRIPTION

[0105] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention are described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes, respectively, are majority carriers. Furthermore, the + and - prefixes in n or p indicate that the impurity concentration is higher or lower, respectively, than in layers or regions not prefixed with + or -. In the following descriptions of the embodiments and the accompanying drawings, identical structures are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0106] (Implementation Method 1)

[0107] The structure of the silicon carbide (SiC) semiconductor device according to the first embodiment will be described. Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 1 A portion of the active region is shown in FIG, and the edge termination region surrounding the active region is omitted (in FIG. Figure 10 The same is true in ). Figure 2 It will Figure 1 A cross-sectional view showing an enlarged portion of the diagram. Figure 2The figure shows the distance from the center of the groove 7 to the center of the mesa region (in Figure 11 The same is true in ).

[0108] In addition, Figure 2 In the figure, different shadows are used to represent the p-type semiconductor region (p-type base region 4, p-type semiconductor region 5) configured in the mesa region. ++ Type contact region 6 and the first p + Type region 21, second p + The impurity concentration distribution in the type region 22). Figure 2 In the p-type impurity concentration graph shown on the right side of the vertical direction, the topmost shaded area has the highest p-type impurity concentration, and the p-type impurity concentration decreases as the area is arranged downward (in Figure 11 The same is true in ).

[0109] The active region is a region through which current flows when the element (here, a MOSFET) is in the on state, and multiple unit cells (component units of the element) of the element are arranged adjacent to each other along a first direction X parallel to the front surface of the semiconductor substrate 30. The edge termination region is a region between the active region and the end (chip end) of the semiconductor substrate 30, and is used to mitigate the electric field on the front side of the semiconductor substrate 30 and maintain the withstand voltage (voltage resistance).

[0110] The breakdown voltage is the limit voltage at which leakage current does not increase excessively and the device does not malfunction or break down. The edge termination region is equipped with breakdown voltage structures such as the field limiting ring (FLR), mesa structure, junction termination extension (JTE) structure, and field plate (FP).

[0111] Figure 1 、 Figure 2 The silicon carbide semiconductor device 10 of the first embodiment shown is a vertical MOSFET having a conventional trench gate MOS gate structure on the front side of a semiconductor substrate 30 made of silicon carbide, and has a first p-type MOSFET facing the bottom surface of the trench 7 in the depth direction Z. + Type region (first second conductivity type high concentration region) 21, in the depth direction Z with p ++ The second p-type contact region 6 is opposite to the + Type region (second second conductivity type high concentration region) 22 and n + type region (first conductivity type high concentration region) 23.

[0112] The semiconductor substrate 30 is formed into n + n type drain region (fifth semiconductor region) 1 +The front surface of the starting substrate 31 is stacked in order to form n - The MOS gate structure is composed of the epitaxial layers 32 and 33 of the p-type drift region (first semiconductor region) 2 and the p-type base region (second semiconductor region) 4. + Type source region (third semiconductor region) 5, p ++ It is composed of a type contact region 6, a trench 7, a gate insulating film 8 and a gate electrode 9.

[0113] The p-type base region 4 is provided between the front surface (the main surface on the p-type epitaxial layer 33 side) of the semiconductor substrate 30 and the n-type epitaxial layer 33. - The p-type base region 4 is in contact with the gate insulating film 8 at the sidewall of the trench 7. - The p-type base region 4 and the n-type drift region 2 are provided between the p-type base region 4 and the n-type drift region 2. - The n-type drift region 2 contacts and becomes an n-type region (n-type current diffusion region: fourth semiconductor region) 3 of a current diffusion layer (CSL) that reduces diffusion resistance of carriers.

[0114] The n-type current diffusion region 3 is located opposite to and adjacent to the gate insulating film 8 on the sidewall of the trench 7. The n-type current diffusion region 3 is arranged on the first p + Type region 21 and the second p + Type 22 and n + type region 23, and having a first p + Type region 21 and the second p + Type 22 and n + The n-type impurity concentration of the JFET region between the n-type regions 23 is higher than that of the n-type regions 24. - The first p-type drift region 2 has the function of reducing the on-resistance. + Type region 21, second p + Type area 22 and n + The molded area 23 will be described later.

[0115] n + Type source region 5 and p ++ The p-type contact regions 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 4 in a manner of contacting the p-type base region 4. + Type source region 5 and p ++ The contact region 6 is exposed on the front surface of the semiconductor substrate 30 between adjacent trenches 7 (mesa region). + Type source region 5 and p ++ The type contact regions 6 are arranged adjacent to each other in the first direction X.

[0116] p ++ The contact area 6 is arranged at a ratio of n + The type source region 5 is further away from the position of the trench 7. ++The contact region 6 is arranged at the center of the mesa region in the first direction X. ++ Type contact area 6. Without setting p ++ In the case of the p-type contact region 6, the p-type base region 4 replaces the p ++ The type contact region 6 reaches the front surface of the semiconductor substrate 30.

[0117] Groove 7 through n + type source region 5 and p-type base region 4, and through the n-type current diffusion region 3 in the first p + The trench 7 is extended in a stripe shape in a second direction Y parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X. Although not shown in the figure, the p-type base region 4 and the n-type base region 21 are terminated. + Type source region 5 and p ++ The contact region 6 is arranged in a straight line extending in the second direction Y in parallel with the trench 7 .

[0118] The trench 7 has a sidewall substantially perpendicular to the front surface of the semiconductor substrate 30 and a sidewall extending toward the drain side (n + The bottom surface of the trench 7 is convex in an arc shape (on the side of the drain region 1). The portion connecting the side wall of the trench 7 and the bottom surface (hereinafter referred to as the bottom surface corner) is in an arc shape continuous with the arc of the bottom surface of the trench 7. The bottom surface of the trench 7 is located at the first p + The bottom corner of the trench 7 is located inside the n-type current diffusion region 3 or the first p + The interior of the molded area 21.

[0119] A gate electrode 9 is provided inside the trench 7 via a gate insulating film 8. An interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 30. A contact hole is provided in the interlayer insulating film 11, penetrating the interlayer insulating film 11 in the depth direction Z and reaching the semiconductor substrate 30. + Type source region 5 and p ++ The type contact region 6 is exposed in the contact hole.

[0120] The source electrode (first electrode) 13 is provided on the entire front surface of the semiconductor substrate 30 in the active region and is connected to the n electrode in the contact hole. + Type source region 5 and p ++ The symbol 12 is electrically connected to the n contact area 6. + Type source region 5 and p ++ Type contact area 6 ohm contact, and n + Type source region 5 and p ++ The metal film (hereinafter referred to as an ohmic electrode (first electrode)) electrically connected to the type contact region 6 and the source electrode 13.

[0121] When p is not set ++In the case of the p-type contact region 6, the source electrode 13 is connected to the p-type base region 4 and the n-type contact region 6 via the ohmic electrode 12. + The back surface (n) of the semiconductor substrate 30 is electrically connected to the source region 5. + The main surface (n + The drain electrode (second electrode) 14 is provided on the entire surface of the back surface of the starting substrate 31. + Type drain region 1 is in contact with n + The type drain region 1 is electrically connected.

[0122] Next, for the first p + Type region 21, second p + Type area 22 and n + The first p + The p-type region 21 is provided directly below the trench 7 (on the drain side) in a manner separate from the p-type base region 4 and faces the bottom surface and bottom corner of the trench 7 in the depth direction Z. + The width w11 of the type region 21 is greater than the width w1 of the trench. + The type region 21 is exposed at the bottom surface of the trench 7 and is in contact with the gate insulating film 8 at the bottom surface of the trench 7. + The die region 21 may be in contact with the gate insulating film 8 at the bottom corner of the trench 7 .

[0123] First p + The n-type region 21 is opposite to the n-type current diffusion region 3 in the first direction X. The first p + The n-type region 21 may also be in contact with the n-type current diffusion region 3 in the first direction X. The first p + The entire n-type region 21 except for the portion in contact with the gate insulating film 8 may be opposed to or in contact with the n-type current diffusion region 3. + The type region 21 may be connected to the drain side portion (including the drain side end) - Type drift region 2 contacts. The first p + Type region 21 is configured to be + type drain region 1 separated.

[0124] First p + The area 21 is not shown in the figure and the second p + Type region 22 is in direct contact with, or in contact with, the second p + The first p-type region 22 is electrically connected to the source potential. + Type region 21 is in contact with the second p + In the case of direct contact between the p-type base region 22 and the second p-type base region 4, the position as far away as possible from the p-type base region 4 in the depth direction Z can be + The mold area 22 is in direct contact with the mold area 22. The reason is as follows.

[0125] Because in the second p + When avalanche breakdown occurs near the p-type region 22, current (hereinafter referred to as avalanche current) flows from the p-type base region 4 to the source electrode 13. + The p-type region 21 is located near the p-type base region 4 and is connected to the second p-type base region 4. + In the case of direct contact with the p-type region 22, the avalanche current may flow from the p-type base region 4 into the first p + Type region 21 and in the first p + Avalanche breakdown occurs near type zone 21.

[0126] In the first p + Type region 21 and the second p + In the case of direct contact of the type region 22, for example, selectively configuring n + Type area 23, and in the unconfigured n + The position of the type region 23 makes the second p + The type region 22 extends toward the drain side and is aligned with the first p-type region 22 in the first direction X. + The first p + The molded area 21 extends in the first direction X toward the second p + Furthermore, as long as the second p + The portion of the type region 22 extending toward the drain side is connected to the first p + The portion of the molded area 21 extending along the first direction X only needs to be in direct contact.

[0127] In this case, for example, n + The molded areas 23 are dispersed at predetermined intervals in the second direction Y. + The second p at the position of the type region 23 + The drain side end of the type region 22 is larger than the first p + The source side end of the type region 21 is closer to the drain side and is larger than the first p + The drain side end of the type region 21 ends closer to the source side. + The second p at the position of the type region 23 + The second p-type region 22, for example, may also be applied to the second embodiment described later. + Type area 22' (refer to Figure 10 、 Figure 11 ) structure.

[0128] First p + The molded area 21 has a substantially rectangular cross-sectional shape with all vertices (corners) rounded. + In the region 21, the curvature of the corner on the drain side is greater than the curvature of the corner on the source side, and the width w11 (w11d) on the drain side is smaller than the width w11 (w11s) on the source side ( Figure 2 ). First p + Of the four vertices of the substantially rectangular cross-sectional shape of the die region 21 , the two vertices on the source side are corners on the source side, and the two vertices on the drain side are corners on the drain side.

[0129] First p + The type region 21 is implanted by the first ion implantation 42 (see Figure 4 ) and the diffusion region formed. The first p + The impurity concentration of the type region 21 shows a maximum value (hereinafter referred to as a concentration peak) near the depth position of the range of the first ion implantation 42, and decreases as the depth position of the concentration peak (representing the first p + The height position of the thick arrow of the type region 21) 21a becomes lower as it moves away from the source side and the drain side in the depth direction Z. + The depth position 21a of the concentration peak of the type region 21 is greater than that of the first p + The center of the molded area 21 in the depth direction Z is closer to the groove 7 .

[0130] In order to make the first + The depth position 21a of the concentration peak of the type region 21 is greater than that of the first p + The center of the region 21 in the depth direction Z is closer to the trench 7, which can be used to form the first p + The range of the first ion implantation 42 of the type region 21 is adjusted in various ways. + The depth position 21a of the concentration peak of the type region 21 is greater than that of the first p + The center of the molded region 21 in the depth direction Z is closer to the trench 7, thereby reducing the first p + The curvature of the lower end portion (drain side end portion) of the type region 21 can be reduced, and electric field concentration can be made difficult to occur.

[0131] Second p + Type region 22 with the first p + The type region 21 is separated from the trench 7 and is arranged between adjacent trenches 7 (mesa region). + The p-type region 22 is opposite to and adjacent to the p-type base region 4 in the depth direction Z. The second p + The molded area 22 is parallel to the p in the depth direction Z. ++ The second p + The n-type region 22 faces the sidewall of the trench 7 across the n-type current diffusion region 3 in the first direction X. The second p + In the type region 22, in addition to the p-type base region 4 and the n + Portions other than the portion in contact with the n-type region 23 may be in contact with the n-type current diffusion region 3 .

[0132] Second p +The drain side end of the type region 22 is located at a position slightly larger than the first p + The drain side end of the type region 21 is closer to the source side. + The drain side end of the type region 22 may be located at a position slightly larger than the first p + The depth position 21a of the concentration peak of the type region 21 is closer to the source side. + The drain side end of the type region 22 is located at a position slightly larger than the first p + The depth position 21a of the concentration peak of the type region 21 is closer to the source side, so that the first p + The concentration peak of type region 21 is related to the second p + Therefore, it is possible to + Type region 21 in the second p + The type region 22 generates avalanche breakdown and suppresses changes in the local electric field inside the gate insulating film 8 and dielectric breakdown of the gate insulating film 8 caused by carrier injection into the gate insulating film 8 at the bottom of the trench 7 .

[0133] Second p + The drain-side end of the type region 22 is the second p + Type region 22 and n + The interface between the type region 23 and the flat surface substantially parallel to the front surface of the semiconductor substrate 30. + The n-type region 22 is formed directly below the + Type 23, second p + The drain side end of the type region 22 becomes a flat surface substantially parallel to the front surface of the semiconductor substrate 30. + The drain side end of the type region 22 becomes a flat surface substantially parallel to the front surface of the semiconductor substrate 30, thereby + There is no n set directly below the mold area 22 + Compared with the case of the type region 23 (embodiment 2 described later), the second p + The die region 22 becomes shallower, thereby reducing the on-resistance.

[0134] From the second p + The depth of the drain-side end of the type region 22 is from the first p + The distance d1 from the p-type base region 4 to the drain-side end of the p-type region 21 is the distance from the p-type base region 4 to the first p-type region 21 in the depth direction Z. + The distance from the p-type base region 4 to the first p-type region 21 on the source side is greater than or equal to the distance from the p-type base region 4 to the source side end of the p-type region 21. + The distance from the source side end of the region 21 to the n-type region 21 is the same as the n-type region 21 which is deposited by epitaxial growth during manufacturing to form the semiconductor substrate 30 described later. - The thickness t of the epitaxial layer 32b (refer to Figure 6) are the same, for example, about 0.5μm.

[0135] From the second p + The depth of the drain-side end of the type region 22 is from the first p + The greater the distance d1 from the depth position of the drain-side end of the type region 21, the lower the on-resistance can be. + The drain side end of the type region 22 is located at a position slightly larger than the first p + The source-side end of the type region 21 is positioned closer to the source side, which can further reduce the on-resistance. + The width w12 of the die region 22 in the first direction X is the same in the depth direction Z. The same width means that the widths are substantially the same within a range including an error allowed due to process variations.

[0136] Caught in the first p + Type region and second p + The n-type impurity concentration of the JFET region between the n-type regions becomes lower than that of the n-type current diffusion region 3. - In the first direction X from the first p + Type region 21 to the second p + The distance d2 from the first p-type region 22 to the first p-type region 22 (hereinafter referred to as the JFET width) is, for example, about 1.1 μm or less. By setting the JFET width d2 within the above range, it is possible to ensure a withstand voltage of about 1400 V or more and reduce the on-resistance to the same level as the first p-type region 22. + Type region 121, the second p + The conventional structure in which the drain-side ends of the type region 122 are located at the same depth as each other (see Figure 13 ) is less than the same level.

[0137] Second p + The type region 22 is implanted by the third ion implantation 45 (see Figure 7 ) and the diffusion region formed. The second p + The impurity concentration of the type region 22 shows a maximum value (concentration peak) near the depth position of the range of the third ion implantation 45, and decreases as the depth position of the concentration peak (indicating the second p + The height position of the thick arrow of the type region 22) 22a becomes lower as it moves away from the source side and the drain side in the depth direction Z. + The depth position 22a of the concentration peak of the type region 22 is greater than that of the second p + The center of the p-type region 22 in the depth direction Z is closer to the p-type base region 4 .

[0138] In order to make the second + The depth position 22a of the concentration peak of the type region 22 is greater than that of the second p +The center of the p-type region 22 in the depth direction Z is closer to the p-type base region 4, which can be used to form the second p-type base region 4. + The range of the third ion implantation 45 in the type region 22 is varied. + The depth position 22a of the concentration peak of the type region 22 is greater than that of the second p + The center of the p-type region 22 in the depth direction Z is closer to the p-type base region 4, so that the first p + The concentration peak of type region 21 is related to the second p + The concentration peaks of the type region 22 are not aligned in the first direction X. + Type region 21, second p + The die region 22 has a function of relaxing the electric field applied to the bottom surface of the trench 7 .

[0139] n + Type region 23 with the first p + The molded area 21 and the groove 7 are separated and arranged in the mesa area. + The molded area 23 is adjacent to the second p in the depth direction Z. + The molded areas 22 are opposite and adjacent to each other. + The type region 23 has a first p + The n-type impurity concentration directly below the p-type region 21 is lower than the second p-type region 21. + The function of suppressing the occurrence of avalanche breakdown at the bottom of the trench 7 by reducing the n-type impurity concentration just below the n-type region 22. + The thickness of the die region 23 is, for example, approximately 0.2 μm.

[0140] n + The n-type region 23 is opposite to the n-type current diffusion region 3 in the first direction X. + The n-type region 23 may contact the n-type current diffusion region 3 in the first direction X. + Type region 23, in addition to the second p + The entire portion other than the portion in contact with the n-type region 22 may be opposed to the n-type current diffusion region 3 or in contact with the n-type current diffusion region 3. + The type region 23 may be connected to the drain side portion (including the drain side end) - Type drift region 2 contact. n + Type region 23 is configured to be + type drain region 1 separated.

[0141] n + The drain-side end of the type region 23 is located deeper than the first p-type region 23 in the depth direction Z. + The source side end of the type region 21 is closer to the drain side. + The drain side end of the type region 23 is located at the same position as the first p + The drain side end of the type region 21 is at the same depth as or deeper than the first p +The drain side end of the type region 21 is closer to the source side. + The depth of the drain-side end of the type region 23 is from the first p + A distance d3 from the depth position of the drain-side end portion of the die region 21 is approximately 0 μm or more and 0.5 μm or less.

[0142] n + The source side end portion of the type region 23 (the second p + Type 22 and n + The interface between the molded areas 23) can be located at a position lower than the first p in the depth direction Z. + The source-side end of the region 21 is positioned closer to the source. + The width w13 of the molded area 23 in the first direction X is the second p + The width w12 of the molded area 22 in the first direction X is greater than n. + The width w13 of the molded area 23 in the first direction X is greater than the width w13 of the molded area 23 in the second direction X. + The reason why the width w12 of the molded area 22 in the first direction X is wide is to reliably cover the second p + The lower end portion (drain side end portion) of the type region 22.

[0143] n + The type region 23 is implanted by the fourth ion implantation 46 (see Figure 8 ) and the diffusion area formed. + The impurity concentration of the type region 23 shows a maximum value (concentration peak) near a depth position (not shown) within the range of the fourth ion implantation 46. + The depth position of the concentration peak of the type region 23 is, for example, n + Type region 23 and the second p + As the depth position of the concentration peak moves away from the drain side in the depth direction Z, n + The impurity concentration of the type region 23 becomes lower.

[0144] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment will be described. Figure 3 This is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 4 to 9 This is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment. + n-type drain region 1 + On the starting substrate 31, n - The n-type epitaxial layer 32 + Type drain region 1 to the first p +A portion (first semiconductor layer) 32a having a thickness extending from the source-side end portion (upper end portion) of the die region 21 is formed (step S1).

[0145] Next, in n - The surface of the epitaxial layer 32a is formed to be connected to the first p + The first ion implantation mask 41 is formed by opening the portion corresponding to the formation area of ​​the p-type region 21 (step S2). Next, the first ion implantation mask 41 is used as a mask to perform the first ion implantation 42 of the p-type impurity (step S3). In the process of step S3, the first ion implantation mask 41 is used as a mask to perform the first ion implantation 42 of the p-type impurity (step S3). - The surface region of the epitaxial layer 32a selectively forms a first p + Type 21( Figure 4 ) Then, the first ion implantation mask 41 is removed.

[0146] Next, a second ion implantation mask (not shown) is formed to open a portion corresponding to the formation region of the n-type current diffusion region 3 (step S4). Next, the second ion implantation mask is used as a mask to perform the second ion implantation 43 of the n-type impurity (step S5). In the process of step S5, the first adjacent p + An n-type region 3a ( Figure 5 Then, the second ion implantation mask is removed. The processes of steps S2 and S3 can be interchanged with the processes of steps S4 and S5.

[0147] Next, deposit n - The first p-type epitaxial layer 32 + The remaining thickness of the portion (second semiconductor layer) 32b from the source side end of the p-type region 21 to the p-type base region 4 is processed (step S6). In the process of step S6, n - The epitaxial layer 32 becomes n + The predetermined thickness between the p-type drain region 1 and the p-type base region 4 ( Figure 6 ). Next, in n - The surface of the epitaxial layer 32b is formed to be connected with the second p + A third ion implantation mask 44 is formed by opening a portion corresponding to the formation region of the die region 22 (step S7).

[0148] Next, the third ion implantation mask 44 is used as a mask to perform the third ion implantation 45 of the p-type impurity (step S8). - The interior of the epitaxial layer 32 is larger than the first p + The shallow depth of the type region 21 forms a second p + Type 22( Figure 7 ). At this time, the second p +The drain-side end (lower end) of the n-type region 22 is arc-shaped and convex toward the drain side (lower side). Next, the fourth ion implantation 46 of the n-type impurity is performed using the same third ion implantation mask 44 used in the process of step S8 as a mask (step S9).

[0149] In the process of step S9, - The interior of the second p-type epitaxial layer 32 is larger than + The position of the molded area 22 is deep, so that it is aligned with the second p in the depth direction Z. + The type region 22 is adjacent to form n + Type 23 ( Figure 8 ). At this time, the second p + The arc-shaped portion of the drain-side end portion of the type region 22 that is convex toward the drain side is inverted to the n-type and becomes n-type. + The die region 23 forms a flat surface substantially parallel to the front surface of the semiconductor substrate 30. + The depth position of the mold region 23 can be variously changed by adjusting the acceleration voltage of the fourth ion implantation 46 .

[0150] In the process of step S9, the process of step S8 (for forming the second p + The third ion implantation mask 44 used in the third ion implantation 45 of the type region 22 is used, and the fourth ion implantation 46 is performed at an acceleration voltage higher than that of the third ion implantation 45 to form an n + Therefore, it is possible to position the second p + The n-type region 22 is formed directly below (on the lower side) + The third ion implantation mask 44 is removed.

[0151] Next, a fourth ion implantation mask (not shown) is formed with an opening corresponding to the formation region of the n-type current diffusion region 3 (step S10). Next, the fifth ion implantation of n-type impurities is performed using the fourth ion implantation mask as a mask (step S11: not shown). In the process of step S11, the adjacent second p + N-type regions 3b reaching the underlying n-type region 3a are formed between the n-type regions 22, and n-type current diffusion regions 3 are formed by connecting the adjacent n-type regions 3a and 3b in the depth direction Z. Next, the fourth ion implantation mask is removed.

[0152] Next, in n - A p-type epitaxial layer (third semiconductor layer) 33 is deposited on the surface of the p-type epitaxial layer 32b to form a p-type base region 4, thereby forming a semiconductor substrate (semiconductor wafer) 30 (step S12, Figure 9). Next, after forming (heat treatment for impurity diffusion) a MOS gate structure, an ohmic electrode 12, a source electrode 13 and / or a drain electrode 14 (refer to Figure 1 ) and other remaining parts (step S13), the semiconductor substrate 30 is singulated (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10.

[0153] As described above, according to the first embodiment, the first p-type transistor having the drain-side end portion located immediately below the trench is provided in the mesa region. + The drain side end of the type region is closer to the source side (upper side) of the second p + Thus, sufficient withstand voltage can be ensured to meet the predetermined rated voltage, and the on-resistance can be reduced. + The second p is set just below the mold area + n adjacent to the type region + type area, thereby reducing the on-resistance.

[0154] In addition, according to the first embodiment, the second p + n just below the type area + Type region, and similarly to the conventional structure, the first p + The n-type impurity concentration directly below the second p-type region is lower than + The n-type impurity concentration directly below the type region is thus able to make the first p + The withstand voltage of the second p + This can suppress avalanche breakdown at the bottom of the trench and improve reliability.

[0155] Furthermore, according to the first embodiment, the second p + The ion implantation mask of the type region is used to position the second p + The n-type region is formed just below the + In addition, there is no need to form a region only for forming the n + This method uses a mask for ion implantation in the molded area. This allows alignment position deviation to be kept within the allowable range (±0.2 μm), preventing characteristic variations caused by alignment position deviation. Furthermore, this method avoids the cost increase caused by an increase in the number of steps.

[0156] (Implementation Method 2)

[0157] Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. Figure 10 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment. Figure 11 It will Figure 10The silicon carbide semiconductor device 10' of the second embodiment is different from the silicon carbide semiconductor device 10 of the first embodiment (see Figure 1 ) is different in that in the second p + There is no n provided directly below the molded area 22' + Type area.

[0158] In embodiment 2, the second p + The drain side end of the type region 22' is closer than the first p + The source side end of the type region 21 ends closer to the drain side. + The drain side end of the type region 22' is similar to the first embodiment and is + The drain side end of the type region 21 ends closer to the source side, preferably at a position lower than the first p + The depth position 21a of the concentration peak of the type region 21 is closer to the source side ( Figure 11 ). The reason is the same as that of the first embodiment. + The drain-side end of the die region 22 ′ is in an arc shape convex toward the drain side.

[0159] From the second p + The depth of the drain-side end of the type region 22' is from the first p + The distance d1′ from the depth position of the drain-side end of the type region 21 is greater than that from the second p-type region 21 in the first embodiment. + The depth of the drain-side end of the type region 22 is from the first p + The distance d1 from the depth position of the drain side end of the region 21 (see Figure 2 ) is short, for example, 0.1 μm or more and 1.0 μm or less. + Type region 21 to the second p + The distance d2′ to the die region 22′ (JFET width) is the same as the JFET width d2 of the first embodiment (see Figure 2 )same.

[0160] The method for manufacturing the silicon carbide semiconductor device 10' of the second embodiment is as follows: in the method for manufacturing the silicon carbide semiconductor device 10 of the first embodiment, the process of step S9 (for performing the second p + The n-type region 22' is formed directly below the + The fourth ion implantation 46 of the type region: Figure 3 and Figure 8 By omitting the processing of step S9, the second p + The drain side end portion of the type region 22' will not be inverted to the n type, and therefore, when the process of step S8 is maintained ( Figure 3 、 Figure 7) is in an arc-shaped state that protrudes toward the drain side.

[0161] As described above, according to Embodiment 2, by not + Set n just below the mold area + type region, thereby with the second p + There is n + Compared with the case of the second p-type region, although the on-resistance and the withstand voltage are higher, the same effect as the first embodiment can be obtained. Therefore, it is useful when the withstand voltage is increased even if the on-resistance is slightly increased. In addition, according to the second embodiment, since the second p-type region can be omitted + The n-type region is formed just below the + Ion implantation in the molded area can simplify the manufacturing process.

[0162] (Example)

[0163] Next, the JFET width d2 (see Figure 2 ) and the relationship between withstand voltage and on-resistance were verified. Figure 12 The characteristic diagram shows the relationship between the JFET width, the breakdown voltage and the on-resistance of the embodiment. Figure 1 、 Figure 2 ) structure of a vertical MOSFET (hereinafter referred to as an embodiment), the JFET width d2 is varied to simulate the breakdown voltage and the on-resistance RonA. The results are shown in FIG. Figure 12 .

[0164] In addition, Figure 12 FIG. 1 shows a conventional silicon carbide semiconductor device 110 (see FIG. Figure 13 ) structure of a vertical MOSFET (hereinafter referred to as the prior art), the JFET width d102 was varied in the same manner as in the embodiment to simulate the breakdown voltage and on-resistance RonA. The difference between the prior art and the embodiment is that the first p + Type region 121, the second p + The depth positions of the drain-side end portions of the die regions 122 are set to be the same.

[0165] according to Figure 12The results show that while the breakdown voltage of the embodiment is lower than that of the conventional example, the embodiment can still ensure a sufficient breakdown voltage (for example, 1200V or more) even when the JFET width d2 is narrowed due to miniaturization. For example, when the JFET width d2 is 1.1μm or less, a breakdown voltage of 1400V or more can be ensured, and an on-resistance comparable to or lower than that of the conventional example can be obtained. Therefore, the embodiment is useful when, for example, the JFET width d2 is set to 1.1μm or less and the rated voltage is set to 1200V.

[0166] Although not shown in the figure, the silicon carbide semiconductor device 10 ′ (see Figure 10 、 Figure 11 ) structure, it was also confirmed that although the on-resistance and the withstand voltage were higher than those of the embodiment, the same effect as the embodiment could be obtained.

[0167] The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. For example, a structure can be formed in which a source electrode is embedded in a trench (hereinafter referred to as a contact trench) formed in a mesa region of a semiconductor substrate, thereby forming a contact between the source electrode and the n electrode on the inner wall of the contact trench. + Type source region and p ++ Furthermore, as an ion implantation mask for forming each semiconductor region, for example, a resist film or an oxide film may be used.

[0168] Industrial applicability

[0169] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices such as power converters and power supply devices for various industrial machines.

Claims

1. A silicon carbide semiconductor device, characterized in that: have: a semiconductor substrate composed of silicon carbide; A first semiconductor region of a first conductivity type is disposed inside the semiconductor substrate; a second semiconductor region of a second conductivity type, provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of the first conductivity type, selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of the first conductivity type, disposed between the first semiconductor region and the second semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench penetrating the third semiconductor region and the second semiconductor region and reaching the fourth semiconductor region; a gate electrode disposed inside the trench via a gate insulating film; a fifth semiconductor region of the first conductivity type, provided between the second main surface of the semiconductor substrate and the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a first second conductivity type high concentration region selectively provided at a position closer to the second main surface than to the bottom surface of the trench so as to be separated from the second semiconductor region and opposed to the bottom surface of the trench in the depth direction, and having an impurity concentration higher than that of the second semiconductor region; a second second-conductivity-type high-concentration region, selectively provided at a position closer to the first main surface than the first second-conductivity-type high-concentration region in a manner separate from the trench and the first second-conductivity-type high-concentration region, in contact with the second semiconductor region, and having an impurity concentration higher than that of the second semiconductor region; a first electrode electrically connected to the second semiconductor region and the third semiconductor region; as well as a second electrode electrically connected to the fifth semiconductor region, An end portion of the second second-conductivity-type high-concentration region on the second principal surface side is located closer to the first principal surface side than an end portion of the first second-conductivity-type high-concentration region on the second principal surface side. The silicon carbide semiconductor device further comprises: A first conductive type high concentration region is selectively arranged inside the fourth semiconductor region at a position closer to the second main surface in the depth direction than the second second conductive type high concentration region in a manner separate from the trench and the first second conductive type high concentration region, and is opposite to and in contact with the second second conductive type high concentration region, and has an impurity concentration higher than the impurity concentration of the first semiconductor region.

2. The silicon carbide semiconductor device according to claim 1, wherein The impurity concentration of the first second conductivity type high concentration region decreases as the impurity concentration reaches the first main surface side and the second main surface side in the depth direction from the concentration peak position where the impurity concentration reaches the maximum value. An end portion of the second second-conductivity-type high-concentration region on the second principal surface side is located closer to the first principal surface than a concentration peak position of the first second-conductivity-type high-concentration region.

3. The silicon carbide semiconductor device according to claim 1, wherein An end portion of the second second-conductivity-type high-concentration region on the second principal surface side has an arc shape that is convex toward the second principal surface side.

4. The silicon carbide semiconductor device according to claim 2, wherein An end portion of the second second-conductivity-type high-concentration region on the second principal surface side has an arc shape that is convex toward the second principal surface side.

5. The silicon carbide semiconductor device according to claim 1, wherein An end portion of the second second-conductivity-type high-concentration region on the second principal surface side is located closer to the first principal surface side than an end portion of the first second-conductivity-type high-concentration region on the first principal surface side.

6. The silicon carbide semiconductor device according to claim 1, wherein An end portion of the second second-conductivity-type high-concentration region on the second main surface side is a flat surface parallel to the second main surface.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein: The distance from the end of the second main surface side of the second second conductive type high concentration region to the end of the second main surface side of the first second conductive type high concentration region is greater than the distance from the second semiconductor region to the end of the first main surface side of the first second conductive type high concentration region in the depth direction.

8. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein: A distance from the first second-conductivity-type high-concentration region to the second second-conductivity-type high-concentration region in a direction parallel to the first main surface is 1.1 μm or less.

9. The silicon carbide semiconductor device according to claim 7, wherein A distance from the first second-conductivity-type high-concentration region to the second second-conductivity-type high-concentration region in a direction parallel to the first main surface is 1.1 μm or less.

10. A method for manufacturing a silicon carbide semiconductor device, characterized in that: include: In a first step, a first semiconductor layer of the first conductivity type composed of silicon carbide having an impurity concentration lower than that of the starting substrate is deposited on a starting substrate of the first conductivity type composed of silicon carbide; In a second step, a first second conductivity type high concentration region is selectively formed in a surface area of ​​the first semiconductor layer by first ion implantation; In a third step, a first first conductivity type region is selectively formed in the surface region of the first semiconductor layer by a second ion implantation, wherein the first first conductivity type region is opposite to the first second conductivity type high concentration region in a direction parallel to the surface of the first semiconductor layer and has an impurity concentration higher than that of the first semiconductor layer; A fourth step is depositing a first conductivity type second semiconductor layer made of silicon carbide having an impurity concentration lower than that of the starting substrate on the first semiconductor layer; A fifth step is forming an ion implantation mask on the second semiconductor layer, the mask being opened at a portion facing the first first conductivity type region in a depth direction; In a sixth step, a third ion implantation is performed using the ion implantation mask as a mask to selectively form a second second conductivity type high concentration region in the surface area of ​​the second semiconductor layer so as to be separated from the first second conductivity type high concentration region. The seventh step is to remove the ion implantation mask; In an eighth step, a second first conductivity type region is selectively formed in the surface region of the second semiconductor layer by the fifth ion implantation, wherein the second first conductivity type region is opposite to the second second conductivity type high concentration region in a direction parallel to the surface of the second semiconductor layer and is in contact with the first first conductivity type region in a depth direction and has an impurity concentration higher than that of the second semiconductor layer. A ninth step is depositing a third semiconductor layer of the second conductivity type made of silicon carbide on the second semiconductor layer; as well as In a tenth step, an insulated gate structure is formed, comprising a trench and a gate electrode, wherein the trench penetrates the second semiconductor layer and reaches the first second conductivity type high concentration region, and the gate electrode is disposed inside the trench via a gate insulating film. In the sixth step, the second second conductivity type high concentration region is formed, the lower end of which is located shallower than the lower end of the first second conductivity type high concentration region. After the fifth step and before the seventh step, the method further includes: In the eleventh step, the fourth ion implantation is performed using the ion implantation mask as a mask to form a first conductive type high concentration region at a position deeper than the second second conductive type high concentration region. The first conductive type high concentration region is adjacent to the second second conductive type high concentration region in the depth direction and has an impurity concentration higher than the impurity concentration of the first first conductive type region.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein: In the sixth step, the second second conductivity type high concentration region is formed, the lower end of which is located at a position shallower than the concentration peak position of the first second conductivity type high concentration region.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein: In the eleventh step, an interface between the second second conductivity type high concentration region and the first conductivity type high concentration region is formed at a position shallower than an upper end portion of the first second conductivity type high concentration region.

13. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 10 to 12, wherein: A distance from the first second conductivity type high concentration region to the second second conductivity type high concentration region in a direction parallel to the surface of the second semiconductor layer is 1.1 μm or less.

Images