Compact three-way doherty amplifier module

Abstract

Embodiments of a method and apparatus are disclosed. In embodiments, a Doherty amplifier module includes a substrate including a mounting surface and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output faces a side of the second amplifier die including a second output. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first signal path and the second signal path.

Description

Technical Field

[0001] This disclosure generally relates to the field of wireless communications, and more specifically to a compact three-way Dougherty amplifier module. Background Technology

[0002] Wireless communication systems employ power amplifiers to amplify the power of radio frequency (RF) signals. In a wireless communication system, the power amplifier forms part of the final amplification stage in the transmission chain before the amplified signal is supplied to the antenna for radiation through the air interface. High gain, high linearity, stability, and high levels of power-added efficiency are desirable characteristics of amplifiers in such wireless communication systems.

[0003] Typically, a power amplifier operates at maximum power efficiency when its output power approaches saturation. However, power efficiency tends to deteriorate as output power decreases. Recently, the Dougherty amplifier architecture has become a focus of attention not only for base stations but also for mobile terminals because it offers high power-added efficiency over a wide power dynamic range.

[0004] The high efficiency of the Dougherty architecture makes it the desired architecture for current and next-generation wireless systems. However, this architecture presents challenges in semiconductor package design. Current Dougherty amplifier semiconductor package designs require the use of discrete devices, conductors, and integrated circuits to implement each amplification path. For example, in a three-way Dougherty architecture including a carrier amplification path, a first peak amplification path, and a second peak amplification path, each amplification path may include different power transistor IC dies along with different inductor and capacitor assemblies. These different power transistor IC dies and assemblies are kept at a distance in a typical device package to limit potential performance degradation that may occur due to signal coupling between the carrier amplifier, the first peak amplifier, and / or the second peak amplifier. More specifically, undesirable signal coupling between the carrier amplifier, the first peak amplifier, and / or the second peak amplifier can involve energy transfer between components in the carrier amplification path, the first peak amplification path, and / or the second peak amplification path through magnetic and / or electric fields associated with the signals carried on those amplification paths.

[0005] Unfortunately, the expectation of maintaining significant spatial distance between amplifier paths within the device package to reduce coupling between paths limits the possibilities for miniaturization of semiconductor packages. Given that low cost, low weight, and small volume and small printed circuit board (PCB) substrate are important attributes for a wide range of applications, limiting miniaturization is undesirable. Summary of the Invention

[0006] Embodiments of a method and apparatus are disclosed. In one embodiment, a Dougherty amplifier module includes a substrate, the substrate including a mounting surface, a first amplifier die on the mounting surface, a second amplifier die on the mounting surface, and a third amplifier die on the mounting surface. The first amplifier die includes a first input terminal proximate to a first side of the first amplifier die and a first output terminal proximate to a second side of the first amplifier die. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path to generate a first amplified RF signal at the first output terminal, the first signal path extending from the first side of the first amplifier die to the second side of the first amplifier die.

[0007] The second amplifier die includes a second input terminal near a first side of the second amplifier die and a second output terminal near a second side of the second amplifier die. The second amplifier die is configured to amplify a second RF signal along a second signal path to generate a second amplified RF signal at the second output terminal. The second signal path extends from the first side of the second amplifier die to the second side of the second amplifier die, wherein the second side of the second amplifier die faces the second side of the first amplifier die, and wherein the second signal path is parallel to the first signal path.

[0008] The third amplifier die includes a third input terminal near a first side of the third amplifier die and a third output terminal near a second side of the third amplifier die. The third amplifier die is configured to amplify a third RF signal along a third signal path to generate a third amplified RF signal at the third output terminal. The third signal path extends from the first side of the third amplifier die to the second side of the third amplifier die, wherein the third signal path is orthogonal to the first signal path and the second signal path.

[0009] In one embodiment, the Dougherty amplifier module further includes a signal combiner device located outside the first amplifier die, the second amplifier die, and the third amplifier die. The signal combiner device is situated on the mounting surface, between the first amplifier die and the second amplifier die. The signal combiner device includes a first combining node configured to combine the first amplified RF signal with at least one of the second amplified RF signal and the third amplified RF signal to produce an amplified RF output signal.

[0010] In one embodiment, the first combining node includes a first bonding pad on the signal combiner device. In this embodiment, the Dougherty amplifier module further includes a first wire bonding array coupled between the first output terminal of the first amplifier die and the first bonding pad; a second wire bonding array coupled between the second output terminal of the second amplifier die and the first bonding pad, wherein the first and second wire bonding arrays are parallel to each other; and a third wire bonding array coupled between the second output terminal of the second amplifier die and the third output terminal of the third amplifier die, wherein the third wire bonding array is orthogonal to the first and second wire bonding arrays.

[0011] In one embodiment, the signal combiner device further includes a first parallel capacitor coupled to the first bonding pad. The Dougherty amplifier module further includes a fourth lead bonding array coupled between the first bonding pad and a conductive contact on the mounting surface. The fourth lead bonding array is orthogonal to the first and second lead bonding arrays. The first parallel capacitor is configured to perform impedance transformation to match the impedance of the load to the source impedance.

[0012] In one embodiment, the signal combiner device further includes a second bonding pad and a parallel DC blocking capacitor coupled to the second bonding pad. The Dougherty amplifier module further includes a fourth lead bonding array coupled between the first output terminal of the first amplifier die and the second bonding pad. The fourth lead bonding array is substantially parallel to the first lead bonding array.

[0013] In one embodiment, the signal combiner device further includes a first parallel capacitor coupled to the first combining node.

[0014] In one embodiment, the first amplifier die includes a first power transistor, and the second amplifier die includes a second power transistor. The drain-source capacitance of the first power transistor, the inductance of the first lead-bond array, and the capacitance of the first parallel capacitor form a first quasi-transmission line, configured to perform a first phase delay and a first impedance transformation for the first amplified RF signal. The drain-source capacitance of the second power transistor, the inductance of the second lead-bond array, and the capacitance of the first parallel capacitor form a second quasi-transmission line, configured to perform a second phase delay and a second impedance transformation for at least one of the second amplified RF signal or the third amplified RF signal.

[0015] In one embodiment, the third amplifier die includes a third power transistor, wherein the drain-source capacitance of the third power transistor, the inductance of the third lead junction array, and the drain-source capacitance of the second power transistor form a third quasi-transmission line, the third quasi-transmission line being configured to perform a third phase delay and a third impedance transformation for the third amplified RF signal.

[0016] In one embodiment, the second amplifier die includes a second combining node. The second combining node is configured to combine the second amplified RF signal and the third amplified RF signal in phase to generate a combined RF signal. The first combining node is further configured to combine the first amplified RF signal and the combined RF signal in phase to generate the amplified RF output signal.

[0017] In one embodiment, the second amplifier die includes a second parallel capacitor coupled to the second output terminal of the second amplifier die. The capacitance of the second parallel capacitor is configured to adjust the second phase delay and the second impedance transformation.

[0018] In one embodiment, the Dougherty amplifier module further includes a fourth lead bonding array coupled between the third output terminal of the third amplifier die and a bonding pad of the third amplifier die. The fourth lead bonding array is orthogonal to the third lead bonding array, and the bonding pad is coupled to a parallel DC blocking capacitor.

[0019] In an embodiment, each of the first phase delay, the second phase delay, and the third phase delay is substantially 90 degrees.

[0020] In one embodiment, the Dougherty amplifier module further includes an RF power splitter coupled to the substrate. The RF power splitter is configured to receive an input RF signal and split the input RF signal into a first RF signal, a second RF signal, and a third RF signal, and transmit the first RF signal, the second RF signal, and the third RF signal to a first output terminal, a second output terminal, and a third output terminal of the RF power splitter. The first output terminal is coupled to a first phase shifter configured to impart a first 90-degree phase delay to the first RF signal, and the second output terminal is coupled to a second phase shifter configured to impart a second 90-degree phase delay to the second RF signal.

[0021] In an embodiment, the signal combiner device includes an integrated passive device, a printed circuit board (PCB), or a low-temperature co-fired ceramic (LTCC).

[0022] In one embodiment, another Dougherty amplifier module is disclosed. The Dougherty amplifier module includes a substrate, the substrate including a mounting surface, a carrier amplifier die on the mounting surface, a first peak amplifier die on the mounting surface, a signal combiner device on the mounting surface, and a second peak amplifier die on the mounting surface. The carrier amplifier die includes a first input terminal near a first side of the carrier amplifier die and a first output terminal near a second side of the carrier amplifier die.

[0023] The first peak amplifier die includes a second input terminal near a first side of the first peak amplifier die and a second output terminal near a second side of the first peak amplifier die. The second side of the first peak amplifier die faces the second side of the carrier amplifier die.

[0024] The signal combiner device includes a first combining node. The signal combiner device is located between the carrier amplifier die and the first peak amplifier die. The first output terminal of the carrier amplifier die is coupled to the first combining node via a first lead bonding array, and the second output terminal of the first peak amplifier die is coupled to the first combining node via a second lead bonding array. The first lead bonding array and the second lead bonding array are parallel to each other.

[0025] The second peak amplifier die includes a third input terminal near a first side of the second peak amplifier die and a third output terminal near a second side of the second peak amplifier die. The second side of the second peak amplifier die is orthogonal to the second side of the first peak amplifier die. The third output terminal of the second peak amplifier die is coupled to the second output terminal of the first peak amplifier die via a third lead bonding array. The third lead bonding array is orthogonal to both the first lead bonding array and the second lead bonding array.

[0026] In one embodiment, the signal combiner device includes a first parallel capacitor coupled to the first combining node. The first combining node is configured to combine the first amplified RF signal with at least one of the second amplified RF signal and the third amplified RF signal to produce an amplified RF output signal.

[0027] In one embodiment, the carrier amplifier die includes a first power transistor, and the first peak amplifier die includes a second power transistor. The drain-source capacitance of the first power transistor, the inductance of the first lead-bond array, and the capacitance of the first parallel capacitor form a first quasi-transmission line, configured to perform a first phase delay and a first impedance transformation for the first amplified RF signal. The drain-source capacitance of the second power transistor, the inductance of the second lead-bond array, and the capacitance of the first parallel capacitor form a second quasi-transmission line, configured to perform a second phase delay and a second impedance transformation for at least one of the second amplified RF signal or the third amplified RF signal.

[0028] In an embodiment, the signal combiner device includes an integrated passive device, a printed circuit board (PCB), or a low-temperature co-fired ceramic (LTCC).

[0029] In one embodiment, a method for manufacturing a Doherty amplifier module is disclosed. The method involves attaching a first amplifier die to a mounting surface of a substrate. The first amplifier die includes a first input terminal near a first side of the first amplifier die and a first output terminal near a second side of the first amplifier die. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path to generate a first amplified RF signal at the first output terminal, the first signal path extending from the first side of the first amplifier die to the second side of the first amplifier die.

[0030] The method further involves attaching a second amplifier die to the mounting surface of the substrate. The second amplifier die includes a second input terminal near a first side of the second amplifier die and a second output terminal near a second side of the second amplifier die. The second amplifier die is configured to amplify a second RF signal along a second signal path to generate a second amplified RF signal at the second output terminal. The second signal path extends from the first side of the second amplifier die to the second side of the second amplifier die. The second side of the second amplifier die faces the second side of the first amplifier die. The second signal path is parallel to the first signal path.

[0031] The method further relates to attaching a third amplifier die to the mounting surface of the substrate. The third amplifier die includes a third input terminal near a first side of the third amplifier die and a third output terminal near a second side of the third amplifier die. The third amplifier die is configured to amplify a third RF signal along a third signal path to generate a third amplified RF signal at the third output terminal, the third signal path extending from the first side of the third amplifier die to the second side of the third amplifier die. The third signal path is orthogonal to both the first and second signal paths.

[0032] In an embodiment, the method further involves attaching a signal combiner device to the mounting surface of the substrate. The signal combiner device is external to the first amplifier die, the second amplifier die, and the third amplifier die. The signal combiner device is attached to the mounting surface between the first amplifier die and the second amplifier die. The signal combiner device includes a first combining node configured to combine the first amplified RF signal with at least one of the second amplified RF signal and the third amplified RF signal to produce an amplified RF output signal.

[0033] In an embodiment, the method further involves coupling a first wire bonding array between the first output terminal of the first amplifier die and the first combination node; coupling a second wire bonding array between the second output terminal of the second amplifier die and the first combination node; and coupling a third wire bonding array between the second output terminal of the second amplifier die and the third output terminal of the third amplifier die. The first and second wire bonding arrays are parallel to each other, and the third wire bonding array is orthogonal to both the first and second wire bonding arrays.

[0034] Other aspects of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention through examples. Attached Figure Description

[0035] A more complete understanding of the subject matter can be obtained by considering the following detailed description and claims in conjunction with the accompanying drawings, wherein similar reference numerals refer to similar elements throughout the drawings.

[0036] Figure 1 A schematic diagram of a three-way Dougherty amplifier according to various embodiments of the present disclosure is depicted.

[0037] Figure 2 A schematic diagram illustrating a three-way Dougherty amplifier according to various embodiments of the present disclosure is depicted.

[0038] Figure 3 A top view of a three-way Dougherty amplifier module according to various embodiments of the present disclosure is depicted.

[0039] Figure 4 Depicting Figure 3 The module is shown in the cross-sectional side view along line 3-3.

[0040] Figure 5 An enlarged top view of a first amplifier die according to various embodiments of the present disclosure is depicted.

[0041] Figure 6 An enlarged top view of a second amplifier die according to various embodiments of the present disclosure is depicted.

[0042] Figure 7 An enlarged top view of a third amplifier die according to various embodiments of the present disclosure is depicted.

[0043] Figure 8 An enlarged top view of a signal combiner device according to various embodiments of the present disclosure is depicted.

[0044] Figure 9A and 9B This is a flowchart of a method for manufacturing a Doherty amplifier module according to various embodiments of the present disclosure. Detailed Implementation

[0045] It will be readily understood that the components of the embodiments described generally herein and illustrated in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the more detailed description of the various embodiments below, as illustrated in the drawings, is not intended to limit the scope of this disclosure, but merely to illustrate the various embodiments. While various aspects of the embodiments are presented in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0046] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments should be considered illustrative rather than restrictive in all respects. Therefore, the scope of the invention is indicated by the appended claims rather than by this specific embodiment. All modifications falling within the equivalent meaning and scope of the claims should be included within the scope of the claims.

[0047] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable using the invention should be present in or in any single embodiment of the invention. Rather, references to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the discussion of features and advantages and similar language throughout this specification may, but does not necessarily, refer to the same embodiment.

[0048] Furthermore, the features, advantages, and characteristics described in this invention can be combined in one or more embodiments in any suitable manner. Those skilled in the art will recognize that, in view of the description herein, the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be recognized in certain embodiments.

[0049] Throughout this specification, references to "an embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, refer to the same embodiment.

[0050] In a three-way Dougherty amplifier, the input signal (e.g., a radio frequency (RF) input signal) is separated at an input or power splitter between the carrier amplification path, the first peak amplification path, and the second peak amplification path. The separated signals are then amplified separately by the carrier amplifier and the peak amplifier of the Dougherty amplifier and combined at the output stage. When combining the outputs of the carrier amplifier and the peak amplifier, it may be desirable to make small adjustments to the phase and amplitude or attenuation of the input splitter of the Dougherty amplifier module to provide an optimal balance between the outputs of each path. To facilitate such adjustments, the Dougherty amplifier may include an adjustable power divider or splitter that can be used to fine-tune the configuration of the input signals to both the carrier amplifier and the peak amplifier. The Dougherty amplifier may also include adjustable phase delay and / or amplitude adjustments configured to selectively modify the phase shift and / or amplitude of one or more amplification paths of the Dougherty amplifier.

[0051] In multipath amplifiers, such as three-way Dougherty amplifiers, coupling between signal paths can adversely affect amplifier performance. Coupling can be of two types: electrical coupling (often referred to as capacitive coupling) and magnetic coupling (often referred to as inductive coupling). Inductive coupling and magnetic coupling (referred to herein as electromagnetic coupling) occur when there is a time-varying magnetic field between closely spaced current-carrying parallel conductors. For example, one type of electromagnetic coupling in a Dougherty amplifier power transistor package can occur between arrays of signal lines (e.g., lead-bonded arrays) that connect various electrical components in each amplifier path, which constitutes the carrier amplifier path and the peak amplifier path. The performance of a Dougherty amplifier can be adversely affected by electromagnetic coupling between adjacent lead-bonded arrays. Therefore, electromagnetic coupling problems have limited miniaturization efforts for Dougherty amplifiers due to the minimum spacing requirements between the carrier amplifier path and the peak amplifier path.

[0052] Figure 1 This is a schematic diagram of a Dougherty amplifier 100 (also referred to as a three-way Dougherty amplifier 100) according to an example embodiment. Some or all of the components of the Dougherty amplifier 100 may be implemented in a single device package or module. As will be explained in detail later and according to various embodiments, the orientation of the various amplifier components allows for a significant reduction in the size of the package or module compared to conventional packaging techniques, while still meeting performance standards for gain, linearity, stability, and efficiency. More specifically, this is achieved by orienting the first and second amplifier components in a head-to-head configuration and by orienting the third amplifier component in an orthogonal configuration relative to the first and second amplifier components. In an embodiment, the first amplifier component may be a carrier amplifier of the Dougherty amplifier 100, the third amplifier component may be a first peak amplifier (also referred to as peak 1 amplifier) ​​of the Dougherty amplifier 100, and the second amplifier component may be a second peak amplifier (also referred to as peak 2 amplifier) ​​of the Dougherty amplifier 100. For example, the orientation of the first and second amplifier components can allow a first signal path (e.g., signal path 111) of the first amplifier component to have an angular offset of approximately 180 degrees relative to a second signal path (e.g., signal path 121) of the second amplifier component, and the orientation of the third amplifier component can allow a third signal path (e.g., signal path 131) of the third amplifier component to have an angular offset of 90 degrees relative to the first and second signal paths. This 90-degree angular offset has the effect of reducing electromagnetic coupling between the third signal path (e.g., signal path 131) and the first and second signal paths (e.g., signal paths 111 and 121).

[0053] In an embodiment, the Dougherty amplifier 100 includes an RF input node 104, an RF output node 106, a power splitter 140, a first signal path 111, a second signal path 121, a third signal path 131, a first combination node 152 (also referred to as a first summing node), and a second combination node (also referred to as a second summing node). In an embodiment, the second combination node may be the output of a second amplifier die 120 (e.g., RF output 124). When incorporated into a larger RF system, the RF input node 104 may be coupled to an RF signal source (not shown), and the RF output node 106 may be coupled to a load 162 (e.g., a resistive load, such as an antenna) via an impedance transformer. For example, the impedance transformer may be configured to match the impedance of the load 162 (e.g., the impedance seen into the output node 106) to the source impedance of 50 Ω or other suitable impedance value. In some embodiments, the impedance transformer may be external to the Dougherty amplifier 100. Essentially, the Dougherty amplifier 100 is configured to amplify the input RF signal and produce an amplified RF output signal at the RF output node 106. Figure 1 As indicated by box 102, some or all of the components of the Dougherty amplifier 100 may be implemented in a single device package or module.

[0054] In one embodiment, power splitter 140 has an input 142 and three outputs 144, 146, and 148. Power splitter input 142 is coupled to RF input node 104 to receive an input RF signal. Power splitter 140 is configured to split the RF input signal received at input 142 into a first RF signal, a second RF signal, and a third RF signal, which are provided to a first signal path 111, a second signal path 121, and a third signal path 131 via outputs 144, 146, and 148. In some embodiments, power splitter 140 may include one or more phase-shifting elements configured to impart a phase shift (also known as a phase delay) to the signals provided at outputs 144, 146, and / or 148. For example, the phase shift may be approximately 90 degrees (e.g., a 90-degree phase delay). In some examples, an approximately 90-degree or substantially 90-degree phase shift may include a variation of ±20 degrees. In some embodiments, one or both of the phase shifters 108, 186 described herein may be implemented in the power splitter 140.

[0055] When the Dougherty amplifier 100 has a symmetrical configuration (i.e., where the first, second, and third amplifiers include a configuration of power transistors that are substantially the same size or power handling capability), the power splitter 140 can split or separate the input RF signal received at input 142 into three signals with approximately equal power. Conversely, when the Dougherty amplifier 100 has an asymmetrical configuration (i.e., where one or more of the first, second, and / or third amplifiers include a configuration of power transistors that are significantly larger than one or more power transistors in the other amplifiers), the power splitter 140 can output signals with unequal power. In some embodiments, the power splitter 140 can be implemented with a fixed-value passive component. In other embodiments, the power splitter 140 can be implemented with one or more controllable variable attenuators and / or variable phase shifters that enable the power splitter 140 to attenuate the first, second, and third RF signals and / or phase shift the first, second, and third RF signals based on an externally provided control signal.

[0056] According to an embodiment, the Dougherty amplifier 100 includes a first amplifier die 110, a second amplifier die 120, and a third amplifier die 130, and a signal combiner device 150. Each amplifier die 110, 120, 130 includes an input terminal 112, 122, 132 adjacent to a first edge of the amplifier die 110, 120, 130, and an output terminal 114, 124, 134 adjacent to a second edge of the amplifier die 110, 120, 130 opposite to (and parallel to) the first edge. One or more power transistors are electrically connected between each of the input and output terminals.

[0057] Outputs 144, 146, and 148 of power splitter 140 are connected to a first signal path 111, a second signal path 121, and a third signal path 131, respectively. As used herein, the term "signal path" refers to the path followed by an RF signal through circuitry (e.g., circuitry implemented within each amplifier die 110, 120, and 130). First signal path 111 includes a first amplifier die 110 configured to receive a first RF signal from power splitter 140 at input 112, amplify the first RF signal, and provide the amplified first RF signal at RF output 114. The amplified first RF signal is transmitted from RF output 114 to a first combination node 152 on signal combiner device 150 via a first signal line 116. In an embodiment, at least a portion of the first signal line 116 may be implemented as a wire bonding array comprising multiple parallel leads extending from bonding pads coupled to RF output 114 to bonding pads coupled to the first combination node 152. In one embodiment, the RF output terminal 114 of the first amplifier die 110 may also be coupled to a first parallel DC blocking capacitor 156 via a second signal line 117 through a terminal 154, wherein the terminal 154 and the capacitor 156 may also be implemented on the signal combiner device 150. In one embodiment, the second signal line 117 may be implemented as a wire bond or a wire bond array (e.g., multiple parallel leads) extending from the RF output terminal 114 to the terminal 154.

[0058] The second signal path 121 and the third signal path 131 are similarly configured to amplify the second RF signal and the third RF signal, respectively. More specifically, the second signal path 121 includes a second amplifier die 120, which is configured to receive the second RF signal from the power splitter 140 at input 122, amplify the second RF signal, and provide the amplified second RF signal at RF output 124. Similarly, the third signal path 131 includes a third amplifier die 130, which is configured to receive the third RF signal from the power splitter 140 at input 132, amplify the third RF signal, and provide the amplified third RF signal at RF output 134.

[0059] An amplified second RF signal and an amplified third RF signal are provided to a second combination node (e.g., a conductive node directly connected to the second amplifier die 120 of the RF output terminal 124, where "directly connected to" means in-phase with or through a negligible resistance conductive path), wherein the amplified second RF signal and the amplified third RF signal are summed in phase to generate a first combined RF signal. The amplified third RF signal can be provided from the RF output terminal 134 to the second combination node via a third signal line 136. In an embodiment, the third signal line 136 can be implemented as a wire bonding array (e.g., multiple leads) extending from a bonding pad coupled to the RF output terminal 134 to a bonding pad coupled to the second combination node. The first combined RF signal at the second combination node can be provided to the first combination node 152 via a fourth signal line 126. In some embodiments, at least a portion of the fourth signal line 126 may be implemented as a wire bonding array extending from a bonding pad coupled to the RF output terminal 124 to a bonding pad coupled to the first combination node 152.

[0060] The first combined RF signal can be combined in phase (e.g., summed) with the amplified first RF signal at the first combined node 152 to generate a second combined RF signal including signal energy from the amplified first RF signal, the amplified second RF signal, and the amplified third RF signal. Signal paths 111, 121, 131 may include or be coupled to various impedance matching elements and / or phase matching elements (e.g., capacitors 128, 138, 149, 156, 158) and phase shift elements 108, 186 (e.g., 90-degree phase shift elements) such that the second amplified RF signal and the third amplified RF signal arrive in phase with each other at the second combined node (e.g., at the RF output 124), and such that the first combined RF signal generated at the second combined node arrives in phase with the amplified first RF signal at the first combined node 152.

[0061] The first combining node 152 may be located on or within the signal combiner device 150, which is external to the first amplifier die 110, the second amplifier die 120, and the third amplifier die 130 (i.e., the signal combiner device 150 is implemented using a substrate separate from the first amplifier die 110, the second amplifier die 120, and the third amplifier die 130). The signal combiner device 150 is located (e.g., positioned on and / or coupled to) the mounting surface, between the first amplifier die 110 and the second amplifier die 120 (between RF output 114 and RF output 124). In embodiments, the signal combiner device 150 may be an integrated passive device (IPD), which may include one or more passive components (e.g., one or more resistors, one or more capacitors, one or more inductors) formed in or on a semiconductor substrate. The IPD semiconductor substrate may be different from the first amplifier die 110, the second amplifier die 120, and the third amplifier die 130. In other embodiments, the substrate of the signal combiner device 150 may be a printed circuit board (PCB) or a low-temperature co-fired ceramic (LTCC) structure including one or more passive components. As explained in detail herein, the signal combiner device 150 provides a combination node (e.g., a first combination node 152) for combining amplified RF signals output from a first amplifier die 110, a second amplifier die 120, and a third amplifier die 130. The signal combiner device 150 may have a small footprint to allow amplifier assemblies 110, 120 to be compactly placed together while minimizing or significantly reducing electromagnetic coupling between the current paths of the first amplifier die 110 and the second amplifier die 120.

[0062] As described above, along the first signal path 111, the first amplifier die 110 includes an RF input 112, an RF output 114, and one or more amplification stages coupled between the input 112 and the output 114. The RF input 112 is coupled to a first output 144 of the power splitter 140, and therefore receives a first RF signal generated by the power splitter 140. Along the second amplifier path 121, the second amplifier die 120 includes an RF input 122, an RF output 124, and one or more amplification stages coupled between the input 122 and the output 124. The RF input 122 is coupled to a second output 146 of the power splitter 140, and therefore receives a second RF signal generated by the power splitter 140. Along the third signal path 131, the third amplifier die 130 includes an RF input 132, an RF output 134, and one or more amplification stages coupled between the input 132 and the output 134. RF input 132 is coupled to the third output 148 of power splitter 140, and therefore RF input 132 receives the third RF signal generated by power splitter 140.

[0063] Each amplification stage of the first amplifier die 110 includes a power transistor. More specifically, each power transistor includes a control terminal (e.g., a gate terminal) and a first current-carrying terminal and a second current-carrying terminal (e.g., a drain terminal and a source terminal). In a single-stage device comprising a single power transistor, the control terminal is electrically connected to the RF input 112, one of the current-carrying terminals (e.g., the drain terminal or the source terminal) is electrically connected to the RF output 114, and the other current-carrying terminal (e.g., the source terminal or the drain terminal) is electrically connected to a ground reference (or another voltage reference). Conversely, a two-stage device will include two power transistors coupled in series, wherein the first transistor acts as a driver amplifier transistor providing relatively low gain amplification, and the second transistor acts as an output amplifier transistor providing relatively high gain amplification. In this embodiment, the control terminal of the driver amplifier transistor is electrically connected to the RF input 112, one of the current-carrying terminals of the driver amplifier transistor (e.g., the drain terminal or the source terminal) is electrically connected to the control terminal of the output amplifier transistor, and the other current-carrying terminal of the driver amplifier transistor (e.g., the source terminal or the drain terminal) is electrically connected to a ground reference (or another voltage reference). Additionally, one of the current-carrying terminals of the output amplifier transistor (e.g., the drain or source terminal) is electrically connected to the RF output terminal 114, and the other current-carrying terminal of the output amplifier transistor (e.g., the source or drain terminal) is electrically connected to the ground reference (or another voltage reference).

[0064] In addition to one or more power transistors, the input impedance matching network and output impedance matching network and bias circuit system ( Figure 1The portion (not shown) can also be integrally formed as part of the first amplifier die 110. Additionally, in embodiments where the first amplifier die 110 is a two-stage device, the inter-stage matching network ( Figure 1 (Not shown in the image) can also be integrally formed as part of the first amplifier die 110.

[0065] Similar to the first amplifier die 110, each amplification stage of the second amplifier die 120 includes a power transistor having a control terminal and a first current-carrying terminal and a second current-carrying terminal. One or more power transistors of the second amplifier die 120 may be electrically coupled between an RF input terminal 122 and an RF output terminal 124 in a manner similar to that described above in conjunction with the description of the first amplifier die 110. In some embodiments, the RF output terminal 124 may be coupled to a first parallel capacitor 128 included in the second amplifier die 120. Other details discussed in conjunction with the description of the first amplifier die 110 also apply to the second amplifier die 120, and for the sake of brevity, those other details will not be repeated here.

[0066] Similar to the first amplifier die 110, each amplification stage of the third amplifier die 130 includes a power transistor having a control terminal and a first current-carrying terminal and a second current-carrying terminal. One or more power transistors of the third amplifier die 130 may be electrically coupled between an RF input terminal 132 and an RF output terminal 134 in a manner similar to that described above in conjunction with the description of the first amplifier die 110. In some embodiments, the RF output terminal 134 may be coupled via a fifth signal line 135 to a second parallel DC blocking capacitor 138 included in the third amplifier die 130. The fifth signal line 135 may be implemented as a wire bonding array (e.g., multiple leads) extending from the RF output terminal 134 to a node 137 coupled to the second parallel DC blocking capacitor. In embodiments, the node 137 may be a bonding pad (e.g., Figure 3 The bonding pad 382 in the first amplifier die 110 is coupled to the end of the second parallel DC blocking capacitor. Other details discussed in conjunction with the description of the first amplifier die 110 also apply to the third amplifier die 130, and for the sake of brevity, those other details will not be repeated here.

[0067] For reference Figure 2 The second parallel capacitor 158 (also referred to herein as the second parallel capacitor C) included in the signal combiner device 150 is described in detail. OThis is used to present appropriate load impedance to each of the first amplifier die 110, the second amplifier die 120, and the third amplifier die 130. In some embodiments, a third parallel capacitor 149 (also referred to herein as the third parallel capacitor C) is included in the signal combiner device 150. Z It can be used as part of an impedance transformer network to transform the load impedance (e.g., the output load R) into a transformer network. O 162) is matched to the source impedance (e.g., 50 Ω). When the impedance of the output load 162 is low, the third parallel capacitor 149 can improve the bandwidth of the Dougherty amplifier 100. For example, the impedance of the output load 162 can be low when the output load includes large peripheral devices or when the Dougherty amplifier 100 operates at a power level further back from the peak power (e.g., a back-off level of approximately 9 dB or greater). The resulting amplified RF output signal generated by the Dougherty amplifier 100 is generated at the RF output node 106, to which the output load 162 (e.g., an antenna) is connected via transmission line 160. In some embodiments, at least a portion of the transmission line 160 can be implemented as a lead-joint array comprising multiple leads.

[0068] In an embodiment, the first amplifier die 110 may be the carrier amplifier of the Dougherty amplifier 100, the third amplifier die 130 may be the first peak amplifier (also referred to as peak 1 amplifier) ​​of the Dougherty amplifier 100, and the second amplifier die 120 may be the second peak amplifier (also referred to as peak 2 amplifier) ​​of the Dougherty amplifier 100. Therefore, the Dougherty amplifier 100 can be configured such that the first signal path 111 (also referred to as the carrier signal path) amplifies a relatively low-level input signal. As the amplitude of the input signal increases, reaching a first input power level, the third signal path 131 (also referred to as the first peak signal path) also becomes active at the first input power level. Finally, as the amplitude of the input signal increases even further, reaching a second input power level, the second signal path 121 (also referred to as the second peak signal path) also becomes active at the second input power level. For example, this can be achieved by biasing the first amplifier die 110 such that the first amplifier die 110 operates in Class AB mode, and biasing the second amplifier die 120 and the third amplifier die 130 such that the second amplifier die 120 and the third amplifier die 130 operate at different Class C bias points.

[0069] According to an embodiment, the physical components of the first signal path 111, the second signal path 121, and the third signal path 131 are oriented relative to each other such that a portion of the third signal path 131 is substantially orthogonal to corresponding portions of the first signal path 111 and the second signal path 121. For example, all or a portion of the first signal path through the first amplifier die 110 extends in a first direction (indicated by arrow 111) between the RF input terminal 112 and the RF output terminal 114; all or a portion of the second signal path through the second amplifier die 120 extends in a second direction (indicated by arrow 121) between the RF input terminal 122 and the RF output terminal 124; and all or a portion of the third signal path through the third amplifier die 130 extends in a third direction (indicated by arrow 131) between the RF input terminal 132 and the RF output terminal 134. In other words, in this embodiment, the direction of each of the first signal path 111, the second signal path 121, and the third signal path 131 is defined to be substantially parallel (or perpendicular to) a line drawn between the input and output terminals of each amplifier die 110, 120, 130. The first direction (indicated by arrow 111) and the second direction (indicated by arrow 121) may be oriented toward each other. For example, the first direction (indicated by arrow 111) may have an angular offset of approximately 180 degrees relative to the second direction (indicated by arrow 121). The third direction (indicated by arrow 131) may have an angular offset of 90 degrees relative to the first and second directions (indicated by arrows 111 and 121). In other embodiments, the third direction may be angularly separated from the first and second directions by more or less than 90 degrees.

[0070] According to an embodiment, the angular spacing between the directions of portions of the first, second, and third signal paths traversing the first amplifier die 110, the second amplifier die 120, and the third amplifier die 130 is achieved by orienting the first amplifier die 110 and the second amplifier die 120 such that the signal path between the RF input terminal 112 and the RF output terminal 114 of the first amplifier die 110 traverses the signal path between the RF input terminal 122 and the RF output terminal 124 of the second amplifier die 120. In an embodiment, the third amplifier die 130 is orthogonal to the first amplifier die 110 and the second amplifier die 120, such that the direction of the signal path through the portion of the third amplifier die 130 is orthogonal to the direction of the signal path through the portions of the first amplifier die 110 and the second amplifier die 120.

[0071] During operation, compared to a system where amplifier dies (e.g., signal paths of amplifier dies) are oriented parallel to and close to other amplifier dies, the angular separation of the signal path via the third amplifier die 130 relative to the signal paths via the first amplifier die 110 and the second amplifier die 120 reduces the amount of electromagnetic coupling between those portions of the signal paths. Given this reduction in electromagnetic coupling between the signal paths, the second amplifier die 120 and the third amplifier die 130 can be positioned closer together than in a conventional parallel orientation, while still achieving acceptable performance. Furthermore, the head-to-head configuration of the first and second amplifier dies 110, 120, as implemented using the signal combiner device 150, allows the first and second amplifier dies 110, 120 to be placed closer together than with conventional designs, while still achieving acceptable performance. Therefore, the embodiments of the various examples enable the implementation of high-performance Dougherty amplifiers in relatively small packages or modules compared to the size of a package or system used to house a conventionally arranged Dougherty amplifier.

[0072] Now refer to Figure 2 The circuit 200 shown illustrates the operation and design of the Dougherty amplifier 100. Circuit 200 represents... Figure 1 A schematic diagram of the Doherty amplifier 100. (Reference) Figure 2 Circuit 200 includes a power splitter 240, a first power transistor 210, a second power transistor 220, a third power transistor 230, and a load 262. Figure 2 In the embodiments, the first power transistor 210 may be Figure 1 The first amplifier die 110 contains the output power transistor, and the second power transistor 220 can be... Figure 1 The output power transistor in the second amplifier die 120, and the third power transistor 230 may be Figure 1 The output power transistor in the third amplifier die 130. Figure 2 In the first power transistor 210, the internal drain-source capacitance (also known as parasitic capacitance or junction capacitance) is indicated as capacitance C. ds_1 292, the internal drain-source capacitance of the second power transistor 220 is indicated as capacitance C. ds_2 294, and the internal drain-source capacitance of the third power transistor 230 is indicated as capacitance C. ds_3 296. Therefore, it should be understood that... Figure 2 The capacitor C shown ds_1 292, C ds_2 294, C ds_3296 does not represent a physical component.

[0073] like Figure 2 As shown, the output of the first power transistor 210 (e.g., the RF output terminal 114 of the first amplifier die 110) is coupled to the first combination node 252 (e.g., the first combination node 152) via an inductor L1 216 (e.g., the inductance of the first signal line 116). In an embodiment, the output of the first power transistor 210 is the drain terminal of the first power transistor 210 coupled to the first node 214. The output of the first power transistor 210 (e.g., the RF output terminal 114 of the first amplifier die 110) is coupled to the first combination node 252 (e.g., the inductance of the first signal line 116) via an inductor L1 216. sh_1 217 (e.g., the inductance of the second signal line 117) is also coupled to the first parallel DC blocking capacitor C. dc_blk 256 (e.g., the first parallel DC blocking capacitor 156).

[0074] like Figure 2 As also shown, the output of the second power transistor 220 (e.g., the RF output terminal 124 of the second amplifier die 120) is coupled to the first combination node 252 (e.g., the first combination node 152) via an inductor L2 226 (e.g., the inductance of the fourth signal line 126). In an embodiment, the output of the second power transistor 220 is coupled to the drain terminal of the second power transistor 220 at the second combination node 224. The output of the second power transistor 220 (e.g., the RF output terminal 124 of the second amplifier die 120) is also coupled to the first parallel capacitor C. sh_2 228 (e.g., the first parallel capacitor 128).

[0075] like Figure 2 As also shown, the output of the third power transistor 230 (e.g., the RF output terminal 134 of the third amplifier die 130) is coupled to the first combination node 252 (e.g., the first combination node 152) via inductor L3 236 (e.g., the inductance of the third signal line 136) and inductor L2 226 (e.g., the inductance of the fourth signal line 126). In an embodiment, the output of the third power transistor 230 is coupled to the drain terminal of the third power transistor 230 at the second node 234 (also referred to as the second combination node 234). The output of the third power transistor 230 (e.g., the RF output terminal 134 of the third amplifier die 130) is coupled to the drain terminal of the third power transistor 230 via inductor L2 226. sh_3 235 (e.g., the inductance of the fifth signal line 135) is also coupled to the second parallel DC blocking capacitor C. dc_blk 238 (e.g., a second parallel DC blocking capacitor 138).

[0076] like Figure 2 Additionally, as shown, the second parallel capacitor CO 258 (e.g., a second parallel capacitor 158) is coupled to the first combined node 252. In some embodiments, a third parallel capacitor C Z 249 (for example, Figure 1 The third parallel capacitor C Z 149) can be used as part of an impedance transformer network. For example, the third parallel capacitor C Z 249 can be configured to perform impedance transformation to transform the load (e.g., output load R) O The impedance of 162) is matched with the source impedance (e.g., 50Ω).

[0077] Power splitter 240 (e.g., power splitter 140) has input 242 (e.g., Figure 1 The input 142) and three output terminals 244, 246, 248 (e.g., Figure 1 Outputs 144, 146, and 148 (as shown in the diagram). Power splitter input 242 can receive an input RF signal and split the RF input signal into a first RF signal, a second RF signal, and a third RF signal. Power splitter 240 can provide the first RF signal from output 244 to the gate of the first power transistor 210. The first power transistor 210 can provide the amplified first RF signal to the first combination node 252. Power splitter 240 can provide the second RF signal from output 246 to the gate of the second power transistor 220. The second power transistor 220 can provide the amplified second RF signal to the second combination node 224. Power splitter 240 can provide the third RF signal from output 248 to the gate of the third power transistor 230. The third power transistor 230 can provide the amplified third RF signal to the second combination node 224. The amplified second RF signal and the amplified third RF signal can be summed in phase at the second combination node 224 to produce a combined RF signal. The combined RF signal generated at the second combination node 224 can reach the first combination node 252 in phase with the amplified first RF signal. The amplified first RF signal can be combined with the combined RF signal at the first combination node 252 to generate an amplified RF output signal. The amplified RF output signal can be provided to the load R. O 262 (for example, Figure 1 Load 162 in the load). In some embodiments, each phase shifting element in phase shifting elements 208, 286 (e.g., load 162 in the load). Figure 1 The phase shifting elements 108 and 186 in the middle can impart approximately 90 degrees of phase shift to the RF signals provided at the output terminals 244 and 246.

[0078] exist Figure 2 In the middle, capacitor Cds_1 292, Inductor L1, 216, and the second parallel capacitor C O 258 forms a first CLC network (also known as a first capacitor-inductor-capacitor network or a first Pi network). The first CLC network can be used as the output network for the first power transistor 210. In an embodiment, the first CLC network can perform both phase delay (e.g., approximately 90-degree phase delay) and impedance transformation on the first power transistor 210. Therefore, since the CLC network (e.g., the first CLC network) can replicate the phase delay and impedance transformation functions of a quarter-wavelength transmission line, the CLC network can also be referred to as a "quasi-transmission line".

[0079] In some scenarios, capacitor C ds_1 292 may not be suitable for a first CLC network to achieve proper phase delay and / or impedance matching for some high-frequency RF signals (e.g., RF signals with frequencies above 2.2 GHz). In these scenarios, inductor L sh_1 The inductor of 217 (e.g., the inductor of the second signal line 117) can be configured to resonate (e.g., reduce) the capacitance C. ds_1 At least some of the capacitors in 292 allow the first CLC network to be tuned to perform appropriate phase delay and / or impedance matching for some high-frequency RF signal energy.

[0080] In the embodiment, capacitor C ds_2 294, inductor L2, 226, and the second parallel capacitor C O 258 forms a second CLC network (also known as a second capacitor-inductor-capacitor network, a second Pi network, or a second quasi-transmission line). The second CLC network can be used as the output network for the second power transistor 220. In embodiments, the second CLC network can perform both phase delay (e.g., approximately 90-degree phase delay) and impedance transformation on the second power transistor 220. Figure 2 In the middle, the first parallel capacitor C sh_2 228 allows for capacitor C ds_2 294 is insufficient (e.g., capacitor C) ds_2 In scenarios where 294 is lower than the expected value, the second CLC network should be appropriately tuned. In an embodiment, the parallel inductor can be connected to the first parallel capacitor C. sh_2 Between 228 and the second combination node 224, it is similar to an inductor L. sh_1 217 and the first parallel DC blocking capacitor C dc_blk The arrangement of 256.

[0081] It should be noted that the second parallel capacitor C O258 is included in both the first CLC network and the second CLC network (e.g., a first quasi-transmission line and a second quasi-transmission line) described herein. In an embodiment, when performing the corresponding phase delay and / or impedance transformation functions of the first CLC network and the second CLC network, both the first CLC network and the second CLC network may simultaneously employ a second parallel capacitor C. O 258.

[0082] In the embodiment, capacitor C ds_3 296, inductor L3, 236, and capacitor C ds_2 294 forms a third CLC network (also known as a third capacitor-inductor-capacitor network, a third Pi network, or a third quasi-transmission line). The third CLC network can be used as the output network for the third power transistor 230. In embodiments, the third CLC network can perform both phase delay (e.g., approximately 90-degree phase delay) and impedance transformation on the third power transistor 230. In some scenarios, capacitor C... ds_3 296 may not be suitable for a third CLC network to achieve proper phase delay and / or impedance matching for some high-frequency RF signals (e.g., RF signals with frequencies above 2.2 GHz). In these scenarios, inductor L sh_3 The inductor of 217 (e.g., the inductor of transmission line 117) can be configured to resonate (e.g., reduce) the capacitance C. ds_3 At least some of the capacitors in 296 allow the third CLC network to be tuned to perform appropriate phase delay and / or impedance matching for some high-frequency RF signal energy.

[0083] In the embodiment, the first parallel DC blocking capacitor C dc_blk 256 can be used to further adjust the phase delay and impedance transformation of the first CLC network, and the second parallel DC blocking capacitor C dc_blk 238 can be used to further adjust the phase delay and impedance transformation of a third CLC network. For example, the first parallel DC blocking capacitor C... dc_blk 256 capacitors and inductors L sh_1 The 217 inductor can be configured to further adjust the phase delay and impedance transformation of the first CLC network. As another example, the second parallel DC blocking capacitor C... dc_blk 238 capacitors and inductors L sh_3 The 235 inductor can be configured to further adjust the phase delay and impedance transformation of the third CLC network. In an embodiment, the first parallel DC blocking capacitor C dc_blk 256 and / or a second parallel DC blocking capacitor C dc_blk238 can provide an RF cold spot (i.e., a node that acts as a virtual ground reference voltage for RF signals). For example, inductor L sh_1 217 and the first parallel DC blocking capacitor C dc_blk Node 267 between 256 and inductor L sh_3 235 and the second parallel DC blocking capacitor C dc_blk Node 277 between nodes 238 can be used as an RF cold spot. In an embodiment, one or more RF cold spots (e.g., at nodes 267, 277) can be used for baseband termination to improve video bandwidth. More specifically, baseband termination circuitry (e.g., including series-coupled inductors, capacitors, and resistors, not shown) can be coupled between each RF cold spot node 267, 277 and ground.

[0084] For reference Figure 3-8 As described, Figure 2 The inductors shown (e.g., inductor L1 216, inductor L2 226, inductor L3 236, inductor L...) sh_1 217 and inductor L sh_3 235) This can be implemented using wire bonding (also known as bonding wires or wire bonding arrays). In embodiments, using one or more wire bondings to obtain the desired inductance value can enhance the tuning and optimization flexibility of the Dougherty amplifier circuit described herein (e.g., Dougherty amplifier circuit 100). In embodiments, the inductance value of the wire bonding can be controlled by selecting an appropriate height of the loop of the wire bonding and / or the relative position of the wire bonding on the bonding pads of the device (e.g., first amplifier die 110, second amplifier die 120, third amplifier die 130, and / or signal combiner device 150). In embodiments, the wire bonding can achieve the minimum required inductance value for tuning the corresponding CLC network (e.g., the previously described first CLC network, second CLC network, and third CLC network) and can have low power loss characteristics. These benefits can be significant for applications involving high-frequency RF input signals (e.g., RF input signals with a center frequency greater than 5.0 GHz).

[0085] Now we will combine Figure 3 and 4 Detailed description reference Figure 1 and 2 An embodiment of the physical implementation of the described three-way Dougherty amplifier. More specifically, Figure 3 This is a top view of the three-way Dougherty amplifier module 300 according to an example embodiment. It should also be viewed... Figure 3 and Figure 4 , Figure 4 yes Figure 3A cross-sectional side view of the Dougherty amplifier module 300 along line 3-3. The Dougherty amplifier module 300 includes a substrate 302, a power splitter 340 (e.g., Figure 1 The power splitter 140 in the first amplifier die 310 (e.g., Figure 1 The first amplifier die 110 and the second amplifier die 320 (e.g., Figure 1 The second amplifier die 120 and the third amplifier die 330 (e.g., Figure 1 The third amplifier die 130 and the signal combiner device 350 (e.g., Figure 1 The signal combiner device 150 and various phase shifting elements 308, 386 (e.g., Figure 1 (Phase shift elements 108 and 186 in the middle).

[0086] According to an embodiment, the Dougherty amplifier module 300 is implemented as a planar grid array (LGA) module. Therefore, the substrate 302 has a component mounting surface 301 and a landing surface 388. According to an embodiment, the substrate 302 is relatively small, which provides a particularly compact Dougherty amplifier. For example, the component mounting surface 301 may have a width ranging from about 5 mm to about 20 mm. Figure 3 (horizontal dimension) and length (in the middle) Figure 3 The vertical dimension (as shown in the figure) may vary, but the width and / or length may also be smaller or larger. In a particular embodiment, for example, the component mounting surface may have a width of about 10 mm and a length of about 8 mm.

[0087] For example, substrate 302 may be a multilayer organic substrate having multiple metal layers 351, 353, 355, 357, 359 separated by a dielectric material. According to an embodiment, a bottom metal layer 361 is used to provide externally accessible conductive landing pads 387, 399 for the LGA, wherein the location of the landing pads 387, 399 is determined by… Figure 3 The dashed box indicates this. These landing pads 387, 399 (among others, not shown) enable the Dougherty amplifier module 300 to be surface-mounted onto a separate substrate (not shown) that provides electrical connections to other parts of the RF system. Although the Dougherty amplifier module 300 is depicted as an LGA module, it can alternatively be packaged as a pin grid array module, a square flat no-lead (QFN) module, or another type of package.

[0088] One or more other metal layers (e.g., layers 357, 359) on substrate 302 can be used to transmit DC voltage (e.g., DC bias voltage) and provide a ground reference. Finally, other layers (e.g., layers 353, 355) can be used to transmit RF and other signals through module 300. Additionally, a patterned metal layer 351 can be formed on mounting surface 301 of substrate 302. As will be discussed in more detail below, the patterned metal layer 351 may include a plurality of conductive contacts 304, 306, 309, 313, 315, 319, 345 on mounting surface 301, which facilitate electrical connections to the die and other components that can be mounted to mounting surface 301. Conductive vias (e.g., via 363, ...) Figure 4 Electrical connections are provided between metal layers 351-361.

[0089] Each of the amplifier dies 310, 320, and 330 can generate significant heat during operation. Additionally, each of the amplifier dies 310, 320, and 330 requires a path to a ground reference. Therefore, in this embodiment, the substrate 302 also includes a plurality of conductive and thermally conductive trenches (e.g., trenches 397, 398) to which the amplifier dies 310, 320, and 330 are coupled (e.g., using solder, brazing material, silver sintering, or other die attachment materials). The trenches (e.g., trenches 397, 398) extend through the substrate thickness in the first die mounting region 323, the second die mounting region 325, and the third die mounting region 327 to provide heat sinks and ground reference paths to the first amplifier die 310, the second amplifier die 320, and the third amplifier die 330. For example, the conductive trenches 397, 398 may be filled with copper or another thermally and electrically conductive material. In alternative embodiments, trenches 397 and 398 may be replaced by conductive blocks (e.g., copper blocks) or by thermal vias.

[0090] refer to Figure 3 A top view of module 300 shows multiple non-overlapping regions defined at the mounting surface 301 of substrate 302. More specifically, the non-overlapping regions include an input signal region 307, a first die mounting region 323, a second die mounting region 325, a third die mounting region 327, an output signal combiner region 329, and an output network region 343. Within the input signal region 307, conductive landing pads 304 exposed at the mounting surface 301 are electrically coupled via substrate 302 to conductive contacts 399 at the landing surface 388. The landing pads 304 and contacts 399, together with the electrical connection between the landing pads 304 and contacts 399, serve as the RF input node of module 300 (e.g., ...). Figure 1 (RF input node 104 in the middle).

[0091] Power splitter 340 (e.g., Figure 1 The power splitter 340 is coupled to the mounting surface 301 in the input signal region 307. According to an embodiment, the power splitter 340 may include one or more discrete dies and / or components, but the power splitter 340 is... Figure 3 The term "power splitter" is represented as a single element. The power splitter 340 includes an input terminal 305 (e.g., ...). Figure 1 The input 142) and three output terminals 344, 346, 348 (e.g., Figure 1 Outputs 344, 346, and 348 are shown in the diagram. Input 305 (e.g., via wire bonding as shown, or via a transmission line in other embodiments) is electrically coupled to conductive contact 399 to receive an input RF signal. Additionally, outputs 344, 346, and 348 (e.g., via additional wire bonding as shown) are electrically coupled to conductive contacts 309, 313, and 319 at mounting surface 301. Power splitter 340 is configured to split the power of the input RF signal received through input 305 into a first RF signal, a second RF signal, and a third RF signal, which are generated at outputs 344, 346, and 348. In some embodiments, power splitter 340 may consist of a fixed-value passive component, or power splitter 340 may include a variable phase shifter and / or attenuator.

[0092] As previously discussed, the first RF signal, the second RF signal, and the third RF signal may have equal or unequal power. The first RF signal, generated at output 344 and transmitted to conductive contact 309, is amplified via a first signal path, which includes a phase-shifting element 386 (e.g., ...) mounted within input signal region 307. Figure 1 The phase shift element 186 in the first amplifier die 310 (e.g., the first amplifier die 310 mounted in the first die mounting area 323) Figure 1 The die 110 in the middle) and the signal combiner device 350 installed in the output signal combiner area 329 (e.g., Figure 1 (Signal combiner device 150 in the middle).

[0093] The illustrated embodiment of the first amplifier die 310 embodies a two-stage amplifier, which includes an RF input 312 (e.g., Figure 1 The RF input terminal 112), input matching network 370, driver transistor 371, interstage matching network 372, output transistor 373, and RF output terminal 314 (e.g., Figure 1The first amplifier die 310 is connected in series with the first amplifier die 310 (RF output terminal 114). Driver transistor 371 and output transistor 373 apply a relatively low gain to the first RF signal, and output transistor 373 applies a relatively high gain to the first RF signal after initial amplification by driver transistor 371. In other embodiments, the first amplifier die 310 may embody a single-stage amplifier or may include more than two amplification stages. The signal path through the first amplifier die 310 extends in a direction from RF input terminal 312 toward RF output terminal 314, indicated by arrow 311.

[0094] The amplified first RF signal is generated by the first amplifier die 310 at the RF output terminal 314. According to an embodiment, the RF output terminal 314 is electrically coupled to a first bonding pad 352 on the signal combiner device 350 via a first wire bond array 316 (e.g., a plurality of parallel, closely spaced wire bonds), and additionally electrically coupled to a second bonding pad 354 on the signal combiner device 350 via second wire bond arrays 317a, 317b. Figure 3 As shown, the lead connections in the lead connection arrays 316, 317a, 317b are aligned in the same direction as the signal path through the first amplifier die 310 (e.g., in the direction indicated by arrow 311).

[0095] The RF output terminal 314 is electrically coupled to parallel capacitors 358 (e.g., second parallel capacitor 158) and 349 (e.g., third parallel capacitor 149) located in the signal combiner device 350 via the first wire bonding array 316 and the first bonding pad 352. The RF output terminal 314 is also electrically coupled to DC blocking capacitors 356a and 356b (e.g., first parallel DC blocking capacitor 156) located in the signal combiner device 350 via the second wire bonding arrays 317a and 317b and the second bonding pad 354.

[0096] Returning to the power splitter 340 in the reference input signal area 307, the second RF signal generated at the output terminal 346 of the power splitter 340 and transmitted to the conductive contact 313 is amplified through a second amplifier path, which includes a second phase shift element 308 (e.g., Figure 1 The phase shift element 108 in the middle), and the second amplifier die 320 installed in the second die mounting area 325 (e.g., Figure 1 The second amplifier die 120 in the middle) and the signal combiner device 350 installed in the output signal combiner area 329 (e.g., Figure 1 (Signal combiner device 150 in the middle).

[0097] The illustrated embodiment of the second amplifier die 320 also embodies a two-stage amplifier, which includes an RF input terminal 322 (e.g., Figure 1 RF input terminal 122), input matching network 374, driver transistor 375, inter-stage matching network 376, output transistor 377, first parallel capacitor 328 (e.g., Figure 1 The first parallel capacitor 128 in the middle Figure 2 The first parallel capacitor C in sh_2 228) and RF output 324 (e.g., Figure 1 The signal path through the second amplifier die 320 extends from the RF input 322 toward the RF output 324, as indicated by arrow 321. Figure 3 As can be seen, the signal paths through the first amplifier die 310 and the second amplifier die 320 are directed toward each other (e.g., offset by 180 degrees).

[0098] Referring again to the power splitter 340 in the input signal area 307, the third RF signal generated at the output terminal 348 of the power splitter 340 and transmitted to the conductive contact 319 is amplified through a third amplifier path, which includes a third amplifier die 330 mounted in the third die mounting area 327 (e.g., Figure 1 The third amplifier die 130), the RF output terminal 324 of the second amplifier die 320, and the signal combiner device 350 (e.g., installed in the output signal combiner area 329) are all included. Figure 1 (Signal combiner device 150 in the middle).

[0099] The illustrated embodiment of the third amplifier die 330 also embodies a two-stage amplifier, which includes an RF input 332 (e.g., Figure 1 The RF input terminal 132), input matching network 378, driver transistor 379, interstage matching network 380, output transistor 381, and RF output terminal 334 (e.g., Figure 1 The signal path through the third amplifier die 330 extends from the RF input 332 toward the RF output 334, as indicated by arrow 331. Figure 3 As can be seen, the signal path through the third amplifier die 330 is orthogonal (e.g., offset by 90 degrees) relative to the signal paths through the first amplifier die 310 and the second amplifier die 320.

[0100] In some embodiments, the first amplifier die 310, the second amplifier die 320, and the third amplifier die 330 are of the same size, thereby making the Dougherty amplifier module 300 a symmetrical Dougherty amplifier. In alternative embodiments, at least one of the first amplifier die 310, the second amplifier die 320, and the third amplifier die 330 may have a different size relative to the other amplifier dies, thereby making the Dougherty amplifier module 300 an asymmetrical Dougherty amplifier. For example, the second amplifier die 320 may be larger than the first amplifier die 310 and / or the third amplifier die 330 by a certain ratio (e.g., 1.6:1, 2:1, or some other ratio).

[0101] In the embodiment, each amplifier die 310, 320, 330 is rectangular in shape, having a parallel first side and a second side, and parallel third and fourth sides extending between the first and second sides. In each amplifier die 310, 320, 330, RF input terminals 312, 322, 332 are located near the first side of the die, and RF output terminals 314, 324, 334 are located near the second side of the die. In the embodiment and as... Figure 3 As shown, the second sides of the first amplifier die 310 and the second amplifier die 320 are oriented toward each other (e.g., head-to-head), while the second side of the amplifier die 330 is arranged orthogonally to the second sides of the first amplifier die 310 and the second amplifier die 320. In other words, the third amplifier die 330 is coupled to the mounting surface 301 of the substrate 302 such that the third amplifier die 330 is orthogonal to the first amplifier die 310 and the second amplifier die 320, such that the RF signal path through the third amplifier die 330 is orthogonal to the RF signal paths through the first amplifier die 310 and the second amplifier die 320.

[0102] The orthogonal orientation of the third amplifier die 330 relative to the first amplifier die 310 and the second amplifier die 320 can significantly reduce the electromagnetic coupling between the signal paths of the third amplifier die 330 and the signal paths of the first amplifier die 310 and the second amplifier die 320. Given this reduction in electromagnetic coupling between signal paths, the second amplifier die 320 and the third amplifier die 330 can be positioned closer together than in a conventional parallel orientation, while still achieving acceptable performance. Furthermore, the head-to-head configuration of the first amplifier die 310 and the second amplifier die 320, as implemented using the signal combiner device 350, allows the first amplifier die 310 and the second amplifier die 320 to be placed closer together than in a conventional orientation, while still achieving acceptable performance.

[0103] The amplified second RF signal is generated by the second amplifier die 320 at the RF output terminal 324 (e.g., the RF output terminal 124 of the second amplifier die 120). According to an embodiment, the RF output terminal 324 is electrically coupled to the first bonding pad 352 via a third lead bonding array 326 (e.g., a plurality of parallel, closely spaced lead bondings) and additionally coupled to a first parallel capacitor 328 (e.g., the first parallel capacitor 128).

[0104] like Figure 3 As shown, the wire bonds in the wire bond array 326 are aligned in the same direction as the signal path through the second amplifier die 320 (e.g., in the direction indicated by arrow 321). The RF output terminal 324 is electrically coupled to a second parallel capacitor 358 (e.g., second parallel capacitor 158) and a parallel capacitor 349 (e.g., third parallel capacitor 149) located in the signal combiner device 350 via the third wire bond array 326 and the first bonding pad 352.

[0105] The amplified third RF signal is generated by the third amplifier die 330 at the RF output terminal 334. According to an embodiment, the RF output terminal 334 utilizes a fourth lead bonding array 336 (e.g., Figure 1 The third signal line 136 is electrically coupled to the RF output terminal 324 of the second amplifier die 320, and additionally uses the fifth lead to connect the array 335 (e.g., Figure 1 The fifth signal line 135 is coupled to the bonding pad 382. For example... Figure 3 As shown, the wire bonds in the fourth wire bond array 336 are aligned in the same direction as the RF signal path through the third amplifier die 330 (e.g., in the direction indicated by arrow 331). In other words, the fourth wire bond array 336 is orthogonal to the first wire bond array 316, the second wire bond arrays 317a, 317b, and the third wire bond array 326. Therefore, even though the third and fourth wire bond arrays 326 are positioned relatively close together, their orthogonal orientation can significantly reduce electromagnetic coupling of the RF signals carried by them. The amplified third RF signal generated by the third amplifier die 330 and the amplified second RF signal generated by the second amplifier die 320 can be combined at the RF output terminal 324 of the second amplifier die 320 (e.g., the second combination node 224). The bonding pad 382 can be coupled to one or more parallel DC blocking capacitors 383 (e.g., Figure 1 The second parallel DC blocking capacitor 138 in the middle.

[0106] In an embodiment, during operation of module 300, a first combining node (e.g., co-located with or directly electrically coupled to the first bonding pad 352) can combine (e.g., sum) an amplified first RF signal with a second amplified RF signal and / or a third amplified RF signal to produce an amplified RF output signal. In an embodiment, the first combining node (e.g., the first bonding pad 352) can combine the amplified first RF signal with the combined signal, wherein the combined signal is a combination of the second amplified RF signal and the third amplified RF signal, as described below.

[0107] Compared to conventional implementations, the signal combiner device 350 can reduce electromagnetic coupling between the signal path (e.g., direction 311) through the first amplifier die 310 and the signal path (e.g., direction 321) through the second amplifier die 320. For example, an amplified first RF signal can flow out of the first amplifier die 310 and through the wire bond 316 to the first bonding pad 352. The amplified first RF signal can then flow along direction 331 towards the wire bond 385 on the first bonding pad 352. An amplified second RF signal and / or an amplified third RF signal can flow out of the RF output terminal 324 and through the wire bond 326 to the first bonding pad 352. The amplified second RF signal and / or the amplified third RF signal can then flow along direction 331 towards the wire bond 385 on the first bonding pad 352. The width 892 of the first bonding pad 352 is sufficient to significantly reduce the electromagnetic coupling between the amplified first RF signal flowing out of the first amplifier die 310 and the amplified second RF signal and / or the amplified third RF signal flowing out of the RF output terminal 324.

[0108] In some embodiments of the signal combiner device 350, the return path electrode (e.g., ground plane) in the signal combiner device 350 can be closer to the top metal signal layer (e.g., first bonding pad 352) compared to the proximity between the return path electrode (e.g., ground plane) in the substrate 302 and the combination node (e.g., conductive contact) on the mounting surface 301 of the substrate 302. Therefore, because the return path electrode in the signal combiner device 350 can be closer to the top metal signal layer in the signal combiner device 350, the signal combiner device 350 can reduce interference between proximity signal paths. Consequently, the signal combiner device 350 can provide an additional reduction in electromagnetic coupling between the amplified first RF signal and the amplified second RF signal and / or the amplified third RF signal.

[0109] although Figure 3Not shown, but module 300 also includes a bias circuitry configured to provide gate and drain bias voltages to some or all of the driver and output transistors 371, 373, 375, 377, 379, 381. For example, among other things, the bias circuitry may include multiple landing pads (at landing surface 388 of substrate 302), contacts (at mounting surface 301 of substrate 302), and other conductive structures and circuitry. The bias voltages provided to the gates and / or drains of transistors 371, 373, 375, 377, 379, 381 facilitate Dougherty operation of module 300. For example, transistors 371 and 373 of the first amplifier die 310 may be biased to operate in Class AB mode, and transistors 375, 377, 379, 381 of the second amplifier die 320 and the third amplifier die 330 may be biased to operate in Class C mode.

[0110] According to an embodiment, all components mounted to the mounting surface 301 of the substrate 302 can be encapsulated with a non-conductive encapsulating material 303. Figure 3 The component is encapsulated. In an alternative embodiment, the component may be contained within an air cavity defined by various structures (not shown) covering the mounting surface 301.

[0111] The first amplifier die 310, the second amplifier die 320, and the third amplifier die 330 can be implemented using various types of semiconductor substrates, such as silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), gallium arsenide (GaA), gallium nitride (GaN), GaN-on-silicon carbide, GaN-on-silicon, or other types of substrate materials. Furthermore, each of the transistors 371, 373, 375, 377, 379, and 381 in the first amplifier die 310, the second amplifier die 320, and the third amplifier die 330 can be a field-effect transistor (FET) (such as a metal-oxide-semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), etc.), wherein the FET includes a gate (control terminal), a source (first current conduction terminal), and a drain (second current conduction terminal). Alternatively, each of the transistors 371, 373, 375, 377, 379, and 381 can be a bipolar junction transistor (BJT). The references to “gate,” “drain,” and “source” commonly used to describe FETs in this document are not intended to be restrictive, as each of these names has similar characteristics for BJT implementations (e.g., base, collector, and emitter, respectively).

[0112] Various modifications can be made to module 300 without departing from the scope of the subject matter of this invention. For example, although in Figure 4 The intermediate substrate 302 is depicted as comprising five metal layers 353-361, but alternatively, a substrate comprising more or fewer metal layers may be used. Additionally, other types of substrates, including ceramic substrates or other types of substrates, may be used. Furthermore, alternative embodiments may include power splitters and / or amplifier dies configured as flip chips. In such embodiments, some or all of the wire bonding arrays (including wire bonding arrays 316, 317a, 317b, 326, 336) may be replaced by conductive traces and other structures in and on the substrate 302. Additionally, the first amplifier die 310, the second amplifier die 320, and the third amplifier die 330 may include single-stage amplifiers. In other embodiments, two different amplifier dies (a driver amplifier die and an output / final stage amplifier die) may be implemented along each path 311, 321, 331. In such embodiments, hybrid technologies can be implemented for both dies (e.g., the driver die can be silicon-based (e.g., LDMOS), and the output / final stage amplifier die can be GaN-based, or vice versa). In addition to the foregoing, module 300 may also include various discrete and / or integrated components (e.g., capacitors, inductors, and / or resistors) electrically coupled to phase shift elements 308, 386 to provide the desired impedance transformation.

[0113] Figure 5 An enlarged top view of the first amplifier die 310 is depicted. (As previously illustrated...) Figure 3 The electrical components of the first amplifier die 310 discussed include an RF input terminal 312, an input matching network 370, a driver transistor 371, an interstage matching network 372, an output transistor 373, and an RF output terminal 314. The first amplifier die 310 may have a parallel first die side 502 and a second die side 503, and parallel third die side 504 and fourth die side 505 extending between the first die side 502 and the second die side 503.

[0114] According to an embodiment, the RF input terminal 312 is configured such that an array or plurality of lead contacts 364 can be coupled to the RF input terminal 312 parallel to each other, such that the lead contacts 364 extend in a direction parallel to (e.g., direction 311) the direction of the signal path through the first amplifier die 310. More specifically, the RF input terminal 312 includes an elongated conductive pad 547 adjacent to a first side 502 of the first amplifier die 310, and the conductive pad 547 has a length extending parallel to the first side 502 of the first amplifier die 310. According to an embodiment, the length of the pad 547 is large enough that a plurality of lead contacts (e.g., 2 to 10 or more) can be connected in parallel to each other along the length of the pad 547. Figure 5 As shown, the length of the pad 547 is large enough to allow the plurality of wire connections 364 to be connected, such that the plurality of wire connections 364 can extend from the side 502 in a vertical direction.

[0115] The RF input terminal 312 of the first amplifier die 310 is electrically coupled to the gate terminal 565 of the transistor 371 via an input matching network 370, and the drain terminal 567 of the transistor 371 is electrically coupled to the gate terminal 593 of the transistor 373 via an interstage matching network 372. Therefore, the signal path through the first amplifier die 310 extends from the first side 502 toward the second side 503 or from the RF input terminal 312 toward the RF output terminal 314, the direction indicated by arrow 311.

[0116] exist Figure 5 In the RF output terminal 314, there is an elongated pad 514 and three sets of lead terminals 317a, 317b, and 326 connected in parallel to each other along a length 589 of the elongated pad 514. Figure 5In this embodiment, each set of wire contacts 317a, 317b comprises two wire contacts, and the set of wire contacts 326 comprises eight wire contacts. In an alternative embodiment, the length 589 may be sufficient to allow more (e.g., 13 or more) wire contacts to be connected in parallel along the length 589 of the elongated pad 514. According to embodiments, the length 589 may range from about 800 micrometers to about 1800 micrometers, or more preferably from 800 micrometers to about 1400 micrometers, but the length may also be smaller or larger. In some embodiments, the width 592 of the elongated pad 514 may range from about 100 micrometers to about 150 micrometers. In other examples, the width 592 may be less than 100 micrometers or greater than 150 micrometers. The pad 514 is “elongated” as used herein because the length 589 of the pad 514 is significantly greater than the width 592 of the pad 514 (e.g., at least three times larger). In one embodiment, an elongated pad 514 is close to the second side 503 of the first amplifier die 310, and the length 589 of the pad 514 is parallel to the second side 503.

[0117] As used herein, a conductive “pad” refers to a conductive feature of a die that is exposed on the surface of the die and configured to accept direct connection to an electrical conductor other than the die itself (e.g., wire bonding, solder bonding, etc.). As used herein, when referring to the relative positioning of a pad (e.g., pads 514, 547) relative to a side (e.g., sides 502-505), the term “proximate to” can mean that the pad is within 100 micrometers of said side. In some embodiments, conductive, active, or passive components integrated within the die without significant intervention are positioned between the pad and the side it is proximate to. In other embodiments, the pad may be considered proximate to said side even if one or more conductive, active, and / or passive components exist between the pad and a side. Alternatively, when referring to the relative positioning of a pad relative to a side, “proximate” can mean that the pad is within the previously defined wire bonding length of said side it is proximate to.

[0118] Driver transistor 371 and output transistor 373 are coupled in series between RF input terminal 312 and RF output terminal 314, wherein driver transistor 371 is configured to apply a relatively low gain to a first RF signal (e.g., a carrier signal), and output transistor 373 is configured to apply a relatively high gain to the first RF signal after initial amplification by driver transistor 371. In the illustrated embodiment, each of transistors 371, 373 includes interleaved source and drain "fingers" (i.e., elongated source and drain regions in and near the upper surface of the first amplifier die 310), wherein gate terminals 565, 593 (control terminals) are interleaved with the source and drain fingers. Each gate terminal 565, 593 consists of a set of elongated conductive gate terminal fingers and a common conductive gate strip interconnecting the gate terminal fingers. Drain terminals 314, 567 (current conduction terminals) carry current from the drain regions of transistors 371, 373. Similar to gate terminals 565 and 593, each drain terminal 314 and 567 can consist of a set of elongated conductive drain terminal fingers (interlaced with the gate terminal fingers) along with a common conductive drain strip interconnecting the drain terminal fingers. Although in Figure 5 Various numbers of gate and drain fingers are shown, but devices may include more or fewer fingers, and / or transistors may have structures other than the interlaced finger structures discussed herein.

[0119] Figure 6 An enlarged top view of the second amplifier die 320 is depicted. (As previously combined...) Figure 3 The electrical components of the second amplifier die 320 discussed include an RF input terminal 322, an input matching network 374, a driver transistor 375, an interstage matching network 376, an output transistor 377, and an RF output terminal 324. The second amplifier die 320 may have parallel first die sides 602 and second die sides 603, and parallel third die sides 604 and fourth die sides 605 extending between the first die side 602 and the second die side 603.

[0120] According to an embodiment, the RF output terminal 324 has an "L" shape, such as... Figure 6As shown, the L-shape includes a first orthogonally arranged pad 624 and a second orthogonally arranged pad 690. Specifically, the RF output terminal 324 is uniquely configured such that an array or plurality of lead contacts 336 can be coupled parallel to each other to the RF output terminal 324, such that the lead contacts 336 extend in a direction orthogonal (perpendicular) to the direction of the signal path through the second amplifier die 320 (e.g., direction 321) (e.g., direction 341). More specifically, the RF output terminal 324 includes an elongated conductive side pad 690 adjacent to the third side 604 of the second amplifier die 320, and the conductive side pad 690 has a length 691 extending parallel to the third side 604 of the second amplifier die 320. According to an embodiment, the length 691 of the side pad 690 is large enough that a plurality of lead contacts (e.g., 2 to 10 or more) can be connected in parallel to each other along the first length of the side pad 690. Figure 6 As shown, the length 691 of the side pad 690 is large enough to allow the plurality of lead connections 336 to be connected, such that the plurality of lead connections 336 can extend vertically from the side 604. The side pad 690 also has a width 694, which is sufficient to couple at least one row of lead connections 336 to the side pad 690. For example, the width 694 can range from about 100 micrometers to about 150 micrometers, but the width can also be smaller or larger.

[0121] In addition to the side pad 690, the RF output terminal 324 may include an elongated second pad 624 electrically coupled to the elongated side pad 690. The first pad 624 and the second pad 690 may form part of a single pad (e.g., an L-shaped pad as shown), or the first pad 624 and the second pad 690 may be separate pads. Either way, in this embodiment, the elongated second pad 624 is adjacent to the second side 603 of the second amplifier die 320, and the elongated second pad 624 has a length 689 extending parallel to the second side 603. According to an embodiment, the side pad 690 and the second pad 624 have lengths 691 and 689 perpendicular to each other. The length 689 of the second pad 624 is large enough that a second plurality of lead connections 326 can be connected in parallel along the length 689 of the second pad 624. Figure 6 As shown, the length 689 of the second pad 624 is large enough to allow the plurality of wire connections 326 to be connected, such that the plurality of wire connections 326 can extend from the side 603 in a vertical direction. Figure 6Ten wire bonds 326 connected in parallel to each other are shown. In an alternative embodiment, the length 689 may be sufficient to allow more (e.g., 11 or more) wire bonds to be connected in parallel along the length 689 of the second pad 624. According to embodiments, the length 689 may range from about 800 micrometers to about 1800 micrometers, or more preferably from 800 micrometers to about 1400 micrometers, but the length may also be smaller or larger.

[0122] The second pad 624 has a width 692, which is sufficient to allow at least one row of lead joints 326 to be coupled to the second pad 624. For example, the width 692 can range from about 100 micrometers to about 500 micrometers, but the width can also be smaller or larger.

[0123] As clearly described above, bonding pad 324 can serve as a combination node for amplified RF signals from amplifier dies 320, 330 (e.g., Figure 1 , 2 (Nodes 124, 224). In other embodiments, the pads 624, 690 implementing the first bonding pad 324 may be separate pads electrically coupled together to act as a combined node.

[0124] The RF input terminal 322 of the second amplifier die 320 is electrically coupled to the gate terminal 665 of the transistor 375 via an input matching network 374, and the drain terminal 667 of the transistor 375 is electrically coupled to the gate terminal 693 of the transistor 377 via an interstage matching network 376. Therefore, the signal path through the second amplifier die 320 extends from the first side 602 toward the second side 603 or from the RF input terminal 322 toward the RF output terminal 324, the direction indicated by arrow 321.

[0125] Driver transistor 375 and output transistor 377 are coupled in series between RF input 322 and RF output 324, wherein driver transistor 375 is configured to apply a relatively low gain to a second RF signal (e.g., a second peak signal), and output transistor 377 is configured to apply a relatively high gain to the second RF signal after initial amplification by driver transistor 375. In the illustrated embodiment, each of transistors 375, 377 includes interleaved source and drain "fingers" (i.e., elongated source and drain regions in and near the upper surface of the second amplifier die 320), wherein gate terminals 665, 693 (control terminals) are interleaved with the source and drain fingers. Each gate terminal 665, 693 consists of a set of elongated conductive gate terminal fingers and a common conductive gate strip interconnecting the gate terminal fingers. Drain terminals 324 and 667 (current conduction terminals) carry current from the drain regions of transistors 377 and 375. Similar to gate terminals 665 and 693, each drain terminal 324 and 667 can consist of a set of elongated conductive drain terminal fingers (interlaced with the gate terminal fingers) along with a common conductive drain strip interconnecting the drain terminal fingers. Although in Figure 6 Various numbers of gate and drain fingers are shown, but devices may include more or fewer fingers, and / or transistors may have structures other than the interlaced finger structures discussed herein.

[0126] Figure 7 An enlarged top view of the third amplifier die 330 is depicted. (As previously combined...) Figure 3 The electrical components of the third amplifier die 330 discussed include an RF input terminal 332, an input matching network 378, a driver transistor 379, an interstage matching network 380, an output transistor 381, and an RF output terminal 334. The third amplifier die 330 may have a parallel first die side 702 and a second die side 703, and parallel third die side 704 and fourth die side 705 extending between the first die side 702 and the second die side 703.

[0127] According to an embodiment, the RF output terminal 334 has an "L" shape, such as Figure 7As shown, the L-shape includes a first orthogonally arranged pad 734 and a second orthogonally arranged pad 790. Specifically, the RF input 332 is configured such that an array or plurality of lead contacts 366 can be coupled parallel to each other to the RF input 332, such that the lead contacts 366 extend in a direction parallel to (e.g., direction 331) the direction of the signal path through the third amplifier die 330. More specifically, the RF input 332 includes an elongated conductive pad 747 adjacent to a first side 702 of the third amplifier die 330, and the conductive pad 747 has a length extending parallel to the first side 702 of the third amplifier die 330. According to an embodiment, the length of the pad 747 is large enough that a plurality of lead contacts (e.g., 2 to 10 or more) can be connected in parallel to each other along the length of the pad 747. Figure 7 As shown, the length of the pad 747 is large enough to allow the plurality of wire connections 366 to be connected, such that the plurality of wire connections 366 can extend from the side 702 in a vertical direction.

[0128] The RF input terminal 332 of the third amplifier die 330 is electrically coupled to the gate terminal 765 of the transistor 379 via an input matching network 378, and the drain terminal 767 of the transistor 379 is electrically coupled to the gate terminal 793 of the transistor 381 via an interstage matching network 380. Therefore, the signal path through the third amplifier die 330 extends from the first side 702 toward the second side 703 or from the RF input terminal 332 toward the RF output terminal 334, as indicated by arrow 331.

[0129] The RF output terminal 334 includes an elongated conductive side pad 790 adjacent to the fourth side 705 of the third amplifier die 330, and the conductive side pad 790 has a length 791 extending parallel to the fourth side 705 of the third amplifier die 330. According to an embodiment, the length 791 of the side pad 790 is large enough that multiple lead connections (e.g., 2 to 10 or more) can be connected in parallel with each other along the length 791 of the side pad 790. Figure 7 As shown, the length 791 of the side pad 790 is large enough to allow the plurality of leads to be joined 335 (e.g., Figure 1 The fifth signal line 135 can extend vertically relative to the fourth side 705. Wire bond 335 can electrically couple side pad 790 to pad 382. As described herein, pad 382 can be electrically coupled to one or more parallel DC blocking capacitors 383 (e.g., Figure 1The second parallel DC blocking capacitor 138 is shown. The side pad 790 also has a width 794, sufficient to allow at least one row of lead connections 335 to be electrically coupled to the side pad 790. For example, the width 794 can range from about 100 micrometers to about 150 micrometers, but it can also be smaller or larger. In the illustrated embodiment, the parallel DC blocking capacitor 383 is integrally formed with the third amplifier die 330. In other embodiments, the parallel DC blocking capacitor 383 can be implemented in different devices. Additionally, in some embodiments, the lead connections 335 can be replaced with one or more integrated spiral inductors.

[0130] In addition to the side pad 790, the RF output terminal 334 may include an elongated second pad 734 electrically coupled to the elongated side pad 790. The first pad 734 and the second pad 790 may form part of a single pad (e.g., an L-shaped pad as shown), or the first pad 734 and the second pad 790 may be separate pads. In either case, in the embodiment, the elongated second pad 734 is adjacent to the second side 703 of the third amplifier die 330, and the elongated second pad 734 has a length 789 extending parallel to the second side 703. According to an embodiment, the side pad 790 and the second pad 734 have lengths 791, 789 perpendicular to each other. The length 789 of the second pad 734 is large enough that a second plurality of lead junctions 336 (e.g., ...) Figure 1 The third signal line 136 in the middle can be connected in parallel along the length 789 of the second pad 734. For example... Figure 7 As shown, the length 789 of the second pad 734 is large enough to allow the plurality of wire connections 336 to be connected, such that the plurality of wire connections 336 can extend from the side 703 in a vertical direction. Figure 7 Ten wire bonds 336 connected in parallel to each other are shown. In an alternative embodiment, the length 789 may be sufficient to allow more (e.g., 11 or more) wire bonds to be connected in parallel along the length 789 of the second pad 734. According to embodiments, the length 789 may range from about 800 micrometers to about 1800 micrometers, or more preferably from 800 micrometers to about 1400 micrometers, but the length may also be smaller or larger. The second pad 734 has a width 796 sufficient to couple at least one row of wire bonds 336 to the second pad 734. For example, the width 796 may range from about 100 micrometers to about 150 micrometers, but the width may also be smaller or larger.

[0131] Driver transistor 379 and output transistor 381 are coupled in series between RF input 332 and RF output 334, wherein driver transistor 379 is configured to apply a relatively low gain to a third RF signal (e.g., a second peak signal), and output transistor 381 is configured to apply a relatively high gain to the third RF signal after initial amplification by driver transistor 379. In the illustrated embodiment, each of transistors 379 and 381 includes interleaved source and drain "fingers" (i.e., elongated source and drain regions in and near the upper surface of the third amplifier die 330), wherein gate terminals 765 and 793 (control terminals) are interleaved with the source and drain fingers. Each gate terminal 765 and 793 consists of a set of elongated conductive gate terminal fingers and a common conductive gate strip interconnecting the gate terminal fingers. Drain terminals 334 and 767 (current conduction terminals) carry current from the drain regions of transistors 381 and 379. Similar to gate terminals 765 and 793, each drain terminal 334 and 767 can consist of a set of elongated conductive drain terminal fingers (interlaced with the gate terminal fingers) along with a common conductive drain strip interconnecting the drain terminal fingers. Although in Figure 7 Various numbers of gate and drain fingers are shown, but devices may include more or fewer fingers, and / or transistors may have structures other than the interlaced finger structures discussed herein.

[0132] Figure 8 An enlarged top view of a signal combiner device 350 according to an example embodiment is depicted. (As previously illustrated...) Figure 3 The electrical components of the signal combiner device 350 discussed include a second parallel capacitor 358 and a third parallel capacitor 349, as well as parallel DC blocking capacitors 356a and 356b. The signal combiner device 350 further includes a first bonding pad 352 electrically coupled to a first end of the second parallel capacitor 358 and the third parallel capacitor 349, and a second bonding pad 354 electrically coupled to a first end of the parallel DC blocking capacitors 356a and 356b. A second end of each of the capacitors 349, 356a, 356b, and 358 is electrically coupled to a ground reference node (e.g., using a substrate via extending to the bottom surface of the signal combiner device 350). The signal combiner device 350 may have parallel first sides 802 and second sides 803, and parallel third sides 804 and fourth sides 805 extending between the first side 802 and the second side 803. The first bonding pad 352 may have a parallel first pad side 802-1 and a second pad side 803-1, and a parallel third pad side 804-1 and a fourth pad side 805-1 extending between the first pad side 802-1 and the second pad side 803-1.

[0133] According to an embodiment, the first bonding pad 352 is configured such that an array or plurality of lead contacts 316 can be coupled parallel to each other to the first bonding pad 352, such that the lead contacts 316 extend in a direction (e.g., direction 321) parallel to the direction of the signal path through the first amplifier die 310 (e.g., direction 311). Figure 8 As shown, the wire bond 316 is connected to the third pad side 804_1 adjacent to the first bonding pad 352. It should be noted that the wire bond 316 does not contact the second bonding pad 354 of the signal combiner device 350. In an embodiment, the first bonding pad 352 has a length 890 extending parallel to the fourth side 805 and is large enough that multiple wire bonds (e.g., 2 to 10 or more) can be connected in parallel to each other along the length 890 of the first bonding pad 352. Figure 8 As shown, the length of the pad 890 is large enough to allow the plurality of lead joints 316 to be connected, such that the plurality of lead joints 316 can extend from the side 804 in a vertical direction.

[0134] The first bonding pad 352 has a width 892, which is large enough to allow another array or plurality of wire bonds 326 to be coupled parallel to each other to the first bonding pad 352, such that the wire bonds 326 extend in a direction (e.g., direction 311) parallel to the direction of the signal path through the second amplifier die 320 (e.g., direction 321). The wire bonds 326 are connected to a fourth pad side 805_1 adjacent to the first bonding pad 352. Figure 8 As shown, the length of the pad 890 is large enough to allow the plurality of wire connections 326 to be connected, such that the plurality of wire connections 326 can extend from the side 805 in a vertical direction. Figure 8 In this embodiment, wire bond 316 includes eight wire bonds, and wire bond 326 includes ten wire bonds. In an alternative embodiment, the length 890 may be sufficient to allow more (e.g., 11 or more) wire bonds to be connected in parallel along the length 890 of the first bonding pad 352. According to embodiments, the length 890 may range from about 800 micrometers to about 1800 micrometers, or more preferably from 800 micrometers to about 1400 micrometers, but the length may also be smaller or larger. In some embodiments, the width 892 may range from about 300 micrometers to about 450 micrometers. In other examples, the width 892 may be less than 300 micrometers or greater than 450 micrometers.

[0135] In an embodiment, the width 892 of the first bonding pad 352 is large enough to allow another array or plurality of wire bonds 385 to be coupled parallel to each other to the first bonding pad 352, such that the wire bonds 385 extend in a direction orthogonal (e.g., perpendicular) to the direction of the signal path through the first amplifier die 310 (e.g., direction 311) and the direction of the signal path through the second amplifier die 320 (e.g., direction 321) (e.g., direction 331). The wire bonds 385 are connected to be close to the second pad side 803_1 of the first bonding pad 352 and close to the second device side 803 of the signal combiner device 350. Figure 8 As shown, the length 890 and width 892 of the first bonding pad 352 are large enough to accommodate the wire bonds 316, 326, and also allow the plurality of wire bonds 385 to be connected, such that the plurality of wire bonds 385 can extend from the side 803 in a vertical direction. Figure 8 In this embodiment, lead joint 385 includes four lead joints. In an alternative embodiment, the width 892 may be sufficient to allow more (e.g., five or more) lead joints to be connected in parallel along the width 892 of the first bonding pad 352.

[0136] although Figure 8 The first bonding pad 352 is shown as rectangular and has a length 890 and a width 892 sufficient to couple three sets of wire bonds 316, 326, and 385 to it. However, in other embodiments, the function of the first bonding pad 352 may be implemented in different ways. For example, an alternative embodiment may use an inverted U-shaped bonding pad instead of the bonding pad 352, wherein the first leg of the bonding pad is configured for attachment of the wire bond 316, the second leg of the bonding pad is configured for attachment of the wire bond 326, and the span of the bonding pad between the first leg and the second leg is configured for attachment of the wire bond 385. In still other embodiments, the first leg, the second leg, and / or the span may be implemented as separate bonding pads electrically connected together within the signal combiner device 350 by various conductive structures (e.g., patterned conductive traces and conductive vias). As clearly described above, in some embodiments, the first bonding pad 352 can act as a composite node (e.g., Figure 1 , 2 (Nodes 152, 252 in the original text), but in other embodiments, the first bonding pad 352 and / or alternative bonding pads that provide the same function may be electrically coupled together to act as a combined node.

[0137] According to an embodiment, a second bonding pad 354 is located on a third side 804 adjacent to the signal combiner device 350. The second bonding pad 354 is configured such that an array or plurality of lead contacts 317a, 317b can be coupled parallel to each other to the second bonding pad 354, such that the lead contacts 317a, 317b extend in a direction (e.g., direction 321) parallel to the direction of the signal path through the first amplifier die 310 (e.g., direction 311). The lead contacts 317a, 317b are connected to the third side 804 adjacent to the device 350. In an embodiment, the second bonding pad 354 also has a length 890 extending parallel to the third side 804 and is large enough that a plurality of lead contacts (e.g., 2 to 10 or more) can be connected in parallel to each other along the length 890 of the second bonding pad 354. Figure 8 As shown, the length 890 of the pad is large enough to allow the plurality of lead joints 317a, 317b to be connected, such that the plurality of lead joints 317a, 317b can extend from the side 804 in a vertical direction.

[0138] At the signal combiner device 350, the orthogonal arrangement of wire bond 385 relative to wire bonds 316, 317a, 317b, 385, and 326 significantly reduces electromagnetic coupling between wire bond 385 and wire bonds 316, 317a, 317b, 385, and 326. Therefore, wire bond 385 can be located near wire bonds 316, 317a, 317b, 385, and 326, allowing the first bonding pad 352 (and the signal combiner device 350) to maintain a compact size.

[0139] In some embodiments, reference Figure 3-8 Some or all of the described wire connections may be wire connections with a high Q factor to limit RF signal combination loss. In some embodiments, references Figure 1-8 The described parallel capacitor can have a high Q factor to limit RF signal combination losses. In some embodiments, reference... Figure 1-8 Some or all of the described parallel capacitors may be metal-insulating metal (MIM) capacitors. In other embodiments, some or all of the parallel capacitors may be implemented as discrete devices coupled to the upper surface of dies 310, 320, 330, device 350, or substrate 302.

[0140] The embodiments described herein can significantly reduce the footprint of a three-way Dougherty amplifier layout while increasing design flexibility and circuit optimization. For example, the head-to-head orientation of the first and second amplifier dies (e.g., first amplifier die 310 and second amplifier die 320) and the orthogonal orientation of the third amplifier die (e.g., third amplifier die 330) of the three-way Dougherty amplifier can reduce electromagnetic coupling effects and allow the first, second, and third amplifier dies to be placed closer together compared to a conventional three-way Dougherty amplifier layout configuration. The reduction in footprint achieved by the embodiments described herein can increase valuable component mounting and / or trace routing area on the semiconductor substrate (e.g., a semiconductor substrate used in a chip package, such as a planar grid array (LGA)).

[0141] The signal combiner devices described herein (e.g., signal combiner devices 150, 350) can significantly reduce transmission losses caused by the CLC networks (e.g., the first, second, and third CLC networks) in the signal path by utilizing high-QMIM capacitors to implement CLC networks (e.g., using high-QMIM capacitors to implement the second parallel capacitor 358 and / or the third parallel capacitor 349) and low-inductance lead connections (e.g., lead connection arrays 316, 317a, 317b, 385, 326). Furthermore, the signal combiner devices may include parallel capacitors (e.g., the third parallel capacitor 349) that can improve the bandwidth of a load (e.g., load 162) to 50Ω converter impedance matching (e.g., when the impedance of load 162 is low or when the average power of the Dougherty amplifier 100 is at a relatively high backoff level).

[0142] Furthermore, as the peak power, design frequency, back-off level, and / or device drain capacitance increase in a three-way Dougherty amplifier, the inductance value required for the CLC network to perform proper phase delay and / or impedance matching may decrease. In conventional three-way Dougherty implementations, achieving such a reduced inductance value may be difficult. However, the signal combiner devices described herein can achieve the previously discussed reduced inductance value because they implement the inductance required for a CLC network with low-inductance lead connections.

[0143] Figure 9A and 9B This is according to an example embodiment for manufacturing a Doherty amplifier module (e.g., Figure 3 The flowchart shows the method for using the Dougherty amplifier module 300. (See reference.) Figure 9A At block 902, the method involves placing a first amplifier die (e.g., Figure 3 The first amplifier die 310 in the middle is attached to the substrate (e.g., Figure 3 On or above the mounting surface of the substrate 302 in the first amplifier die, the first amplifier die includes a first input terminal (e.g., near a first side of the first amplifier die) Figure 3 The RF input terminal 312) and the first output terminal (e.g., near the second side of the first amplifier die) are located near the first amplifier die. Figure 3 The first amplifier die is configured to amplify a first RF signal along a first signal path (e.g., indicated by arrow 311) to generate a first amplified RF signal at the first output terminal, the first signal path extending from the first side of the first amplifier die to the second side of the first amplifier die.

[0144] At block 904, the method involves placing a second amplifier die (e.g., Figure 3 The second amplifier die 320 is attached to or above the mounting surface of the substrate, and the second amplifier die includes a second input terminal (e.g., near a first side of the second amplifier die) Figure 3 The RF input terminal 322) and the second output terminal (e.g., near the second side of the second amplifier die) are located. Figure 3 The second amplifier die is configured to amplify a second RF signal along a second signal path to generate a second amplified RF signal at the second output terminal (RF output terminal 324), the second signal path (e.g., indicated by arrow 321) extends from the first side of the second amplifier die to the second side of the second amplifier die, wherein the second side of the second amplifier die faces the second side of the first amplifier die, and wherein the second signal path is parallel to the first signal path.

[0145] At block 906, the method involves attaching a third amplifier die (e.g., third amplifier die 330) to or above a mounting surface of a substrate, the third amplifier die including a third input terminal (e.g., ...) near a first side of the third amplifier die. Figure 3 The RF input terminal 332) and the third output terminal (e.g., near the second side of the third amplifier die) are located in the third amplifier die. Figure 3 The third amplifier die is configured to amplify a third RF signal along a third signal path (e.g., indicated by arrow 331) to generate a third amplified RF signal at the third output terminal, the third signal path extending from the first side of the third amplifier die to the second side of the third amplifier die, wherein the third signal path is orthogonal to the first signal path and the second signal path.

[0146] refer to Figure 9B At block 908, the method relates to combining a signal combiner device (e.g., Figure 3 The signal combiner device 350 is attached to or above the mounting surface of the substrate, between the first amplifier die and the second amplifier die. In an embodiment, the signal combiner device is external to the first, second, and third amplifier dies and includes a first combining node (e.g., a first bonding pad 352) and a first parallel capacitor (e.g., a second parallel capacitor 358) coupled to the first combining node. The first combining node is configured to combine the first amplified RF signal with at least one of the second and third amplified RF signals to produce an amplified RF output signal.

[0147] At block 910, the method involves bonding a first lead array (e.g., Figure 3 The first lead bonding array 316 in the first amplifier die is coupled to the first output terminal of the first amplifier die and the first bonding pad (e.g., included on the signal combiner device). Figure 3 Between the first bonding pads 352 in the array. In other embodiments, alternatively, all or part of the conductive path provided by the first lead bonding array may be implemented using conductive traces on or within the substrate to which the amplifier die and signal combiner device are attached.

[0148] At block 912, the method involves bonding a second lead array (e.g., Figure 3 The third lead bonding array 326 is coupled between the second output terminal of the second amplifier die and the first bonding pad, wherein the first lead bonding array and the second lead bonding array are parallel to each other. In other embodiments, alternatively, all or part of the conductive path provided by the second lead bonding array may be implemented using conductive traces on or within the substrate to which the amplifier die and signal combiner device are attached.

[0149] At box 914, the method involves bonding a third lead array (e.g., Figure 3 The fourth lead bonding array 336 is coupled between the second output terminal of the second amplifier die and the third output terminal of the third amplifier die, wherein the third lead bonding array is orthogonal to the first and second lead bonding arrays. In other embodiments, alternatively, all or part of the conductive path provided by the third lead bonding array may be implemented using conductive traces on or within the substrate to which the amplifier die and signal combiner device are attached.

[0150] The preceding specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as superior to or better than other embodiments. Furthermore, it is not intended to be limited to any theory represented or implied as presented in the preceding technical field, background art, or specific embodiments.

[0151] The connecting lines shown in the various figures included herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and the terms “first,” “second,” and other numerical terms of such reference structures do not imply a sequence or order unless the context clearly indicates otherwise.

[0152] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented using a single physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished, even if the signals are received or output at a common node).

[0153] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless explicitly stated otherwise, "connected" means one element is directly and not necessarily mechanically engaged to (or directly connected to) another element. Similarly, unless explicitly stated otherwise, "coupled" means one element is directly or indirectly and not necessarily mechanically engaged to (or directly or indirectly connected to) another element via electrical or other means. Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0154] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed descriptions will provide those skilled in the art with a convenient roadmap for implementing one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including equivalents known or foreseeable at the time of filing this patent application.

Claims

1. A Doherty amplifier module characterized by, include: Substrate, the substrate including a mounting surface; A first amplifier die, the first amplifier die on the mounting surface, the first amplifier die including a first input terminal near a first side of the first amplifier die and a first output terminal near a second side of the first amplifier die, the first amplifier die being configured to amplify a first radio frequency (RF) signal along a first signal path to generate a first amplified RF signal at the first output terminal, the first signal path extending from the first side of the first amplifier die to the second side of the first amplifier die; A second amplifier die, the second amplifier die on the mounting surface, the second amplifier die including a second input terminal near a first side of the second amplifier die and a second output terminal near a second side of the second amplifier die, the second amplifier die being configured to amplify a second RF signal along a second signal path to generate a second amplified RF signal at the second output terminal, the second signal path extending from the first side of the second amplifier die to the second side of the second amplifier die, wherein the second side of the second amplifier die faces the second side of the first amplifier die, and wherein the second signal path is parallel to the first signal path; A third amplifier die, the third amplifier die on the mounting surface, the third amplifier die including a third input terminal near a first side of the third amplifier die and a third output terminal near a second side of the third amplifier die, the third amplifier die being configured to amplify a third RF signal along a third signal path to generate a third amplified RF signal at the third output terminal, the third signal path extending from the first side of the third amplifier die to the second side of the third amplifier die, wherein the third signal path is orthogonal to both the first signal path and the second signal path. The Doherty amplifier module further includes: A signal combiner device is located outside of a first amplifier die, a second amplifier die, and a third amplifier die, situated on a mounting surface between the first and second amplifier dies. The signal combiner device includes a first combining node configured to combine a first amplified RF signal with at least one of a second amplified RF signal and a third amplified RF signal to produce an amplified RF output signal. The first combining node includes a first bonding pad on the signal combiner device, and the Dougherty amplifier module further includes: A first lead bonding array is coupled between the first output terminal of the first amplifier die and the first bonding pad. A second lead bonding array, coupled between the second output terminal of the second amplifier die and the first bonding pad, wherein the first lead bonding array and the second lead bonding array are parallel to each other; and A third lead bonding array is coupled between the second output terminal and the third output terminal of the second amplifier die, wherein the third lead bonding array is orthogonal to the first lead bonding array and the second lead bonding array.

2. The Dougherty amplifier module according to claim 1, characterized in that: The signal combiner device further includes A first parallel capacitor is coupled to the first bonding pad; and The Dougherty amplifier module further includes a fourth lead bonding array coupled between the first bonding pad and a conductive contact on the mounting surface, wherein the fourth lead bonding array is orthogonal to the first and second lead bonding arrays, and wherein the first parallel capacitor is configured to perform impedance transformation to match the impedance of the load to the source impedance.

3. The Dougherty amplifier module according to claim 1, characterized in that: The signal combiner device further includes a second bonding pad and a parallel DC blocking capacitor coupled to the second bonding pad; and The Doherty amplifier module further includes a fourth lead bonding array coupled between the first output terminal of the first amplifier die and the second bonding pad, wherein the fourth lead bonding array is substantially parallel to the first lead bonding array.

4. The Doherty amplifier module of claim 1, wherein, The signal combiner device further includes: A first parallel capacitor is coupled to the first combined node.

5. The Doherty amplifier module of claim 4, wherein, The first amplifier die includes a first power transistor, and the second amplifier die includes a second power transistor, wherein the drain-source capacitance of the first power transistor, the inductance of the first lead-bond array, and the capacitance of the first parallel capacitor form a first quasi-transmission line, the first quasi-transmission line being configured to perform a first phase delay and a first impedance transformation for the first amplified RF signal, and wherein the drain-source capacitance of the second power transistor, the inductance of the second lead-bond array, and the capacitance of the first parallel capacitor form a second quasi-transmission line, the second quasi-transmission line being configured to perform a second phase delay and a second impedance transformation for at least one of the second amplified RF signal or the third amplified RF signal.

6. The Doherty amplifier module of claim 5, wherein, The third amplifier die includes a third power transistor, wherein the drain-source capacitance of the third power transistor, the inductance of the third lead junction array, and the drain-source capacitance of the second power transistor form a third quasi-transmission line, the third quasi-transmission line being configured to perform a third phase delay and a third impedance transformation for the third amplified RF signal.

7. A Doherty amplifier module characterized by include: Substrate, the substrate including a mounting surface; A carrier amplifier die, the carrier amplifier die being on the mounting surface, the carrier amplifier die including a first input terminal near a first side of the carrier amplifier die and a first output terminal near a second side of the carrier amplifier die; A first peak amplifier die, the first peak amplifier die on the mounting surface, the first peak amplifier die including a second input terminal near a first side of the first peak amplifier die and a second output terminal near a second side of the first peak amplifier die, wherein the second side of the first peak amplifier die faces the second side of the carrier amplifier die; A signal combiner device is provided on a mounting surface. The signal combiner device includes a first combining node, wherein the signal combiner device is located between a carrier amplifier die and a first peak amplifier die. The first output terminal of the carrier amplifier die is coupled to the first combining node via a first lead bonding array, and the second output terminal of the first peak amplifier die is coupled to the first combining node via a second lead bonding array, wherein the first lead bonding array and the second lead bonding array are parallel to each other. as well as A second peak amplifier die is located on the mounting surface. The second peak amplifier die includes a third input terminal near a first side of the second peak amplifier die and a third output terminal near a second side of the second peak amplifier die. The second side of the second peak amplifier die is orthogonal to the second side of the first peak amplifier die. The third output terminal of the second peak amplifier die is coupled to the second output terminal of the first peak amplifier die via a third lead bonding array, wherein the third lead bonding array is orthogonal to the first lead bonding array and the second lead bonding array.

8. A method of manufacturing a Doherty amplifier module, characterized by, The method includes: A first amplifier die is attached to a mounting surface of a substrate. The first amplifier die includes a first input terminal near a first side of the first amplifier die and a first output terminal near a second side of the first amplifier die. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path to generate a first amplified RF signal at the first output terminal. The first signal path extends from the first side of the first amplifier die to the second side of the first amplifier die. A second amplifier die is attached to the mounting surface of the substrate. The second amplifier die includes a second input terminal near a first side of the second amplifier die and a second output terminal near a second side of the second amplifier die. The second amplifier die is configured to amplify a second RF signal along a second signal path to generate a second amplified RF signal at the second output terminal. The second signal path extends from the first side of the second amplifier die to the second side of the second amplifier die, wherein the second side of the second amplifier die faces the second side of the first amplifier die, and wherein the second signal path is parallel to the first signal path. A third amplifier die is attached to the mounting surface of the substrate. The third amplifier die includes a third input terminal near a first side of the third amplifier die and a third output terminal near a second side of the third amplifier die. The third amplifier die is configured to amplify a third RF signal along a third signal path to generate a third amplified RF signal at the third output terminal. The third signal path extends from the first side of the third amplifier die to the second side of the third amplifier die, wherein the third signal path is orthogonal to both the first and second signal paths. The method further includes attaching a signal combiner device to the mounting surface of the substrate, wherein the signal combiner device is external to the first amplifier die, the second amplifier die, and the third amplifier die, and wherein the signal combiner device is attached to the mounting surface between the first amplifier die and the second amplifier die, wherein the signal combiner device includes a first combining node, wherein the first combining node is configured to combine the first amplified RF signal with at least one of the second amplified RF signal and the third amplified RF signal to generate an amplified RF output signal. Furthermore, the method further includes coupling a first wire bonding array between the first output terminal of the first amplifier die and the first combination node; coupling a second wire bonding array between the second output terminal of the second amplifier die and the first combination node; and coupling a third wire bonding array between the second output terminal of the second amplifier die and the third output terminal of the third amplifier die, wherein the first wire bonding array and the second wire bonding array are parallel to each other, and the third wire bonding array is orthogonal to the first wire bonding array and the second wire bonding array.

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