An operational amplifier

Abstract

An operational amplifier includes a first-stage gain circuit and a second-stage gain circuit connected to each other, the first-stage gain circuit being provided with an input terminal, the second-stage gain circuit being provided with an output terminal, the first-stage gain circuit including at least a tail current source, and the operational amplifier further including a tail current compensation circuit, one end of the tail current compensation circuit being connected to the tail current source and the other end being connected to the output terminal of the second-stage gain circuit, the tail current compensation circuit being configured to compensate the output signal to the tail current source. An embodiment of the present invention replaces the conventional pole-separating Miller compensation technology with a tail current compensation circuit, alleviating the deterioration of power supply rejection introduced by the compensation capacitor under high-frequency conditions. The tail current compensation technology can improve the power supply rejection characteristics of the operational amplifier while ensuring circuit stability.

Description

Technical Field

[0001] This article relates to but is not limited to an operational amplifier. Background Art

[0002] With the advancement of CMOS (Complementary Metal Oxide Semiconductor) technology and the increasing sophistication of SoCs (System-on-a-Chip), wireless transceiver chips not only integrate RF transceivers, digital-to-analog converters, and analog-to-digital converters, but also large-scale digital circuits such as digital signal processors. RF circuits are sensitive to power supply noise, which directly impacts their performance. High-frequency power supply noise, in particular, can modulate into useful frequencies, ultimately impacting both transmit and receive performance.

[0003] Low-power, low-dropout voltage LDO (Low Dropout Regulator) circuits are crucial components for powering critical circuits and suppressing power supply noise. Currently, the power supply rejection ratio (PSR) is commonly used to measure the noise suppression capability of LDOs. As the core module within an LDO, the operational amplifier (op amp)'s PSRR directly impacts the overall LDO circuit's PSRR performance. Therefore, improving the amplifier's PSRR characteristics is crucial to ensure system performance.

[0004] Currently, techniques such as cascode, negative feedback, and additional power supply rejection circuits are primarily used to improve the power supply rejection characteristics of operational amplifiers. Miller compensation / cascode compensation are also used to enhance amplifier stability to ensure proper operation. However, Miller compensation / cascode compensation can degrade power supply rejection, particularly at higher frequencies. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present invention provides an operational amplifier to avoid deterioration of power supply rejection at high frequencies.

[0007] An embodiment of the present invention provides an operational amplifier, comprising a first-stage gain circuit and a second-stage gain circuit connected to each other, wherein the first-stage gain circuit is provided with an input terminal, the second-stage gain circuit is provided with an output terminal, the first-stage gain circuit includes at least a tail current source, and the operational amplifier further includes a tail current compensation circuit, wherein

[0008] One end of the tail current compensation circuit is connected to the tail current source, and the other end is connected to the output end of the second-stage gain circuit. The tail current compensation circuit is used to compensate the output signal to the tail current source.

[0009] The embodiment of the present invention adopts a tail current compensation circuit to replace the traditional pole separation Miller compensation technology, thereby alleviating the power supply rejection deterioration introduced by the compensation capacitor under high frequency conditions. The tail current compensation technology can improve the power supply rejection characteristics of the operational amplifier while ensuring circuit stability.

[0010] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the structure of the operational amplifier according to the embodiment of the present application;

[0012] Figure 2 This is a structural diagram of an operational amplifier according to another embodiment of the present application;

[0013] Figure 3 This is a structural diagram of an exemplary circuit of an operational amplifier of the present application;

[0014] Figure 4 This is a structural diagram of another exemplary circuit of the operational amplifier of the present application;

[0015] Figure 5 This is a structural diagram of another exemplary circuit of the operational amplifier of the present application;

[0016] Figure 6 This is a structural diagram of another exemplary circuit of the operational amplifier of the present application;

[0017] Figure 7 This is a structural diagram of another exemplary circuit of the operational amplifier of the present application;

[0018] Figure 8 Schematic diagram of the circuit structure of an operational amplifier based on Miller compensation;

[0019] Figure 9 Schematic diagram of the circuit structure of an operational amplifier based on cascode compensation;

[0020] Figure 10 This is a schematic diagram of the power supply rejection principle of an operational amplifier based on tail current compensation according to an embodiment of the present application;

[0021] Figure 11 This is a schematic diagram of the positive feedback suppression principle of an operational amplifier based on tail current compensation according to an embodiment of the present application;

[0022] Figure 12A schematic diagram comparing the power supply rejection simulation results of LDOs built based on operational amplifiers with different compensation methods. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0024] To ensure the normal operation of operational amplifiers, Miller compensation / cascode compensation is used to improve amplifier stability. However, power supply noise is directly coupled to the output of the operational amplifier through the compensation capacitor, reducing the operational amplifier's power supply rejection (PSR) and causing degradation of PSR, particularly at higher frequencies. In other words, Miller / cascode compensation in operational amplifiers can lead to degraded PSR, particularly at higher frequencies.

[0025] The embodiment of the present application provides an operational amplifier, such as Figure 1 As shown, it includes: a first-stage gain circuit, a second-stage gain circuit and a tail current compensation circuit.

[0026] The first-stage gain circuit and the second-stage gain circuit are connected, the first-stage gain circuit is provided with an input end, the second-stage gain circuit is provided with an output end, and the first-stage gain circuit at least includes a tail current source.

[0027] One end of the tail current compensation circuit is connected to the tail current source, and the other end is connected to the output end of the second-stage gain circuit. The tail current compensation circuit is used to compensate the output signal to the tail current source.

[0028] The embodiment of the present invention adopts a tail current compensation circuit to replace the traditional pole separation Miller compensation technology, thereby alleviating the power supply rejection deterioration introduced by the compensation capacitor under high frequency conditions. The tail current compensation technology can improve the power supply rejection characteristics of the operational amplifier while ensuring circuit stability.

[0029] like Figure 1 As shown, in one embodiment, the operational amplifier further includes: a positive feedback tuning circuit, one end of which is connected to the first-stage gain circuit and the other end is grounded, for suppressing the positive feedback path introduced by the tail current compensation circuit.

[0030] In this embodiment, the first-stage gain circuit realizes the input and amplification of the differential signal; the second-stage gain circuit realizes the amplification of the output signal of the first-stage gain circuit and drives the circuit load; the compensation circuit introduces additional zeros and poles to realize the normal closed-loop operation of the operational amplifier; and the positive feedback tuning circuit cuts off the positive feedback path introduced by the compensation circuit.

[0031] like Figure 2As shown, the input end may include a non-inverting input end and an inverting input end, and the first gain stage circuit is connected to the non-inverting input end and the inverting input end.

[0032] like Figure 2 As shown, the operational amplifier of the present application may also have: a power supply end, the first gain stage circuit and the second gain stage circuit are both connected to the power supply end, and the power supply end is responsible for an external power supply to supply power to the operational amplifier through the external power supply.

[0033] In an embodiment of the present application, the main amplification circuit of the operational amplifier may include a first gain stage circuit and a second gain stage circuit, a main signal path is formed by the first gain stage circuit and the second gain stage circuit, a left half plane zero point is formed based on the tail current compensation circuit, the phase margin is improved and the amplifier stability is improved, and the positive feedback signal introduced by the tail current compensation circuit is suppressed by the positive feedback suppression circuit.

[0034] like Figure 2 As shown, in one embodiment, the first-stage gain circuit further includes a first-stage amplifier circuit and a current mirror load circuit connected to each other, and the first-stage amplifier circuit is connected to the tail current source and the tail current compensation circuit.

[0035] In one embodiment, the positive feedback tuning circuit is connected to the first stage amplifier circuit. In another embodiment, the positive feedback tuning circuit is connected to the first stage amplifier circuit and the current mirror load circuit.

[0036] The first-stage amplifier circuit may include an input differential pair of transistors. One end of the tail current compensation circuit is connected to the connection between the common source terminal of the input differential pair of transistors and the tail current source, and the other end is connected to the second-stage gain circuit and the output terminal. In this way, tail current compensation can be achieved.

[0037] The input differential pair transistors refer to the two MOS transistors in the first-stage gain circuit that are connected to the same-direction input terminal and the reverse input terminal of the operational amplifier. These two MOS transistors can be NMOS transistors or PMOS transistors. As part of the first-stage gain circuit, the tail current source is responsible for generating a constant tail current and can be implemented by one or more MOS transistors. For example, Figures 3 to 6 In the circuit structure shown, the input differential pair transistors are NMOS transistors M3 and NMOS transistors M4. For another example, Figure 3 In the circuit structure shown, the structure including NMOS tubes M1 and M2 is the tail current source of the first-stage gain circuit. Figure 6 In the circuit structure shown, the structure including the NMOS transistor M2 is the tail current source of the first-stage gain circuit.

[0038] As described above, an embodiment of the present application provides an operational amplifier based on tail current compensation, which uses a tail current compensation circuit to compensate the output signal to the tail current of the common source end of the input differential pair. The tail current compensation circuit can form a left half plane zero point to improve the phase margin, avoid directly coupling the power supply noise to the output end at higher frequencies, and thus avoid the deterioration of power supply suppression.

[0039] In one implementation of the present application, the first-stage amplifier circuit can be a cascode amplifier circuit with differential input and single-ended output. Additionally, the first-stage amplifier circuit can be another circuit structure that provides circuit gain and has differential input and single-ended output. For example, the first-stage amplifier circuit can be a common-source amplifier circuit with differential input and single-ended output, or an amplifier circuit with differential input and differential output. This document does not limit the specific structure of the first-stage amplifier circuit.

[0040] In one implementation of the present application, the second-stage gain circuit can be a common-source amplifier circuit with a single-ended input and a single-ended output. Additionally, the second-stage gain circuit can be another circuit structure that provides circuit gain and has a single-ended input and a single-ended output. For example, the second-stage gain circuit can be a common-source common-gate amplifier circuit with a single-ended input and a single-ended output, or an amplifier circuit with a differential input and a single-ended output. This document does not limit the specific structure of the second-stage gain circuit.

[0041] Among them, when the first-stage amplifier circuit is a differential input, single-ended output common-source common-gate amplifier circuit or a differential input, single-ended output common-source amplifier circuit, the second-stage gain circuit can be a single-ended input, single-ended output common-source amplifier circuit or a single-ended input, single-ended output common-source common-gate amplifier circuit.

[0042] When the first-stage amplifier circuit is an amplifier circuit with differential input and differential output, the second-stage gain circuit may be an amplifier circuit with differential input and single-ended output.

[0043] In the embodiment of the present application, the signal output terminal of the first stage amplifier circuit is connected to the signal input terminal of the second stage gain circuit. Figure 3 、 Figure 4 、 Figure 6 In the circuit structure shown, the connection between the drain terminal of M6 and the drain terminal of PMOS tube M8 serves as the signal output terminal OUT1 of the first stage amplifier circuit, which is connected to the signal input terminal of the second stage gain circuit, namely the gate terminal of M11. Figure 5 In the circuit structure shown, the connection between the drain terminal of M4 and the drain terminal of M8 serves as the signal output terminal of the first stage amplifier circuit, which is connected to the signal input terminal of the second stage gain circuit, namely the gate terminal of M11.

[0044] In an embodiment of the present application, the positive feedback tuning circuit may include a positive feedback tuning capacitor, the positive end of the positive feedback tuning capacitor is connected to the first-stage gain circuit, and the negative end of the positive feedback tuning capacitor is grounded GND to suppress the positive feedback signal from the output to the input formed by the tail current compensation circuit. In one implementation, the positive end of the positive feedback tuning capacitor is connected to the drain end of the MOS tube connected to the same-direction input end of the operational amplifier in the input differential pair of the first-stage gain circuit. It should be noted that the positive feedback tuning circuit of the embodiment of the present application can be a capacitor, a resistor, an inductor, an active device, or a series-parallel combination of the above four types of devices. The specific structure of the positive feedback tuning circuit is not limited in this article.

[0045] In the embodiment of the present application, the tail current compensation circuit may include: a compensation capacitor; wherein the negative end of the compensation capacitor is connected to the connection between the input differential pair tube and the tail current source in the first-stage gain circuit, and the positive end of the compensation capacitor is connected to the second-stage gain circuit and the output end. It should be noted that the tail current compensation circuit of the embodiment of the present application can also be implemented by a series structure of a compensation capacitor and a compensation resistor, such as Figure 7 In addition, the tail current compensation circuit can also be a capacitor, a resistor, an inductor, or a series-parallel combination of the above three types of devices, and can also be implemented using active devices.

[0046] From the above, it can be seen that in the operational amplifier of the embodiment of the present application, tail current compensation is used to isolate the compensation capacitor from the power supply noise, thereby solving the problem of power supply suppression degradation introduced by the compensation capacitor at higher frequencies; at the same time, since the input differential pair and the input common-gate tube can provide a larger current gain, compared with the Miller compensation / common-source compensation circuit with the same phase margin, the compensation capacitor based on tail current compensation has a smaller capacitance requirement.

[0047] The following describes the implementation of the operational amplifier in the embodiment of the present application.

[0048] Example 1

[0049] In this example, the operational amplifier may include a first-stage gain circuit, a second-stage gain circuit, a compensation circuit, and a positive feedback tuning circuit. The first-stage gain circuit and the second-stage gain circuit serve as the main signal path, the compensation circuit improves the amplifier's phase margin, and the positive feedback tuning circuit suppresses the positive feedback signal introduced by the compensation circuit.

[0050] like Figure 3 FIG. 1 shows an exemplary circuit structure of an operational amplifier.

[0051] like Figure 3As shown, the operational amplifier of this embodiment has a power supply terminal VDD, a non-inverting input port VIP, an inverting input port VIN, an output port Vout, and bias voltage ports Vbias0 / Vbias1 / Vbias2 / Vbias3.

[0052] like Figure 3 As shown, in this example, the first-stage gain circuit may include: NMOS transistors M1, M2, M3, M4, M5, M6 and PMOS transistors M7, M8, M9, M10. Among them, M1 and M2 are tail current sources, M3-M6 are the first-stage amplifier circuit (input differential transistors), and M7-M10 are current mirror load circuits.

[0053] The gates of NMOS transistors M3 and M4 are connected to the operational amplifier's non-inverting input port VIP and inverting input port VIN, respectively. The sources of M3 and M4 are connected to the drain of NMOS transistor M2 and the negative terminal of compensation capacitor Ctail. The drain of M3 is connected to the source of NMOS transistor M5 and the positive terminal of positive feedback tuning capacitor Cadd. The drain of M4 is connected to the source of NMOS transistor M6. The gates of NMOS transistors M5 and M6 are connected to the bias voltage terminal Vbias2. The drain of M5 is connected to the drain of PMOS transistor M7 and the gates of PMOS transistors M9 and M10. The junction between the drain of M6 and the drain of PMOS transistor M8 serves as the signal output terminal OUT1 of the first-stage gain circuit and is connected to the gate of PMOS transistor M11.

[0054] The gate terminals of PMOS transistors M7 and M8 are connected to the bias voltage terminal Vbias3; the source terminals of M7 and M8 are connected to the drain terminals of PMOS transistors M9 and M10, respectively. The gate terminals of PMOS transistors M9 and M10 are connected to the drain terminals of NMOS transistor M5 and PMOS transistor M7; the source terminals of M9 and M10 are connected to the power supply terminal VDD.

[0055] The gate terminal of the NMOS transistor M2 is connected to the bias voltage terminal Vbias1, and the source terminal of M2 is connected to the drain terminal of the NMOS transistor M1. The gate terminal of the NMOS transistor M1 is connected to the bias voltage terminal Vbias0, and the source terminal of M1 is connected to the ground GND.

[0056] like Figure 3As shown, in this example, the second-stage gain circuit may include: a PMOS transistor M11 and NMOS transistors M12 and M13. The gate terminal of the PMOS transistor M11 is connected to the signal output terminal OUT1 of the first-stage gain circuit (i.e., the connection between the drain terminals of M6 and M8); the source terminal of M11 is connected to the power supply terminal VDD; the drain terminal of M11 is connected to the output terminal Vout of the operational amplifier, the drain terminal of the NMOS transistor M12, and the positive terminal of the compensation capacitor Ctail. The gate terminal of the NMOS transistor M12 is connected to the bias voltage terminal Vbias1; the source terminal of M12 is connected to the drain terminal of the NMOS transistor M13. The gate terminal of the NMOS transistor M13 is connected to the bias voltage terminal Vbias0, and the source terminal of M13 is connected to ground GND.

[0057] like Figure 3 As shown, in this example, the compensation circuit may include a compensation capacitor Ctail. The positive terminal of the compensation capacitor Ctail is connected to the output terminal Vout of the operational amplifier and to the drain terminals of the PMOS transistor M11 and the NMOS transistor M12. The negative terminal of the compensation capacitor Ctail is connected to the drain terminals of the NMOS transistors M3 and M4 and the source terminal of the NMOS transistor M2.

[0058] like Figure 3 As shown, in this example, the positive feedback tuning circuit may include: a positive feedback tuning capacitor Cadd. The positive terminal of the positive feedback tuning capacitor Cadd is connected to the drain terminal of the NMOS transistor M3 and the source terminal of the NMOS transistor M5; and the negative terminal of the positive feedback tuning capacitor Cadd is connected to the ground GND.

[0059] Example 2

[0060] In this example, the operational amplifier may include a first-stage gain circuit, a second-stage gain circuit, a compensation circuit, and a positive feedback tuning circuit. The first-stage gain circuit and the second-stage gain circuit serve as the main signal path, the compensation circuit improves the amplifier's phase margin, and the positive feedback tuning circuit suppresses the positive feedback signal introduced by the compensation circuit.

[0061] like Figure 4 As shown, it is an exemplary circuit structure of the operational amplifier of this example.

[0062] like Figure 4 As shown, the operational amplifier of this embodiment has a power supply terminal VDD, a non-inverting input port VIP, an inverting input port VIN, an output port Vout, and bias voltage ports Vbias0 / Vbias1 / Vbias2.

[0063] like Figure 4As shown, in this example, the first-stage gain circuit may include: NMOS transistors M1, M2, M3, M4, M5, M6 and PMOS transistors M7 and M8. Among them, M1 and M2 are tail current sources, M3-M6 are the first-stage amplifier circuit (input differential transistors), and M7-M8 are current mirror load circuits.

[0064] The gates of NMOS transistors M3 and M4 are connected to the operational amplifier's non-inverting input port VIP and inverting input port VIN, respectively. The sources of M3 and M4 are connected to the drain of NMOS transistor M2 and the negative terminal of compensation capacitor Ctail. The drain of M3 is connected to the source of NMOS transistor M5 and the positive terminal of positive feedback tuning capacitor Cadd. The drain of M4 is connected to the source of NMOS transistor M6. The gates of NMOS transistors M5 and M6 are connected to the bias voltage terminal Vbias2. The drain of M5 is connected to the drain of PMOS transistor M7. The drain of M6 is connected to the drain of PMOS transistor M8. This connection serves as the signal output terminal OUT1 of the first-stage gain circuit and is connected to the signal input terminal of the second-stage gain circuit (i.e., the gate of PMOS transistor M11).

[0065] The gate terminals of the PMOS transistors M7 and M8 are connected to the drain terminals of the NMOS transistor M5 and the PMOS transistor M7; the source terminals of M7 and M8 are connected to the power supply terminal VDD respectively.

[0066] The gate terminal of the NMOS transistor M2 is connected to the bias voltage terminal Vbias1, and the source terminal of M2 is connected to the drain terminal of the NMOS transistor M1. The gate terminal of the NMOS transistor M1 is connected to the bias voltage terminal Vbias0, and the source terminal of M1 is connected to the ground GND.

[0067] like Figure 4 As shown, in this example, the second-stage gain circuit may include: a PMOS transistor M11 and NMOS transistors M12 and M13. The gate terminal of the PMOS transistor M11 is connected to the signal output terminal OUT1 of the first-stage gain circuit (i.e., the connection between the drain terminals of M6 and M8), the source terminal of M11 is connected to the power supply terminal VDD, and the drain terminal of M11 is connected to the output terminal Vout of the operational amplifier, the drain terminal of the NMOS transistor M12, and the positive terminal of the compensation capacitor Ctail. The gate terminal of the NMOS transistor M12 is connected to the bias voltage terminal Vbias1; the source terminal of M12 is connected to the drain terminal of the NMOS transistor M13. The gate terminal of the NMOS transistor M13 is connected to the bias voltage terminal Vbias0, and the source terminal of M13 is connected to ground GND.

[0068] like Figure 4 As shown, the structures and connection relationships of the compensation circuit and the positive feedback tuning circuit in this example are the same as those in Example 1 and will not be repeated here.

[0069] Example 3

[0070] In this example, the operational amplifier may include a first-stage gain circuit, a second-stage gain circuit, a compensation circuit, and a positive feedback tuning circuit. The first-stage gain circuit and the second-stage gain circuit serve as the main signal path, the compensation circuit improves the amplifier's phase margin, and the positive feedback tuning circuit suppresses the positive feedback signal introduced by the compensation circuit.

[0071] like Figure 5 As shown, it is an exemplary circuit structure of the operational amplifier of this example.

[0072] like Figure 5 As shown, the operational amplifier of this embodiment has a power supply terminal VDD, a non-inverting input port VIP, an inverting input port VIN, an output port Vout, and bias voltage ports Vbias0 / Vbias1 / Vbias3.

[0073] like Figure 5 As shown, in this example, the first-stage gain circuit may include: NMOS transistors M1, M2, M3, M4 and PMOS transistors M7, M8, M9, M10. Among them, M1 and M2 are input tail current sources, M3-M4 are the first-stage amplifier circuit (input differential transistors), and M7-M10 are current mirror load circuits.

[0074] The gate terminals of NMOS transistors M3 and M4 are connected to the operational amplifier's non-inverting input port VIP and inverting input port VIN, respectively. The sources of M3 and M4 are connected to the drain terminal of NMOS transistor M2 and the negative terminal of compensation capacitor Ctail. The drain terminal of M3 is connected to the drain terminal of NMOS transistor M7 and the positive terminal of positive feedback tuning capacitor Cadd. The drain terminal of M4 is connected to the drain terminal of NMOS transistor M8. The drain terminal of M4 is connected to the drain terminal of PMOS transistor M8, and this connection serves as the signal output terminal OUT1 of the first-stage gain circuit and is connected to the signal input terminal of the second-stage gain circuit (i.e., the gate terminal of PMOS transistor M11).

[0075] The gates of PMOS transistors M7 and M8 are connected to the bias voltage terminal Vbias3; the sources of M7 and M8 are connected to the drains of PMOS transistors M9 and M10, respectively. The gates of PMOS transistors M9 and M10 are connected to the drains of NMOS transistors M3 and M7; the sources of M9 and M10 are connected to the power supply terminal VDD. The gate of NMOS transistor M2 is connected to the bias voltage terminal Vbias1, and its source is connected to the drain of NMOS transistor M1. The gate of NMOS transistor M1 is connected to the bias voltage terminal Vbias0, and its source is connected to ground GND.

[0076] like Figure 5As shown, in this example, the second-stage gain circuit may include: a PMOS transistor M11 and NMOS transistors M12 and M13. The gate terminal of the PMOS transistor M11 is connected to the signal output terminal OUT1 of the first-stage gain circuit (i.e., the connection between the drain terminal of M4 and the drain terminal of the PMOS transistor M8); the source terminal of M11 is connected to the power supply terminal VDD; the drain terminal of M11 is connected to the output terminal Vout of the operational amplifier, the drain terminal of the NMOS transistor M12, and the positive terminal of the compensation capacitor Ctail. The gate terminal of the NMOS transistor M12 is connected to the bias voltage terminal Vbias1; the source terminal of M12 is connected to the drain terminal of the NMOS transistor M13. The gate terminal of the NMOS transistor M13 is connected to the bias voltage terminal Vbias0, and the source terminal of M13 is connected to ground GND.

[0077] like Figure 5 As shown, in this example, the compensation circuit may include a compensation capacitor Ctail. The positive terminal of the compensation capacitor Ctail is connected to the output terminal Vout of the operational amplifier and to the drain terminals of the PMOS transistor M11 and the NMOS transistor M12. The negative terminal of the compensation capacitor Ctail is connected to the drain terminals of the NMOS transistors M3 and M4 and the source terminal of the NMOS transistor M2.

[0078] like Figure 5 As shown, in this example, the positive feedback tuning circuit may include: a positive feedback tuning capacitor Cadd. The positive terminal of the positive feedback tuning capacitor Cadd is connected to the drain terminal of the NMOS transistor M3 and the drain terminal of the NMOS transistor M7; the negative terminal of the positive feedback tuning capacitor Cadd is connected to the ground GND.

[0079] Example 4

[0080] In this example, the operational amplifier may include a first-stage gain circuit, a second-stage gain circuit, a compensation circuit, and a positive feedback tuning circuit. The first-stage gain circuit and the second-stage gain circuit serve as the main signal path, the compensation circuit improves the amplifier's phase margin, and the positive feedback tuning circuit suppresses the positive feedback signal introduced by the compensation circuit.

[0081] like Figure 6 As shown, it is an exemplary circuit structure of the operational amplifier of this example.

[0082] like Figure 6 As shown, the operational amplifier of this embodiment has a power supply terminal VDD, a non-inverting input port VIP, an inverting input port VIN, an output port Vout, and bias voltage ports Vbias1 / Vbias2 / Vbias3 .

[0083] like Figure 6As shown, in this example, the first-stage gain circuit may include: NMOS transistors M2, M3, M4 and PMOS transistors M7, M8, M9, M10. Among them, M2 is a tail current source, M3-M6 are the first-stage amplifier circuit (input differential transistors), and M7-M10 are current mirror load circuits.

[0084] The gates of NMOS transistors M3 and M4 are connected to the operational amplifier's non-inverting input port VIP and inverting input port VIN, respectively. The sources of M3 and M4 are connected to the drain of NMOS transistor M1 and the negative terminal of compensation capacitor Ctail. The drain of M3 is connected to the source of NMOS transistor M5 and the positive terminal of positive feedback tuning capacitor Cadd. The drain of M4 is connected to the source of NMOS transistor M6. The gates of NMOS transistors M5 and M6 are connected to the bias voltage terminal Vbias2. The drain of M5 is connected to the drain of PMOS transistor M7 and the gates of PMOS transistors M9 and M10. The drain of M6 is connected to the drain of PMOS transistor M8. The junction serves as the signal output OUT1 of the first-stage gain circuit and is connected to the signal input of the second-stage gain circuit (i.e., the gate of PMOS transistor M11).

[0085] The gates of PMOS transistors M7 and M8 are connected to the bias voltage terminal Vbias3; the sources of M7 and M8 are connected to the drains of PMOS transistors M9 and M10, respectively. The gates of PMOS transistors M9 and M10 are connected to the drains of NMOS transistors M5 and M7; the sources of M9 and M10 are connected to the power supply terminal VDD. The gate of NMOS transistor M2 is connected to the bias voltage terminal Vbias1, and its source is connected to ground GND.

[0086] like Figure 6 As shown, in this example, the second-stage gain circuit may include: a PMOS transistor M11 and an NMOS transistor M12. The gate terminal of the PMOS transistor M11 is connected to the signal output terminal OUT1 of the first-stage gain circuit (i.e., the connection between the drain terminals of M6 and M8); the source terminal of M11 is connected to the power supply terminal VDD; the drain terminal of M11 is connected to the output terminal Vout of the operational amplifier, the drain terminal of the NMOS transistor M12, and the positive terminal of the compensation capacitor Ctail. The gate terminal of the NMOS transistor M12 is connected to the bias voltage terminal Vbias1; and the source terminal of M12 is connected to ground GND.

[0087] like Figure 6 As shown, in this example, the compensation circuit may include a compensation capacitor Ctail. The positive terminal of the compensation capacitor Ctail is connected to the output terminal Vout of the operational amplifier and to the drain terminals of the PMOS transistor M11 and the NMOS transistor M12. The negative terminal of the compensation capacitor Ctail is connected to the drain terminals of the NMOS transistors M3 and M4 and the source terminal of the NMOS transistor M2.

[0088] like Figure 6As shown, in this example, the positive feedback tuning circuit may include: a positive feedback tuning capacitor Cadd. The positive terminal of the positive feedback tuning capacitor Cadd is connected to the drain terminal of the NMOS transistor M3 and the source terminal of the NMOS transistor M5; and the negative terminal of the positive feedback tuning capacitor Cadd is connected to the ground GND.

[0089] Example 5

[0090] In this example, the operational amplifier may include a first-stage gain circuit, a second-stage gain circuit, a compensation circuit, and a positive feedback tuning circuit. The first-stage gain circuit and the second-stage gain circuit serve as the main signal path, the compensation circuit improves the amplifier's phase margin, and the positive feedback tuning circuit suppresses the positive feedback signal introduced by the compensation circuit.

[0091] like Figure 7 FIG. 1 shows an exemplary circuit structure of an operational amplifier.

[0092] like Figure 7 As shown, the operational amplifier of this embodiment has a power supply terminal VDD, a non-inverting input port VIP, an inverting input port VIN, an output port Vout, and bias voltage ports Vbias0 / Vbias1 / Vbias2 / Vbias3.

[0093] like Figure 7 As shown, in this example, the first-stage gain circuit may include: NMOS transistors M1, M2, M3, M4, M5, M6 and PMOS transistors M7, M8, M9, M10. Among them, M1 and M2 are tail current sources, M3-M6 are the first-stage amplifier circuit (input differential transistors), and M7-M10 are current mirror load circuits.

[0094] The gates of NMOS transistors M3 and M4 are connected to the operational amplifier's non-inverting input port VIP and inverting input port VIN, respectively. The sources of M3 and M4 are connected to the drain of NMOS transistor M2 and the negative terminal of compensation capacitor Ctail. The drain of M3 is connected to the source of NMOS transistor M5 and the positive terminal of positive feedback tuning capacitor Cadd. The drain of M4 is connected to the source of NMOS transistor M6. The gates of NMOS transistors M5 and M6 are connected to the bias voltage terminal Vbias2. The drain of M5 is connected to the drain of PMOS transistor M7 and the gates of PMOS transistors M9 and M10. The junction between the drain of M6 and the drain of PMOS transistor M8 serves as the signal output terminal OUT1 of the first-stage gain circuit and is connected to the gate of PMOS transistor M11.

[0095] The gate terminals of PMOS transistors M7 and M8 are connected to the bias voltage terminal Vbias3; the source terminals of M7 and M8 are connected to the drain terminals of PMOS transistors M9 and M10, respectively. The gate terminals of PMOS transistors M9 and M10 are connected to the drain terminals of NMOS transistor M5 and PMOS transistor M7; the source terminals of M9 and M10 are connected to the power supply terminal VDD.

[0096] The gate terminal of the NMOS transistor M2 is connected to the bias voltage terminal Vbias1, and the source terminal of M2 is connected to the drain terminal of the NMOS transistor M1. The gate terminal of the NMOS transistor M1 is connected to the bias voltage terminal Vbias0, and the source terminal of M1 is connected to the ground GND.

[0097] like Figure 7 As shown, in this example, the second-stage gain circuit may include: a PMOS transistor M11 and NMOS transistors M12 and M13. The gate terminal of the PMOS transistor M11 is connected to the signal output terminal OUT1 of the first-stage gain circuit (i.e., the connection between the drain terminals of M6 and M8); the source terminal of M11 is connected to the power supply terminal VDD; the drain terminal of M11 is connected to the output terminal Vout of the operational amplifier, the drain terminal of the NMOS transistor M12, and the positive terminal of the compensation capacitor Ctail. The gate terminal of the NMOS transistor M12 is connected to the bias voltage terminal Vbias1; the source terminal of M12 is connected to the drain terminal of the NMOS transistor M13. The gate terminal of the NMOS transistor M13 is connected to the bias voltage terminal Vbias0, and the source terminal of M13 is connected to ground GND.

[0098] like Figure 7 As shown, in this example, the compensation circuit may include: a compensation capacitor Ctail and a compensation resistor Rtail. The positive end of the compensation resistor Rtail is connected to the output terminal Vout of the operational amplifier and is connected to the drain terminal of the PMOS tube M11 and the drain terminal of the NMOS tube M12; the negative end of the compensation capacitor Ctail is connected to the drain terminals of the NMOS tubes M3 and M4 and the source terminal of the NMOS tube M2, and the positive end of the compensation capacitor Ctail is connected to the negative end of the compensation resistor Rtail. It should be noted that in actual applications, the connection order of the compensation capacitor Ctail and the compensation resistor Rtail is not limited. In other words, in addition to the above connection method, the following connection method can also be adopted: the negative end of the compensation resistor Rtail is connected to the drain terminals of the NMOS tubes M3 and M4 and the source terminal of the NMOS tube M2, the positive end of the compensation capacitor Ctail is connected to the output terminal Vout of the operational amplifier and is connected to the drain terminal of the PMOS tube M11 and the drain terminal of the NMOS tube M12, and the positive end of the compensation resistor Rtail is connected to the negative end of the compensation capacitor Ctail.

[0099] like Figure 7 As shown, in this example, the positive feedback tuning circuit may include: a positive feedback tuning capacitor Cadd. The positive terminal of the positive feedback tuning capacitor Cadd is connected to the drain terminal of the NMOS transistor M3 and the source terminal of the NMOS transistor M5; and the negative terminal of the positive feedback tuning capacitor Cadd is connected to the ground GND.

[0100] The following will Figure 8 The operational amplifier based on Miller compensation shown Figure 9The operational amplifier based on common source and common gate compensation is compared with the operational amplifier based on tail current compensation in the embodiment of the present application to explain why the operational amplifier based on tail current compensation in the embodiment of the present application has better power supply suppression performance at high frequencies.

[0101] like Figure 8 The figure shows an operational amplifier based on Miller compensation. The output transistor is generally large, and at high frequencies, the degradation of power supply rejection introduced by the parasitic gate-source capacitance Cgs11 of M11 must be considered. As the frequency increases, power supply interference is coupled to the gate of M11 through Cgs11, and then to the output terminal Vout through the Miller compensation resistor Rmc and the Miller compensation capacitor Cmc, thus degrading the power supply rejection of the operational amplifier at high frequencies.

[0102] like Figure 9 The figure shows an operational amplifier based on cascode compensation. Since the compensation capacitor Ccas is not connected to the gate of the PMOS output transistor, the gate-source parasitic capacitance Cgs11 of M11 does not need to be considered during high-frequency analysis. Specifically, as the frequency increases, power supply interference is coupled to the drain of M4 through the PMOS transistors M10, M8, and NMOS transistor M6, and then coupled to the output terminal Vout through the cascode compensation capacitor Ccas. Because M10, M8, and M6 suppress power supply noise more than the gate-source parasitic capacitance Cgs11, the power supply noise coupled to the output terminal through the compensation capacitor is much lower than that of the Miller compensation structure, thus improving the power supply rejection of the operational amplifier at high frequencies.

[0103] like Figure 10 The figure shows an exemplary circuit structure of an operational amplifier based on tail current compensation in an embodiment of the present application. Since the compensation capacitor Ctail is not connected to the gate terminal of the PMOS output tube, the gate-source parasitic capacitance Cgs11 of M11 does not need to be considered during high-frequency analysis. As the frequency increases, the interference on the power supply is coupled to the drain terminal of M1 through the PMOS tubes M10, M8 and the NMOS tubes M6, M4, and then coupled to the output terminal Vout through the tail current compensation capacitor Ctail. Since there is a feedforward tuning capacitor Cadd to the ground at the source terminal of M5, the power supply noise coupled from M9, M10 and M5 is short-circuited to the ground and will not be coupled to the output terminal. In this way, the tail current compensation capacitor passes through more suppression paths, so the power supply noise coupled to the output terminal through the compensation capacitor is lower than the common source and common gate compensation structure, so the power supply suppression characteristics at high frequencies are better.

[0104] like Figure 11 As shown, after the tail current compensation capacitor Ctail is introduced into the operational amplifier of the embodiment of the present application, there is a positive feedback loop in which the output signal passes through M3, M5, M10, M8 and M11. In this way, the positive feedback loop gain can be attenuated by introducing the positive feedback tuning circuit. In the embodiment of the present application, Figure 11As shown, one implementation of the positive feedback tuning circuit is to use a ground capacitor Cadd, which is connected to the drain terminal of M3 and the source terminal of M5 to ensure the stability of the operational amplifier.

[0105] The following describes the circuit stability when constructing an LDO circuit using operational amplifiers with Miller compensation, cascode compensation, and tail current compensation.

[0106] Table 1 below compares the compensation component values ​​and compensation results for operational amplifiers based on Miller compensation, cascode compensation, and tail current compensation. This table compares the compensation component values ​​and compensation results for the same phase margin. It can be seen that, under the same phase margin conditions, tail current compensation has the smallest compensation capacitance and the highest gain margin, while Miller compensation has the largest compensation capacitance and the lowest gain margin.

[0107] Table 1

[0108]

[0109] Figure 12 The simulation results of power supply rejection performance when constructing LDO based on operational amplifiers with different compensation methods are given. The solid line corresponds to tail current compensation (Tail Compensation), and the two dotted lines correspond to cascode compensation (Cascode Compensation) and Miller compensation (Miller Compensation). Figure 12 It can be seen that the maximum power supply rejection ratio (PSRR) of the LDO built with the Miller-compensated operational amplifier is -4.90dB; the PSRR of the LDO built with the cascode-compensated operational amplifier is -12.64dB; and the maximum PSRR of the LDO built with the tail-current-compensated operational amplifier in the embodiment of the present application is -25.19dB. This shows that when the LDO built with the tail-current-compensated operational amplifier in the embodiment of the present application is built, the PSRR at higher frequencies can be improved by 20dB.

[0110] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. An operational amplifier comprising a first-stage gain circuit and a second-stage gain circuit connected to each other, wherein the first-stage gain circuit is provided with an input terminal, the second-stage gain circuit is provided with an output terminal, and the first-stage gain circuit includes at least a tail current source, characterized in that: The operational amplifier further includes a tail current compensation circuit, wherein One end of the tail current compensation circuit is connected to the tail current source, and the other end is connected to the output end of the second-stage gain circuit, and the tail current compensation circuit is used to compensate the output signal to the tail current source; Also includes: positive feedback tuning circuit, One end of the positive feedback tuning circuit is connected to the first-stage gain circuit, and the other end is grounded, so as to suppress the positive feedback path introduced by the tail current compensation circuit.

2. The operational amplifier according to claim 1, wherein The tail current compensation circuit includes a compensation capacitor.

3. The operational amplifier according to claim 2, wherein: The tail current compensation circuit further includes a compensation resistor connected in series with the compensation capacitor.

4. The operational amplifier according to claim 1, wherein The positive feedback tuning circuit includes one of the following or a series-parallel combination thereof: capacitance; resistance; inductance; Active devices.

5. The operational amplifier according to claim 1, wherein The first-stage gain circuit further includes a first-stage amplifier circuit and a current mirror load circuit connected to each other. The first-stage amplifier circuit is connected to the tail current source and the tail current compensation circuit.

6. The operational amplifier according to claim 5, wherein: The first-stage amplifier circuit includes one of the following: Differential input, single-ended output common-source common-gate amplifier circuit; A common source amplifier circuit with differential input and single-ended output.

7. The operational amplifier according to claim 6, wherein: The second-stage gain circuit includes one of the following: Common source amplifier circuit with single-ended input and single-ended output; A common-source common-gate amplifier circuit with single-ended input and single-ended output.

8. The operational amplifier according to claim 5, wherein: The first-stage amplifier circuit includes: an amplifier circuit with differential input and differential output; The second-stage gain circuit includes an amplifier circuit with differential input and single-ended output.

9. The operational amplifier according to claim 5, wherein: The current mirror load circuit includes a cascode current mirror circuit.

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