Imaging element, imaging device and imaging method

Abstract

The present disclosure relates to an imaging element. The imaging element includes a first pixel. The first pixel includes a first photoelectric conversion region, which is arranged in a first substrate and converts incident light into a first charge. The first pixel includes a first readout circuit, which includes a first converter, and the first converter converts the first charge into a first logarithmic voltage signal. The imaging element includes at least one bonding pad, which is located on the first substrate and is in electrical contact with the first converter. The at least one bonding pad overlaps with at least a portion of the first pixel. For example, the present disclosure can reduce noise, provide more design flexibility and / or improve sensitivity and speed.

Description

Technical Field

[0001] The present disclosure relates to an imaging element having dynamic vision sensor capabilities. Background Art

[0002] Conventional imaging devices and the like use synchronous imaging elements that capture image data in synchronization with a synchronization signal, such as a vertical synchronization signal. Typical synchronous imaging elements have difficulty acquiring image data for each period of the synchronization signal (e.g., every 1 / 60 second), making it difficult to cope with relatively high-speed processing required in fields such as autonomous vehicles and robots, where high-speed (e.g., real-time) processing is required. Summary of the Invention

[0003] [Technical Issues]

[0004] At least one example embodiment provides an asynchronous imaging element, in which a detection circuit is set for each pixel to detect in real time the situation where the light contrast exceeds a threshold as an address event. The asynchronous imaging element that detects address events for each pixel is also called a dynamic vision sensor (DVS). In addition to the circuit structure for reading out the pixel signal of the voltage value corresponding to the amount of light received, the DVS system also uses a circuit structure for detecting address events. Therefore, since these two circuit structures are formed in the same substrate as the light receiving element, the occupancy rate of the light receiving element on the light receiving surface is reduced. However, due to wiring congestion, this 2-D architecture will lead to bottlenecks, resulting in reduced design flexibility, increased dark noise and / or limited sensitivity and speed.

[0005] Thus, example embodiments provide an imaging element that can reduce noise, provide more design flexibility, and / or improve sensitivity and speed.

[0006] [Solution to the problem]

[0007] At least one example embodiment relates to an imaging element, comprising: a first pixel including a first photoelectric conversion region disposed in a first substrate and converting incident light into first charges; and a first readout circuit including a first converter that converts the first charges into a first logarithmic voltage signal. The imaging element includes at least one bonding pad located on the first substrate and electrically contacting the first converter, the at least one bonding pad overlapping at least a portion of the first pixel.

[0008] In at least one example embodiment, the first converter includes a first portion disposed in the first substrate, and the first portion includes a transistor coupled to the first photoelectric conversion region. In a plan view, a source of the transistor is wider than a drain of the transistor.

[0009] In at least one example embodiment, the imaging element includes a second substrate bonded to the first substrate via the at least one bonding pad.The first converter includes a second portion disposed in the second substrate.

[0010] In at least one example embodiment, the first portion includes a node coupled to the photoelectric conversion region, and the second portion includes a plurality of transistors coupled to the node through the at least one bonding pad.

[0011] In at least one example embodiment, the imaging element includes a plurality of through-vias disposed in the first substrate and in electrical contact with the at least one bonding pad and the first converter.

[0012] In at least one example embodiment, the first converter is disposed in the first substrate. The at least one bonding pad includes a first bonding pad electrically contacting a first node of the first converter and a second bonding pad electrically contacting a second node of the first converter.

[0013] In at least one example embodiment, the first node is a power node of the first converter, the power node receiving a power signal, and the second node is an output node of the first converter, the output node outputting an output signal to another component of the first readout circuit.

[0014] In at least one example embodiment, the at least one bonding pad includes a third bonding pad electrically contacting a third node of the first converter, wherein the third node is a node of the photoelectric conversion region or a ground node of the first converter, the ground node receiving a ground signal or a common signal.

[0015] In at least one example embodiment, the first node is a node of the photoelectric conversion region, and the second node is a ground node of the first converter, the ground node receiving a ground signal or a common signal.

[0016] In at least one example embodiment, the at least one bonding pad includes a third bonding pad electrically contacting a third node of the first converter. The third node is a power node of the first converter, the power node receiving a power signal, or an output node of the first converter, the power node outputting an output signal to another component of the first readout circuit.

[0017] In at least one example embodiment, the at least one bonding pad includes a third bonding pad in electrical contact with a third node of the first converter and a fourth bonding pad in electrical contact with a fourth node of the first converter.

[0018] In at least one example embodiment, the third node is a power node of the first converter, the power node receiving a power supply voltage. The fourth node is an output node of the first converter, the output node outputting an output signal to another component of the first readout circuit.

[0019] In at least one example embodiment, the imaging element further includes a second readout circuit. The first readout circuit controls the second readout circuit.

[0020] At least one example embodiment relates to an imaging element, comprising a first pixel. The first pixel comprises a first photoelectric conversion region disposed in a first substrate and converting incident light into a first charge; and a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal. The imaging element comprises at least one first bonding pad disposed on the first substrate and electrically contacting the first converter, the at least one first bonding pad overlapping at least a portion of the first pixel. The imaging element comprises a second pixel adjacent to the first pixel. The second pixel comprises a second photoelectric conversion region disposed in the first substrate and converting incident light into a second charge; and a second readout circuit comprising a second converter that converts the second charge into a second logarithmic voltage signal. The imaging element comprises at least one second bonding pad disposed on the first substrate and electrically contacting the second converter, the at least one second bonding pad overlapping at least a portion of the second pixel.

[0021] In at least one example embodiment, the imaging element further includes an isolation region disposed in the first substrate between the first pixel and the second pixel.

[0022] In at least one example embodiment, the at least one first bonding pad includes a plurality of first bonding pads electrically connected to respective first nodes of the first converter.The at least one second bonding pad includes a plurality of second bonding pads electrically connected to respective second nodes of the second converter.

[0023] In at least one example embodiment, one of the plurality of second bonding pads overlaps at least a portion of the second pixel and the isolation region.

[0024] In at least one example embodiment, one of the plurality of second bonding pads overlaps with a portion of the first pixel.

[0025] At least one example embodiment relates to an imaging element, comprising a first pixel. The first pixel includes a first photoelectric conversion region disposed in a first substrate and converting incident light into a first charge; and a first readout circuit including a first converter that converts the first charge into a first logarithmic voltage signal. The imaging element includes a plurality of first bonding pads located on the first substrate and electrically contacting corresponding nodes of the first converter, each of the plurality of first bonding pads overlapping at least a portion of the first pixel.

[0026] In at least one example embodiment, the corresponding nodes of the first converter include two or more of the following nodes: a power supply node that receives a power supply voltage, an output node that outputs an output signal to another component of the first readout circuit, a node of the first photoelectric conversion region, and a ground node that receives a ground signal or a common signal.

[0027] [Beneficial Effects]

[0028] The imaging element according to the present disclosure can reduce noise, provide more design flexibility, and / or improve sensitivity and speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a schematic configuration example of an imaging device according to at least one example embodiment.

[0030] Figure 2 is a diagram illustrating an example of a stacked structure of an imaging element according to at least one example embodiment.

[0031] Figure 3A is a block diagram illustrating a functional configuration example of an imaging element according to at least one example embodiment.

[0032] Figure 3B is a block diagram illustrating a functional configuration example of an imaging element according to at least one example embodiment.

[0033] Figure 4 is a schematic diagram illustrating an array example of unit pixels according to at least one example embodiment in a case where a Bayer array is adopted in a color filter array.

[0034] Figure 5A is a circuit diagram illustrating a schematic configuration example of a unit pixel according to at least one example embodiment.

[0035] Figure 5Bis a circuit diagram illustrating a schematic configuration example of a unit pixel according to at least one example embodiment.

[0036] Figure 6 is a block diagram illustrating a schematic configuration example of an address event detection unit according to at least one example embodiment.

[0037] Figure 7 is a circuit diagram illustrating a schematic configuration example of a subtractor and a quantizer according to at least one example embodiment.

[0038] Figure 8 is a block diagram illustrating a schematic configuration example of a column ADC according to at least one example embodiment.

[0039] Figure 9 is a timing chart illustrating an example of the operation of an imaging element according to at least one example embodiment.

[0040] Figure 10A is a flowchart illustrating an example of the operation of an imaging element according to at least one example embodiment.

[0041] Figure 10B is a flowchart illustrating an example of the operation of an imaging element according to at least one example embodiment.

[0042] Figure 11 is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0043] Figure 12 is a plan view of an example layout of a portion of a converter 410 and a photoelectric conversion region according to at least one example embodiment.

[0044] Figure 13 is a plan view of an example layout of a portion of a converter 410 and a photoelectric conversion region according to at least one example embodiment.

[0045] Figure 14 is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0046] Figure 15 is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0047] Figure 16 is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0048] Figure 17is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0049] Figure 18 is a plan view of an example layout of a portion of a converter and a photoelectric conversion region according to at least one example embodiment.

[0050] Figure 19A According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0051] Figure 19B Shown is a view taken along line XIX-XIX Figure 19A Cross-sectional view.

[0052] Figure 20 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0053] Figure 21 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0054] Figure 22 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0055] Figure 23 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0056] Figure 24 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0057] Figure 25 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0058] Figure 26 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0059] Figure 27 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0060] Figure 28 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0061] Figure 29 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0062] Figure 30 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0063] Figure 31 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0064] Figure 32 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0065] Figure 33 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0066] Figure 34 According to at least one example embodiment, Figure 5BAn example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0067] Figure 35 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0068] Figure 36 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0069] Figure 37 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0070] Figure 38 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0071] Figure 39 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0072] Figure 40 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0073] Figure 41 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0074] Figure 42 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0075] Figure 43 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0076] Figure 44 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0077] Figure 45 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0078] Figure 46 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0079] Figure 47 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0080] Figure 48 According to at least one example embodiment, Figure 5B An example schematic of a converter in FIG. 1 and an example layout of bonding pads that electrically connect circuitry in a logic chip to nodes for each pixel.

[0081] Figure 49 An example structure of a transistor according to at least one example embodiment is shown.

[0082] Figure 50 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0083] Figure 51 2 is a diagram showing an example of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0084] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. In addition, in the following embodiments, the same reference numerals are used for the same parts, and redundant descriptions thereof will be omitted.

[0085] A typical dynamic vision sensor (DVS) adopts a so-called event-driven driving method, in which the presence or absence of an address event trigger is detected for each unit pixel, and a pixel signal is read out from the unit pixel where the address event trigger is detected.

[0086] In addition, the unit pixel in this specification refers to the minimum unit of a pixel including one photoelectric conversion element (also referred to as a "light receiving element"), and can correspond to each point in the image data read out from the image sensor as an example. In addition, an address event refers to an event that occurs for each address that can be assigned to each of a plurality of unit pixels arranged in a two-dimensional grid. Examples of address events include events in which the current value of the photocurrent based on the charge generated in the photoelectric conversion element or the amount of change thereof exceeds a desired constant threshold. That is, the DVS device can respond asynchronously to changes in light intensity. Changes in light intensity are correlated with changes in photocurrent, and if the change in photocurrent exceeds a desired threshold, an event can be detected.

[0087] Figure 1 1 is a block diagram showing a schematic configuration example of an imaging device according to at least some embodiments of the present disclosure. Figure 1 As shown, for example, the apparatus 100 includes an imaging lens 110, a solid-state imaging element (or imaging element) 200, a recording unit (or memory) 120, and a control unit (or controller) 130. As an example, the apparatus 100 may be configured as a camera or a portion thereof installed in a hypothetical industrial robot, a vehicle-mounted camera, or the like.

[0088] The imaging lens 110 may include an optical system that converges incident light and images an image of the incident light on a light-receiving surface of the imaging element 200. The light-receiving surface is a surface on which the photoelectric conversion element in the imaging element 200 is arranged. The imaging element 200 performs photoelectric conversion on the incident light to generate image data. In addition, the imaging element 200 may perform predetermined signal processing such as noise removal and white balance adjustment with respect to the generated image data. The result obtained by the signal processing and the detection signal indicating the presence or absence of an address event trigger (or event) are output to the recording unit 120 through the signal line 209. In addition, the method of generating the detection signal indicating the presence or absence of an address event trigger will be described later.

[0089] For example, the recording unit 120 is configured by a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, and records data input from the imaging element 200 .

[0090] The control unit 130 is configured by, for example, a central processing unit (CPU) or the like, and outputs various instructions through a signal line 139 to control the respective units such as the imaging element 200 in the device 100 .

[0091] Next, a configuration example of the imaging element 200 will be described in detail with reference to the drawings.

[0092] Figure 2 is a diagram showing an example of a stacked structure of an imaging element according to at least some embodiments of the present disclosure. Figure 2 As shown, the imaging element 200 can have a structure in which a light receiving chip (or substrate) 201 and a logic chip (or substrate) 202 are vertically stacked. For example, the light receiving chip 201 and the logic chip 202 can be bonded together using so-called direct bonding, in which the bonding surfaces of the chips are flattened and the chips are stacked using inter-electron forces. However, this is not limited to this, and for example, so-called Cu-Cu bonding, in which copper (Cu) electrode pads formed on the bonding surfaces are bonded, or bump bonding can also be used.

[0093] In addition, for example, the light receiving chip 201 and the logic chip 202 are electrically connected to each other via a connection portion such as a through-silicon via (TSV) that penetrates the semiconductor substrate. In connection using TSVs, for example, a so-called double TSV method and a so-called shared TSV method can be adopted. In the so-called double TSV method, the two TSVs, including a TSV formed in the light receiving chip 201 and a TSV formed from the light receiving chip 201 to the logic chip 202, are connected to each other on the chip outer surface. In the so-called shared TSV method, the light receiving chip 201 and the logic chip 202 are connected using a TSV that penetrates the two chips.

[0094] However, in the case of using Cu-Cu bonding or bump bonding in bonding the light receiving chip 201 and the logic chip 202 , the light receiving chip 201 and the logic chip 202 are electrically connected to each other through the Cu-Cu joint or the bump joint.

[0095] Figure 3A is a block diagram illustrating an example of a functional configuration of an imaging element according to at least some embodiments of the present disclosure. Figure 3A As shown, the imaging element 200 includes a driving circuit 211 , a signal processing unit (or signal processor) 212 , an arbitrator 213 , a column ADC 220 , and a pixel array unit 300 .

[0096] A plurality of unit cells or unit pixels (or pixels) 310 are arranged in a two-dimensional lattice in a pixel array unit (or pixel array) 300. The details of the unit pixel 310 will be described later. For example, each unit pixel 310 includes a photoelectric conversion element (or photoelectric conversion area) such as a photodiode and a circuit (hereinafter referred to as a pixel circuit or a pixel imaging signal generation readout circuit) that generates a pixel signal of a voltage value corresponding to the amount of charge generated in the photoelectric conversion element. Here, the pixel circuit can be shared by multiple photoelectric conversion elements. In this case, each unit pixel 310 includes a photoelectric conversion element and a shared pixel circuit.

[0097] A plurality of unit pixels 310 are arranged in a two-dimensional grid in the pixel array unit 300. The plurality of unit pixels 310 can be grouped into a plurality of pixel blocks, each of which includes a desired number of unit pixels. Hereinafter, a set of unit pixels arranged in a horizontal direction is referred to as a "row," and a set of unit pixels arranged in a direction orthogonal to a row is referred to as a "column."

[0098] Each unit pixel 310 generates a charge corresponding to the amount of light received at each photoelectric conversion element. Furthermore, a unit pixel 310 can operate alone or in conjunction with one or more other unit pixels 310 in the same group to detect the presence or absence of an address event trigger based on whether the value of the current of the charge generated in the photoelectric conversion element (hereinafter referred to as photocurrent) or the amount of change in the current exceeds a predetermined threshold. Furthermore, when an address event is triggered, a request for a pixel signal to read out a voltage value corresponding to the amount of light received by the photoelectric conversion element is output to the arbitrator 213.

[0099] The driving circuit 211 drives each unit pixel 310 and allows each unit pixel 310 to output a pixel signal to the column ADC 220 .

[0100] The arbitrator 213 arbitrates requests from the respective unit pixels and, based on the arbitration result, transmits a predetermined response to the requesting unit pixel 310. The unit pixel 310 that receives the response supplies a detection signal indicating the presence or absence of an address event trigger (hereinafter, simply referred to as an "address event detection signal") to the driving circuit 211 and the signal processing unit 212.

[0101] The column ADC 220 converts the analog pixel signal from each column of the unit pixels 310 into a digital signal, and supplies the digital signal generated by the conversion to the signal processing unit 212 .

[0102] The signal processing unit 212 performs predetermined signal processing such as correlated double sampling (CDS) processing (noise removal) and white balance adjustment on the digital signal transmitted from the column ADC 220. In addition, the signal processing unit 212 supplies the signal processing result and the address event detection signal to the recording unit 120 through the signal line 209.

[0103] exist Figure 3A In the illustrated configuration, for example, pixel array unit 300 is composed of a collection of unit pixels that receive wavelength components to reconstruct colors. For example, when reconstructing colors based on the three primary colors of RGB, in pixel array unit 300, unit pixels 310 that receive red (R) light, unit pixels 310 that receive green (G) light, and unit pixels 310 that receive blue (B) light are arranged in a predetermined color filter array.

[0104] Examples of color filter arrays include various arrays such as a 2×2 pixel Bayer array, a 3×3 pixel color filter array adopted in an X-Trans (registered trademark) CMOS sensor (hereinafter, also referred to as an "X-Trans (registered trademark) type array"), a 4×4 pixel Quad Bayer array (also referred to as a "Quadra array"), and a 4×4 pixel color filter array in which white RGB filters are combined into a Bayer array (hereinafter, also referred to as a "white RGB array"). Here, in the following description, a case where a Bayer array is adopted as a color filter array will be exemplified. However, the example embodiment is not limited to the pixel array unit 300 having a color filter. For example, in a case where color detection is not required, the color filter can be omitted from the pixel 310. In this case, the imaging element 200 can be used to detect an event without color information (refer to Figure 3B In at least one example embodiment, the pixel 310 may include different types of filters, such as an infrared (IR) cut-off filter.

[0105] Figure 3B 1 is a block diagram showing an example of a functional configuration of an imaging element 200A according to at least one example embodiment. Figure 3B Excluding column ADC 220, Figure 3B The imaging element 200A in Figure 3A The imaging element 200 in is the same or similar. Figure 3B Can be used for event detection-only applications (ie, applications that do not require color detection). Figure 5B Shown Figure 3B In the circuit of pixel 310A, Figure 10B An example operation of the imaging element 200A is shown.

[0106] Figure 41 is a schematic diagram showing an example of an array of unit pixels in the case where the Bayer array is adopted in the color filter array. Figure 4 As shown, when the Bayer array is used as the color filter array, a basic pattern 312 of four unit pixels, consisting of 2×2 pixels, is repeatedly arranged in the column and row directions in the pixel array unit 300. For example, the basic pattern 312 is composed of a unit pixel 310R including a red (R) color filter, a unit pixel 310Gr including a green (Gr) color filter, a unit pixel 310Gb including a green (Gb) color filter, and a unit pixel 310B including a blue (B) color filter.

[0107] Next, a configuration example of the unit pixel 310 will be described. Figure 5A is a circuit diagram showing a schematic configuration example of a unit pixel 310 according to at least some embodiments of the present disclosure. Figure 5A As shown, for example, the unit pixel 310 includes a pixel imaging signal generating unit (or readout circuit) 320, a light receiving unit 330, and an address event detecting unit (or readout circuit) 400. According to at least one example embodiment, the readout circuit 400 is configured to control the readout circuit 320 based on the charge generated by the photoelectric conversion element (or photoelectric conversion region) 333. In addition, Figure 5A The logic circuit 210 includes, for example, Figure 3A The driving circuit 211, the signal processing unit 212 and the logic circuit of the arbiter 213 are shown in FIG.

[0108] For example, the light receiving unit 330 includes a transfer transistor (first transistor) 331, an overflow gate (OFG) transistor (fifth transistor) 332, and a photoelectric conversion element 333. A transmission signal TRG transmitted from the drive circuit 211 is supplied to the gate of the transfer transistor 331 of the light receiving unit 330, and a control signal OFG transmitted from the drive circuit 211 is supplied to the gate of the OFG transistor 332. The output of the transfer transistor 331 of the light receiving unit 330 is connected to the pixel imaging signal generating unit 320, and the output of the OGF transistor 332 is connected to the address event detecting unit 400.

[0109] For example, the pixel imaging signal generating unit 320 includes a reset transistor (second transistor) 321 , an amplifying transistor (third transistor) 322 , a selecting transistor (fourth transistor) 323 , and a floating diffusion layer (FD) 324 .

[0110] For example, the transfer transistor 331 and the OFG transistor 332 of the light receiving unit 330 are constructed by using an N-type metal oxide semiconductor (MOS) transistor (hereinafter referred to as an "NMOS transistor"). Similarly, for example, the reset transistor 321, the amplifying transistor 322, and the selection transistor 323 of the pixel imaging signal generating unit 320 are each constructed by using an NMOS transistor. Here, it should be understood that, for example, if color detection is not required, the OFG transistor 332 can be omitted when necessary. In this case, an electrical short circuit replaces the OFG transistor 332.

[0111] For example, the address event detection unit 400 includes a current-voltage conversion unit (or converter) 410 and a subtractor 430. However, the address event detection unit 400 is further provided with a buffer (eg, Figure 6 In the following description, the buffer 420 in the quantizer and the transmission unit are used. Figure 6 Details of the address event detection unit 400 will be described in detail.

[0112] In this configuration, the photoelectric conversion element 333 of the light receiving unit 330 performs photoelectric conversion on incident light to generate electric charge. In response to a transfer signal TRG, the transfer transistor 331 transfers the electric charge generated in the photoelectric conversion element 333 to the floating diffusion layer 324. In response to a control signal OFG, the OFG transistor 332 supplies an electric signal (photocurrent) based on the electric charge generated in the photoelectric conversion element 333 to the address event detection unit 400.

[0113] The floating diffusion layer 324 accumulates the charge transferred from the photoelectric conversion element 333 via the transfer transistor 331. The reset transistor 321 discharges (initializes) the charge accumulated in the floating diffusion layer 324 in accordance with a reset signal transmitted from the driver circuit 211. The amplifier transistor 322 allows a pixel signal having a voltage value corresponding to the amount of charge accumulated in the floating diffusion layer 324 to appear on the vertical signal line (VSL). The select transistor 323 switches the connection between the amplifier transistor 322 and VSL in accordance with a select signal SEL transmitted from the driver circuit 211. Furthermore, the analog pixel signal appearing in VSL is read out by the column ADC 220 and converted into a digital pixel signal.

[0114] When the control unit 130 gives an instruction for address event detection start, the drive circuit 211 in the logic circuit 210 outputs a control signal OFG for setting the OFG transistors 332 of all the light receiving cells 330 in the pixel array unit 300 to a conductive state. With this configuration, the photocurrent generated in the photoelectric conversion element 333 of the light receiving cell 330 is supplied to the address event detection unit 400 of each unit pixel 310 through the OFG transistor 332.

[0115] When an address event trigger is detected based on the photocurrent from the light receiving unit 330, the address event detection unit 400 of each unit pixel 310 outputs a request to the arbiter 213. To this end, the arbiter 213 arbitrates the requests sent from the respective unit pixels 310 and sends a response based on the arbitration result to the unit pixel 310 that issued the request. The unit pixel 310 that receives the response supplies a detection signal indicating the presence or absence of the address event trigger (hereinafter referred to as an "address event detection signal") to the drive circuit 211 and the signal processing unit 212 in the logic circuit 210.

[0116] The driving circuit 211 turns off the OFG transistor 332 in the unit pixel 310 that is the supply source of the address event detection signal. With this configuration, the supply of photocurrent from the light receiving unit 330 to the address event detection unit 400 is stopped in the unit pixel 310.

[0117] Next, the drive circuit 211 turns on the transfer transistor 331 in the light receiving unit 330 of the unit pixel 310 via the transfer signal TRG. With this configuration, the charge generated in the photoelectric conversion element 333 of the light receiving unit 330 is transferred to the floating diffusion layer 324 via the transfer transistor 331. Furthermore, a pixel signal having a voltage value corresponding to the amount of charge accumulated in the floating diffusion layer 324 appears on the vertical signal line VSL connected to the select transistor 323 of the pixel imaging signal generating unit 320.

[0118] As described above, in the imaging element 200 , the pixel signal SIG is output to the column ADC 220 from the unit pixel 310 in which the address event trigger is detected.

[0119] Furthermore, for example, two logic (LG) transistors (sixth and seventh transistors) 411 and 414 and two amplifying transistors (eighth and ninth transistors) 412 and 413 in the light receiving unit 330, the pixel imaging signal generating unit 320, and the current-voltage converting unit 410 of the address event detecting unit 400 are arranged in, for example Figure 2 The light receiving chip 201 is shown in FIG. 1 , and other components (e.g., the logic circuit 210) are configured in the logic chip 202 that is bonded to the light receiving chip 201 by, for example, Cu-Cu bonding or joining. However, example embodiments are not limited thereto, and the transistors 411, 412, 413, and 414 may be located in the logic chip 202 (e.g., see FIG. 1 ). Figure 21 ). Figure 5A Node 510 is shown, which indicates the point at which electrical contact is made between node 510 and a bond pad (e.g., a copper bond pad). Here, it should be understood that Figure 5A A schematic diagram is shown in which both event detection and color detection are required. However, if only event detection is required, then Figure 5A The schematic diagram can be changed to include only the event detection component 515 (see Figure 5B That is, if the application does not need to detect color information, it can be obtained from Figure 5A The circuits related to color detection are omitted or skipped in the circuit diagram.

[0120] Figure 5B is a circuit diagram illustrating a schematic configuration example of a unit pixel (or pixel) 310A according to at least some embodiments of the present disclosure. For example, Figure 5B Shown Figure 5A It should be understood that when color detection is not required, the event detection component 515 can be used. Figure 5B .Right now, Figure 5B Only event detection is involved. Figure 5B The OFG transistor 332 is shown as included, however, the OFG transistor 332 may be omitted when necessary, so that the photoelectric conversion element 333 is directly coupled to the transistors 411 and 413 (eg, referring to FIG. 4 ). Figures 11-18 In this case, the signal line from the logic circuit 210 to the OFG transistor 332 can also be omitted.

[0121] and Figure 5A Same as in Figure 5B Example nodes 510 are shown representing locations of electrical contact to bond pads. Figures 19A-51 Various examples of node 510 for converter 410 and bond pad configurations for bond pad CC are shown.

[0122] Here, it should also be understood that Figure 5A and Figure 5B A four transistor (4T) configuration of converter 410 is shown. Figures 11-13 An example layout of a 4T configuration is shown in more detail. However, example embodiments are not limited thereto. For example, in at least one example embodiment, transistors 414 and 412 may be omitted to form a two-transistor (2T) configuration. The 2T configuration can reduce the overall footprint of each unit pixel 310. In the 2T configuration, transistor 411 is coupled to power supply terminal VDD instead of transistor 414, and transistor 413 is coupled to constant current circuit 415 instead of transistor 412. Figures 14-18 An example layout of a 2T formation is shown in more detail.

[0123] Figure 6 1 is a block diagram illustrating a schematic configuration example of an address event detection unit according to at least some example embodiments of the present disclosure. Figure 6As shown, the address event detection unit 400 includes a current-voltage conversion unit 410 , a buffer 420 , a subtractor 430 , a quantizer 440 , and a transmission unit 450 .

[0124] The current-voltage conversion unit 410 converts the photocurrent from the light receiving unit 330 into a voltage signal in the logarithmic form thereof, and supplies the voltage signal generated by the conversion to the buffer 420 .

[0125] The buffer 420 corrects the voltage signal transmitted from the current-voltage conversion unit 410 and outputs the corrected voltage signal to the subtractor 430 .

[0126] The subtractor 430 lowers the voltage level of the voltage signal transmitted from the buffer 420 according to the row driving signal transmitted from the driving circuit 211 and supplies the lowered voltage signal to the quantizer 440 .

[0127] The quantizer 440 quantizes the voltage signal transmitted from the subtractor 430 into a digital signal, and outputs the digital signal generated by the quantization to the transmission unit 450 as a detection signal.

[0128] The transmission unit 450 transmits the detection signal transmitted from the quantizer 440 to the signal processing unit 212, etc. For example, when an address event trigger is detected, the transmission unit 450 supplies a request to the arbiter 213 to transmit the address event detection signal from the transmission unit 450 to the driver circuit 211 and the signal processing unit 212. In addition, when a response to the request is received from the arbiter 213, the transmission unit 450 supplies the detection signal to the driver circuit 211 and the signal processing unit 212.

[0129] For example, Figure 6 The current-voltage conversion unit 410 in the illustrated configuration has a 4T configuration including two LG transistors 411 and 414 , two amplifying transistors 412 and 413 , and a constant current circuit 415 as shown in FIG. 5 .

[0130] For example, the source of the LG transistor 411 and the gate of the amplifier transistor 413 are connected to the drain of the OFG transistor 332 of the light receiving unit 330. In addition, for example, the drain of the LG transistor 411 is connected to the source of the LG transistor 414 and the gate of the amplifier transistor 412. For example, the drain of the LG transistor 414 is connected to the power supply terminal VDD.

[0131] In addition, for example, the source of the amplifier transistor 413 is grounded, and the drain thereof is connected to the gate of the LG transistor 411 and the source of the amplifier transistor 412. For example, the drain of the amplifier transistor 412 is connected to the power supply terminal VDD via the constant current circuit 415. For example, the constant current circuit 415 is composed of a load MOS transistor such as a p-type MOS transistor.

[0132] This connection forms a ring-shaped source follower circuit. This configuration converts the photocurrent from the light receiving element 330 into a voltage signal in the form of a logarithmic value corresponding to the amount of charge. Furthermore, for example, the LG transistors 411 and 414 and the amplifier transistors 412 and 413 can each be formed of an NMOS transistor.

[0133] Figure 7 1 is a circuit diagram showing a schematic configuration example of a subtractor and a quantizer according to at least some embodiments of the present disclosure. Figure 7 As shown, the subtractor 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. In addition, the quantizer 440 includes a comparator 441.

[0134] One end of the capacitor 431 is connected to the output end of the buffer 420, and the other end is connected to the input end of the inverter 432. The capacitor 433 is connected in parallel with the inverter 432. The switch 434 opens or closes the path connecting both ends of the capacitor 433 according to the row driving signal.

[0135] The inverter 432 inverts the voltage signal input through the capacitor 431 . The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441 .

[0136] When switch 434 is closed, voltage signal Vinit is input to the buffer 420 side of capacitor 431. Furthermore, the opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance of capacitor 431 is set to C1, the potential Qinit accumulated in capacitor 431 is expressed by the following equation (1). On the other hand, since both ends of capacitor 433 are short-circuited, the accumulated charge becomes zero.

[0137] Qinit=C1×Vinit···(1)

[0138] Next, when considering a case where the switch 434 is turned off and the voltage of the capacitor 431 on the buffer 420 side changes and reaches Vafter, the charge Qafter accumulated in the capacitor 431 is expressed by the following equation (2).

[0139] Qafter=C1×Vafter···(2)

[0140] On the other hand, when the output voltage is set to Vout, the charge Q2 accumulated in the capacitor 433 is expressed by the following equation (3).

[0141] Q2=-C2×Vout···(3)

[0142] At this time, the total amount of charge of capacitors 431 and 433 does not change, so the following equation (4) is established.

[0143] Qinit=Qafter+Q2···(4)

[0144] When equations (1) to (3) are substituted into equation (4), the following equation (5) is obtained.

[0145] Vout=-(C1 / C2)×(Vafter-Vinit)···(5)

[0146] Formula (5) represents the subtraction operation of the voltage signal, and the gain of the subtraction result becomes C1 / C2. Generally, it is desired to maximize the gain (or alternatively, improve it), so it is preferable to form a design that makes C1 larger and C2 smaller. On the other hand, when C2 is too small, the kTC noise increases, so there is a concern that the noise characteristics will deteriorate. Therefore, the reduction of the capacitor C2 is limited to a range that can allow noise. In addition, since the address event detection unit 400 including the subtractor 430 is installed for each unit pixel 310, there is a limit on the area in the capacitors C1 and C2. The values ​​of the capacitors C1 and C2 are determined in consideration of this limit.

[0147] The comparator 441 compares the voltage signal transmitted from the subtractor 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (−) and outputs a signal indicating a comparison result to the transmission unit 450 as a detection signal.

[0148] In addition, when the conversion gain of the current-voltage conversion unit 410 is set to CG log When the gain of the buffer 420 is set to "1", the gain A of the entire address event detection unit 400 is expressed by the following equation (6).

[0149] [Mathematical formula 1]

[0150]

[0151] In formula (6), i photo _n represents the photocurrent of the n-th unit pixel 310, and its unit is, for example, ampere (A). N represents the number of unit pixels 310 in the pixel block, and is "1" in the present embodiment.

[0152] Figure 8Column ADC 220 includes a plurality of ADCs 230 provided for each column of unit pixels 310 .

[0153] Each ADC 230 converts the analog pixel signal appearing in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal in which the bit length is greater than the bit length of the detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three or more bits (16 bits, etc.). The ADC 230 supplies the generated digital signal to the signal processing unit 212. Here, it should be understood that, for example, if color detection is not required, it can be omitted (such as Figure 3B ) or do not use the column ADC 220.

[0154] Next, the operation of the imaging element 200 according to at least some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0155] First, an example of the operation of the imaging element 200 is described by using a timing chart. Figure 9 is a timing chart showing an example of the operation of the imaging element according to the first embodiment.

[0156] like Figure 9 As shown, at time T0, when the control unit 130 gives an instruction for start of address event detection, the drive circuit 211 raises the control signal OFG applied to the gates of the OFC transistors 332 of all the light receiving cells 330 in the pixel array unit 300 to a high level. With this configuration, the plurality of OFG transistors 332 of all the light receiving cells 330 enter a conductive state, and a photocurrent based on the charge generated in the photoelectric conversion element 333 of each light receiving cell 330 is supplied from each light receiving cell 330 to each of the plurality of address event detection units 400.

[0157] In addition, during the period when the control signal OFG is at a high level, all the transmission signals TRG applied to the gates of the transmission transistors 331 in the respective light receiving cells 330 are maintained at a low level. Therefore, during this period, the plurality of transmission transistors 331 in all the light receiving cells 330 are in an off state.

[0158] Next, assume the following situation: during a period in which the control signal OFG is at a high level, the address event detection unit 400 of any unit pixel 310 detects an address event trigger. In this case, the address event detection unit 400 that detects the address event trigger sends a request to the arbitrator 213. In response, the arbitrator 213 arbitrates the request and returns a response to the request to the address event detection unit 400 that issued the request.

[0159] For example, in the period from time T1 to time T2, the address event detection unit 400 that receives the response raises the detection signal input to the driver circuit 211 and the signal processing unit 212 to a high level. In this specification, it is assumed that the detection signal is a one-bit signal.

[0160] The driver circuit 211, to which the high-level detection signal is input from the address event detection unit 400 at time T1, lowers all the control signals OFG to a low level at the subsequent time T2. With this configuration, the supply of photocurrent from all the light receiving units 330 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0161] Furthermore, at time T2, the drive circuit 211 raises the select signal SEL applied to the gate of the select transistor 323 in the pixel imaging signal generating unit 320 of the unit pixel 310 in which the address event trigger is detected (hereinafter referred to as the "target unit pixel for readout") to a high level, and raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel imaging signal generating unit 320 to a high level at a constant pulse period, thereby discharging (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel imaging signal generating unit 320. In this manner, the voltage appearing in the vertical signal line VSL in a state where the floating diffusion layer 324 is initialized is read out by the ADC 230 in the column ADC 220, which is connected to the vertical signal line VSL, as a reset-level pixel signal (hereinafter simply referred to as the "reset level") and converted into a digital signal.

[0162] Next, at time T3 after the reset level is read out, the drive circuit 211 applies a transfer signal TRG of a constant pulse period to the gate of the transfer transistor 331 of the light receiving cell 330 in the target unit pixel 310 being read out. With this configuration, the charge generated in the photoelectric conversion element 333 of the light receiving cell 330 is transferred to the floating diffusion layer 324 in the pixel imaging signal generating unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this manner, the voltage appearing in the vertical signal line VSL is read out as a signal level pixel signal of the light receiving cell 330 (hereinafter, simply referred to as "signal level") by the ADC 230 in the column ADC 220, which is connected to the vertical signal line VSL, and converted into a digital value.

[0163] The signal processing unit 212 performs CDS processing in which the difference between the reset level and the signal level read out as described above is obtained as a net pixel signal corresponding to the light reception amount of the photoelectric conversion element 333 .

[0164] Next, at time T4, the drive circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 in the pixel imaging signal generation unit 320 of the target unit pixel 310 to be read out to a low level, and raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving cells 330 in the pixel array unit 300 to a high level. With this configuration, address event trigger detection in all the light receiving cells 330 within the pixel array unit 300 is resumed.

[0165] Next, an example of the operation of the imaging element 200 is described by using a flowchart. Figure 10A is a flowchart illustrating an example of the operation of an imaging element according to at least some embodiments of the present disclosure. For example, when a predetermined application for detecting an address event is executed, the operation is initiated.

[0166] like Figure 10A As shown, in this operation, first, each unit pixel 310 in the pixel array unit 300 detects the presence or absence of an address event trigger (step S901). In addition, the driving circuit 211 determines whether an address event trigger is detected in any unit pixel 310 (step S902).

[0167] If the address event trigger is not detected ("No" in step S902), the operation proceeds to step S904. On the other hand, if the address event trigger is detected ("Yes" in step S902), the drive circuit 211 reads out the pixel signal with respect to the unit pixel 310 in which the address event trigger is detected (step S903), and proceeds to step S904.

[0168] In step S904, it is determined whether to terminate the operation. If the operation is not terminated ("No" in step S904), the operation returns to step S901 and the subsequent operation is repeated. On the other hand, if the operation is terminated ("Yes" in step S904), the operation is terminated.

[0169] Figure 10B is a diagram illustrating at least some embodiments of the present disclosure. Figure 3B Flowchart of an example of the operation of the imaging element 200A. For example, Figure 10B An operation in which only event detection is performed by the imaging element 200A is shown.

[0170] In step S950, the temporal contrast of the brightness of a pixel (e.g., pixel 310A) is monitored. For example, according to the description provided above, the change in light intensity of the pixel is monitored by event detection component 515. In this case, transistor 332 (if included) and transistors 411, 412, 413, and 414 are all turned on simultaneously to monitor the change in light intensity.

[0171] In step S955, it is determined whether the change in temporal contrast is greater than a threshold. If the change in temporal contrast is not greater than the threshold, the method returns to step S950. If the change in temporal contrast is greater than the threshold, the method proceeds to step S960, where an event is detected, thereby outputting the address of the pixel and recording a timestamp of when the event occurred.

[0172] In step S965, the pixel is reset (eg, by closing switch 434).

[0173] Figures 11-18 Various example layouts of the photoelectric conversion region 333 and the converter 410 are shown. Although not explicitly shown, it should be understood that the transistors (e.g., source / drain regions) of the converter 410 and the photoelectric conversion region 333 are formed in a semiconductor substrate, such as a semiconductor substrate having p-type conductivity or a p-well. In addition, it should be further understood that Figures 11-18 The OFG transistor 332 has been omitted between the photoelectric conversion region 333 and the transistor 411. However, the OFG transistor 332 may be included when necessary.

[0174] Figure 11 is a plan view of an example layout 1100 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. Figure 11 As shown, the source of transistor 411 can be coupled to the central region of one side of photoelectric conversion region 333. Transistor 411 can extend in a first direction (e.g., horizontal direction). As further shown, transistor 413 is formed on one side of the drain of transistor 411 and extends in a second direction (e.g., vertical direction) perpendicular to the first direction. Transistors 412 and 414 are adjacent to each other and are located on the other side of the drain of transistor 413. Figure 11 The layout shown may be used in applications where a smaller footprint is desired for the pixels 310 to improve resolution.

[0175] Figure 121 is a plan view of an example layout 1200 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. As shown, transistor 411 is coupled to photoelectric conversion region 333 in a region offset from (e.g., below) the central region of photoelectric conversion region 333. Additionally, transistor 414 is located on one side of the drain of transistor 411, while transistors 412 and 413 are located on the other side of the drain of transistor 411. As shown, transistors 412 and 413 share a source / drain region, and transistors 412, 413, and 414 extend in a second direction and are aligned with one another in the second direction. Figure 12 The layout shown may be used for applications tailored for a larger footprint of pixel 310 or a larger photoelectric conversion area requiring higher quality images and / or higher contrast sensitivity.

[0176] Figure 13 is a plan view of an example layout 1300 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. Figure 13 As shown, transistor 411 is coupled to photoelectric conversion region 333 at a central region on one side of photoelectric conversion region 333. Also as shown, transistor 413 is on one side of the drain of transistor 411, while transistors 412 and 414 are on the other side of the drain of transistor 411. Transistors 411, 412, 413, and 414 all extend in a first direction, and transistors 412 / 414 are aligned with each other in a second direction. Although not explicitly shown, it should be understood that transistor 413 can also be aligned with transistors 412 / 414 when desired. Figure 13 It can be used in applications where it is necessary to reduce the connections between the gates of the transistors 411 , 412 , 413 , and 414 .

[0177] exist Figures 11-13 , transistor 411 may have a reference Figure 49 The structure is used to reduce dark current.

[0178] Figure 14 is a plan view of an example layout 1400 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. Here, it should be understood that, as described above, Figure 14 The 2T configuration for the converter 410 is shown in which the transistors 412 and 414 are omitted. As shown in the figure, the transistor 411 is coupled to one side of the photoelectric conversion region 333 and is located in a region offset from (e.g., below) the central region of the photoelectric conversion region 333, while the transistor 413 is formed on one side of the transistor 411 and extends in the second direction. Figure 14The layout in can be used for applications requiring smaller pixels 310. In this case, transistor 411 can have Figure 49 The structure shown.

[0179] Figure 15 is a plan view of an example layout 1500 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. Figure 14 similar, Figure 15 There is a 2T configuration for the converter 410. Figure 15 In the embodiment, the transistor 411 is coupled to one side of the photoelectric conversion region 333 at a position offset from (eg, above) the central region of the photoelectric conversion region 333. The transistor 413 is formed on one side of the transistor 411 and extends in the first direction. Figure 15 The layout in can be used for applications that require flexibility in the metal wiring electrically connected to transistors 411 / 413 and other components of pixel 310. In this case, transistor 411 can have Figure 49 The structure shown.

[0180] Figure 16 is a plan view of an example layout 1600 of a portion of the converter 410 and the photoelectric conversion region 333 according to at least one example embodiment. Here, it should be understood that, as described above, Figure 16 The 2T configuration for the converter 410 is shown in which the transistors 412 and 414 are omitted. As shown in the figure, the transistor 411 is coupled to one side of the photoelectric conversion region 333 and is located in a region offset from (e.g., above) the central region of the photoelectric conversion region 333, while the transistor 413 is formed on one side of the transistor 411 and extends in the second direction. Figure 16 The layout in can be used for applications requiring smaller pixels 310. In this case, transistor 411 can have Figure 49 The structure shown.

[0181] Figure 17 is a plan view of an example layout 1700 of a portion of the converter 410 and the photoelectric conversion region 333 according to at least one example embodiment. Here, it should be understood that, as described above, Figure 17 4 shows a 2T configuration for converter 410 in which transistors 412 and 414 are omitted. Figure 17 As shown, the transistor 413 is located on one side of the photoelectric conversion region 333 and extends in the second direction, while the transistor 411 is connected to a corner portion of the photoelectric conversion region 333 and extends in a direction forming an angle with the second direction. In this case, the transistor 411 may have Figure 49 The structure shown.

[0182] Figure 18 is a plan view of an example layout 1800 of a portion of a converter 410 and a photoelectric conversion region 333 according to at least one example embodiment. Here, it should be understood that, as described above, Figure 18 4 shows a 2T configuration for converter 410 in which transistors 412 and 414 are omitted. Figure 18 As shown, the transistor 413 is located on one side of the photoelectric conversion region 333 and extends in the first direction, while the transistor 411 is connected to a corner portion of the photoelectric conversion region 333 and extends in a direction forming an angle with the second direction. In this case, the transistor 411 may have Figure 49 The structure shown.

[0183] Here, it should be understood that Figures 11-18 The layout is shown from a plan view in which the transistor may include some portions formed in the same semiconductor substrate as the photoelectric conversion region 333 and other portions formed in a wiring layer attached to the semiconductor substrate (where the wiring layer and the semiconductor substrate are part of the light receiving chip 201). For example, the source / drain of the transistor may be formed in the non-light receiving surface of the semiconductor substrate opposite to the light receiving surface of the semiconductor substrate, while the gate of the transistor may be formed in the surface of the wiring layer attached to and facing the non-light receiving surface of the semiconductor substrate.

[0184] Now, refer to Figures 19A to 48 Various example schematic diagrams and example layouts of bonding pads for pixel 310 are described. Figures 19A-48 You can use the reference Figures 11-18 One or more layouts described above, but various details are omitted from the drawings to clearly illustrate the bonding pad configuration associated with the photoelectric conversion region 333 and the isolation region RFTI (e.g., rear full trench isolation extending through the semiconductor substrate having the photoelectric conversion region 333). Figures 19A-48 Omitted Figures 11-18 The transistors shown are not shown, but it should be understood that they are present in the transistor region TR, which may include an area of ​​the pixel 310 that is not visible due to the illustration of the bonding pad CC. In addition, for ease of illustration, the metal wiring layers (e.g., M1, M2, M3, etc.) have been omitted from the layout of the bonding pads. In addition, the schematic diagrams omit the OFG transistor 332 between the transistor 411 and the photoelectric conversion region 333. However, the OFG transistor 332 can be included if necessary.

[0185] Figure 19AAn example schematic diagram of a converter 410 having a node 510 for each pixel 310 and an example layout 1900 of bonding pads electrically connecting circuitry in the logic chip 202 to the node 510 for each pixel 310 is shown according to at least one example embodiment. Figure 19A As shown, node 510 is the output node of converter 410 (e.g., see FIG. 5 ). As further shown, layout 1900 includes pixels 310, wherein each pixel 310 has a transistor region TR adjacent to photoelectric conversion region 333, bonding pads CC (e.g., CC1, CC2, CC3, CC4) for bonding to logic chip 202, and vias V1 and V2 for forming an electrical connection between bonding pads CC and node 510. Figure 19A As shown, each bonding pad CC overlaps at least a portion of the corresponding pixel 310 and may have a rectangular shape (e.g., a square shape). For example, each bonding pad CC is entirely overlapped by the corresponding pixel 310. As further shown, the through holes V1 / V2 may be aligned with each other in the second direction at the central area of ​​each bonding pad CC. Here, it should be understood that more or fewer through holes may be included as needed. Through holes V1 and V2 may overlap with the transistor region TR without overlapping with the photoelectric conversion region 333. However, the example embodiment is not limited thereto, and the relative positions of V1 / V2 and the photoelectric conversion region 333 may be changed when necessary. Figures 19A to 48 A node VRL is illustrated, which may represent an electrical contact with the substrate having the photoelectric conversion region 333. The electrical contact may receive a potential, for example, a ground potential GND (or VSS), or a common signal having a negative potential to control parasitic capacitance.

[0186] Figure 19A Also shown is an isolation region RFTI having a grid shape that isolates pixels 310 from each other. Thus, according to at least one example embodiment, the isolation region RFII passes through the optical receiver chip 201 (i.e., full trench isolation). However, example embodiments are not limited thereto, and the isolation region RFTI may only partially pass through the chip 201 (i.e., partial trench isolation).

[0187] Figure 19B Shown is a view taken along line XIX-XIX Figure 19A Cross-sectional view. Figure 19B Also shown are connections between bonding pads CC in the light receiving chip 201 and bonding pads CC2 in the logic chip 202, contacts 1905, vias 1910, and one or more wiring layers M1 / M2 (e.g., wiring layers comprising metal or other conductors) to form connections with pixels 310 (e.g., Figure 19A1905 and / or vias 1910). It should be understood that more or fewer metal wiring layers M1 / M2 may be present as needed, and that wiring layers M1 / M2 may be formed in the insulating layer of chip 201. It should also be understood that the transistors of converter 410 may be electrically connected to one another through one or more of wiring layers M1 / M2, contacts 1905, and / or vias 1910.

[0188] although Figures 20-48 It is not explicitly shown, but it should be understood that Figure 19B The same or similar bonding pad structure and metal wiring structure M1 / M2 / 1905 shown in the cross-sectional view can be applied to Figures 20-51 The layout in .

[0189] Figure 20 An example schematic diagram of a converter 410 having a node 510 for each pixel 310 and an example layout 2000 of bonding pads electrically connecting circuitry in a logic chip 202 to the node 510 for each pixel 310 are shown according to at least one example embodiment. Each bonding pad CC includes four vias V1, V2, V3, and V4. Figure 20 Same as FIG19 . As shown, through holes V3 and V4 overlap with the photoelectric conversion region 333, while through holes V1 and V2 overlap with the transistor region TR. Furthermore, through holes V1 and V2, as well as through holes V3 and V4, are aligned with each other in the second direction, while through holes V1 and V3, as well as through holes V2 and V4, are aligned with each other in the first direction. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0190] Figure 21 An example schematic diagram of a converter 410 for each pixel 310 having a node 510A and an example layout 2100 of bonding pads electrically connecting circuitry in a logic chip 202 to the node 510A for each pixel 310 is shown according to at least one example embodiment. As shown, the node 510A may be a node that stores charge from the photoelectric conversion region 333. Figure 21 1 shows an embodiment in which the node 510A exists in the light receiving chip 201 and the transistors 411, 412, 413 and / or 414 are formed in the logic chip 202. Therefore, for example, the transistor region TR can be omitted to allow the photoelectric conversion region 333 to be larger than Figure 19A and Figure 20 In this case, the through holes V1 and V2 overlap the photoelectric conversion region 333, while the bonding pad CC only overlaps the corresponding pixel 310. In at least one example embodiment, the bonding pad CC has a Figure 20The above bonding pad formation may be repeated for all pixels 310A in the array.

[0191] Figure 22 An exemplary schematic diagram of a converter 410 for each pixel 310 having a node 510 and a node 510B and an exemplary layout 2200 of bonding pads electrically connecting circuits in a logic chip 202 to nodes 510 and 510B for each pixel 310 is shown according to at least one example embodiment. Node 510B may be a power supply node for the converter 410 that receives a power supply signal VDD. Here, it should be understood that bonding pads CC1 / CC2 belong to one pixel 310. For example, in each pixel 310, bonding pad CC1 is electrically connected to node 510B, while bonding pad CC2 is electrically connected to node 510. However, it should be understood that the electrical connections may be reversed when desired. As Figure 22 As shown, each bonding pad CC can have an octagonal shape. In addition, the bonding pads CC2 can be aligned with each other in the first and second directions, while the bonding pads CC1 can be aligned with each other in the first and second directions. Each bonding pad CC2 overlaps two pixels 310 and the isolation region RFTI. For example, the through holes V1 and V2 of each bonding pad can overlap with a portion of the photoelectric conversion region 333 of each pixel 310. The bonding pad CC1 can also overlap with various portions of the two pixels 310 and the isolation region RFTI. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0192] Figure 23 FIG2 shows an exemplary schematic diagram of a converter 410 for each pixel 310 having a node 510 and a node 510B and an exemplary layout 2300 of bonding pads electrically connecting circuits in a logic chip 202 to the nodes 510 and 510B for each pixel 310 according to at least one example embodiment. Layout 2300 is similar to FIG2 except that bonding pads CC are rectangular in shape. Figure 22. That is, the bonding pad CC1 and the bonding pad CC2 belong to one pixel 310 (e.g., the lower left pixel). The bonding pad CC1 can be electrically connected to the node 510, and the bonding pad CC2 can be electrically connected to the node 510B. However, these electrical connections can be reversed when necessary. As shown in the figure, the bonding pad CC1 overlaps with the various parts and isolation regions RFTI of the adjacent pixel 310, and the bonding pad CC2 also overlaps with the various parts and isolation regions RFTI of the adjacent pixel 310. The bonding pad CC1 can be aligned with each other in the first and second directions, and the bonding pad CC2 can be aligned with each other in the first and second directions. As shown in the figure, the through holes V1 and V2 of each bonding pad can overlap with the various parts and / or isolation regions RFTI of the pixel 310. This bonding pad formation can be repeated for all pixels 310A in the array.

[0193] Figure 24 An example schematic diagram of a converter 410 for each pixel 310 having a node 510C and a node 510D is shown, along with an example layout 2400 of bonding pads electrically connecting circuitry in the logic chip 202 to the nodes 510C and 510D for each pixel 310, according to at least one example embodiment. Node 510C may be a ground node of the converter 410 that receives a ground signal or a common signal, while node 510D may be a node of the photoelectric conversion region 333. Alternatively, node 510D may be a contact on or in a substrate in which a PD is formed, and may receive a potential (e.g., a negative potential). Layout 2400 is identical to layout 2300, except that bonding pads CC1 and CC2 in each pixel 310 are electrically connected to nodes 510C and 510D instead of nodes 510 and 510B. For example, for the bottom left pixel 310, bonding pad CC1 is electrically connected to either node 510D or 510C, while bonding pad CC2 is electrically connected to the other of nodes 510D or 510C. Bonding pads CC1 may be aligned with each other in the first and second directions, and bonding pads CC2 may be aligned with each other in the first and second directions. The same bonding configuration may be repeated for all pixels 310A in the array.

[0194] Figure 25An example schematic diagram of a converter 410 for each pixel 310 having a node 510, a node 510C, and a node 510D and an example layout 2500 of bonding pads electrically connecting circuits in a logic chip 202 to the nodes 510, 510C, and 510D for each pixel 310 is shown according to at least one example embodiment. As shown, each pixel 310 may include bonding pads CC1 to CC3 for forming corresponding electrical connections between the nodes 510, 510C, and 510D and the logic chip 202. In each pixel 310, bonding pad CC1 may be electrically connected to node 510C, bonding pad CC2 may be electrically connected to node 510, and bonding pad CC3 may be electrically connected to node 510D. However, the electrical connections between the bonding pads and the nodes in each pixel 310 may be changed as needed. As shown Figure 25 As shown, the bonding pad CC1 can overlap with a portion of the pixel 310 and the isolation region RFTI, the bonding pad CC2 can overlap with a portion of the photoelectric conversion region 333 and the isolation region RFTI, and the bonding pad CC3 can be completely overlapped by the photoelectric conversion region 333. The bonding pads CC1 and CC2 can be aligned with each other in a first direction, while the bonding pads CC1 and CC2 of adjacent pixels can be aligned with each other in a second direction. The bonding pads CC3 of adjacent pixels 310 can be aligned with each other in the first direction and the second direction. The through hole V2 of the bonding pad CC2 can overlap with the photoelectric conversion region 333, while the through hole V1 does not overlap with the photoelectric conversion region 333. In at least one example embodiment, the size of the bonding pads CC1 to CC3 relative to the photoelectric conversion region 333 can be smaller than the size shown, so that the relative distance between each bonding pad can be smaller than the relative distance shown. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0195] Figure 26 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510C, and 510D, and an example layout 2600 of bonding pads electrically connecting circuits in the logic chip 202 to the nodes 510, 510C, and 510D for each pixel 310, according to at least one example embodiment, is shown. Except that the bonding pad CC3 in each pixel 310 is located in the lower region of the pixel 310 so as to overlap with a portion of the photoelectric conversion region 333, the transistor region TR, and the isolation region RFIT, Figure 26 and Figure 25 As shown, vias V1 and V2 for bonding pad CC3 may be overlapped by photoelectric conversion region 333. This bonding pad configuration may be repeated for all pixels 310A in the array.

[0196] Figure 27An example schematic diagram of converter 410 for each pixel 310 having nodes 510, 510C, and 510D, and an example layout 2700 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510, 510C, and 510D for each pixel 310, according to at least one example embodiment, is shown. The example layout 2700 includes bonding pads CC1 and CC3, except that bonding pads CC1 and CC3 have been moved closer to the center region of each pixel 310. Figure 27 and Figure 26 As shown in the figure, the bonding pad CC1 can overlap with a portion of the transistor region TR and the isolation region RFTI, while the bonding pad CC3 can be completely overlapped by the photoelectric conversion region 333. As shown in the figure, the through holes V1 and V2 of CC1 can overlap with both the transistor region TR and the isolation region RFTI. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0197] Figure 28 An example schematic diagram of converter 410 for each pixel 310 having node 510, node 510B, and node 510D is shown, along with an example layout 2800 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510, 510B, and 510D for each pixel 310, according to at least one example embodiment. Bond pad CC3 is located in a different position, except that one of the bonding pads is electrically connected to node 510B instead of node 510C. Figure 28 and Figure 26 Similarly. In at least one example embodiment, bonding pad CC1 is electrically connected to power supply node 510B, bonding pad CC2 is electrically connected to node 510D, and bonding pad CC3 is electrically connected to node 510. However, these electrical connections can be reversed if desired. As shown, bonding pads CC1 and CC2 are aligned with each other in the first and second directions, while bonding pad CC3 is aligned with each other in the second direction but offset from bonding pad CC2 in the first direction. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0198] Figure 29 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, and 510D, and an example layout 2900 of bonding pads electrically connecting circuits in logic chip 202 to nodes 510, 510B, and 510D for each pixel 310, according to at least one example embodiment, is shown. Except for the location of bonding pad CC3 at the lower center region of each pixel 310, Figure 29 and Figure 28As shown, the bonding pad CC3 may overlap a portion of the photoelectric conversion region 333, a portion of the transistor region TR, and a portion of the isolation region RFTI. This bonding pad configuration may be repeated for all pixels 310A in the array.

[0199] Figure 30 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, and 510D and an example layout 3000 of bonding pads electrically connecting circuits in logic chip 202 to nodes 510, 510B, and 510D for each pixel 310 is shown according to at least one example embodiment. Except for the different locations of bonding pads CC1 and CC2, Figure 30 and Figure 29 The same. For example, in each pixel 310, the bonding pads CC1 and CC2 are closer to the bonding pad CC3. As shown in the figure, the entire bonding pad CC2 may be overlapped by the photoelectric conversion region 333, while the bonding pad CC1 may overlap with the transistor region TR and the isolation region RFTI, wherein the through holes V1 and V2 overlap with both the transistor region TR and the isolation region RFTI. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0200] Figure 31 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510B, 510C, and 510D is shown, along with an example layout 3100 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510B, 510C, and 510D for each pixel 310, according to at least one example embodiment. For each pixel 310, bonding pad CC1 can be electrically connected to node 510B, bonding pad CC2 can be electrically connected to node 510C, and bonding pad CC3 can be electrically connected to node 510D. However, the electrical connections between the nodes and bonding pads can be varied as desired. As shown, bonding pad CC1 can overlap isolation region RFTI and transistor region TR, bonding pad CC2 can overlap isolation region RFTI and photoelectric conversion region 333, and bonding pad CC3 can overlap photoelectric conversion region 333. As shown, vias V1 and V2 of each bonding pad can overlap various portions of layout 3100. Bond pads CC1 and CC2 may be aligned with each other in the first and second directions, and bond pads CC3 may be aligned with each other in the first and second directions.This bond pad configuration may be repeated for all pixels 310A in the array.

[0201] Figure 32An example schematic diagram of a converter 410 for each pixel 310 having nodes 510B, 510C, and 510D and an example layout 3200 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510B, 510C, and 510D for each pixel 310 is shown in accordance with at least one example embodiment. The locations of bonding pads CC3 are different. Figure 32 and Figure 31 As shown, the bonding pad CC3 is located in the lower region of each pixel 310 and overlaps with the photoelectric conversion region 333, the transistor region TR, and the isolation region RFTI. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0202] Figure 33 An example schematic diagram of converter 410 for each pixel 310 having nodes 510B, 510C, and 510D and an example layout 3300 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510B, 510C, and 510D for each pixel 310 is shown, according to at least one example embodiment. Bond pads CC1 and CC2 are positioned closer to bond pad CC3 in each pixel 310. Figure 33 and Figure 32 As shown in the figure, the bonding pad CC1 may overlap with the transistor region and the isolation region RFTI, and the bonding pad CC2 may be completely overlapped by the photoelectric conversion region 333. The through holes V1 and V2 of the bonding pad CC1 may overlap with the transistor region TR and the isolation region RFTI.

[0203] Figure 34 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D and an example layout 3400 of bonding pads electrically connecting circuitry in the logic chip 202 to the nodes 510, 510B, 510C, and 510D for each pixel 310 is shown according to at least one example embodiment. Figure 34As shown, bonding pads CC1, CC2, CC3, and CC4 can be located in corner portions of each pixel 310. In one embodiment, bonding pad CC1 is electrically connected to node 510B, bonding pad CC2 is electrically connected to node 510, bonding pad CC3 is electrically connected to node 510C, and bonding pad CC4 is electrically connected to node 510D. However, the electrical connections can be changed as needed. As shown, bonding pads CC1 and CC3 are aligned with each other in the second direction, bonding pads CC2 and CC4 are aligned with each other in the second direction, bonding pads CC1 and CC2 are aligned with each other in the first direction, and bonding pads CC3 and CC4 are aligned with each other in the first direction. Also as shown, bonding pads CC1 and CC3 overlap with transistor region TR and isolation region RFTI, while bonding pads CC2 and CC4 overlap with photoelectric conversion region 333 and isolation region RFTI. As shown, through holes V1 and V2 of each bonding pad CC overlap with a portion of transistor region TR, a portion of isolation region RFTI, and / or a portion of photoelectric conversion region 333. This bond pad formation may be repeated for all pixels 310A in the array.

[0204] Figure 35 An example schematic diagram of converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D is shown, along with an example layout 3500 of bonding pad configurations that electrically connect circuitry in logic chip 202 to nodes 510, 510B, 510C, and 510D for each pixel 310, according to at least one example embodiment. Bond pads CC1 through CC4 for each pixel 310 are arranged in a diamond configuration rather than a rectangular configuration, such that bond pads CC1 and CC3 are aligned with each other in a first direction and bond pads CC1 (and CC3) of vertically adjacent pixels are aligned with each other in a second direction. Figure 35 and Figure 34 The same. The bonding pads CC2 and CC4 are aligned with each other in the second direction, and the bonding pads CC2 (and CC4) of horizontally adjacent pixels are aligned with each other in the first direction. The bonding pad CC1 can overlap with the isolation region RFTI and the transistor region TR, and the bonding pad CC2 can overlap with the transistor region TR, the isolation region RFTI and the photoelectric conversion region 333. The bonding pad CC3 can be completely overlapped by the photoelectric conversion region 333, and the bonding pad CC4 can overlap with the photoelectric conversion region 333 and the transistor region TR. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0205] Figure 36An example schematic diagram of converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D, and an example layout 3600 of bonding pads electrically connecting circuits in logic chip 202 to nodes 510, 510B, 510C, and 510D for each pixel 310, according to at least one example embodiment, is shown. Except that bonding pads CC1 through CC4 are rectangular in shape, CC1 through CC4 are located differently, and bonding pads CC1 through CC4 are smaller in size and have smaller distances between them, Figure 36 and Figure 35 The same. As shown in the figure, CC1 and CC2 can be located on the same side of the photoelectric conversion region 333, while CC3 and CC4 can be located on the same other side of the photoelectric conversion region 333. As shown in the figure, the bonding pads CC1 and CC2 are aligned with each other in the second direction and aligned with the bonding pads CC1 and CC2 of the adjacent pixel 310 in the first direction. The bonding pads CC3 and CC4 are aligned with each other in the first direction and aligned with the bonding pads CC3 and CC4 of the adjacent pixel 310 in the second direction. The bonding pads CC1 and CC2 can overlap with the isolation region RFTI and the transistor region TR, while the bonding pads CC3 and CC4 overlap with the photoelectric conversion region 333. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0206] Here, it should be understood that Figures 20-36 Various topologies are described in which the converter 410 has a 4T configuration. Figures 37-51 Explain, and Figures 37-51 Referring to the example embodiment in which the converter 410 has a 2T configuration, it may allow for a smaller transistor region TR and thus a larger photoelectric conversion region 333 than a 4T configuration.

[0207] Figure 37 An example schematic diagram of a converter 410 for each pixel 310 having a node 510 and a node 510B and an example layout 3700 of bonding pads electrically connecting circuitry in a logic chip 202 to nodes 510 and 510B for each pixel 310 is shown according to at least one example embodiment. As shown, each pixel 310 has two associated bonding pads CC1 and CC2. Bonding pad CC1 can be electrically connected to node 510B, and bonding pad CC2 can be electrically connected to node 510. Figures 20-36As shown, node 510 is the output node of converter 410, and node 510B is the power node of converter 410, which receives power signal VDD. As shown, bonding pads CC1 and CC2 overlap two pixels 310 and isolation region RFTI. In addition, bonding pads CC1 of adjacent pixels 312 can be aligned with each other in the first and second directions, while bonding pads CC2 of adjacent pixels 312 can be aligned with each other in the first and second directions. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0208] Figure 38 An example schematic diagram of converter 410 for each pixel 310 having node 510 and node 510B and an example layout 3800 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510 and 510B for each pixel 310 is shown according to at least one example embodiment. Except that bonding pads CC1 and CC2 are of different shapes and / or sizes, Figure 38 and Figure 37 For example, the bonding pads CC1 / CC2 have an octagonal shape. As further shown, the bonding pads CC1 and CC2 overlap with the photoelectric conversion region 333 and the isolation region RFTI of the adjacent pixel 310. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0209] Figure 39 An example schematic diagram of a converter 410 for each pixel 310 having a node 510A and an example layout 3900 of bonding pads electrically connecting circuitry in a logic chip 202 to the node 510A for each pixel 310 is shown according to at least one example embodiment. As shown, the node 510A may be a node that stores charge from the photoelectric conversion region 333. Figure 39 1 shows an embodiment in which the node 510A exists in the light receiving chip 201 and the transistors 411 and / or 413 are formed in the logic chip 202. Therefore, for example, the transistor region TR can be omitted to allow the photoelectric conversion region 333 to be larger than Figure 37 and 38 In this case, the bonding pads CC1 of adjacent pixels 310 may be aligned with each other in the first and second directions and may overlap with portions of the adjacent pixels 310 and the isolation region RFTI. This bonding pad configuration may be repeated for all pixels 310A in the array.

[0210] Figure 40An example schematic diagram of a converter 410 for each pixel 310 having a node 510C and a node 510D is shown, along with an example layout 4000 of bonding pads electrically connecting circuitry in the logic chip 202 to the nodes 510C and 510D for each pixel 310, according to at least one example embodiment. Bonding pad CC1 can be electrically connected to node 510D, and bonding pad CC2 can be electrically connected to node 510C. However, the electrical connections can be reversed as desired. The layout of bonding pads CC1 and CC2 can be similar to Figure 37 This bonding pad configuration may be repeated for all pixels 310A in the array.

[0211] Figure 41 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510C and 510D and an example layout 4100 of bonding pads electrically connecting circuits in logic chip 202 to nodes 510C and 510D for each pixel 310 is shown according to at least one example embodiment. In addition to bonding pads CC1 and CC2 being electrically connected to nodes 510C and 510D, Figure 41 and Figure 38 For example, bonding pad CC1 is electrically connected to node 510D, and bonding pad CC2 is electrically connected to node 510C. However, these electrical connections can be reversed as needed. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0212] Figure 42An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, and 510D is shown, along with an example layout 4200 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510, 510B, and 510D for each pixel 310, according to at least one example embodiment. In at least one example embodiment, bonding pad CC1 is electrically connected to node 510B, bonding pad CC2 is electrically connected to node 510, and bonding pad CC3 is electrically connected to node 510D. As shown, bonding pads CC1 and CC2 are located at the corners of pixel 310, while bonding pad CC3 is completely overlapped by photoelectric conversion region 333. As also shown, bonding pad CC1 overlaps isolation region RFTI and transistor region TR, while bonding pad CC2 overlaps isolation region RFTI and photoelectric conversion region 333. Vias V1 in bonding pads CC1 and CC2 may overlap isolation region RFTI. The through hole V2 in the bonding pad CC1 can overlap with the transistor region TR, while the through hole V2 in the bonding pad CC2 can overlap with the photoelectric conversion region 333. As shown, the bonding pads CC1 and CC2 are aligned with each other in the first and second directions, while the bonding pad CC3 is aligned with each other in the first and second directions. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0213] Figure 43 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, and 510D, and an example layout 4300 of bonding pads electrically connecting circuits in the logic chip 202 to the nodes 510, 510B, and 510D for each pixel 310, according to at least one example embodiment, is shown. Except for the location of the bonding pad CC3, which is located in the lower region of each pixel 310 to overlap with the photoelectric conversion region 333 and the isolation region RFTI, Figure 43 and Figure 42 This bond pad formation may be repeated for all pixels 310A in the array.

[0214] Figure 44 An example schematic diagram of converter 410 for each pixel 310 having node 510, node 510B, and node 510C is shown, along with an example layout 4400 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510, 510B, and 510C for each pixel 310, according to at least one example embodiment. The example layout 4400 includes bonding pads CC1 through CC3, except that one of bonding pads CC1 through CC3 is electrically connected to node 510C instead of 510D. Figure 44 and Figure 42For example, bonding pad CC1 is electrically connected to node 510B, bonding pad CC2 is electrically connected to node 510, and bonding pad CC3 is electrically connected to node 510C. However, these electrical connections can be changed as needed. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0215] Figure 45 An example schematic diagram of converter 410 for each pixel 310 having nodes 510, 510B, and 510C is shown, along with an example layout 4500 of bonding pads electrically connecting circuitry in logic chip 202 to nodes 510, 510B, and 510C for each pixel 310, according to at least one example embodiment. The example layout 4500 includes bonding pads CC1 through CC3, except that one of bonding pads CC1 through CC3 is electrically connected to node 510C instead of 510D. Figure 45 and Figure 43 For example, bonding pad CC1 is electrically connected to node 510B, bonding pad CC2 is electrically connected to node 510, and bonding pad CC3 is electrically connected to node 510C. However, these electrical connections can be changed as needed. This bonding pad configuration can be repeated for all pixels 310A in the array.

[0216] Figure 46 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D, and an example layout 4600 for electrically connecting circuitry in logic chip 202 to bonding pads for each pixel 310, 510B, 510C, and 510D, according to at least one example embodiment, is shown. As shown, bonding pads CC1 to CC4 for each pixel 310 are located at the corners of each pixel 310. Bonding pad CC1 can be electrically connected to node 510B, bonding pad CC2 can be electrically connected to node 510, bonding pad CC3 can be electrically connected to node 510C, and bonding pad CC4 can be electrically connected to node 510D. However, these electrical connections can be changed as desired. As shown, bonding pads CC1 and CC3 can overlap with transistor region TR and photoelectric conversion region 333. Bonding pads CC2 and CC4 can overlap with the photoelectric conversion region and isolation region RFTI. Bonding pads CC1 and CC3 (and CC2 and CC4) may be aligned with each other in the second direction. Bonding pads CC1 and CC2 (and CC3 and CC4) may be aligned with each other in the first direction. This bonding pad configuration may be repeated for all pixels 310A in the array.

[0217] Figure 47An example schematic diagram of converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D and an example layout 4700 of bonding pad configurations electrically connecting circuitry in logic chip 202 to nodes 510, 510B, 510C, and 510D for each pixel 310 is shown according to at least one example embodiment. The layout 4700 includes bonding pads CC1 through CC4 for each pixel, except that they are positioned in a diamond configuration rather than a rectangular configuration. Figure 47 and Figure 46 As shown, bonding pads CC1 to CC4 are located within pixel 310. This bonding pad configuration may be repeated for all pixels 310A in the array.

[0218] Figure 48 An example schematic diagram of a converter 410 for each pixel 310 having nodes 510, 510B, 510C, and 510D, and an example layout 4800 of bonding pads electrically connecting circuits in the logic chip 202 to the nodes 510, 510B, 510C, and 510D for each pixel 310, according to at least one example embodiment, is shown. Except for the different locations and shapes of the bonding pads CC1 to CC4, Figure 48 and Figure 47 For example, the shape and position of the bonding pads are the same as Figure 36 The shape and position of the bonding pads in are the same.

[0219] Figure 49 1 shows an example structure of transistor 411 according to at least one example embodiment. Figure 49 As shown, a portion of the transistor 411 coupled to the photoelectric conversion region 333 (eg, the source S) has a larger width W2 than a portion including the drain D of the transistor 411 having a width W1 . Figure 49 It is also shown that the portion at the width W2 may extend below the gate G of the transistor 411. This structure of the transistor 411 may reduce dark current.

[0220] Figure 50 1 is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0221] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 50In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional components of integrated control unit 12050 include a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0222] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates the vehicle's braking force.

[0223] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, taillights, brake lights, flashers, and fog lights. In this case, radio waves transmitted from a portable device in place of buttons or signals from various switches can be input to the main system control unit 12020. The main system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and other devices.

[0224] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 allows the imaging unit 12031 to capture images of the vehicle exterior and receive the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection processing such as people, vehicles, obstacles, signs, text on the road, and the like, or distance detection processing.

[0225] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as distance measurement information. In addition, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0226] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver is dozing off.

[0227] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information inside or outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including vehicle collision avoidance or collision mitigation, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0228] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can be used for automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0229] Furthermore, the microcomputer 12051 can output control instructions to the main system control unit 12020 based on information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control to achieve glare protection, such as switching the headlights from high beam to low beam.

[0230] The sound and image output unit 12052 transmits at least one output signal of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Figure 50 In the example of FIG, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0231] Figure 51 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0232] exist Figure 51In the figure, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0233] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed in locations such as the front of vehicle 12100, sideview mirrors, rear bumper, rear door, and the upper portion of the windshield of the vehicle's cab. Imaging unit 12101 located on the front of the vehicle and imaging unit 12105 located on the upper side of the windshield of the vehicle's cab primarily capture images of the front side of vehicle 12100. Imaging units 12102 and 12103 located in the sideview mirrors primarily capture images of the sides of vehicle 12100. Imaging unit 12104 located in the rear bumper or rear door primarily captures images of the rear side of vehicle 12100. Imaging unit 12105 located on the upper side of the windshield of the vehicle's cab can primarily be used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0234] also, Figure 51 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located in the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, when multiple pieces of image data captured by imaging units 12101 to 12104 are superimposed on each other, a top-down image of vehicle 12100 as viewed from above can be obtained.

[0235] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element including pixels for phase difference detection.

[0236] For example, based on the distance information obtained from imaging units 12101-12104, by obtaining the distance to each 3D object within imaging ranges 12111-12114 and the change in distance over time (relative to the speed of vehicle 12100), microcomputer 12051 can identify as the leading vehicle a 3D object, particularly the closest 3D object on the travel path of vehicle 12100, traveling in approximately the same direction as vehicle 12100, which is traveling at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a predetermined inter-vehicle distance ahead of the leading vehicle to execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up acceleration control), and the like. As described above, coordinated control for autonomous driving, in which the vehicle travels autonomously without relying on driver input, can be executed.

[0237] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can extract 3D object data related to the objects by classifying them into data on two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other objects such as utility poles. This data can then be used to automatically avoid obstacles. For example, microcomputer 12051 distinguishes obstacles around vehicle 12100 into those visually recognizable by the driver of vehicle 12100 and those difficult for the driver to visually recognize. Furthermore, microcomputer 12051 determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk is equal to or greater than a set value and a collision is likely, microcomputer 12051 can assist in collision avoidance by outputting a warning to the driver via audio speaker 12061 or display unit 12062, or by initiating forced deceleration or evasive steering via drive system control unit 12010.

[0238] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether a pedestrian is present in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which function as infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. Furthermore, the audio and video output unit 12052 may control the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0239] An example of a vehicle control system to which the technology of the present disclosure can be applied has been given so far. The technology of the present disclosure can be applied to the imaging unit 12031 and the driver state detection unit 12041 in the above-mentioned configuration.

[0240] The embodiments of the present disclosure have been described so far, but the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made within the scope not departing from the gist of the present disclosure. In addition, the constituent elements of other embodiments and modifications can be appropriately combined.

[0241] In addition, the effects of the embodiments described in this specification are merely exemplary, and other effects may exist but are not limited thereto.

[0242] Furthermore, the present technology can adopt the following configurations.

[0243] (1) An imaging element comprising:

[0244] A first pixel, the first pixel comprising:

[0245] a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and

[0246] a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; and

[0247] At least one bonding pad is located on the first substrate and is in electrical contact with the first converter, the at least one bonding pad overlapping at least a portion of the first pixel.

[0248] (2) The imaging element described in (1), wherein the first converter includes a first portion configured in the first substrate, wherein the first portion includes a transistor connected to the first photoelectric conversion region, and wherein in a plan view, a source of the transistor is wider than a drain of the transistor.

[0249] (3) The imaging element according to (1) or (2), further comprising:

[0250] A second substrate is bonded to the first substrate via the at least one bonding pad, wherein the first converter includes a second portion disposed in the second substrate.

[0251] (4) The imaging element according to any one of (1) to (3), wherein the first portion includes a node coupled to the photoelectric conversion region, and wherein the second portion includes a plurality of transistors coupled to the node through the at least one bonding pad.

[0252] (5) The imaging element according to any one of (1) to (4), further comprising:

[0253] A plurality of through-vias are disposed in the first substrate and are in electrical contact with the at least one bonding pad and the first transducer.

[0254] (6) An imaging element as described in any one of (1) to (5), wherein the first converter is configured in the first substrate, and wherein the at least one bonding pad includes a first bonding pad electrically contacting a first node of the first converter and a second bonding pad electrically contacting a second node of the first converter.

[0255] (7) An imaging element as described in any one of (1) to (6), wherein the first node is a power supply node of the first converter, the power supply node receives a power supply signal, and wherein the second node is an output node of the first converter, the output node outputs an output signal to another component of the first readout circuit.

[0256] (8) An imaging element as described in any one of (1) to (7), wherein the at least one bonding pad includes a third bonding pad electrically contacting a third node of the first converter, and wherein the third node is a node of the photoelectric conversion region or a ground node of the first converter, and the ground node receives a ground signal or a common signal.

[0257] (9) The imaging element as described in any one of (1) to (8), wherein the first node is a node of the photoelectric conversion region, and wherein the second node is a ground node of the first converter, and the ground node receives a ground signal or a common signal.

[0258] (10) An imaging element as described in any one of (1) to (9), wherein the at least one bonding pad includes a third bonding pad electrically contacting a third node of the first converter, and wherein the third node is a power supply node of the first converter or an output node of the first converter, the power supply node receiving a power supply signal, and the output node outputting an output signal to another component of the first readout circuit.

[0259] (11) The imaging element as described in any one of (1) to (10), wherein the at least one bonding pad includes a third bonding pad electrically contacting the third node of the first converter and a fourth bonding pad electrically contacting the fourth node of the first converter.

[0260] (12) An imaging element as described in any one of (1) to (11), wherein the third node is a power supply node of the first converter, the power supply node receives a power supply voltage, and wherein the fourth node is an output node of the first converter, the output node outputs an output signal to another component of the first readout circuit.

[0261] (13) The imaging element according to any one of (1) to (12), further comprising:

[0262] A second readout circuit, wherein the first readout circuit controls the second readout circuit.

[0263] (14) An imaging element comprising:

[0264] A first pixel, the first pixel comprising:

[0265] a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and

[0266] a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; and

[0267] at least one first bonding pad on the first substrate and in electrical contact with the first converter, the at least one first bonding pad overlapping at least a portion of the first pixel;

[0268] a second pixel adjacent to the first pixel, the second pixel comprising:

[0269] a second photoelectric conversion region that is disposed in the first substrate and converts incident light into second charges; and

[0270] a second readout circuit comprising a second converter that converts the second charge into a second logarithmic voltage signal; and

[0271] At least one second bonding pad is located on the first substrate and is in electrical contact with the second converter, the at least one second bonding pad overlapping at least a portion of the second pixel.

[0272] (15) The imaging element according to (14), further comprising:

[0273] An isolation region is disposed in the first substrate between the first pixel and the second pixel.

[0274] (16) An imaging element as described in (14) or (15), wherein the at least one first bonding pad includes a plurality of first bonding pads electrically connected to the corresponding first nodes of the first converter, and wherein the at least one second bonding pad includes a plurality of second bonding pads electrically connected to the corresponding second nodes of the second converter.

[0275] (17) The imaging element according to any one of (1) to (16), wherein one of the plurality of second bonding pads overlaps with at least a portion of the second pixel and the isolation region.

[0276] (18) The imaging element according to any one of (1) to (17), wherein one of the plurality of second bonding pads overlaps with a portion of the first pixel.

[0277] (19) An imaging element comprising:

[0278] A first pixel, the first pixel comprising:

[0279] a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and

[0280] a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; and

[0281] A plurality of first bonding pads are located on the first substrate and are in electrical contact with corresponding nodes of the first converter, each of the plurality of first bonding pads overlapping at least a portion of the first pixel.

[0282] (20) An imaging element as described in (19), wherein the corresponding nodes of the first converter include two or more of the following nodes: a power supply node that receives a power supply voltage, an output node that outputs an output signal to another component of the first readout circuit, a node of the first photoelectric conversion region, and a ground node that receives a ground signal or a common signal.

Claims

1. An imaging element, comprising: A first pixel, the first pixel comprising: a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; at least one bonding pad on the first substrate and in electrical contact with the first converter, the at least one bonding pad overlapping at least a portion of the first pixel; and a second substrate bonded to the first substrate via the at least one bonding pad, The first converter includes a first portion disposed in the first substrate, wherein the first portion includes a transistor coupled to the first photoelectric conversion region, and wherein a source of the transistor is wider than a drain of the transistor in a plan view.

2. The imaging element according to claim 1, The first converter includes a second portion configured in the second substrate. 3 . The imaging element according to claim 2 , wherein the first portion includes a node coupled to the photoelectric conversion region, and wherein the second portion includes a plurality of transistors coupled to the node through the at least one bonding pad.

4. The imaging element according to any one of claims 1 to 3, further comprising: A plurality of through-vias are disposed in the first substrate and are in electrical contact with the at least one bonding pad and the first transducer.

5. The imaging element according to any one of claims 1 to 3, wherein the first converter is arranged in the first substrate, and wherein the at least one bonding pad includes a first bonding pad electrically contacting a first node of the first converter and a second bonding pad electrically contacting a second node of the first converter.

6. An imaging element as described in claim 5, wherein the first node is a power supply node of the first converter, the power supply node receives a power supply signal, and wherein the second node is an output node of the first converter, the output node outputs an output signal to another component of the first readout circuit.

7. The imaging element of claim 6 , wherein the at least one bonding pad comprises a third bonding pad electrically contacting a third node of the first converter, and wherein the third node is a node of the photoelectric conversion region or a ground node of the first converter, the ground node receiving a ground signal or a common signal. 8 . The imaging element according to claim 5 , wherein the first node is a node of the photoelectric conversion region, and wherein the second node is a ground node of the first converter, the ground node receiving a ground signal or a common signal.

9. An imaging element as described in claim 8, wherein the at least one bonding pad includes a third bonding pad electrically contacting a third node of the first converter, and wherein the third node is a power supply node of the first converter or an output node of the first converter, the power supply node receiving a power supply signal, and the output node outputting an output signal to another component of the first readout circuit. 10 . The imaging element of claim 8 , wherein the at least one bonding pad comprises a third bonding pad electrically contacting a third node of the first converter and a fourth bonding pad electrically contacting a fourth node of the first converter.

11. An imaging element as described in claim 10, wherein the third node is a power supply node of the first converter, the power supply node receiving a power supply voltage, and wherein the fourth node is an output node of the first converter, the output node outputting an output signal to another component of the first readout circuit.

12. The imaging element according to any one of claims 1 to 3, further comprising: A second readout circuit, wherein the first readout circuit controls the second readout circuit.

13. An imaging element, comprising: A first pixel, the first pixel comprising: a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; and at least one first bonding pad on the first substrate and in electrical contact with the first converter, the at least one first bonding pad overlapping at least a portion of the first pixel; a second pixel adjacent to the first pixel, the second pixel comprising: a second photoelectric conversion region that is disposed in the first substrate and converts incident light into second charges; and a second readout circuit comprising a second converter that converts the second charge into a second logarithmic voltage signal; at least one second bonding pad on the first substrate and in electrical contact with the second converter, the at least one second bonding pad overlapping at least a portion of the second pixel; and a second substrate bonded to the first substrate via the at least one first bonding pad, wherein the first converter includes a first portion configured in the first substrate, wherein the first portion includes a transistor coupled to the first photoelectric conversion region, and wherein in a plan view, a source of the transistor is wider than a drain of the transistor.

14. The imaging element according to claim 13, further comprising: An isolation region is disposed in the first substrate between the first pixel and the second pixel.

15. The imaging element of claim 14, wherein the at least one first bonding pad comprises a plurality of first bonding pads electrically connected to respective first nodes of the first converter, and wherein the at least one second bonding pad comprises a plurality of second bonding pads electrically connected to respective second nodes of the second converter. 16 . The imaging element according to claim 15 , wherein one of the plurality of second bonding pads overlaps at least a portion of the second pixel and the isolation region. 17 . The imaging element according to claim 16 , wherein one of the plurality of second bonding pads overlaps with a portion of the first pixel.

18. An imaging element, comprising: A first pixel, the first pixel comprising: a first photoelectric conversion region that is arranged in the first substrate and converts incident light into first charges; and a first readout circuit comprising a first converter that converts the first charge into a first logarithmic voltage signal; a plurality of first bonding pads on the first substrate and in electrical contact with respective nodes of the first converter, each of the plurality of first bonding pads overlapping at least a portion of the first pixel; and a second substrate bonded to the first substrate via the plurality of first bonding pads, The first converter includes a first portion disposed in the first substrate, wherein the first portion includes a transistor coupled to the first photoelectric conversion region, and wherein a source of the transistor is wider than a drain of the transistor in a plan view.

19. An imaging element as described in claim 18, wherein the corresponding nodes of the first converter include two or more of the following nodes: a power supply node that receives a power supply voltage, an output node that outputs an output signal to another component of the first readout circuit, a node of the first photoelectric conversion region, and a ground node that receives a ground signal or a common signal.

Images