Integrated chip and metal-insulator-metal capacitor and method for forming the same

Abstract

Various embodiments of the present invention are directed to a metal insulator metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer.

Description

Technical Field

[0001] The embodiments of the present invention are related to an integrated chip and a metal-insulator-metal capacitor and a method for forming the same. Background Art

[0002] Contemporary integrated chips include millions or billions of transistor devices that are configured to enable logic functionality for the integrated chip (e.g., forming a processor configured to perform logic functions). Integrated chips may also typically include passive devices such as capacitors, resistors, inductors, varactors, and the like. Metal-insulator-metal (MIM) capacitors are a common type of passive device that is typically integrated into the back-end metal interconnect layer of an integrated chip. For example, MIM capacitors can be used as decoupling capacitors that are configured to reduce power or switching noise caused by current changes flowing through various parasitic inductances associated with the integrated chip and the package in which the integrated chip is located (e.g., switching input / output (I / O) and core circuits). Summary of the invention

[0003] A metal-insulator-metal capacitor according to an embodiment of the present invention comprises: a bottom electrode overlying a substrate, a capacitor dielectric layer overlying the bottom electrode, and a top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer.

[0004] An integrated chip according to an embodiment of the present invention comprises: an internal connection structure overlying a substrate, wherein the internal connection structure comprises an alternating stack of conductive vias and conductive lines; a bottom electrode overlying at least one of the conductive lines; a capacitor dielectric layer overlying the bottom electrode; a top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises: a first top electrode layer; and a second top electrode layer overlying the first top electrode layer, wherein the first top electrode layer and the second top electrode layer respectively have a first columnar grain and a second columnar grain, wherein the second columnar grain overlies the first columnar grain and has a sidewall laterally offset from the sidewall of the first columnar grain.

[0005] A method for forming a metal-insulator-metal capacitor according to an embodiment of the present invention comprises: forming a bottom electrode above a substrate; forming a capacitor dielectric layer above the bottom electrode; depositing a first top electrode layer above the capacitor dielectric layer; depositing a diffusion barrier layer above the first top electrode layer; performing an annealing process on the diffusion barrier layer, wherein after the annealing process, the diffusion barrier layer is enriched with a treatment substance; and depositing a second top electrode layer above the diffusion barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1C Cross-sectional views of some embodiments of metal-insulator-metal (MIM) capacitors with diffusion barriers are shown.

[0008] Figure 2A Cross-sectional views of some embodiments of metal-insulator-metal-insulator-metal (MIMIM) capacitors having multiple diffusion barriers are shown.

[0009] Figure 2B to Figure 2D As shown by Figure 2A The dashed box in the Figure 2A Cross-sectional view of an alternative embodiment of a segment of a MIMIM capacitor.

[0010] Figure 3 A cross-sectional view of an integrated circuit (IC) including a MIM capacitor disposed in an interconnect structure is shown.

[0011] Figure 4 Show Figure 3 Circuit diagrams of some embodiments of the IC.

[0012] Figure 5 Show Figure 3 Cross-sectional views of some alternative embodiments of an IC in which a bonding structure overlies an interconnect structure.

[0013] Figure 6 As shown by Figure 5 The dashed box in the Figure 5 Cross-sectional views of some alternative embodiments of sections of an IC.

[0014] Figure 7A cross-sectional view of an IC including a MIMIM capacitor overlying an interconnect structure is shown.

[0015] Figure 8 Show Figure 7 Circuit diagrams of some embodiments of the IC.

[0016] Fig. 9 Show Figure 7 Cross-sectional views of some alternative embodiments of an IC in which a bonding structure overlies a MIMIM capacitor.

[0017] Fig.10 As shown by Fig. 9 The dashed box in the Fig. 9 Cross-sectional views of some alternative embodiments of sections of an IC.

[0018] Figures 11 to 16 A series of cross-sectional views illustrating some embodiments of methods for forming a metal-insulator-metal (MIM) capacitor having a diffusion barrier layer.

[0019] Fig.17 Show Figures 11 to 16 A block diagram of some embodiments of the method.

[0020] Description of Figure Numbers

[0021] 100a, 100b, 100c: metal-insulator-metal capacitor;

[0022] 100p1, 802p1, 804p1: first board;

[0023] 100p2, 802p2, 804p2: second board;

[0024] 102: substrate;

[0025] 104: bottom electrode;

[0026] 106: capacitor dielectric layer;

[0027] 106cr: central area;

[0028] 106pr: peripheral area;

[0029] 108: top electrode;

[0030] 110a: first top electrode layer;

[0031] 110b: second top electrode layer;

[0032] 112: diffusion barrier layer;

[0033] 112a: upper zone;

[0034] 112ts: top surface;

[0035] 114, 116, 204ag, 204bg: grains;

[0036] 114a, 116a: first crystal grains;

[0037] 114b, 116b: second crystal grains;

[0038] 118: diffusion barrier grains;

[0039] 200a: Metal-insulator-metal-insulator-metal capacitor;

[0040] 200b, 200c, 200d, 600, 1000, 1100, 1200, 1300, 1400, 1500, 1600: cross-sectional views;

[0041] 202: middle electrode;

[0042] 204a: a first intermediate electrode layer;

[0043] 204b: second intermediate electrode layer;

[0044] 206: intermediate electrode diffusion barrier layer;

[0045] 208: upper capacitor dielectric layer;

[0046] 210: lower dielectric layer;

[0047] 212: intermediate dielectric layer;

[0048] 214: upper dielectric layer;

[0049] 300, 500, 700, 900: integrated circuits;

[0050] 301: transistor body node;

[0051] 302: source / drain region;

[0052] 303: Internal connection structure;

[0053] 304: gate dielectric;

[0054] 305: well region;

[0055] 306: gate electrode;

[0056] 308: access metal oxide semiconductor field effect transistor;

[0057] 310: conductive via;

[0058] 312: Conductive wire;

[0059] 312a, 508a: electrical conductor;

[0060] 312b, 508b: conductive lining;

[0061] 314: interlayer dielectric layer;

[0062] 314u: upper ILD layer;

[0063] 316a, 316b, 316c: upper through holes;

[0064] 318a, 318b, 318c: upper conductors;

[0065] 320: Connector;

[0066] 400, 800: Circuit diagram;

[0067] 502: Isolation structure;

[0068] 504: sidewall spacer structure;

[0069] 505: joint structure;

[0070] 506: Rewiring via;

[0071] 506a: first redistribution via;

[0072] 506b: second rewiring via;

[0073] 508: redistribution layer;

[0074] 510: first passivation layer;

[0075] 512: second passivation layer;

[0076] 514: top dielectric structure;

[0077] 515: bump structure;

[0078] 516: bonding pad;

[0079] 518: engagement bump;

[0080] 520: solder ball;

[0081] 802: a first capacitor;

[0082] 804: a second capacitor;

[0083] 1402: masking layer;

[0084] 1700: Methods;

[0085] 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, 1718: action;

[0086] A: Box;

[0087] BL: bit line;

[0088] H: height;

[0089] SL: source line;

[0090] W: width;

[0091] W1: first width;

[0092] W2: second width;

[0093] WL: word line;

[0094] d1, d2: distance;

[0095] t a ,t b ,t cr ,t db ,t pr :thickness. DETAILED DESCRIPTION

[0096] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0097] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0098] Metal-insulator-metal (MIM) capacitors can be implemented into the back-end-of-the-line (BEOL) metal interconnect layer of an integrated chip. MIM capacitors typically have a top electrode and a bottom electrode separated by a capacitor dielectric layer. During the formation of the MIM capacitor, the capacitor dielectric layer is formed above the bottom electrode. A top electrode film is deposited above the capacitor dielectric layer. A masking layer is formed above the top electrode film, and the top electrode film is patterned according to the masking layer, thereby forming a top electrode. A masking layer removal process is performed to remove the masking layer, and a cleaning process is performed to remove byproducts from the top electrode film deposition and / or patterning process. The removal process and / or cleaning process use one or more chemicals from a diffusion substance (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolate (DHF), etc.).

[0099] The above-mentioned difficulty of MIM capacitor relates to the structure of the top electrode. The top electrode film can be formed by a physical vapor deposition (PVD) process to have a larger thickness (e.g., 400 angstroms), so that the top electrode has larger columnar grains. The larger thickness increases the structural integrity of the MIM capacitor, but at the expense of larger grain size. Due to the columnar grains, the diffused substances from the removal process and / or the cleaning process diffuse to the capacitor dielectric layer through the top electrode (e.g., along the grain boundaries between adjacent columnar grains). The diffused substances react with the capacitor dielectric layer or otherwise interact, thereby forming voids in the capacitor dielectric layer. These voids can cause electrical breakdown of the capacitor dielectric layer, and can therefore cause the top electrode to be electrically shorted to the bottom electrode at high operating voltages (e.g., in the range of 2.3 volts to 3.5 volts (V)). Such electrical short circuits, in turn, cause MIM capacitor failures.

[0100] Various embodiments of the present application are directed to a top electrode having a diffusion barrier layer that blocks and / or prevents diffusion of a diffusion substance. In some embodiments, a first top electrode layer is formed over a capacitor dielectric layer by a PVD process such that the first top electrode layer includes a first material (e.g., titanium nitride (TiN)) having columnar grains and a first thickness (e.g., 200 angstroms). The diffusion barrier layer is formed over the first top electrode layer by an atomic layer deposition (ALD) process, and an annealing process in a process substance (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) is performed on the diffusion barrier layer. The diffusion barrier layer includes a first material having a second thickness (e.g., 10 angstroms to 15 angstroms). By performing the annealing process in the process substance, the diffusion barrier layer is nitrogen-rich (e.g., N-rich) and has a higher ratio of nitrogen atoms to titanium atoms than the first top electrode layer. This results in at least partial crystallization of the diffusion barrier layer, wherein the grain size is smaller than the columnar grains of the first top electrode layer. The second top electrode layer is formed over the diffusion barrier layer by a PVD process, so that the second top electrode layer includes a first material having columnar grains and having a first thickness of about 200 angstroms. The aforementioned layers are patterned according to the masking layer, thereby defining the top electrode. During the subsequent removal process and / or cleaning process, the partially crystalline structure and smaller grain size of the diffusion barrier layer block the diffusion of the diffusion material to the capacitor dielectric layer. Therefore, the diffusion barrier layer prevents the formation of voids in the capacitor dielectric layer, thereby preventing breakdown in the MIM capacitor at high operating voltages. This increases the operating voltage, withstand capability, and reliability of the MIM capacitor to some extent.

[0101] See also Figure 1A , a cross-sectional view of some embodiments of a metal-insulator-metal (MIM) capacitor 100a having a diffusion barrier layer 112 is provided.

[0102] The MIM capacitor 100a includes a top electrode 108, a bottom electrode 104, and a capacitor dielectric layer 106 disposed between the top electrode 108 and the bottom electrode 104. The bottom electrode 104 overlies the substrate 102. The top electrode 108 overlies the bottom electrode 104 and has a first width W1 that is smaller than a second width W2 of the bottom electrode 104. The top electrode 108 includes a first top electrode layer 110a, a second top electrode layer 110b, and a diffusion barrier layer 112 disposed between the first top electrode layer 110a and the second top electrode layer 110b.

[0103] In some embodiments, the top electrode 108 and the bottom electrode 104 may be or include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, or the like. The first top electrode layer 110a and the second top electrode layer 110b include a metal nitride having a first ratio of nitrogen atoms to metal atoms (e.g., titanium atoms), such that the aforementioned layers have grains (e.g., columnar grains) with a first grain size. The diffusion barrier layer 112 includes a metal nitride having a second ratio of nitrogen atoms to metal atoms (e.g., titanium atoms), such that the diffusion barrier layer has diffusion barrier grains (e.g., non-columnar grains) with a second grain size smaller than the first grain size. In some embodiments, the first ratio of nitrogen atoms to metal atoms is 1:1, and the second ratio of nitrogen atoms to metal atoms is 1.0x:1 (where x is in the range of about 2 to 5). For example, for every 100 metal atoms, the first top electrode layer 110a and / or the second top electrode layer 110b may include 100 nitrogen atoms, whereas for every 100 metal atoms, the diffusion barrier layer 112 may include 102 to 105 nitrogen atoms. Therefore, the diffusion barrier layer 112 is nitrogen-rich (N-rich) (i.e., has a greater number of nitrogen atoms than metal atoms). By virtue of the fact that nitrogen atoms have a smaller atomic radius than metal atoms, the distance between atoms in the diffusion barrier layer 112 is smaller than the distance between atoms in the first top electrode layer 110a and / or the second top electrode layer 110b. Therefore, compared to the atoms in the first top electrode layer 110a and / or the second top electrode layer 110b, the atoms in the diffusion barrier layer 112 are more densely packed together, so that the diffusion barrier layer 112 has a smaller grain size. In some embodiments, the atoms in the diffusion barrier layer 112 are so densely packed together that the diffusing species (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolate (DHF), etc.) cannot travel between adjacent atoms in the diffusion barrier layer 112. As a result, the diffusion barrier layer 112 has more densely packed atoms, non-columnar grains, and / or at least a partially crystalline structure that affects the ability to block and / or slow down the diffusion of the diffusing species. This prevents the diffusing species from adversely affecting the structural integrity of the capacitor dielectric layer 106, thereby mitigating degradation of the MIM capacitor 100a. In some embodiments, the bottom electrode 104 includes a metal nitride having a first ratio of nitrogen atoms to metal atoms, wherein the bottom electrode 104 has columnar grains.

[0104] For example, during the formation of the MIM capacitor 100a, the first top electrode layer 110a is formed over the capacitor dielectric layer 106 by a first deposition process (e.g., a physical vapor deposition (PVD) process). With the first deposition, the first top electrode layer 110a has a first grain size (e.g., columnar grains). The diffusion barrier layer 112 is formed over the first top electrode layer 110a by a second deposition process (e.g., an atomic layer deposition (ALD) process) to have a second thickness (e.g., about 10 angstroms to 15 angstroms). After performing the second deposition process, an annealing process in a process substance (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) is performed on the diffusion barrier layer 112, so that the diffusion barrier layer is rich in the process substance (e.g., N-rich). In some embodiments, the annealing process in the first process substance (e.g., nitrogen (N2)) and the second process substance (e.g., hydrogen (H2)) is performed, wherein the second process substance helps to inject the first process substance into the diffusion barrier layer. In such embodiments, the second process substance may help dissociate the molecules of the first process substance into the first process substance atoms, so that the first process substance atoms can be more easily implanted into the diffusion barrier layer 112. This ensures that the diffusion barrier layer 112 has a second grain size (e.g., equiaxed grains) that is smaller than the first grain size. In addition, the second top electrode layer 110b is formed over the diffusion barrier layer 112 by a first deposition process, so that the second top electrode layer 110b has the first grain size. After forming the aforementioned layers, a patterning process is performed, thereby defining the top electrode 108 having a first width W1. Subsequently, a removal process may be performed to remove the mask (e.g., a photoresist mask) and / or a cleaning process may be performed to remove byproducts from the aforementioned deposition process and / or patterning process.

[0105] The removal process and / or the cleaning process uses one or more chemicals from the diffusing species, such as oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), etc. In some embodiments, if the diffusing species reaches the capacitor dielectric layer 106, the diffusing species may react or otherwise interact with the capacitor dielectric layer 106, thereby forming voids in the capacitor dielectric layer 106. During the removal process and / or the cleaning process, the diffusing species may travel along the grain boundaries of the grains in the second top electrode layer 110b to the diffusion barrier layer 112. However, the second grain size of the diffusion barrier layer 112 slows down and / or blocks the diffusing species from reaching the capacitor dielectric layer 106. Therefore, the second grain size of the diffusion barrier layer 112 prevents the formation of voids in the capacitor dielectric layer 106. By preventing the formation of voids in the capacitor dielectric layer 106, breakdown of the capacitor dielectric layer 106 may not occur at high operating voltages (e.g., in the range of 2.3 volts to 3.5 volts). Thus, the diffusion barrier layer 112 increases the operating voltage (eg, up to about 4.8 volts), withstand capability, and reliability of the MIM capacitor 100a.

[0106] See also Figure 1B , provide the basis Figure 1A 100a of the MIM capacitor 100b of some alternative embodiments. In some embodiments, Figure 1B The cross-sectional view of the MIM capacitor 100b in FIG. 1 is an enlarged view so that the grain sizes of the different layers are visible.

[0107] The capacitor dielectric layer 106 has a thickness t defined in a central region of the capacitor dielectric layer 106. cr The top electrode 108 overlies the central region of the capacitor dielectric layer 106, such that the capacitor dielectric layer 106 has a thickness t between the top surface of the bottom electrode 104 and the bottom surface of the first top electrode layer 110a. cr The capacitor dielectric layer 106 has a thickness t defined in a peripheral region of the capacitor dielectric layer 106. pr , such that the peripheral region surrounds the central region and is laterally offset from the top electrode 108. In some embodiments, the thickness t pr Less than thickness t cr Therefore, the capacitor dielectric layer 106 has two discontinuous thicknesses. In some embodiments, the capacitor dielectric layer 106 may be or include a high dielectric constant (κ) dielectric material, such as aluminum oxide (Al2O3). x O y )、ZrO x ) or the like. As used herein, a high-κ dielectric material is a dielectric material having a dielectric constant greater than 3.9. In yet other embodiments, the capacitor dielectric layer 106 includes a plurality of dielectric materials and / or a plurality of dielectric layers. For example, the capacitor dielectric layer 106 may include a first zirconium oxide layer (e.g., ZrO2), a second zirconium oxide layer (e.g., ZrO2), and an aluminum oxide layer (e.g., Al2O3) disposed between the first zirconium oxide layer and the second zirconium oxide layer (not shown).

[0108] The first top electrode layer 110a includes a plurality of grains 114. For ease of illustration, only some of the grains 114 are labeled 114. The grains 114 define grain boundaries that may extend from the upper surface of the capacitor dielectric layer 106 to the lower surface of the diffusion barrier layer 112. In some embodiments, the grains 114 are columnar grains, and the first grains may have an area and / or width different from that of the second grains. For example, the first grains 114a may have a greater width and / or area than the second grains 114b. In some embodiments, the first top electrode layer 110a may, for example, be or include a first material such as titanium nitride, tantalum nitride, tungsten nitride, or the like, and / or may have a maximum thickness t of approximately 100 angstroms, 200 angstroms, or in a range of approximately 100 angstroms to 200 angstroms. a .

[0109] The second top electrode layer 110b includes a plurality of grains 116. For ease of illustration, only some of the grains 116 are labeled 116. The grains 116 define grain boundaries that may extend from the upper surface of the diffusion barrier layer 112 to a point above the upper surface of the diffusion barrier layer 112. In some embodiments, the grains 116 are columnar grains, and the first grains may have a different area and / or width than the second grains. For example, the first grain 116a may have a larger width and / or area than the second grain 116b. In some embodiments, the grain boundary of the first grain 116a of the second top electrode layer 110b is laterally offset from the grain boundary of the first grain 114a of the first top electrode layer 110a by a distance d1. In some embodiments, the distance d1 is non-zero. Therefore, the grains 116 of the second top electrode layer 110b and the grains 114 of the first top electrode layer 110a may both be columnar grains with different layouts and / or different grain boundary positions. In such embodiments, the non-zero distance d1 increases the ability of the top electrode 108 to prevent diffusion of the diffusing species into the capacitor dielectric layer 106. The distance d1 can act as another barrier to the diffusing species. For example, in some embodiments, the diffusing species can diffuse vertically through the first top electrode layer 110a and the diffusion barrier layer 112. In such embodiments, the shifted grain boundaries between the first top electrode layer 110a and the second top electrode layer 110b (e.g., due to the distance d1) can cause the diffusing species to diffuse laterally before they can diffuse vertically through the second top electrode layer 110b. Therefore, the shifted grain boundaries between the first electrode layer 110a and the second electrode layer 110b increase the ability to slow down and / or block the diffusion of the diffusing species.

[0110] In some embodiments, the second top electrode layer 110b includes the first material, so that the first top electrode layer 110a and the second top electrode layer 110b include the same material. In some embodiments, the second top electrode layer 110b may be or include, for example, titanium nitride, tantalum nitride, tungsten nitride, or the like, and / or may have a maximum thickness t of about 100 angstroms, 200 angstroms, or in the range of about 100 angstroms to 200 angstroms. b In some embodiments, the maximum thickness t of the first top electrode layer 110a is a is equal to the maximum thickness t of the second top electrode layer 110b b .

[0111] The diffusion barrier layer 112 is between the first top electrode layer 110a and the second top electrode layer 110b and has diffusion barrier grains 118. Box A shows an enlarged view of the diffusion barrier layer 112 so that the diffusion barrier grains 118 can be more easily shown. In some embodiments, the entire diffusion barrier layer 112 includes diffusion barrier grains 118. For ease of illustration, only some of the diffusion barrier grains 118 are labeled as 118. In some embodiments, the diffusion barrier grains 118 are smaller than the grains 114 of the first top electrode layer 110a and / or the grains 116 of the second top electrode layer 110b. The diffusion barrier grains 118 may be, for example, equiaxed grains and / or non-columnar grains. In other embodiments, the diffusion barrier layer 112 may have a partially crystalline structure. In the aforementioned embodiments, the diffusion barrier grains 118 have a grain size smaller than the grains 114 of the first top electrode layer 110a and / or the grains 116 of the second top electrode layer 110b.

[0112] The smaller grain size of the diffusion barrier grains 118 (relative to the grains 116) allows the diffusion barrier grains 118 to be packed more densely together, so that the diffusion barrier grains 118 have smaller grain boundaries than the grains 116. In some embodiments, the grain size is small enough to block and / or slow down the diffusion of the diffusion species. Therefore, the diffusion barrier layer 112 is configured to block and / or slow down the diffusion of the diffusion species to the capacitor dielectric layer 106. The diffusion species may be, for example, or include oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolate (DHF), a combination of the foregoing, or the like. In some embodiments, the diffusion species may travel along the grain boundaries of the grains 116 of the second top electrode layer 110b to the diffusion barrier layer 112. However, the diffusion species may not enter the diffusion barrier layer 112 and / or travel along the grain boundaries of the diffusion barrier grains 118. Therefore, the diffusion barrier layer 112 blocks the diffusion species from reaching the capacitor dielectric layer 106. In other embodiments, the diffusion barrier layer 112 includes titanium nitride having a higher concentration of nitrogen than titanium.

[0113] The diffusion barrier layer 112 has a maximum thickness t smaller than that of the first top electrode layer 110a. a and / or the maximum thickness t of the second top electrode layer 110b b Thickness t db For example, the thickness t db In some embodiments, if the thickness t db If the thickness t is less than 10 angstroms, the diffusion barrier layer 112 may fail to block the diffusion of the diffusion species, thereby causing the capacitor dielectric layer 106 to break down at high operating voltages (e.g., in the range of 2.3 volts to 3.5 volts). dbIf the thickness of the diffusion barrier layer 112 is greater than 15 angstroms, the time and cost associated with forming the diffusion barrier layer 112 may increase. The first top electrode layer 110a, the second top electrode layer 110b, and the diffusion barrier layer 112 may include the same material (e.g., TiN). In some embodiments, the diffusion barrier layer 112 may be, for example, or include titanium nitride, tantalum nitride, tungsten nitride, tungsten, nickel, titanium, tantalum, zirconium, nickel chromium, palladium, or the like. In some embodiments, the maximum thickness of the diffusion barrier layer 112 is greater than the maximum thickness of the first top electrode layer 110a. a and / or the maximum thickness t of the second top electrode layer 110b b About 20 times, 15 times, 13 times, or in the range of 10 times to 20 times smaller.

[0114] In some embodiments, the diffusion barrier grains 118 are small grains of approximately the same size. In some embodiments, if all dimensions (e.g., height H, width W, and depth D) of the diffusion barrier grains 118 are within approximately 30 percent, 20 percent, or 10 percent of the average dimension (e.g., (H+W+D) / 3), then the diffusion barrier grains 118 have approximately the same size. In some embodiments, one, some, or all dimensions of the diffusion barrier grains 118 are between about 1 nanometer and 4.5 nanometers, about 2.5 nanometers and 4.5 nanometers, or about 0.5 nanometers and 2.5 nanometers. For example, the maximum dimension of the diffusion barrier grains 118 may be between one of these ranges. In addition, in some embodiments, one (e.g., the maximum dimension), some, or all dimensions of the diffusion barrier grains 118 are less than about 4 nanometers or 4.5. For example, the maximum dimension of the diffusion barrier grains 118 may be less than one of these thresholds or greater than one.

[0115] See also Figure 1C , provide the basis Figure 1B 100b. The diffusion barrier layer 112 has a rough bottom surface that is consistent with the rough upper surface of the first top electrode layer 110a. In some embodiments, the upper surface of the first top electrode layer 110a includes a plurality of protrusions, and the bottom surface of the diffusion barrier layer 112 includes a plurality of grooves adjacent to the protrusions of the first top electrode layer 110a. In addition, the sidewalls of the second top electrode layer 110b are laterally offset from the sidewalls of the diffusion barrier layer 112 by a distance d2. In some embodiments, the distance d2 is non-zero.

[0116] See also Figure 2A , a cross-sectional view of some embodiments of a metal-insulator-metal-insulator-metal (MIMIM) capacitor 200a including a top electrode 108 having a diffusion barrier layer 112 and an intermediate electrode 202 including an intermediate electrode diffusion barrier layer 206 is provided.

[0117] The bottom electrode 104 overlies the substrate 102. The capacitor dielectric layer 106 overlies the substrate 102 and the bottom electrode 104. The capacitor dielectric layer 106 continuously extends over the sidewalls and the upper surface of the bottom electrode 104. The middle electrode 202 extends over the upper surface of the capacitor dielectric layer 106 and overlies a portion of the bottom electrode 104. The middle electrode 202 is separated from the bottom electrode 104 by the capacitor dielectric layer 106.

[0118] The middle electrode 202 includes a first middle electrode layer 204a, a second middle electrode layer 204b, and a middle electrode diffusion barrier layer 206 disposed between the first middle electrode layer 204a and the second middle electrode layer 204b. In some embodiments, the middle electrode 202 is configured as follows: Figure 1A to Figure 1C The top electrode 108 of the capacitor 106 is formed so that the intermediate electrode diffusion barrier layer 206 is configured to block and / or slow down the diffusion of diffusion substances (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), etc.) to the capacitor dielectric layer 106. In addition, the first intermediate electrode layer 204a and the second intermediate electrode layer 204b may each have columnar grains, and the intermediate electrode diffusion barrier layer 206 has grains smaller than the columnar grains. In other embodiments, the intermediate electrode diffusion barrier layer 206 includes titanium nitride with a high concentration of nitrogen, so that the intermediate electrode diffusion barrier layer 206 is at least partially crystallized. In the aforementioned embodiments, the at least partially crystalline structure of the intermediate electrode diffusion barrier layer 206 blocks and / or slows down the diffusion of diffusion substances. In yet other embodiments, the intermediate electrode diffusion barrier layer 206 includes equiaxed grains.

[0119] The upper capacitor dielectric layer 208 overlies the upper surface of the middle electrode 202. In some embodiments, the upper capacitor dielectric layer 208 comprises the same material as the capacitor dielectric layer 106. In some embodiments, the upper capacitor dielectric layer 208 may be or include a high-κ dielectric material, such as aluminum oxide (Al2O3). x O y )、ZrO x ) or the like. In yet other embodiments, the upper capacitor dielectric layer 208 includes a plurality of dielectric materials and / or a plurality of dielectric layers. For example, the upper capacitor dielectric layer 208 may include a first zirconium oxide layer (e.g., ZrO2), a second zirconium oxide layer (e.g., ZrO2), and an aluminum oxide layer (e.g., Al2O3) disposed between the first zirconium oxide layer and the second zirconium oxide layer (not shown).

[0120] The top electrode 108 overlies the upper capacitor dielectric layer 208 and the capacitor dielectric layer 106. The top electrode 108 is configured as follows: Figure 1A to Figure 1CThe top electrode 108 is formed by the top capacitor dielectric layer 208, so that the diffusion barrier layer 112 is disposed between the first top electrode layer 110a and the second top electrode layer 110b. The diffusion barrier layer 112 is configured to block and / or slow down the diffusion of the diffusion species to the upper capacitor dielectric layer 208 and / or the capacitor dielectric layer 106. In some embodiments, the top electrode 108 is separated from the middle electrode 202 by the upper capacitor dielectric layer 208, and the top electrode 108 is separated from the bottom electrode 104 by the capacitor dielectric layer 106.

[0121] See also Figure 2B , provided by Figure 2A The dashed box in the Figure 2A A cross-sectional view 200b of a portion of the MIMIM capacitor 200a is shown.

[0122] The first intermediate electrode layer 204a includes a plurality of crystal grains 204ag, which may be, for example, columnar crystal grains forming grain boundaries extending from the capacitor dielectric layer 106 to the intermediate electrode diffusion barrier layer 206. The second intermediate electrode layer 204b includes a plurality of crystal grains 204bg, which may be, for example, columnar crystal grains forming grain boundaries extending from the intermediate electrode diffusion barrier layer 206 to the upper capacitor dielectric layer 208. The intermediate electrode diffusion barrier layer 206 may, for example, include diffusion barrier crystal grains (not shown) that are smaller than the crystal grains 204ag and / or the crystal grains 204bg. In some embodiments, the diffusion barrier crystal grains of the intermediate electrode diffusion barrier layer 206 may be configured as follows: Figure 1B The top electrode 108 overlies the upper capacitor dielectric layer 208 and is configured as follows: Figure 1A to Figure 1C The top electrode 108 is formed on the surface of the substrate.

[0123] See also Figure 2C ,supply Figure 2B FIG. 2 is a cross-sectional view 200 c of an alternative embodiment of the present invention, wherein the first intermediate electrode layer 204 a includes a plurality of protruding portions adjacent to the plurality of recesses of the intermediate electrode diffusion barrier layer 206. The second intermediate electrode layer 204 b includes a plurality of protruding portions adjacent to the plurality of recesses of the upper capacitor dielectric layer 208. In addition, the first top electrode layer 110 a includes a plurality of protruding portions adjacent to the plurality of recesses of the diffusion barrier layer 112.

[0124] See also Figure 2D , provided by Figure 2A The dashed box in the Figure 2A200d is a cross-sectional view of a portion of a MIMIM capacitor 200a, wherein the capacitor dielectric layer 106 includes a lower dielectric layer 210, an intermediate dielectric layer 212, and an upper dielectric layer 214. The intermediate dielectric layer 212 is disposed between the upper dielectric layer 214 and the lower dielectric layer 210. In some embodiments, the upper dielectric layer 214 and the lower dielectric layer 210 may each include zirconium oxide, and the intermediate dielectric layer 212 may include aluminum oxide. In other embodiments, the upper capacitor dielectric layer 208 is configured as follows: Figure 2D The capacitor dielectric layer 106 (not shown) in FIG.

[0125] See also Figure 3 , a cross-sectional view of some embodiments of an integrated circuit (IC) 300 including a metal-insulator-metal (MIM) capacitor 100a is provided. The MIM capacitor 100a is disposed in an interconnect structure 303 configured for a one-transistor one-capacitor (1T1C) arrangement.

[0126] IC 300 includes an interconnect structure 303 overlying substrate 102. Substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. An access metal-oxide-semiconductor field-effect transistor (MOSFET) 308 is disposed on substrate 102. Access MOSFET 308 includes a pair of source / drain regions 302 disposed in substrate 102 and laterally spaced apart. A gate dielectric 304 overlies substrate 102 between the individual source / drain regions 302, and a gate electrode 306 overlies gate dielectric 304. In some embodiments, gate electrode 306 may be, for example, or include polysilicon or another suitable conductive material. Substrate 102 includes a first doping type (e.g., p-type), and source / drain regions 302 include a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, source / drain regions 302 include a doping concentration greater than a doping concentration of substrate 102 . Well region 305 is disposed between source / drain regions 302 and includes a first doping type having a higher doping concentration than substrate 102 .

[0127] The interconnect structure 303 includes a plurality of inter-level dielectric (ILD) layers 314 overlying the substrate 102 and the access MOSFET 308. The ILD layer 314 may include one or more ILD materials. In some embodiments, the one or more ILD materials may be, for example, a low-κ dielectric material, an oxide (e.g., silicon dioxide), a combination of the foregoing, or another suitable dielectric material. As used herein, a low-κ dielectric material is a dielectric material having a dielectric constant of less than 3.9. A plurality of conductive wires 312 and conductive vias 310 are stacked within the ILD layer 314 and are configured to provide electrical connections between various devices (e.g., access MOSFET 308 and / or MIM capacitor 100a) disposed throughout the IC 300. In some embodiments, the conductive wires 312 and / or conductive vias 310 may be, for example, or include copper, aluminum, or some other conductive material.

[0128] The MIM capacitor 100a is disposed in the upper ILD layer 314u. The MIM capacitor 100a includes a top electrode 108, a bottom electrode 104, and a capacitor dielectric layer 106 disposed between the top electrode 108 and the bottom electrode 104. A plurality of upper vias 316a to 316c electrically couple the MIM capacitor 100a to the bottom conductive line 312. A plurality of upper vias 316a to 316c are electrically coupled to upper conductive lines 318a to 318c. In some embodiments, the first upper conductive line 318a is electrically coupled to the second upper conductive line 318b by means of a connector 320 (shown schematically for each illustration). In some embodiments, the connector 320 includes conductive lines and / or vias overlying the MIM capacitor 100a. The upper via 316b extends from the second upper conductive line 318b to the bottom electrode 104 of the MIM capacitor 100a, and the upper via 316c extends from the third upper conductive line 318c to the top electrode 108 of the MIM capacitor 100a. In some embodiments, the MIM capacitor 100a is configured as follows: Figure 1A to Figure 1C MIM capacitor 100a.

[0129] In some embodiments, the gate electrode 306 is electrically coupled to a word line (WL) so that an appropriate WL voltage can be applied to the gate electrode 306 to electrically couple the MIM capacitor 100a to a bit line (BL) and a source line (SL). SL is electrically coupled to the source / drain region 302, and BL is electrically coupled to another source / drain region 302 by means of the interconnect structure 303 and the MIM capacitor 100a. Therefore, in some embodiments, after applying an appropriate WL voltage, the output of the BL and / or the MIM capacitor 100a can be accessed at SL. In other embodiments, a voltage can be applied at a transistor body node 301 that is electrically coupled to a well region 305 (i.e., the body of the access MOSFET 308) disposed below the gate electrode 306. The voltage applied at the transistor body node 301 can be configured to assist in controlling a conductive channel formed in the well region 305.

[0130] See also Figure 4 ,supply Figure 3 A circuit diagram 400 of some embodiments of the IC 300 is shown.

[0131] like Figure 4 As shown in , SL is electrically coupled to a first source / drain region of access MOSFET 308. WL is electrically coupled to a gate electrode of access MOSFET 308, and a second source / drain region of access MOSFET 308 is electrically coupled to MIM capacitor 100a. Bottom electrode 104 is configured as a first plate 100p1 of MIM capacitor 100a, and top electrode 108 is configured as a second plate 100p2 of MIM capacitor 100a, such that first plate 100p1 is parallel to second plate 100p2. In some embodiments, capacitor dielectric layer ( Figure 3 106) is disposed between the first plate 100p1 and the second plate 100p2. In some embodiments, the first plate 100p1 is electrically coupled to the second source / drain region of the access MOSFET 308, and the second plate 100p2 is electrically coupled to the BL.

[0132] See also Figure 5 , provide the basis Figure 3 5 is a cross-sectional view of an IC 500 of some alternative embodiments of the IC 300 , wherein a bonding structure 505 overlies the interconnect structure 303 .

[0133] The access MOSFET 308 includes source / drain regions 302, a gate electrode 306, and a gate dielectric 304. The source / drain regions 302 are disposed between isolation structures 502 extending from an upper surface of the substrate 102 to a point below the upper surface of the substrate 102. In some embodiments, the isolation structures 502 are configured as shallow trench isolation (STI) structures and include one or more dielectric materials (e.g., silicon dioxide). The access MOSFET 308 further includes a sidewall spacer structure 504 surrounding the gate electrode 306 and the gate dielectric 304. At least a portion of the sidewall spacer structure 504 overlies the source / drain regions 302.

[0134] The bonding structure 505 overlies the interconnect structure 303 and the MIM capacitor 100a. The bonding structure 505 includes a first passivation layer 510, a second passivation layer 512, a top dielectric structure 514, a bump structure 515, a redistribution layer 508, and a redistribution via 506. The redistribution layer 508 is disposed in the second passivation layer 512. The redistribution via 506 is disposed in the first passivation layer 510 and extends from the redistribution layer 508 to the first upper conductive line 318a. Therefore, the redistribution layer 508 is electrically coupled to the MIM capacitor 100a. The bump structure 515 extends through the top dielectric structure 514 and contacts the redistribution layer 508. The bump structure 515 includes a bonding pad 516, a bonding bump 518, and a solder ball 520. The bump structure 515 is electrically coupled to the interconnect structure 303 by means of the redistribution layer 508. In some embodiments, bump structure 515 is configured to electrically couple IC 500 to another IC (not shown).

[0135] See also Figure 6 , provided by Figure 5 The dashed box in the Figure 5 A cross-sectional view 600 of some alternative embodiments of a portion of IC 500 .

[0136] like Figure 6As shown in FIG. 1 , the MIM capacitor 100a is disposed within the ILD layer 314 and overlies the conductive lines 312. The conductive lines 312 each include a conductor 312a surrounded by a conductive liner 312b. A first upper conductor 318a overlies the top electrode 108 and includes one or more protrusions that directly contact the top electrode 108. A second upper conductor 318b overlies the bottom electrode 104 and includes a protrusion that extends through the capacitor dielectric layer 106 and directly contacts the bottom electrode 104. In some embodiments, the first upper conductor 318a and the second upper conductor 318b each include a conductor 312a surrounded by a conductive liner 312b. In some embodiments, the conductor 312a may be, for example, or include aluminum, copper, an alloy thereof, or the like. In other embodiments, the conductive liner 312b may be, for example, or include tungsten or the like.

[0137] See also Figure 7 , providing the corresponding Figure 3 300. The IC 700 includes a metal-insulator-metal-insulator-metal (MIMIM) capacitor 200a disposed in a first passivation layer 510 and configured for a one-transistor two-capacitor (1T2C) arrangement.

[0138] Access MOSFET 308 is configured and / or shown as Figure 3 The access MOSFET 308 of the MIMIM capacitor 200a is provided. The junction structure 505 overlies the interconnect structure 303 and the access MOSFET 308. The junction structure 505 includes a first passivation layer 510, a second passivation layer 512, a redistribution layer 508, and a first redistribution via 506a and a second redistribution via 506b. The MIMIM capacitor 200a is disposed in the first passivation layer 510. The MIMIM capacitor 200a includes a bottom electrode 104, a capacitor dielectric layer 106, an upper capacitor dielectric layer 208, a top electrode 108, and an intermediate electrode 202 disposed between the top electrode 108 and the bottom electrode 104.

[0139] The first redistribution via 506a extends from the redistribution layer 508 to the uppermost layer of the conductive line 312 in the interconnect structure 303. The first redistribution via 506a extends through the top electrode 108, the capacitor dielectric layer 106, and the bottom electrode 104, so that the top electrode 108 is electrically coupled to the bottom electrode 104. The second redistribution via 506b extends from the redistribution layer 508 to the uppermost layer of the conductive line 312 and is electrically coupled to the source / drain region 302 of the access MOSFET 308. The second redistribution via 506b extends through the upper capacitor dielectric layer 208, the middle electrode 202, and the capacitor dielectric layer 106. Therefore, the middle electrode 202 is electrically coupled to the source / drain region 302 of the access MOSFET 308. In some embodiments, the redistribution layer 508 is electrically coupled to the BL.

[0140] See also Figure 8 ,supply Figure 7 A circuit diagram 800 of some embodiments of IC 700 is shown.

[0141] like Figure 8 As shown in FIG, SL is electrically coupled to a first source / drain region of access MOSFET 308. WL is electrically coupled to a gate electrode of access MOSFET 308, and a second source / drain region of access MOSFET 308 is electrically coupled to MIMIM capacitor 200a. The second source / drain region of access MOSFET 308 is electrically coupled to BL through MIMIM capacitor 200a.

[0142] In some embodiments, the MIMIM capacitor 200a includes a first capacitor 802 electrically coupled to a second capacitor 804 in parallel with each other. The first capacitor 802 includes a first plate 802p1 and a second plate 802p2, such that the first plate 802p1 is parallel to the second plate 802p2. The second capacitor 804 includes a first plate 804p1 and a second plate 804p2, such that the first plate 804p1 is parallel to the second plate 804p2. In some embodiments, the middle electrode 202 is configured as the first plate 802p1 of the first capacitor 802 and the first plate 804p1 of the second capacitor 804. In other embodiments, the bottom electrode 104 is configured as the second plate 802p2 of the first capacitor 802, and the top electrode 108 is configured as the second plate 804p2 of the second capacitor 804. The second plate 802p2 of the first capacitor 802 and the second plate 804p2 of the second capacitor 804 are electrically coupled to BL.

[0143] See also Fig. 9 , provide the basis Figure 7 FIG. 9 is a cross-sectional view of an IC 900 of some alternative embodiments of the IC 700 , wherein a bonding structure 505 having a bump structure 515 overlies an interconnect structure 303 .

[0144] The access MOSFET 308 includes source / drain regions 302, a gate electrode 306, and a gate dielectric 304. The source / drain regions 302 are disposed between isolation structures 502 extending from an upper surface of the substrate 102 to a point below the upper surface of the substrate 102. In some embodiments, the isolation structures 502 are configured as shallow trench isolation (STI) structures and include one or more dielectric materials (e.g., silicon dioxide). The access MOSFET 308 further includes a sidewall spacer structure 504 surrounding the gate electrode 306 and the gate dielectric 304. At least a portion of the sidewall spacer structure 504 overlies the source / drain regions 302.

[0145] The bonding structure 505 overlies the interconnect structure 303 and the access MOSFET 308. The bonding structure 505 includes a first passivation layer 510, a second passivation layer 512, a top dielectric structure 514, a bump structure 515, a redistribution layer 508, and a first redistribution via 506a and a second redistribution via 506b. The redistribution layer 508 is disposed in the second passivation layer 512. The first redistribution via 506a and the second redistribution via 506b are disposed in the first passivation layer 510 and extend from the redistribution layer 508 to the conductive line 312. In some embodiments, the redistribution layer 508 is electrically coupled to the MIMIM capacitor 200a. The bump structure 515 extends through the top dielectric structure 514 and contacts the redistribution layer 508. The bump structure 515 includes a bonding pad 516, a bonding bump 518, and a solder ball 520. The bump structure 515 is electrically coupled to the interconnect structure 303 via the redistribution layer 508. In some embodiments, the bump structure 515 is configured to electrically couple the IC 900 to another IC (not shown).

[0146] See also Fig.10 , provided by Fig. 9 The dashed box in the Fig. 9 A cross-sectional view 1000 of some alternative embodiments of a portion of IC 900 .

[0147] like Fig.10 , the MIMIM capacitor 200a is disposed within the first passivation layer 510 and directly below the redistribution layer 508. The redistribution layer 508 includes a conductor 508a surrounded by a conductive liner 508b. In some embodiments, the redistribution layer 508 has a protruding portion of the conductive line 312 extending through the first passivation layer 510 to the ILD layer 314. In some embodiments, the conductor 508a may be or include aluminum, copper, alloys of the foregoing, or the like, for example. In other embodiments, the conductive liner 508b may be or include tungsten or the like, for example.

[0148] Figures 11 to 16Cross-sectional views 1100 to 1600 illustrate some embodiments of methods of forming a metal-insulator-metal (MIM) capacitor having a diffusion barrier layer according to aspects of embodiments of the present invention. Figures 11 to 16 1100 to 1600, but it should be understood that Figures 11 to 16 The structure shown in is not limited to the method described but can actually be independent of the method described. Figures 11 to 16 Although described as a series of actions, it should be understood that these actions are not limited to changing the order of actions in other embodiments, and some actions shown and / or described may be omitted in whole or in part. In some embodiments, for example, Figures 11 to 16 form Figure 1B Some embodiments of the MIM capacitor 100b.

[0149] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a bottom electrode 104 is formed over the substrate 102. In some embodiments, the bottom electrode 104 may be, for example, or include titanium nitride, tantalum nitride, titanium, tantalum, tungsten, or the like. A capacitor dielectric layer 106 is formed over the bottom electrode 104. A first deposition process is performed to form a first top electrode layer 110 a over the capacitor dielectric layer 106. In some embodiments, the first top electrode layer 110 a may be a first material (e.g., titanium nitride (TiN)) and / or may have a thickness t in the range of about 100 angstroms to 200 angstroms. a In some embodiments, the first deposition process includes performing physical vapor deposition (PVD) so that the first top electrode layer 110a has a plurality of grains 114 (eg, Figure 1B 106). However, other deposition processes may also be applicable. For example, in some embodiments, the first top electrode layer 110a may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or some other suitable deposition process. The grains 114 may, for example, be columnar grains having grain boundaries extending from the top surface of the capacitor dielectric layer 106 to a point above the top surface of the capacitor dielectric layer 106. In some embodiments, the thickness t a is the maximum thickness of the first top electrode layer 110a. In some embodiments, the bottom electrode 104 and / or the capacitor dielectric layer 106 may be deposited by thermal oxidation, CVD, PVD, ALD, some other deposition process, or any combination of the foregoing.

[0150] like Fig.12As shown in the cross-sectional view 1200 of FIG. 1 , the diffusion barrier layer 112 is formed above the first top electrode layer 110a. In some embodiments, the diffusion barrier layer 112 may be, for example, or include a first material (e.g., TiN) and / or may have a thickness t in the range of about 10 angstroms to 15 angstroms. db In some embodiments, the thickness t db is the maximum thickness of the diffusion barrier layer 112. In some embodiments, the process for forming the diffusion barrier layer 112 includes: 1) performing a second deposition process to deposit the diffusion barrier layer 112; and 2) performing an annealing process on the diffusion barrier layer 112. In some embodiments, the annealing process may be increased from a minimum annealing temperature (e.g., about 250 degrees Celsius) to a maximum annealing temperature (e.g., about 400 degrees Celsius). In some embodiments, the second deposition process includes performing an ALD process such that the thickness t db The diffusion barrier layer 112 may be formed to be in the range of about 10 angstroms to 15 angstroms. However, other deposition processes may also be applicable. In some embodiments, the diffusion barrier layer 112 and the first top electrode layer 110a are deposited by different deposition processes. For example, in such embodiments, the diffusion barrier layer 112 is deposited by ALD and the first top electrode layer 110a is deposited by PVD. In other embodiments, the diffusion barrier layer 112 may be formed by CVD, PVD, or some other suitable deposition process.

[0151] In some embodiments, when the annealing process is performed, Fig.12The structure is exposed to a process substance (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.), wherein after performing an annealing process, the diffusion barrier layer 112 is rich in the process substance (e.g., N-rich). In some embodiments, during the annealing process, the process substance may be injected and / or absorbed into the diffusion barrier layer 112, wherein the diffusion barrier layer 112 is rich in the process substance (e.g., N-rich). In some embodiments, the diffusion barrier layer 112 includes a titanium to nitrogen ratio of approximately 1:1.02, 1:1.03, 1:1.04, or 1:1.05. For example, for every 100 titanium atoms, the diffusion barrier layer 112 may include 102 to 105 nitrogen atoms. In addition, nitrogen atoms have a smaller atomic radius than titanium atoms, wherein a layer having a greater number of nitrogen atoms than titanium atoms will have a shorter distance between adjacent atoms (i.e., a smaller grain size). Because the diffusion barrier layer 112 is N-rich (i.e., has a greater number of nitrogen atoms than titanium atoms), the distance between atoms in the diffusion barrier layer 112 is smaller than the distance between atoms in the first top electrode layer 110a. Therefore, the atoms in the diffusion barrier layer 112 are more densely packed together than the atoms in the first top electrode layer 110a, resulting in a smaller grain size for the diffusion barrier layer 112. In other embodiments, the atoms in the diffusion barrier layer 112 are so densely packed together that the diffusion species cannot travel between adjacent atoms in the diffusion barrier layer 112.

[0152] In other embodiments, the diffusion barrier layer 112 may be N-rich in the upper region 112a. Fig.12 The upper region 112a is defined by the dashed line in FIG. 1 to the top surface 112ts of the diffusion barrier layer 112. In some embodiments, after performing the annealing process and exposing the diffusion barrier layer 112 to the treatment substance, the diffusion barrier layer 112 has at least a portion of a crystalline structure that is different from the crystalline structure of the first top electrode layer 110a. For example, the diffusion barrier layer 112 has a plurality of grains that are non-columnar and smaller than the grains 114 of the first top electrode layer 110a. In some embodiments, the grains of the diffusion barrier layer 112 may be as follows: Figure 1B In other embodiments, the annealing process performed in the process material contributes to a partially crystalline structure of the diffusion barrier layer 112, so that the diffusion barrier layer 112 has grains with a grain size less than about 3 angstroms. In subsequent processing steps (e.g. Fig.15 and Fig.16During the patterning, removal and / or cleaning process of the diffusion barrier layer 112, the partially crystalline structure, non-columnar grain size and / or N-rich characteristics of the diffusion barrier layer 112 block and / or slow down the diffusion of diffusion species through the diffusion barrier layer 112. This is in part because the nitrogen atoms disposed in the diffusion barrier layer 112 reduce the distance between adjacent titanium and nitrogen atoms during the annealing process. Therefore, the diffusion species cannot travel between adjacent titanium and nitrogen atoms in the diffusion barrier layer 112. The diffusion species may be, for example, or include oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolate (DHF), or a combination of the foregoing.

[0153] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the second top electrode layer 110 b is formed over the diffusion barrier layer 112. In some embodiments, the second top electrode layer 110 b is formed by a third deposition process (e.g., a PVD process) such that the second top electrode layer 110 b includes the first material (e.g., TiN) and / or has a thickness t in the range of about 100 angstroms to 200 angstroms. b The second top electrode layer 110b has a plurality of crystal grains 116 (eg, Figure 1B ). In some embodiments, the third deposition process is the same as the first deposition process (e.g., a PVD process) and is different from the second deposition process (e.g., an ALD process). In other embodiments, the first deposition process, the second deposition process, and the third deposition process each include a PVD process. However, other deposition processes may also be applicable to the first deposition process, the second deposition process, and the third deposition process.

[0154] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a masking layer 1402 is formed over the second top electrode layer 110 b. In some embodiments, the masking layer 1402 may be or include, for example, a photoresist, a hard mask, or the like.

[0155] like Fig.15As shown in the cross-sectional view 1500 of FIG. 140 , a patterning process is performed on the first top electrode layer 110 a and the second top electrode layer 110 b, the diffusion barrier layer 112, and the capacitor dielectric layer 106, thereby defining the top electrode 108 and the metal-insulator-metal (MIM) capacitor 100 a. The top electrode 108 includes the first top electrode layer 110 a and the second top electrode layer 110 b and the diffusion barrier layer 112. The MIM capacitor 100 a includes the top electrode 108, the bottom electrode 104, and the capacitor dielectric layer 106. In some embodiments, the patterning process may include performing wet etching on the first top electrode layer 110 a and the second top electrode layer 110 b, the diffusion barrier layer 112, and the capacitor dielectric layer 106. The aforementioned layers may be exposed to one or more etchants according to the masking layer 1402. In some embodiments, the one or more etchants may be, for example, or include at least one of the diffusion substances (e.g., hydrogen peroxide (H2O2)).

[0156] In other embodiments, after performing the patterning process, the capacitor dielectric layer 106 has a thickness t defined in the central region 106cr of the capacitor dielectric layer 106. cr and a thickness t defined in the peripheral region 106pr of the capacitor dielectric layer 106 pr The top electrode 108 overlies the central region 106cr of the capacitor dielectric layer 106, such that the capacitor dielectric layer 106 has a thickness t between the top surface of the bottom electrode 104 and the bottom surface of the first top electrode layer 110a. cr The peripheral region 106pr surrounds the central region 106cr and is laterally offset from the top electrode 108. In some embodiments, the thickness t pr Less than thickness t cr Therefore, the capacitor dielectric layer 106 has two discontinuous thicknesses.

[0157] like Fig.16 As shown in the cross-sectional view 1600, Fig.15 The structure is subjected to a removal process to remove the masking layer ( Fig.15 1402). In some embodiments, the removal process includes performing wet etching and / or dry etching, such as wet ashing and / or dry ashing. The removal process may, for example, include removing the top electrode 108, the masking layer ( Fig.15 1402) and or the capacitor dielectric layer is exposed to at least one of the diffusion substances.

[0158] In some embodiments, after performing the removal process, a cleaning process may be performed on the top electrode 108 and the capacitor dielectric layer 106 to, for example, remove byproducts from the patterning process and / or the removal process. The cleaning process may include exposing the top electrode 108 and the capacitor dielectric layer 106 to at least one of a diffusion substance, such as H2O2 and / or dihydrofolate (DHF). During and / or after the patterning process, the cleaning process, and / or the removal process, the diffusion barrier layer 112 is configured to block diffusion of the diffusion substance to the central region 106cr of the capacitor dielectric layer 106, thereby preventing and / or slowing down the formation of voids in at least the central region 106cr of the capacitor dielectric layer 106. This prevents the MIM capacitor 100a from breaking down at a high operating voltage to some extent, thereby increasing the operating voltage, withstand capability, and reliability of the MIM capacitor 100a.

[0159] Fig.17 A method 1700 of forming a MIM capacitor with a diffusion barrier layer according to an embodiment of the present invention is shown. Although method 1700 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in a different order than shown, and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0160] At act 1702, a bottom electrode is formed over a substrate, and a capacitor dielectric layer is formed over the bottom electrode. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 1702 .

[0161] At act 1704, a first deposition process is performed to deposit a first top electrode layer over the capacitor dielectric layer. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of act 1704 .

[0162] At act 1706, a second deposition process is performed to deposit a diffusion barrier layer over the first top electrode layer. In some embodiments, the first deposition process (eg, a PVD process) is different from the second deposition process (eg, an ALD process). Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 1706 .

[0163] At act 1708, an annealing process is performed on the diffusion barrier layer. The diffusion barrier layer is exposed to a process substance (eg, nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) during the annealing process. Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 1708 .

[0164] At act 1710, a third deposition process is performed to deposit a second top electrode layer over the diffusion barrier layer. Fig.13 Cross-sectional view 1300 is shown corresponding to some embodiments of act 1710 .

[0165] At act 1712, a masking layer is formed over the second top electrode layer. Fig.14 Cross-sectional view 1400 is shown corresponding to some embodiments of act 1712 .

[0166] At act 1714, a patterning process is performed on the first and second top electrode layers, the diffusion barrier layer, and the capacitor dielectric layer, thereby defining a top electrode. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 1714 .

[0167] At act 1716, a removal process is performed to remove the masking layer. Fig.16 Cross-sectional view 1600 is shown corresponding to some embodiments of act 1716 .

[0168] At act 1718, a clean process is performed on the top electrode and capacitor dielectric layer. Fig.16 Cross-sectional view 1600 is shown corresponding to some embodiments of act 1718 .

[0169] Therefore, in some embodiments, the present invention relates to a MIM capacitor having a top electrode, a bottom electrode, and a capacitor dielectric layer disposed between the top electrode and the bottom electrode. The top electrode has a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer.

[0170] In some embodiments, the present application provides a metal-insulator-metal (MIM) capacitor, comprising: a bottom electrode overlying a substrate; a capacitor dielectric layer overlying the bottom electrode; and a top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer. In one embodiment of the present invention, the metal-insulator-metal capacitor, wherein the first top electrode layer, the second top electrode layer, and the diffusion barrier layer each comprise a metal nitride. In one embodiment of the present invention, the metal-insulator-metal capacitor, wherein the metal nitride of the diffusion barrier layer is nitrogen-rich. In one embodiment of the present invention, the metal-insulator-metal capacitor, wherein the first top electrode layer and the second top electrode layer each comprise a first material, in which most of the grains are columnar grains, wherein the diffusion barrier layer comprises a second material, in which the grains are smaller than the grains of the first material. In one embodiment of the present invention, the metal-insulator-metal capacitor, wherein the first material and the second material comprise titanium nitride. In one embodiment of the present invention, the above-mentioned metal-insulator-metal capacitor, wherein the bottom electrode includes titanium nitride, and the capacitor dielectric layer includes a high dielectric constant dielectric material. In one embodiment of the present invention, the above-mentioned metal-insulator-metal capacitor, wherein the maximum thickness of the diffusion barrier layer is at least times smaller than the maximum thickness of the first top electrode layer. In one embodiment of the present invention, the above-mentioned metal-insulator-metal capacitor, wherein the maximum thickness of the diffusion barrier layer is at least times smaller than the maximum thickness of the second top electrode layer. In one embodiment of the present invention, the above-mentioned metal-insulator-metal capacitor, wherein the thickness of the capacitor dielectric layer increases discontinuously from the outer sidewall of the bottom electrode to the sidewall of the top electrode. In one embodiment of the present invention, the above-mentioned metal-insulator-metal capacitor, wherein the capacitor dielectric layer includes a first zirconium oxide layer, a second zirconium oxide layer, and an aluminum oxide layer disposed between the first zirconium oxide layer and the second zirconium oxide layer.

[0171] In some embodiments, the present application provides an integrated chip, comprising: an interconnect structure overlying a substrate, wherein the interconnect structure comprises an alternating stack of conductive vias and conductive lines; a bottom electrode overlying at least one of the conductive lines; a capacitor dielectric layer overlying the bottom electrode; a top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises a first top electrode layer; and a second top electrode layer overlying the first top electrode layer, wherein the first top electrode layer and the second top electrode layer respectively have a first columnar grain and a second columnar grain, wherein the second columnar grain overlies the first columnar grain and has a sidewall laterally offset from the sidewall of the first columnar grain. In one embodiment of the present invention, the above-mentioned integrated chip further comprises: a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer. And wherein the first top electrode layer and the second top electrode layer comprise a metal nitride having a first ratio of nitrogen atoms to metal atoms, and wherein the diffusion barrier layer comprises a metal nitride having a second ratio of nitrogen atoms to metal atoms greater than the first ratio. In one embodiment of the present invention, the above-mentioned integrated chip, wherein the metal nitride comprises titanium nitride. In one embodiment of the present invention, the above-mentioned integrated chip further comprises: an intermediate electrode, overlying the capacitor dielectric layer. And an upper capacitor dielectric layer, disposed between the top electrode and the intermediate electrode. In one embodiment of the present invention, the above-mentioned integrated chip, wherein the intermediate electrode comprises a first intermediate electrode layer, a second intermediate electrode layer, and an intermediate electrode diffusion barrier layer disposed between the first intermediate electrode layer and the second intermediate electrode layer, and wherein the first intermediate electrode layer and the second intermediate electrode layer respectively comprise the metal nitride having the first ratio, and the intermediate electrode diffusion barrier layer comprises the metal nitride having the second ratio. In one embodiment of the present invention, the above-mentioned integrated chip, wherein the top electrode comprises a first lateral segment overlying the top surface of the intermediate electrode and a second lateral segment vertically offset from the first lateral segment, wherein the bottom surface of the first lateral segment extends along the top surface of the intermediate electrode, and the bottom surface of the second lateral segment is disposed below the top surface of the intermediate electrode.

[0172] In some embodiments, the present application provides a method for forming a metal-insulator-metal (MIM) capacitor, the method comprising: forming a bottom electrode above a substrate; forming a capacitor dielectric layer above the bottom electrode; depositing a first top electrode layer above the capacitor dielectric layer; depositing a diffusion barrier layer above the first top electrode layer; performing an annealing process on the diffusion barrier layer, wherein after the annealing process, the diffusion barrier layer is rich in a treatment substance; and depositing a second top electrode layer above the diffusion barrier layer. In one embodiment of the present invention, the above method for forming a metal-insulator-metal capacitor, wherein the first top electrode layer and the second top electrode layer are respectively deposited by a physical vapor deposition process, and the diffusion barrier layer is deposited by an atomic layer deposition process. In one embodiment of the present invention, the above method for forming a metal-insulator-metal capacitor, wherein during the annealing process, the diffusion barrier layer is exposed to a treatment substance. In one embodiment of the present invention, the above method for forming a metal-insulator-metal capacitor, wherein the treatment substance includes nitrogen and the diffusion barrier layer is nitrogen-rich.

[0173] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and those skilled in the art can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A metal-insulator-metal capacitor, comprising: a bottom electrode overlying the substrate; a capacitor dielectric layer overlying the bottom electrode; as well as A top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first top electrode layer and the second top electrode layer, wherein the diffusion barrier layer has a thickness in a range of 10 angstroms to 15 angstroms. 2 . The metal-insulator-metal capacitor of claim 1 , wherein the first and second top electrode layers and the diffusion barrier layer each comprise a metal nitride.

3. The metal-insulator-metal capacitor of claim 2, wherein the metal nitride of the diffusion barrier layer is nitrogen-rich.

4. The metal-insulator-metal capacitor of claim 1 , wherein the first top electrode layer and the second top electrode layer each comprise a first material in which a majority of grains are columnar grains, wherein the diffusion barrier layer comprises a second material in which grains are smaller than the grains of the first material. 5 . The metal-insulator-metal capacitor of claim 4 , wherein the first material and the second material comprise titanium nitride.

6. The metal-insulator-metal capacitor of claim 5, wherein the bottom electrode comprises titanium nitride and the capacitor dielectric layer comprises a high-k dielectric material. 7 . The metal-insulator-metal capacitor of claim 1 , wherein a maximum thickness of the diffusion barrier layer is at least 10 times smaller than a maximum thickness of the first top electrode layer. 8 . The metal-insulator-metal capacitor of claim 7 , wherein the maximum thickness of the diffusion barrier layer is at least 10 times smaller than the maximum thickness of the second top electrode layer.

9. The metal-insulator-metal capacitor of claim 1, wherein a thickness of the capacitor dielectric layer increases discontinuously from an outer sidewall of the bottom electrode to a sidewall of the top electrode.

10. The metal-insulator-metal capacitor of claim 1, wherein the capacitor dielectric layer comprises a first zirconium oxide layer, a second zirconium oxide layer, and an aluminum oxide layer disposed between the first zirconium oxide layer and the second zirconium oxide layer.

11. An integrated chip, comprising: an internal connection structure overlying the substrate, wherein the internal connection structure comprises an alternating stack of conductive vias and conductive lines; a bottom electrode overlying at least one of the conductive lines; a capacitor dielectric layer overlying the bottom electrode; A top electrode overlying the capacitor dielectric layer, wherein the top electrode comprises: a first top electrode layer; a second top electrode layer overlying the first top electrode layer, wherein the first top electrode layer and the second top electrode layer have first columnar grains and second columnar grains, respectively, wherein the second columnar grains overlying the first columnar grains and having sidewalls laterally offset from sidewalls of the first columnar grains; and A diffusion barrier layer is disposed between the first top electrode layer and the second top electrode layer, wherein a thickness of the diffusion barrier layer is in a range of 10 angstroms to 15 angstroms.

12. The integrated chip according to claim 11, Wherein the first top electrode layer and the second top electrode layer include a metal nitride having a first ratio of nitrogen atoms to metal atoms, and wherein the diffusion barrier layer includes a metal nitride having a second ratio of nitrogen atoms to metal atoms greater than the first ratio.

13. The integrated chip of claim 12, wherein the metal nitride comprises titanium nitride.

14. The integrated chip according to claim 12, further comprising: an intermediate electrode, covering the capacitor dielectric layer; as well as An upper capacitor dielectric layer is disposed between the top electrode and the middle electrode.

15. An integrated chip according to claim 14, wherein the intermediate electrode includes a first intermediate electrode layer, a second intermediate electrode layer, and an intermediate electrode diffusion barrier layer disposed between the first intermediate electrode layer and the second intermediate electrode layer, and wherein the first intermediate electrode layer and the second intermediate electrode layer respectively include the metal nitride having the first ratio, and the intermediate electrode diffusion barrier layer includes the metal nitride having the second ratio.

16. An integrated chip according to claim 15, wherein the top electrode includes a first lateral segment overlying the top surface of the middle electrode and a second lateral segment vertically offset from the first lateral segment, wherein the bottom surface of the first lateral segment extends along the top surface of the middle electrode, and the bottom surface of the second lateral segment is disposed below the top surface of the middle electrode.

17. A method for forming a metal-insulator-metal capacitor, the method comprising: forming a bottom electrode over the substrate; forming a capacitor dielectric layer over the bottom electrode; depositing a first top electrode layer over the capacitor dielectric layer; depositing a diffusion barrier layer over the first top electrode layer; performing an annealing process on the diffusion barrier layer, wherein after the annealing process, the diffusion barrier layer is enriched with a treatment substance; as well as A second top electrode layer is deposited over the diffusion barrier layer, wherein the diffusion barrier layer has a thickness in a range of 10 angstroms to 15 angstroms.

18. The method for forming a metal-insulator-metal capacitor of claim 17, wherein the first top electrode layer and the second top electrode layer are each deposited by a physical vapor deposition process, and the diffusion barrier layer is deposited by an atomic layer deposition process.

19. The method for forming a metal-insulator-metal capacitor of claim 17, wherein during the annealing process, the diffusion barrier layer is exposed to a treatment substance.

20. The method for forming a metal-insulator-metal capacitor of claim 19, wherein said process substance comprises nitrogen and said diffusion barrier layer is nitrogen rich.

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