Integrated circuit and its stack and its manufacturing method

Abstract

The present disclosure relates to a three-dimensional integrated circuit stack and a method for manufacturing the same, wherein the three-dimensional integrated circuit stack includes a first integrated circuit die having a first substrate and a first internal connection structure above the front side of the first substrate; a second integrated circuit die having a second substrate and a second internal connection structure above the front side of the second substrate; and a third integrated circuit die vertically between the first integrated circuit die and the second integrated circuit die and having a third substrate, a third internal connection structure above the front side of the third substrate, and a third bonding structure above the back side of the third substrate. A heat dissipation path extends from the third substrate to at least the first substrate or the second substrate and includes a backside contact, the backside contact extends from the third bonding structure to the back side of the third substrate and is thermally coupled to at least the first internal connection structure or the second internal connection structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit and its stack and its manufacturing method, and more particularly to a backside contact for heat displacement in a multi-chip stacked integrated circuit and its manufacturing method. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by, for example, reducing the minimum feature size to allow more components to be integrated into a given area. Smaller packaging structures are developed to package semiconductor devices using less area or less height. For example, in order to further increase the circuit density per unit area, three-dimensional (3D) integrated circuits (ICs) have been studied. Summary of the invention

[0003] In some embodiments, a three-dimensional integrated circuit stack includes: a first IC die including a first semiconductor substrate, a first interconnect structure arranged on a front side of the first semiconductor substrate, and a first bonding structure arranged above the first interconnect structure; a second IC die including a second semiconductor substrate, a second interconnect structure arranged on a front side of the second semiconductor substrate, and a bonding structure arranged on the second interconnect structure, wherein the second bonding structure faces the first bonding structure; a third IC die including a third semiconductor substrate, a third interconnect structure arranged on a front side of the third semiconductor substrate, and a third bonding structure arranged on a back side of the third semiconductor substrate, wherein the third IC die is vertically arranged between the first IC die and the second IC die; and a heat dissipation path extending from the third semiconductor substrate to at least one of the first semiconductor substrate or the second semiconductor substrate, the heat dissipation path including a first backside contact extending from the third bonding structure, the first backside contact extending to a back side of the third semiconductor substrate, wherein the first backside contact is thermally coupled to at least one of the first interconnect structure or the second interconnect structure.

[0004] In some embodiments, an integrated circuit die includes: a semiconductor substrate; a semiconductor device integrated on the front side of the semiconductor substrate; an internal wiring structure arranged on the front side of the semiconductor substrate, coupled to the semiconductor device and including an internal wiring via and an internal wiring line embedded in a dielectric layer; a first bonding structure arranged above the internal wiring structure; a second bonding structure arranged on the back side of the semiconductor substrate and including a bonding wire and a bonding via in the bonding dielectric structure; and a back side contact arranged in the second bonding structure, wherein a top surface of the back side contact is thermally coupled to the back side of the semiconductor substrate, wherein the top surface of the back side contact is spaced apart from the front side of the semiconductor substrate by the semiconductor substrate, and wherein the back side contact is thermally and electrically coupled to the second bonding structure.

[0005] In some embodiments, a method for forming an integrated circuit includes: forming a semiconductor device on the front side of a semiconductor substrate; forming an interconnect structure above the semiconductor device; forming a first bonding structure above the interconnect structure; depositing a second dielectric layer above the back side of the semiconductor substrate; patterning the second dielectric layer to form a first opening in the second dielectric layer, wherein the first opening exposes a surface of the back side of the semiconductor substrate, wherein when the back side of the semiconductor substrate is located above the front side of the semiconductor substrate, the surface of the back side of the semiconductor substrate is located above the semiconductor device; depositing a colloidal layer having a first thickness above the first opening; filling the first opening with a first material to form a backside contact, wherein the backside contact is separated from the semiconductor substrate by the colloidal layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers above the second dielectric layer to form a second bonding structure above the back side of the semiconductor substrate, wherein the backside contact is coupled to the bonding contacts and the bonding wire layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B as well as Figure 1C Cross-sectional views of some embodiments of three-dimensional (3D) integrated circuit (IC) stacks including backside contacts in dies of the three-dimensional integrated circuit stack are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of a 3DIC stack including front-to-back bonded third and fourth IC dies with two backside contacts are shown.

[0009] Figure 3 Cross-sectional views of some additional embodiments of a 3DIC stack including front-to-back bonded third and fourth IC dies with three backside contacts are shown.

[0010] Figure 4 Cross-sectional views of some additional embodiments of a 3D IC stack including back-to-back bonding a third IC die and a fourth IC die with backside contacts are shown.

[0011] Figures 5 to 20 A cross-sectional view of some embodiments of a method of forming a 3D IC stack is shown, wherein a third IC die includes backside contacts coupled to a substrate through-via.

[0012] Fig.21 Shown with Figures 5 to 20 Flowcharts of some embodiments of the corresponding methods.

[0013] Description of Figure Numbers

[0014] 100A, 100B, 100C, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100: cross-sectional views;

[0015] 102: first IC die;

[0016] 104: a third IC die;

[0017] 106: second IC die;

[0018] 108: semiconductor substrate;

[0019] 108a: a first substrate;

[0020] 108b: a second substrate;

[0021] 108c: a third substrate;

[0022] 108d: fourth substrate;

[0023] 108f: front side;

[0024] 108s: dorsal;

[0025] 110: Semiconductor devices;

[0026] 110a: a first semiconductor device;

[0027] 110b: a second semiconductor device;

[0028] 110c: a third semiconductor device;

[0029] 1102: a first etching stop layer;

[0030] 1104: a second dielectric layer;

[0031] 112: Internal connection structure;

[0032] 112a: a first internal connection structure;

[0033] 112b: a second internal connection structure;

[0034] 112c: third inner connection structure;

[0035] 114: internal connection line;

[0036] 116: Internal connection perforation;

[0037] 118: Inner connection dielectric structure;

[0038] 120: Joint structure;

[0039] 120a: first bonding structure;

[0040] 120b: second engagement structure;

[0041] 120c: third bonding structure;

[0042] 122: bonding wire layer;

[0043] 123: joint perforation;

[0044] 124: bonding dielectric structure;

[0045] 126: Joint structure;

[0046] 128: Through substrate via (TSV);

[0047] 129: chemical isolation layer;

[0048] 1202: Second opening;

[0049] 130: pad;

[0050] 131: colloid layer;

[0051] 132: back contact;

[0052] 132t: topmost surface;

[0053] 134: heat dissipation path;

[0054] 1302: Second conductive material

[0055] 1304: conformal colloidal layer;

[0056] 1502: first etching stop layer;

[0057] 1504: a third dielectric layer;

[0058] 160: doping well region;

[0059] 162: gate dielectric layer;

[0060] 1602: The third opening;

[0061] 164: gate electrode;

[0062] 166: source / drain region;

[0063] 1702: Fourth opening;

[0064] 1802: Dorsal internal connection structure;

[0065] 204: fourth IC die;

[0066] 2004: Joining technology;

[0067] 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116: operation;

[0068] 210: front to back interface;

[0069] 220: front-to-front interface;

[0070] 310: internal connection line level;

[0071] 410: back-to-back interface;

[0072] 602: a first dielectric layer;

[0073] 702: First opening;

[0074] 802: electrical insulation layer;

[0075] B: Cube;

[0076] d1: first distance;

[0077] t1: first thickness;

[0078] t2: second thickness;

[0079] t3: third thickness. DETAILED DESCRIPTION

[0080] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed or arranged in direct contact, and may also include an embodiment in which an additional feature may be formed or arranged between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0081] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like are used herein for ease of description to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0082] A three-dimensional (3D) integrated circuit (IC) may include a third IC die stacked vertically between a first IC die and a second IC die. The first IC die, the second IC die, and the third IC die may each include a semiconductor substrate, a semiconductor device integrated on the semiconductor substrate, and an internal wiring structure including alternately stacked wiring layers and perforations embedded in a dielectric structure. The third IC die may be bonded to the first IC die and the second IC die through a bonding structure. The bonding structure may include a bonding wire layer and a bonding contact embedded in a bonding dielectric layer. In addition, the third IC die may include a through substrate via (TSV), which is electrically coupled to the first IC die, the second IC die, and the third IC die. The TSV may have a sidewall liner that electrically insulates the TSV from the semiconductor device of the third IC die. The sidewall liner typically includes a dielectric material, such as an oxide (e.g., silicon dioxide) or a nitride (e.g., silicon nitride).

[0083] Thus, the semiconductor substrate of the third IC die may be surrounded by and in direct contact with the dielectric material that is an electrical insulator. The semiconductor device of the third IC die may generate heat during operation in the semiconductor substrate, which may damage the semiconductor device due to inefficient heat dissipation of the surrounding dielectric material in the third IC die. Furthermore, if the 3D IC includes more than three IC dies with similar or identical designs (e.g., size / location of semiconductor devices, interconnect structures, etc.), the heat build-up in the semiconductor substrate of the multiple IC dies between the first IC die and the second IC die may be larger and therefore more destructive than heat build-up in a 3D IC with one IC die between the first IC die and the second IC die.

[0084] Various embodiments of the present disclosure present a 3D IC including a third IC die stacked vertically between a first IC die and a second IC die. The third IC die includes a semiconductor device integrated on the front side of a third semiconductor substrate. The third IC die may also include a backside contact on the back side of the third semiconductor substrate, but spaced apart from the active area of ​​the semiconductor device to avoid electrical interference. The backside contact includes a material with high thermal conductivity, which is coupled to bonding wires and internal connections in the 3D IC. The colloid layer can separate the backside contact from the third semiconductor substrate without direct contact. The colloid layer is thinner than the sidewall liner of the TSV. Therefore, during the operation of the semiconductor device in the third semiconductor substrate, the heat generated can be dissipated through the backside contact faster than the TSV, and the heat generated is propagated through the internal connection and dissipated through the semiconductor substrate of the first IC die and / or the second IC die, thereby preventing heat accumulation and ultimately the performance degradation of the 3D IC.

[0085] Figure 1A A cross-sectional view 100A of some embodiments of a three-dimensional (3D) integrated circuit (IC) including backside contacts is shown.

[0086] The 3D IC stack of cross-sectional view 100A includes a first IC die 102, a third IC die 104 disposed over and coupled to the first IC die 102, and a second IC die 106 disposed over and coupled to the third IC die 104. Each of the first IC die 102, the third IC die 104, and the second IC die 106 includes a semiconductor substrate, a semiconductor device (e.g., a transistor, a capacitor, a diode, etc.) on a front side of the semiconductor substrate, an interconnect structure disposed over the front side of the semiconductor substrate, and a semiconductor device and a bonding structure disposed over the interconnect structure and the front side of the semiconductor substrate. For example, the first IC die 102 includes a first substrate 108a, a first semiconductor device 110a, a first interconnect structure 112a, and a first bonding structure 120a; the second IC die 106 includes a second substrate 108b, a second semiconductor device 110b, a second interconnect structure 112b, and a second bonding structure 120b; and the third IC die 104 includes a third substrate 108c, a third semiconductor device 110c, a third interconnect structure 112c, and a third bonding structure 120c. Each interconnect structure (e.g., interconnect structure 112a, interconnect structure 112b, interconnect structure 112c) may include a network of interconnect lines 114 and interconnect vias 116 surrounded by an interconnect dielectric structure 118. The network of interconnect lines 114 and the interconnect vias 116 of the first interconnect structure 112a, the second interconnect structure 112b, and the third interconnect structure 112c are electrically connected to the first semiconductor device 110a, the second semiconductor device 110b, and the third semiconductor device 110c, respectively. In some embodiments, each of the first bonding structure 120a, the second bonding structure 120b, and the third bonding structure 120c may include a bonding via 123 and a bonding wire layer 122 embedded in a bonding dielectric structure 124. In some embodiments, the bonding structure (e.g., the bonding structure 120a, the bonding structure 120b, and the bonding structure 120c) may be, for example, a hybrid bond (HB) structure. In some embodiments, the second bonding structure 120b is bonded to the third bonding structure 120c, and the first bonding structure 120a is bonded to another bonding structure 126 of the third IC die 104.

[0087] For example, in an embodiment, the additional bonding structure 126 of the third IC die 104 may also be a hybrid bonding (HB) structure. In some embodiments, the additional bonding structure 126 may include a bonding through-hole 123, a bonding wire layer 122, an inner wiring through-hole 116, and / or an inner wiring line 114 embedded in a bonding dielectric structure 124. The additional bonding structure 126 is disposed on the back side 108s of the third substrate 108c of the third IC die 104. A through substrate via (TSV) 128 extends from the back side 108s of the third substrate 108c to the front side 108f. The TSV 128 may be electrically connected to the conductive components (e.g., inner wiring line 114, inner wiring through-hole 116, bonding wire layer 122, bonding through-hole 123) of the third inner wiring structure 112c and the additional bonding structure 126. Thus, the TSV 128 may include a conductive first material, and thus may electrically connect the vertically stacked first IC die 102, the third IC die 104, and the second IC die 106. In some embodiments, the TSV 128 includes a TSV liner 130 surrounding the sidewalls of the TSV 128. In some embodiments, the TSV liner 130 includes a dielectric material (e.g., silicon nitride, silicon dioxide) to prevent the TSV 128 from electrically leaking into the third substrate 108c and approaching the third semiconductor device 110c. In some embodiments, the uppermost and lowermost surfaces of the TSV 128 are exposed by the TSV liner 130 to allow electrical signals to propagate through the TSV 128 from the lowermost surface to the uppermost surface, and thus the TSV 128 is electrically connected to at least the first and third interconnect structures 112a and 112c. In addition, the TSV 128 may be in direct contact with the chemical isolation layer 129 to prevent the TSV 128 from chemically leaking (e.g., diffusing) in the third substrate 108c. In some embodiments, the chemical isolation layer 129 may include, for example, tantalum nitride.

[0088] In some embodiments, the additional bonding structure 126 may further include a backside contact 132. The backside contact 132 extends from the internal connection line 114 of the additional bonding structure 126 toward the back side 108s of the third substrate 108c. In some embodiments, the backside contact 132 extends into the back side 108s of the third substrate 108c. The backside contact 132 may be surrounded by a colloid layer 131 to facilitate adhesion between the backside contact 132 and the third substrate 108c. In some embodiments, the colloid layer 131 may include, for example, titanium or titanium nitride. The colloid layer 131 is thinner than the TSV liner 130 and the chemical isolation layer 129. The backside contact 132 is spaced apart from the active area of ​​the third semiconductor device 110c to avoid electrical interference with the third semiconductor device 110c. In some embodiments, the backside contacts 132 may not use an electrically isolating barrier layer because, for example, the area of ​​the backside contacts 132 contacting the third substrate 108 c is small compared to the contact area of ​​the TSV 128 .

[0089] It should be understood that during operation of the third semiconductor device 110c, heat may be generated. Therefore, in some embodiments, the heat dissipation path 134 may include a backside contact 132 disposed near the third semiconductor device 110c to allow any heat within the third substrate 108c to dissipate from the third semiconductor device 110c and dissipate outside the third substrate 108c. The heat may then continue to leave the third substrate 108c through different heat dissipation paths 134 and dissipate from the 3D IC stack through the backside 108s of at least one of the first substrate 108a or the second substrate 108b. Because the colloid layer 131 is thinner than the TSV liner 130 and the chemical isolation layer 129, the heat will be dissipated more quickly in the backside contact 132 than in the TSV 128. Therefore, the heat dissipation path 134 is more efficient than the TSV dissipation path (not shown) when the heat generated through the TSV liner 130 and the chemical isolation layer 129 from the third substrate 108c is dissipated. Therefore, the backside contacts 132 may provide a more efficient heat dissipation path 134 to reduce thermal degradation to the 3D IC stack, thereby increasing the life of the 3D IC stack.

[0090] Figure 1B Shown with Figure 1A Block B in the cross-sectional view 100A corresponds to the cross-sectional view 100B of some embodiments to highlight the components of the backside contact 132 .

[0091] In some embodiments, the semiconductor device 110 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET). In such embodiments, the third semiconductor device 110c may include a doped well region 160 in the third substrate 108c, wherein the doped well region 160 is more heavily doped and / or has a different doping type than the third substrate 108c. A source / drain region 166 may be present in the doped well region 160, and a gate electrode 164 may be disposed on the front side 108f of the third substrate 108c above the gate dielectric layer 162. The backside contact 132 has a topmost surface 132t, which may be defined as the topmost surface of the colloidal layer 131, and the topmost surface of the colloidal layer 131 is spaced apart from the third semiconductor device 110c, so that the backside contact 132 does not electrically interfere with the third semiconductor device 110c. Therefore, in some embodiments, the colloidal layer 131 and the backside contact 132 contact an area of ​​the third substrate 108c that has a different doping concentration and / or a different doping type than an active area of ​​the third semiconductor device 110c (e.g., the doped well region 160, the source / drain region 166). In some embodiments, the topmost surface 132t of the backside contact 132 extends a first distance d1 into the back side 108s of the third substrate 108c.

[0092] In some embodiments, the TSV liner 130 may have a first thickness t1 in the range of about 200 angstroms and about 2000 angstroms, and the chemical isolation layer 129 may have a second thickness t2 in the range of, for example, about 50 angstroms and about 500 angstroms. In some embodiments, the colloid layer 131 may have a third thickness t3 in the range of, for example, about 20 angstroms and about 300 angstroms. In some embodiments, the first thickness t1 is greater than the third thickness t3. In addition, in some embodiments, the third thickness t3 is at least less than the sum of the first thickness t1 and the second thickness t2.

[0093] Figure 1C Show that it can be Figure 1B The cross-sectional view 100B corresponds to the cross-sectional view 100C and further includes some embodiments of heat dissipation paths 134 between the third semiconductor device 110 c , the backside contacts 132 , and the TSV 128 .

[0094] In some embodiments, the TSV 128 and the backside contact 132 have a material with a higher thermal conductivity than the material of the TSV liner 130, the chemical isolation layer 129, and the colloid layer 131. Therefore, the heat can be dissipated from the third semiconductor device 110c as soon as it reaches the backside contact 132 or the TSV 128. Because the colloid layer 131 is thinner than the TSV liner 130 and the chemical isolation layer 129, any heat generated from the third semiconductor device 110c can be dissipated more efficiently through the backside contact 132 than through the TSV 128 to the third substrate 108c. Therefore, in some embodiments, the backside contact 132 is in direct contact and thermally coupled with one of the interconnects 114 to continuously dissipate heat, so that a heat dissipation path 134 for heat dissipation passes through the backside contact 132 and continuously passes through other thermally conductive materials (e.g., the interconnects 114, the interconnect vias 116, the TSV 128, the bonding vias 123, etc.) to dissipate heat from the third semiconductor device 110c during operation. Therefore, some heat can be dissipated from the third substrate 108c via the TSV liner 130 and the chemical isolation layer 129, however, because the thickness of the colloid layer 131 is less than the thickness of the TSV liner 130 and the chemical isolation layer 129, more heat will be dissipated from the third substrate 108c and through the colloid layer 131 and the backside contact 132.

[0095] Figure 2 A cross-sectional view 200 of some embodiments of a 3D IC stack including a third IC die and a fourth IC die with front-to-back bonding is shown.

[0096] The 3D IC stack in the cross-sectional view 200 includes a first IC die 102, a third IC die 104 disposed over and bonded to the first IC die 102, a fourth IC die 204 disposed over and bonded to the third IC die 104, and a second IC die 106 disposed over and bonded to the fourth IC die 204. In some embodiments, the fourth IC die 204, like the third IC die 104, includes a fourth additional bonding structure 226. The fourth additional bonding structure 226 may be disposed on the back side 108s of the fourth substrate 108d of the fourth IC die 204. In some embodiments, the fourth additional bonding structure 226 of the fourth IC die 204 can be bonded to the third bonding structure 120c at the front-to-back interface 210, representing that the front side 108f of the third substrate 108c of the third IC die 104 faces the back side 108s of the fourth substrate 108d. In addition, the second bonding structure 120b can be bonded to the fourth bonding structure 120d at the front-to-front interface 220, representing that the front side 108f of the second substrate 108b faces the front side 208f of the fourth substrate 108d.

[0097] It should be understood that some embodiments of the 3D IC stack include the third IC die 104 and the fourth IC die 204 bonded to each other with different interface types (e.g., front-to-front, front-to-back). However, in some embodiments, each of the third IC die 104 and the fourth IC die 204 may include a backside contact 132 to provide access to a heat dissipation path 134 that effectively dissipates any heat generated by the semiconductor device (e.g., semiconductor device 110c, semiconductor device 110d) away from the semiconductor device (e.g., semiconductor device 110c, semiconductor device 110d). In some embodiments, the backside contact 132 may be coupled to the TSV 128, so the heat dissipation path 134 passes through the TSV 128. In some embodiments, without passing through the TSV 128, the heat dissipation path 134 may be shorter and more efficient, as shown between the third substrate 108c and the first substrate 108a.

[0098] In some embodiments, the third substrate 108c and the fourth substrate 108d may include two TSVs 128 and two backside contacts 132. However, it should be understood that the number of TSVs 128 may depend on the design of the 3D IC stack and the number of backside contacts 132 may depend on the amount of heat generated by the semiconductor device (e.g., semiconductor device 110c, semiconductor device 110d) during operation and / or other design requirements (e.g., the number of TSVs, the width of the substrate, the size of the semiconductor device, etc.). Therefore, the number of TSVs 128 and the number of backside contacts 132 may vary depending on the design of the 3D IC stack. Figure 2 In addition, in some embodiments, as shown in the cross-sectional view 200. Figure 2 As depicted in the cross-sectional view 200 of FIG. 1 , each IC die (IC die 102, IC die 104, IC die 204, IC die 106) may have the same or nearly the same IC design with respect to the location of semiconductor devices (semiconductor devices 110a, semiconductor devices 110b, semiconductor devices 110c, semiconductor devices 110d), interconnect structures (interconnect structures 112a, interconnect structures 112b, interconnect structures 112c, interconnect structures 112d), and bonding structures (bonding structures 120a, bonding structures 120b, bonding structures 120c, bonding structures 120d). In such an embodiment, heat may accumulate even faster when the IC dies (IC die 102, IC die 104, IC die 204, IC die 106) are vertically stacked. Thus, for example, in embodiments where the IC die (IC die 102, IC die 104, IC die 204, IC die 106) have the same or approximately the same die design as an IC die having a different IC design, the 3D IC stack may include more backside contacts 132. Additionally, depending on the IC die design, in some embodiments, each of the third IC die 104 and the fourth IC die 204 may include the same or different number of backside contacts 132. However, the backside contacts 132 in the 3D IC stack may provide access to the heat dissipation paths 134 for efficient heat dissipation away from at least the third semiconductor device 110c and the fourth semiconductor device 110d.

[0099] Figure 3 Some further embodiments of a 3D IC stack including a third IC die and a fourth IC die with front-to-back bonding are shown in a cross-sectional view 300 , wherein each of the third substrate 108 c and the fourth substrate 108 d includes three backside contacts 132 and one TSV 128 .

[0100] In some embodiments, the backside contacts 132 in the third and fourth bonding structures 120c and 120d are coupled to the interconnect wires 114 at the same interconnect wire level 310 of the third and fourth bonding structures 120c and 120d. Although the interconnect wires 114 at the interconnect wire level 310 are not continuously connected in the cross-sectional view 300, it should be understood that each of the interconnect wires 114 at the interconnect wire level 310 of the third and fourth bonding structures 120c and 120d is electrically connected through other portions of the interconnect wire 114 that are not visible in the cross-sectional view 300 due to the wiring design. In other embodiments, the interconnect wires 114 at each of the interconnect wire levels 310 in the third and fourth bonding structures 120c and 120d may be continuously connected in the cross-sectional view 300. By coupling the backside contact 132 to the interconnect line 114 at the interconnect line level 310, any heat in the third substrate 108c and the fourth substrate 108d can be dissipated from the third semiconductor device 110c and the fourth semiconductor device 110d and pass through at least one of the first interconnect structure 112a, the second interconnect structure 112b, the third interconnect structure 112c, or the fourth interconnect structure 112d.

[0101] Figure 4 A cross-sectional view 400 of some embodiments of a 3D IC stack including a third IC die and a fourth IC die with back-to-back bonding is shown.

[0102] In some embodiments, the further bonding structures 126 of the third IC die 104 may be bonded to the fourth further bonding structures 226 of the fourth IC die 204 along a back-to-back interface 410 , representing the back side 108s of the third substrate 108c facing the back side 108s of the fourth substrate 108d .

[0103] Figures 5 to 20 Cross-sectional views 500 through 2000 illustrate some embodiments of a method of forming an integrated circuit (IC) die having backside contacts coupled to substrate vias. Figures 5 to 20 , but it should be understood that Figures 5 to 20 The structures disclosed in are not limited to the method, but instead can stand alone as structures independent of the method.

[0104] like Figure 5, a semiconductor substrate 108 is provided. In some embodiments, the semiconductor substrate 108 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.) such as a semiconductor chip or one or more dies on a chip, and any other type of semiconductor and / or epitaxial layer formed thereon and / or associated therewith. In some embodiments, the thickness of the semiconductor substrate 108 may be, for example, between about 2.4 microns and about 3 microns. The semiconductor device 110 may be deposited on the front side 108f of the semiconductor substrate 108. In some embodiments, the semiconductor device 110 may be, for example, a transistor, a capacitor, a resistor, or the like. An internal wiring structure 112 may be deposited above the semiconductor device 110 and above the front side 108f of the semiconductor substrate 108, the internal wiring structure 112 including an internal wiring through hole 116 and an internal wiring line 114 embedded in an internal wiring dielectric structure 118. In some embodiments, the thickness of the internal wiring structure 112 may be, for example, between about 5 microns and about 8 microns.

[0105] In some embodiments, the interconnect vias 116 and the interconnect lines 114 include the same material that is capable of conducting electricity. For example, in some embodiments, the interconnect vias 116 and the interconnect lines 114 include copper. Because copper is known to chemically diffuse into the surrounding interconnect dielectric structure 118, a thin barrier layer can separate each of the interconnect vias 116 and the interconnect lines 114 from the interconnect dielectric structure 118. For example, in some embodiments, the thin barrier layer can include tantalum nitride to chemically separate (e.g., prevent diffusion) the interconnect vias 116 and the interconnect lines 114 in the interconnect dielectric structure 118. In other embodiments, the interconnect vias 116 and the interconnect lines 114 can include other conductive materials such as tungsten, aluminum, or the like. In some embodiments, the interconnect dielectric structure 118 may include a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), or the like. In addition, a bonding structure 120 may be formed over the interconnect structure 112. In some embodiments, the bonding structure 120 may include a bonding through-hole 123 and a bonding wire layer 122 embedded in the bonding dielectric structure 124. In some embodiments, the bonding through-hole 123, the bonding wire layer 122, and the bonding dielectric structure 124 include the same materials as the interconnect through-hole 116, the interconnect line 114, and the interconnect dielectric structure 118, respectively. In some embodiments, the interconnect line 114 may be coupled to the bonding through-hole 123. In some embodiments, the thickness of the bonding structure 120 can range between, for example, about 1.5 microns and about 2 microns.

[0106] like Figure 6As shown in the cross-sectional view 600 of FIG. 1 , the semiconductor substrate 108 is flipped so that the back side 108s of the semiconductor substrate 108 can be processed. A first dielectric layer 602 can be deposited on the back side 108s of the semiconductor substrate 108. The first dielectric layer 602 can include a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), or the like. In some embodiments, the first dielectric layer 602 can include the same material as the bonding dielectric structure 124. The first dielectric layer 602 can be formed by a vapor deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.).

[0107] like Figure 7 As shown in cross-sectional view 700 of , a first opening 702 is formed and extends completely through the first dielectric layer 602 and the semiconductor substrate 108. The first opening 702 can be formed by a selective patterning process based on a mask layer (not shown) formed above the first dielectric layer 602. For example, in some embodiments, the mask layer may include a photosensitive material (e.g., a photoresist) formed by a spin coating process. In such embodiments, the photosensitive material layer is selectively exposed to electromagnetic radiation based on a photomask. The electromagnetic radiation modifies the solubility of the exposed area within the photosensitive material to define a soluble region. The photosensitive material is then developed to define an opening in the photosensitive material by removing the soluble region. In other embodiments, the mask layer may include a hard mask layer (e.g., a silicon nitride layer, a silicon carbide layer, or the like). An etching process is then performed based on the opening in the mask layer. Figure 7 In the cross-sectional view 700 of FIG. 1 , an etching process (e.g., wet etching, dry etching) removes portions of the first dielectric layer 602, the semiconductor substrate 108, and the interconnect dielectric structure 118, thereby forming a first opening 702. The first opening 702 exposes one of the interconnect lines 114 in the interconnect structure 112. In addition, the first opening 702 is spaced apart from the semiconductor device 110 to avoid interfering with and / or damaging the semiconductor device 110.

[0108] like Figure 8As shown in the cross-sectional view 800 of FIG. 8 , an electrically insulating layer 802 is deposited over the first dielectric layer 602 and within the first opening 702. In some embodiments, the electrically insulating layer 802 includes, for example, silicon dioxide, silicon nitride, aluminum oxide, or some other electrically insulating material. In some embodiments, the electrically insulating layer 802 can be deposited by a vapor deposition process (e.g., CVD, PE-CVD, PVD, ALD, etc.).

[0109] like Fig. 9 As shown in the cross-sectional view 900 of FIG. Figure 8 The horizontal portion of the first opening 702 is removed, thereby forming a through substrate via (TSV) liner 130 within the first opening 702. In some embodiments, the electrically insulating layer ( Figure 8 The horizontal portion of the first opening 702 is removed using a vertical etching process (e.g., vertical dry etching), so no mask layer is required. In some embodiments, from the cross-sectional view 900, after the vertical etching process, the remaining TSV liner 130 may have an upper inner corner that is rounded. However, the TSV liner 130 may completely cover the inner sidewall of the semiconductor substrate 108 exposed from the formation of the first opening 702 to provide electrical insulation in the horizontal direction.

[0110] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , the conductive material fills the first opening ( Fig. 9 702) to form a through substrate via (TSV) 128. In some embodiments, the chemical isolation layer 129 is first formed in the first opening ( Fig. 9 702) by, for example, a vapor deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.). Chemical isolation layer 129 may include, for example, tantalum or tantalum nitride, and the chemical isolation layer 129 has a thickness, for example, in the range of about 50 angstroms and about 500 angstroms. Subsequently, in some embodiments, the conductive material of TSV 128 may include, for example, copper. By, for example, a vapor deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.) on first dielectric layer 602, on chemical isolation layer 129, and on first opening ( Fig. 9102) to form TSV 128. Subsequently, a planarization process (e.g., chemical mechanical planarization (CMP)) may be used to remove excess conductive material and any additional material deposited for the chemical isolation layer, so that TSV 128 has an upper surface that is substantially coplanar with the first dielectric layer 602. The outermost sidewall of the chemical isolation layer 129 is surrounded by a TSV liner 130, so that TSV 128 does not directly contact semiconductor substrate 108. The chemical isolation layer 129 may prevent TSV 128 from diffusing into semiconductor substrate 108, and the TSV liner 130 may prevent any electrical signal passing through TSV 128 from leaking into semiconductor substrate 108 during operation. Therefore, both the chemical isolation layer 129 and the TSV liner 130 prevent TSV 128 from damaging and / or interfering with semiconductor device 110. In addition, TSV 128 may be electrically connected to the interconnect structure 112. In some embodiments, TSV 128 may have a height ranging between about 0.7 microns and about 3.2 microns, for example. Because TSV 128 extends completely through semiconductor substrate 108 , TSV 128 has a height that is greater than the thickness of semiconductor substrate 108 .

[0111] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a first etch stop layer 1102 may be deposited over the first dielectric layer 602 and the TSV 128, and a second dielectric layer 1104 may be deposited over the first etch stop layer 1102. In some embodiments, the first etch stop layer 1102 may include, for example, a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0112] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a second opening 1202 may be formed, and the second opening 1202 extends from the second dielectric layer 1104 to the back side 108s of the semiconductor substrate 108. The second opening 1202 exposes the back side 108s of the semiconductor substrate 108. The second opening 1202 may be formed by a selective patterning process according to a mask layer (not shown). Figure 7 12 is formed similarly to the formation of the first opening 702 in the back side 108s of the semiconductor substrate 108. In some embodiments, the second opening 1202 extends a first distance d1 into the back side 108s of the semiconductor substrate 108. The second opening 1202 is laterally spaced apart from the TSV 128 and vertically spaced apart from the semiconductor device 110. In some embodiments, there are two second openings 1202, however in other embodiments, one second opening 1202 or more than two second openings 1202 are formed.

[0113] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1 , a conformal colloid layer 1304 and a second conductive material 1302 are deposited on the second dielectric layer 1104 and the second opening ( Fig.12 1202). In some embodiments, the conformal colloidal layer 1304 includes, for example, titanium or titanium nitride, and the conformal colloidal layer 1304 has a thickness ranging, for example, between about 20 angstroms and about 300 angstroms. In some embodiments, the second conductive material 1302 includes, for example, tungsten. The conformal colloidal layer 1304 and / or the second conductive material 1302 can be deposited, for example, by a vapor deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.).

[0114] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , the second conductive material ( Fig.13 1302) is removed, thereby forming a back side contact 132 surrounded by the first dielectric layer 602 and the second dielectric layer 1104, and the back side contact 132 extends into the back side 108s of the semiconductor substrate 108. In some embodiments, the second conductive material ( Fig.13 The backside contacts 132 are removed by a planarization process (e.g., CMP), and thus, the backside contacts 132 can have a top surface that is substantially coplanar with the second dielectric layer 1104. In some embodiments, the backside contacts 132 can have a height, for example, in a range between about 0.1 microns and about 1 micron. In some embodiments, from the perspective of the cross-sectional view 1400, the backside contacts 132 have a bottommost surface below the topmost surface of the TSV 128, and have a topmost surface on the topmost surface of the TSV 128.

[0115] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a first etch stop layer 1502 may be deposited over the second dielectric layer 1104 and the backside contact 132, and a third dielectric layer 1504 may be deposited over the second etch stop layer 1502. In some embodiments, the second etch stop layer 1502 and the third dielectric layer 1504 may include the same material as the first etch stop layer 1102 and the second dielectric layer 1104, respectively.

[0116] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a third opening 1602 extending from the top surface of the third dielectric layer 1504 to the top surface of the TSV 128 may be formed. Therefore, in some embodiments, the third opening 1602 may directly overlie the TSV 128 and expose the top surface of the TSV 128. The third opening 1602 is formed by a selective patterning process according to a mask layer (not shown). Figure 7 The formation of the first opening 702 in is similar.

[0117] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , a fourth opening 1702 extending from the top surface of the third dielectric layer 1504 to the top surface of the backside contact 132 may be formed. In some embodiments, the fourth opening 1702 extends laterally across the backside contact 132 and the TSV 128. The fourth opening 1702 is formed by a selective patterning process according to a mask layer (not shown). Figure 7 The formation of the first opening 702 in is similar.

[0118] like Fig.18 As shown in the cross-sectional view 1800, the third conductive material is deposited into the fourth opening ( Fig.17 1702), followed by planarization to form a backside interconnect structure 1802. Figure 16 to Figure 18 The formation of the backside interconnect structure 1802 shown may represent a dual damascene process. Thus, the backside interconnect structure 1802 may include copper. In addition, an isolation layer (not shown) may be surrounded by the backside interconnect structure 1802 to chemically separate the backside interconnect structure 1802 from the backside contacts 132, the TSV 128, and the surrounding dielectric layer (dielectric layer 1104, dielectric layer 1504). The barrier metal layer may include, for example, tantalum nitride.

[0119] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 19 , in some embodiments, the bonding dielectric structure 124, the bonding through-via 123, and the bonding wire layer 122 may also be formed above the third dielectric layer 1504 and the backside interconnect structure 1802. In some embodiments, the first dielectric layer 602, the second dielectric layer 1104, and the third dielectric layer 1504 may include the same dielectric material as the bonding dielectric structure 124. In addition, in some embodiments, the bonding dielectric structure 124 may include the same dielectric material as the interconnect dielectric structure 118. In some embodiments, the bonding through-via 123 and the bonding wire layer 122 may include the same conductive material as the backside interconnect structure 1802. The bonding through-via 123 and the bonding wire layer 122 may also be formed by a dual damascene process, such as the backside interconnect structure 1802. In some embodiments, the bonding through-via 123 and the bonding wire layer 122 may be coupled to the backside interconnect structure 1802. The backside contacts 132, the backside interconnect structures 1802, the bonding vias 123, the bonding wire layer 122, and the surrounding dielectric material together may form an additional bonding structure 126 on the backside 108s of the semiconductor substrate 108. In some embodiments, the additional bonding structure 126 may have a height ranging, for example, between about 3 microns and about 3.5 microns. Thus, in some embodiments, the additional bonding structure 126 may have a greater height than the bonding structure 120. In addition, Fig.19The illustrated IC die may be classified as the third IC die 104 because the bonding structures (bonding structure 120 , bonding structure 126 ) are both on the front side 108 f and the back side 108 s of the semiconductor substrate 108 .

[0120] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , in some embodiments, a bonding process 2004 may be performed to form a 3DIC stack, wherein the additional bonding structure 126 of the third IC die 104 is bonded to the first bonding structure 120a of the first IC die 102, and the third bonding structure 120c ( Fig.19 120) is bonded to the second bonding structure 120b of the second IC die 106. The bonding process 2004 for bonding the various bonding structures to each other can be a fusion bonding process, a eutectic bonding process, a metallic bonding process, and / or a combination thereof. Therefore, in some embodiments, the bonding process 2004 is a hybrid bonding process. In some embodiments, the first substrate 108a and the second substrate 108b of the first IC die 102 and the second IC die 106 can each have a thickness ranging between about 750 microns and about 800 microns. Therefore, in some embodiments, the third substrate 108c ( Fig.19 108) is thinner than each of the first substrate 108a and the second substrate 108b. The first substrate 108a and the second substrate 108b may define the bottommost surface and the topmost surface of the 3D IC stack, respectively. Therefore, during operation of the 3D IC stack, any generated heat from the semiconductor devices (e.g., semiconductor devices 110a, semiconductor devices 110b, semiconductor devices 110c) may be dissipated from the semiconductor devices (e.g., semiconductor devices 110a, semiconductor devices 110b, semiconductor devices 110c) and leave the 3D IC stack through the first substrate 108a and the second substrate 108b. In addition, due to the back side contacts 132 in the third IC die 104, the heat generated in the third substrate 108c can be effectively dissipated toward the first substrate 108a and the second substrate 108b through the back side contacts 132 and through the bonding structures (e.g., bonding structures 120a, bonding structures 120b, bonding structures 120c), other bonding structures 126, TSVs 128, and internal connection structures (e.g., internal connection structures 112a, internal connection structures 112b, internal connection structures 112c) to reduce thermal damage to the semiconductor devices (e.g., semiconductor devices 110a, semiconductor devices 110b, semiconductor devices 110c).

[0121] Fig.21A flow chart illustrating some embodiments of a method 2100 of forming an integrated circuit (IC) die having backside contacts coupled to through-substrate vias.

[0122] Although method 2100 is shown and described as a series of actions or events below, it should be understood that the shown ordering of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described in this article, some actions may occur in different orders and / or at the same time as other actions or events. In addition, not all of the shown actions may be required to implement one or more aspects or embodiments of the description herein. In addition, one or more of the actions depicted herein may be performed with one or more separate actions and / or stages.

[0123] At operation 2102 , a semiconductor device is formed on a front side of a semiconductor substrate.

[0124] At operation 2104, an interconnect structure is formed over the semiconductor device.

[0125] At operation 2106 , a bonding structure is formed over the interconnect structure. Figure 5 A cross-sectional diagram 500 of some embodiments corresponding to operation 2102 , operation 2104 , and operation 2106 is shown.

[0126] At operation 2108 , a through substrate via (TSV) is formed extending from the backside of the semiconductor substrate to the frontside of the semiconductor substrate. Figures 7 to 10 Cross-sectional views 700 through 1000 are shown corresponding to some embodiments of operation 2108 .

[0127] At operation 2110 , a second dielectric layer is deposited over the backside of the semiconductor substrate. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of operation 2110 .

[0128] In operation 2112 , a first opening is formed in the second dielectric layer to expose a surface of a backside of the semiconductor substrate. Fig.12 A cross-sectional view 1200 is shown corresponding to some embodiments of operation 2112 .

[0129] At operation 2114 , the first opening is filled with a first material to form a backside contact over the backside of the semiconductor substrate. Fig.13 and Fig.14 Cross-sectional view 1300 and cross-sectional view 1400 are shown corresponding to some embodiments of operation 2114 .

[0130] At operation 2116, more bonding dielectric layers, bonding contacts, and bonding wire layers are deposited over the second dielectric layer, with backside contacts coupled to the bonding contacts and bonding wire layers. Fig.19 A cross-sectional view 1900 is shown corresponding to some embodiments of operation 2116 .

[0131] Therefore, the present disclosure relates to a 3D IC stack that uses back side contacts on the back side of the semiconductor substrate of the third IC die, which are vertically located between the first IC die and the second IC die to provide an effective heat dissipation path for the heat generated in the semiconductor substrate of the third IC die during operation, thereby improving the device life and reliability.

[0132] Therefore, in some embodiments, the present disclosure relates to a three-dimensional (3D) integrated circuit (IC) stack including: a first IC die including a first semiconductor substrate, a first interconnect structure arranged on a front side of the first semiconductor substrate, and a first bonding structure arranged above the first interconnect structure; a second IC die including a second semiconductor substrate, a second interconnect structure arranged on a front side of the second semiconductor substrate, and a bonding structure arranged on the second interconnect structure, wherein the second bonding structure faces the first bonding structure; a third IC die including a third semiconductor substrate, a third interconnect structure arranged on a front side of the third semiconductor substrate, and a third bonding structure arranged on a back side of the third semiconductor substrate, wherein the third IC die is vertically arranged between the first IC die and the second IC die; and a heat dissipation path extending from the third semiconductor substrate to at least one of the first semiconductor substrate or the second semiconductor substrate, the heat dissipation path including a first backside contact extending from the third bonding structure, the first backside contact extending to the back side of the third semiconductor substrate, wherein the first backside contact is thermally coupled to at least one of the first interconnect structure or the second interconnect structure.

[0133] In some embodiments, the third integrated circuit die further comprises a through-substrate via, a chemical isolation layer, and an electrical insulator liner, wherein the through-substrate via extends through from the back side of the third semiconductor substrate to the front side of the third semiconductor substrate, wherein the through-substrate via is laterally spaced apart from the first back side contact, and wherein the through-substrate via is electrically connected to the first back side contact; the chemical isolation layer is in direct contact with an outer surface of the through-substrate via; and the electrical insulator liner separates the third semiconductor substrate from the chemical isolation layer, wherein the electrical insulator liner and the chemical isolation layer are thicker than a colloid layer, and the colloid layer separates the third semiconductor substrate from the first back side contact. In some embodiments, the through-substrate via comprises copper and the first back side contact comprises tungsten. In some embodiments, the three-dimensional integrated circuit stack further includes a fourth integrated circuit die and a second backside contact, the fourth integrated circuit die including a fourth semiconductor substrate, a fourth internal wiring structure arranged on the front side of the fourth semiconductor substrate, and a fourth bonding structure arranged on the back side of the fourth semiconductor substrate, wherein the third integrated circuit die is vertically arranged between the second integrated circuit die and the third integrated circuit die; the second backside contact extends from the fourth bonding structure to the back side of the third semiconductor substrate, wherein a second colloid layer surrounds the second backside contact and separates the fourth semiconductor substrate from the second backside contact, and wherein the second backside contact is thermally coupled to the second internal wiring structure. In some embodiments, the third internal wiring structure separates the fourth bonding structure from the third bonding structure. In some embodiments, the third bonding structure directly contacts the fourth bonding structure.

[0134] In other embodiments, the present disclosure relates to an integrated circuit (IC) die including: a semiconductor substrate; a semiconductor device integrated on the front side of the semiconductor substrate; an internal wiring structure arranged on the front side of the semiconductor substrate, coupled to the semiconductor device and including internal wiring vias and internal wiring lines embedded in a dielectric layer; a first bonding structure arranged above the internal wiring structure; a second bonding structure arranged on the back side of the semiconductor substrate and including bonding wires and bonding vias within the bonding dielectric structure; and a back side contact arranged within the second bonding structure, wherein a top surface of the back side contact is thermally coupled to the back side of the semiconductor substrate, wherein a top surface of the back side contact is spaced apart from the front side of the semiconductor substrate by the semiconductor substrate, and wherein the back side contact is thermally and electrically coupled to the second bonding structure.

[0135] In some embodiments, the backside contact protrudes into the back side of the semiconductor substrate. In some embodiments, the backside contact is directly below the semiconductor device and is spaced apart from the semiconductor device by the semiconductor substrate. In some embodiments, the semiconductor device is a transistor, the transistor comprising a doping well region arranged in the semiconductor substrate, wherein the doping well region has a first doping concentration and the semiconductor device has a second doping concentration different from the first doping concentration, wherein the backside contact is spaced apart from the doping well region. In some embodiments, the backside contact is spaced apart from the semiconductor substrate by a colloid layer, the colloid layer having a first thickness. In some embodiments, the integrated circuit die further comprises a substrate through-hole and a substrate through-hole pad, the substrate through-hole extending from the second bonding structure to the first bonding structure, the substrate through-hole pad being arranged on the outer side wall of the substrate through-hole, wherein the substrate through-hole pad spaces the semiconductor substrate from the substrate through-hole. In some embodiments, the substrate through-hole pad has a second thickness greater than the first thickness. In some embodiments, the backside contact is electrically connected to the substrate through-hole and the bonding through-hole of the second bonding structure via the bonding wire. In some embodiments, the backside contact comprises a different material than the substrate through-hole.

[0136] In yet other embodiments, the present disclosure relates to a method for forming an integrated circuit, the method comprising: forming a semiconductor device on the front side of a semiconductor substrate; forming an interconnect structure above the semiconductor device; forming a first bonding structure above the interconnect structure; depositing a second dielectric layer above the back side of the semiconductor substrate; patterning the second dielectric layer to form a first opening in the second dielectric layer, wherein the first opening exposes the surface of the back side of the semiconductor substrate, and wherein when the back side of the semiconductor substrate is located above the front side of the semiconductor substrate, the surface of the back side of the semiconductor substrate is located above the semiconductor device; depositing a colloidal layer having a first thickness above the first opening; filling the first opening with a first material to form a back side contact, the back side contact being separated from the semiconductor substrate by the colloidal layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers above the second dielectric layer to form a second bonding structure above the back side of the semiconductor substrate, wherein the back side contact is coupled to the bonding contacts and the bonding wire layers.

[0137] In some embodiments, before the first opening is formed, the method further includes forming a second opening, the second opening extending from the back side of the semiconductor substrate to the front side of the semiconductor substrate, wherein the second opening exposes the metal line in the interconnect structure; forming a liner in the second opening using a second material; and filling the second opening with a third material different from the first material and the second material to form a substrate through-hole, wherein the liner separates the semiconductor substrate from the substrate through-hole. In some embodiments, the liner is thicker than the colloid layer. In some embodiments, the substrate through-hole is coupled to the backside contact. In some embodiments, the liner includes a chemical isolation layer and an electrical insulation layer.

[0138] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A three-dimensional integrated circuit stack, comprising: A first integrated circuit die comprising a first semiconductor substrate, a first interconnect structure disposed on a front side of the first semiconductor substrate, and a first bonding structure disposed over the first interconnect structure; a second integrated circuit die comprising a second semiconductor substrate, a second interconnect structure disposed on a front side of the second semiconductor substrate, and a second bonding structure disposed on the second interconnect structure, wherein the second bonding structure faces the first bonding structure; a third integrated circuit die, comprising a third semiconductor substrate, a third interconnect structure disposed on a front side of the third semiconductor substrate, and a third bonding structure disposed on a back side of the third semiconductor substrate, wherein the third integrated circuit die is vertically disposed between the first integrated circuit die and the second integrated circuit die; as well as a heat dissipation path extending from the third semiconductor substrate to at least one of the first semiconductor substrate or the second semiconductor substrate, the heat dissipation path comprising a first backside contact extending from the third bonding structure, the first backside contact extending to the back side of the third semiconductor substrate, wherein the first backside contact is thermally coupled to at least one of the first interconnect structure or the second interconnect structure, wherein the third integrated circuit die further comprises: a through substrate via extending through from the back side of the third semiconductor substrate to the front side of the third semiconductor substrate, wherein the through substrate via is laterally spaced apart from the first back side contact, and wherein the through substrate via is electrically connected to the first back side contact; a chemical isolation layer directly contacting an outer surface of the substrate through-hole; and An electrical insulator liner separates the third semiconductor substrate from the chemical isolation layer, wherein the electrical insulator liner and the chemical isolation layer are thicker than a colloid layer separating the third semiconductor substrate from the first backside contact. 2 . The three-dimensional integrated circuit stack of claim 1 , wherein the through-substrate via comprises copper and the first backside contact comprises tungsten.

3. The three-dimensional integrated circuit stack according to claim 1, further comprising: a fourth integrated circuit die comprising a fourth semiconductor substrate, a fourth interconnect structure disposed on a front side of the fourth semiconductor substrate, and a fourth bonding structure disposed on a back side of the fourth semiconductor substrate, wherein the third integrated circuit die is vertically disposed between the second integrated circuit die and the third integrated circuit die; as well as A second backside contact extends from the fourth bonding structure to the back side of the third semiconductor substrate, wherein a second colloid layer surrounds the second backside contact and separates the fourth semiconductor substrate from the second backside contact, and wherein the second backside contact is thermally coupled to the second interconnect structure. 4 . The three-dimensional integrated circuit stack of claim 3 , wherein the third interconnect structure separates the fourth bonding structure from the third bonding structure. 5 . The three-dimensional integrated circuit stack of claim 3 , wherein the third bonding structure directly contacts the fourth bonding structure.

6. An integrated circuit die, comprising: Semiconductor substrate; a semiconductor device integrated on the front side of the semiconductor substrate; an interconnect structure disposed on the front side of the semiconductor substrate, coupled to the semiconductor device, and comprising an interconnect via and an interconnect line embedded in a dielectric layer; A first bonding structure, arranged above the inner connection structure; a second bonding structure disposed on the back side of the semiconductor substrate and comprising a bonding wire and a bonding through-via within a bonding dielectric structure; a backside contact disposed within the second bonding structure, wherein a top surface of the backside contact is thermally coupled to the backside of the semiconductor substrate, wherein the top surface of the backside contact spaces the semiconductor substrate from the frontside of the semiconductor substrate, and wherein the backside contact is thermally coupled and electrically connected to the second bonding structure; as well as A through substrate via extends from the second bonding structure to the first bonding structure, wherein a portion of the through substrate via is disposed within the bonding dielectric structure of the second bonding structure.

7. The integrated circuit die of claim 6 wherein the backside contacts protrude into the backside of the semiconductor substrate.

8. The integrated circuit die of claim 6, wherein the backside contacts are directly beneath the semiconductor device and are spaced apart from the semiconductor device by the semiconductor substrate.

9. The integrated circuit die of claim 6 , wherein the semiconductor device is a transistor, the transistor comprising a doped well region arranged within the semiconductor substrate, wherein the doped well region has a first doping concentration and the semiconductor device has a second doping concentration different from the first doping concentration, wherein the backside contact is spaced apart from the doped well region.

10. The integrated circuit die of claim 6, wherein the backside contacts are spaced apart from the semiconductor substrate by a gel layer, the gel layer having a first thickness.

11. The integrated circuit die of claim 10, further comprising: A through substrate via liner is arranged on an outer sidewall of the through substrate via, wherein the through substrate via liner separates the semiconductor substrate from the through substrate via.

12. The integrated circuit die of claim 11 wherein the through substrate via liner has a second thickness greater than the first thickness.

13. The integrated circuit die of claim 6, wherein the backside contacts are electrically connected to the through-substrate vias and the bonding through-vias of the second bonding structure via the bonding wires.

14. The integrated circuit die of claim 6, wherein the backside contacts comprise a different material than the through-substrate vias.

15. A method of forming an integrated circuit, comprising: forming a semiconductor device on the front side of the semiconductor substrate; forming an interconnect structure above the semiconductor device; forming a first bonding structure above the inner connection structure; depositing a first dielectric layer over a back side of the semiconductor substrate, wherein the back side of the semiconductor substrate and the front side of the semiconductor substrate are opposite to each other; depositing a second dielectric layer over the first dielectric layer; patterning the second dielectric layer to form a first opening in the second dielectric layer, wherein the first opening exposes a surface of the backside of the semiconductor substrate and wherein the surface of the backside of the semiconductor substrate is located above the semiconductor device when the backside of the semiconductor substrate is located above the frontside of the semiconductor substrate; depositing a colloid layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact, the backside contact being separated from the semiconductor substrate by the colloid layer; as well as depositing more dielectric layers, bonding contacts, and bonding wire layers over the second dielectric layer to form a second bonding structure on the back side of the semiconductor substrate, wherein the back side contacts are coupled to the bonding contacts and the bonding wire layers, wherein Before the first opening is formed, the method further comprises: forming a second opening extending through the first dielectric layer and extending from the back side of the semiconductor substrate to the front side of the semiconductor substrate, wherein the second opening exposes a metal line within the interconnect structure; forming a liner in the second opening using a second material; and The second opening is filled with a third material different from the first material and the second material to form a through substrate via, wherein the liner separates the semiconductor substrate from the through substrate via.

16. The method of forming an integrated circuit according to claim 15, wherein the liner is thicker than the colloid layer.

17. The method of forming an integrated circuit of claim 15, wherein the through substrate via is coupled to the backside contact.

18. The method of forming an integrated circuit according to claim 15, wherein the liner comprises a chemical isolation layer and an electrical insulation layer.

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