A display panel driving method and a display device

Abstract

The embodiment of the present application discloses a display panel driving method and display device. The display panel driving method, at least one picture update cycle includes data writing stage, data holding stage and data compensation stage; the data compensation stage is located before the data writing stage; in the data compensation stage, the gate scanning signal is provided to the pixel unit and the compensation data voltage is written, the compensation data voltage is less than the target data voltage; the target data voltage is the theoretical data voltage corresponding to the target brightness of the current picture update cycle; in the data writing stage, the gate scanning signal is provided to the pixel unit and the target data voltage is written, and in the data holding stage, no data voltage is written to the pixel unit. The embodiment of the present application solves the problem of picture flicker caused by transistor hysteresis effect, ensures that the picture reaches the target brightness as soon as possible when switching, reduces the picture brightness difference in the same picture update cycle, thereby improving the picture display quality and effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and more particularly to a driving method for a display panel and a display device. Background Art

[0002] The pixel circuit in an organic light-emitting diode (OLED) display realizes the display function by controlling the driving current flowing through the OLED via a driving transistor. The magnitude of this driving current is related to the characteristic parameters of the driving transistor, including the threshold voltage.

[0003] In the existing OLED display process, when displaying two different images, due to the difference in image brightness, the image brightness will slowly change during the switching process. This brightness change process takes a long time and is easily noticeable to the human eye, which will cause the image to flicker, resulting in poor image display effects. This has become an urgent problem that needs to be solved to improve the quality of OLED displays. Summary of the Invention

[0004] The present invention provides a display panel driving method and a display device to compensate for the unstable electrical performance of transistors when display images are switched, reduce brightness differences and change time, enable the display image to reach the target brightness more quickly, and solve the problem of image flickering caused by the hysteresis effect of transistors.

[0005] In a first aspect, an embodiment of the present invention provides a method for driving a display panel, comprising a plurality of picture update cycles, at least one of which includes a data writing phase, a data holding phase, and a data compensation phase;

[0006] The data compensation stage is located before the data writing stage;

[0007] In the data compensation phase, a gate scanning signal is provided to the pixel unit and a compensation data voltage is written, wherein the compensation data voltage is less than the target data voltage; the target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle;

[0008] In the data writing phase, a gate scanning signal is provided to the pixel unit and the target data voltage is written.

[0009] During the data holding phase, no data voltage is written into the pixel unit.

[0010] In a second aspect, an embodiment of the present invention further provides a display device, including:

[0011] A display panel comprising a plurality of pixel units, the display panel comprising a plurality of picture update cycles, at least one of the picture update cycles comprising a data writing phase, a data compensation phase, and a data holding phase, and at least one of the picture update cycles further comprising the data compensation phase being located before the data writing phase;

[0012] A scan driving unit, configured to provide a gate scan signal to each pixel unit during the data writing phase and the data compensation phase;

[0013] The data writing unit is used to provide a gate scanning signal to the pixel unit and write a target data voltage during the data writing phase, where the target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle; and is also used to provide a gate scanning signal to the pixel unit and write a compensation data voltage during the data compensation phase, where the compensation data voltage is less than the target data voltage.

[0014] The present invention provides a method for driving a display panel and a display device. The method includes configuring the display panel to include multiple picture update cycles during the display driving process, wherein at least one picture update cycle includes a data writing phase, a data holding phase, and a data compensation phase. The data compensation phase is configured to precede the data writing phase. In the data compensation phase, a gate scan signal is provided to a pixel unit and a compensation data voltage is written. The compensation data voltage is less than a target data voltage. The target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle. In the data writing phase, a gate scan signal is provided to the pixel unit and the target data voltage is written. In the data holding phase, no data voltage is written to the pixel unit. This allows the display panel to implement data compensation in at least one picture update cycle, thereby improving the display brightness of the display panel during the data compensation process. The present invention can solve the problem of screen flickering caused by the hysteresis effect of transistors, compensate for the defect of unstable electrical performance of transistors, ensure that the screen reaches the target brightness of the current picture update cycle as quickly as possible when switching, reduce the difference in screen brightness within the same picture update cycle, and thus improve the quality and effect of screen display. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the brightness change of the OLED display panel provided by the inventor during the research process;

[0016] Figure 2 is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0017] Figure 3 yes Figure 2 A schematic structural diagram of a pixel driving circuit in the display device shown;

[0018] Figure 4 is a timing diagram of a display panel driving method provided by an embodiment of the present invention;

[0019] Figure 5 and Figure 6 is a timing diagram of two other display panel driving methods provided by embodiments of the present invention;

[0020] Figure 7 is a timing diagram of another display panel driving method provided by an embodiment of the present invention;

[0021] Figure 8 is a timing diagram of another display panel driving method provided by an embodiment of the present invention;

[0022] Figure 9 is a timing diagram of another display panel driving method provided by an embodiment of the present invention;

[0023] Figure 10 is a timing diagram of another display panel driving method provided by an embodiment of the present invention;

[0024] Figure 11 is a timing diagram of the data compensation phase provided by an embodiment of the present invention;

[0025] Figure 12 is a timing diagram of the data writing phase provided by an embodiment of the present invention;

[0026] Figure 13 is a timing diagram of the data retention phase provided by an embodiment of the present invention;

[0027] Figure 14 This is a schematic structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention;

[0028] Figure 15 is another timing diagram of the data writing phase provided by an embodiment of the present invention;

[0029] Figure 16 This is a schematic structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention;

[0030] Figure 17 This is another timing diagram of the data writing phase provided by an embodiment of the present invention;

[0031] Figure 18 This is a schematic structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention;

[0032] Figure 19 This is another timing diagram of the data writing phase provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0034] Figure 1 This is a schematic diagram of the brightness change of the OLED display panel provided by the inventor during the research process, reference Figure 1 For example, taking the display panel's screen refresh rate as 1 Hz as an example, the inventors have found through research that when the OLED display panel switches from a black state to a display screen of a certain brightness during the driving display process, if multiple data refresh frames are set, the pixel driving circuit can achieve multi-frame driving display by repeatedly writing data voltages. During this process, the hysteresis effect of the driving transistor of the pixel driving circuit gradually weakens, and the electrical performance gradually stabilizes. As shown in the figure, the first 4 seconds (the first four frames) are the process of multiple refresh and writing data voltages. During this process, the electrical performance of the transistor gradually stabilizes, and the brightness of the display panel screen also shows a trend of gradually increasing, and finally reaches the target brightness in the 4th second. It should be noted that during the data refresh and writing process of the first 4 seconds, the data voltage written to the pixel driving circuit is the same, and both are the theoretical data voltage Vdata0 corresponding to the target brightness of the screen update cycle. However, although the written data voltage is the same, due to the hysteresis effect of the driving transistor itself, the actual brightness of the screen in the first few refresh frames is significantly different from the target brightness, which can be perceived by the human eye and form a display effect of the screen. In response to the above problems, an embodiment of the present invention provides a driving method for a display panel.

[0035] Figure 2 is a structural diagram of a display device provided by an embodiment of the present invention, Figure 3 yes Figure 2 A schematic structural diagram of a pixel driving circuit in a display device shown in FIG. Figure 4 This is a timing diagram of a display panel driving method provided by an embodiment of the present invention. First, refer to Figure 2 The display device for which the display panel driving method provided in the embodiment of the present invention is directed is introduced. The display device provided in the embodiment of the present invention specifically includes a display panel 100, a scan drive unit 200, and a data write unit 300. The display panel 100 includes a plurality of pixel units 110. The pixel units 110 are generally arranged in an array along row and column directions. The pixel units 110 can be configured to include at least three color pixel units: red pixel units, green pixel units, and blue pixel units. By using the color matching of the three primary colors of red, green, and blue, a full-color image can be driven and displayed.

[0036] Continue to refer Figure 2and Figure 3 Specifically, the driving and emitting process of each pixel unit 110 is essentially realized by the pixel driving circuit provided in the display panel 100 corresponding to each pixel unit 110. Figure 3 Taking the 7T1C pixel driving circuit shown in FIG. 1 as an example, the driving process of the pixel driving circuit is briefly introduced.

[0037] It is understood that in addition to the pixel unit 110, the display panel is also provided with a plurality of gate scanning lines 120 and a plurality of data signal lines 130, and the pixel driving circuit is electrically connected to the gate scanning lines 120 and the data signal lines 130 respectively. The pixel driving circuit receives the gate scanning signal provided by the scanning driving unit 200 through the gate scanning line 120, and also receives the data voltage signal provided by the data writing unit 300 through the data signal line 130. According to the gate scanning signal and the data voltage signal, the pixel driving circuit drives the pixel unit 110 to emit light. Figure 3 In the illustrated 7T1C pixel driver circuit, a gate scan line 120 is electrically connected to a first scan signal terminal S1, which provides a gate scan signal to the gate of a driver transistor T in the pixel driver circuit, thereby controlling the switching of the pixel driver circuit. A data signal line 130 is electrically connected to a data signal terminal Vdata, which writes a data voltage to a storage capacitor Cst, thereby driving the light-emitting diode (LED), i.e., the pixel unit 110, via the driver transistor T to emit light.

[0038] Of course, if Figure 3 The 7T1C pixel driving circuit shown is only an example of an embodiment of the present invention. The display panel driving method provided by the embodiment of the present invention is also applicable to other pixel driving circuits, which will not be introduced here.

[0039] The display panel driving method provided by the embodiment of the present invention is mainly to improve the timing of the display panel in the picture update cycle. It can be understood that the display panel includes multiple picture update cycles in the display driving process, and in each picture update cycle, the display panel displays a picture. And the picture displayed by the display panel, from a microscopic point of view, is actually the process of multiple pixel units arranged thereon emitting light. From a macroscopic point of view, multiple pixel units can realize the display of a picture by matching colors and brightness. A picture update cycle of the display panel is actually the process in which all pixel units thereon are driven and lit by the corresponding pixel driving circuits. In other words, in one picture update cycle of the display panel, each pixel driving circuit on the display panel is refreshed once. During the refresh process, the pixel driving circuit drives the pixel unit 110 to emit light once through the gate scanning signal and the data voltage signal provided by the gate scanning line 120 and the data signal line 130 respectively, which is the data writing stage; and when the pixel driving circuit drives the pixel unit 110 to emit light only through the gate scanning signal provided by the gate scanning line 120 during the refresh process, without writing the data voltage signal, which is the data holding stage.

[0040] After research, the inventors found that when the display panel needs to display a dynamic picture, it may need to refresh 60 pictures within 1 second; but when the picture displayed within a period of time is a static picture, taking a pixel unit as an example, the pixel unit may only need to maintain the same brightness within 1 second or several consecutive seconds, so there is no need to continuously write data within this 1 second. For example, compared with the high-frequency drive case where data is written to each of the 60 frames in 1 second, the display panel provided by the embodiment of the present invention includes a low-frequency drive, for example, only some of the 60 frames in 1 second do not have data written. That is, in the embodiment of the present application, for each pixel unit and pixel driving circuit, in a picture update cycle of the display panel, it includes a data writing stage and multiple data retention stages.

[0041] It can be understood that in some optional embodiments of the present application, the display panel can include both low-frequency driving and high-frequency driving, and one of the two driving modes can be selected according to the image requirements.

[0042] It is understandable that the low-frequency drive mentioned in this application does not mean that all signal lines are low-frequency driven. Optionally, the low-frequency driven signal in this application mainly refers to the light-emitting control signal Emit. The effective pulse of the light-emitting control signal Emit enables the pixel driving circuit to control the light-emitting element 60 to emit light. It is understandable that the driving process of the pixel driving circuit requires the coordination of multiple scanning signals and control signals. The signals on other signal lines in the pixel driving circuit can also be coordinated with low-frequency drive. Specifically, Figure 4As shown, the display panel refreshes 60 images within 1 second. This essentially means that the pixel driver circuit corresponding to each pixel unit on the display panel receives 60 valid pulses of the light-emitting control signal Emit within 1 second, and the pixel unit emits light 60 times within 1 second. It is understood that the pixel unit's light-emitting process is not only controlled by the light-emitting control signal Emit. The operation process of the corresponding pixel driver circuit driving the pixel unit to emit light once may include a data voltage writing period and a light-emitting period. The data voltage writing period is the preparatory process for writing the data voltage to the storage capacitor, and the light-emitting period is the process of directly controlling the light-emitting control signal Emit. In other words, a picture update cycle as referred to in this application may include at least one data writing phase, at least one data holding phase, and at least one data compensation phase. The data writing phase, data holding phase, and data compensation phase all correspond to at least one light-emitting process of the pixel driver circuit.

[0043] The following is a detailed introduction to the driving method of the display panel provided by the embodiment of the present invention. In the driving method of the display panel provided by the embodiment of the present invention, the display panel includes multiple picture update cycles during the driving display process, and at least one picture update cycle can be set to include a data writing stage, a data holding stage and a data compensation stage; the data compensation stage is located before the data writing stage.

[0044] During display, a display panel typically updates multiple images, each with varying brightness. A frame update cycle refers to the process of updating and displaying a specific image within a certain period of time. Each frame update cycle can include multiple phases, such as a data compensation phase, a data write phase, or a data hold phase. The display panel can be driven to display a frame in each phase. For example, the frame corresponding to the current frame update cycle can be driven to display during the first few phases, while the frame remains displayed during the subsequent phases. For example, assuming a frame update cycle duration of 1 second and a refresh frequency of 60 Hz for the display panel's light control signal Emit, the display panel maintains the same frame within 1 second, but effectively refreshes 60 identical frames. In other words, a 1-second frame update cycle can be divided into 60 phases, each lasting 1 / 60 second. Of course, in embodiments of the present invention, the duration of each phase in the frame update cycle can be set to different values ​​based on actual needs, and this is not a limitation here.

[0045] The following is a detailed introduction to the picture update cycle in the driving method provided by the embodiment of the present invention with reference to the accompanying drawings. Figure 2-Figure 4Specifically, in the driving method of the display panel, optionally, in the data compensation stage A, a gate scan signal is provided to the pixel unit 110 and a compensation data voltage is written, and the compensation data voltage is less than the target data voltage; the target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle.

[0046] In the embodiments of the present invention, the driving process of the display panel is essentially a process of synchronously or individually driving multiple pixel units thereon. Generally, when the display panel displays an image, a data voltage must be written to each pixel unit 110 to drive the pixel unit to emit light at a corresponding brightness, thereby realizing the image display of the entire display panel. Therefore, for each pixel unit 110 in the display panel, when writing the data voltage, it is necessary to sequentially turn on the corresponding pixel unit 110 through the gate scan signal provided by the gate scan line 120, and write the data voltage signal through the data signal line 130.

[0047] In other words, a data writing phase actually includes the sequential writing of data to multiple pixel units in coordination with the scan lines. For the sake of convenience, this embodiment uses a single pixel unit as an example. The data compensation phase and the data retention phase are similar and will not be described in detail.

[0048] refer to Figure 4The data compensation phase A comprises multiple data compensation phases. During this phase, the data compensation phase essentially involves writing a compensation data voltage to the pixel cell. After the compensation data voltage is written, the pixel cell is driven to display. However, the brightness of the pixel cell or display panel is affected by the hysteresis effect of the driver transistor in the pixel driver circuit. In this case, the brightness of the pixel cell or display panel is not consistent with the brightness theoretically corresponding to the compensation data voltage. For OLED display panels, the brightness of a pixel cell is positively correlated with the current flowing through the driver transistor in the pixel driver circuit, while the current flowing through the driver transistor is inversely proportional to the data voltage written to the pixel cell. Based on this, in this data compensation phase, embodiments of the present invention set the written compensation data voltage to be lower than the target data voltage. In theory, this will result in the brightness of the pixel cell or display panel exceeding the target brightness for the current frame update cycle. However, due to the hysteresis effect of the driver transistor in the pixel driver circuit, the compensation data voltage at this stage does not increase the brightness of the pixel cell to exceed the target brightness for the current frame update cycle. Instead, it compensates for the brightness of the pixel cell that was originally below the target brightness due to the hysteresis effect, and can even bring the brightness of the pixel cell to exactly the target brightness. In other words, during this data compensation phase, by writing a smaller compensation data voltage, a higher screen brightness can actually be achieved. Furthermore, because the screen brightness during the compensation phase is higher, it is closer to the target brightness, and the time to reach the target brightness can be shortened to a certain extent. As a result, during this screen update cycle, the difference in brightness change before reaching the target brightness is relatively small, shortening the brightness buffer time, achieving the target brightness more quickly, and ensuring the display quality.

[0049] Optionally, in the data writing phase, a gate scanning signal is provided to the pixel unit 110 and a target data voltage is written.

[0050] refer to Figure 4 Data writing phase B must occur after data compensation phase A within the same frame update cycle. As can be seen from the aforementioned data compensation phase, the electrical performance of the driver transistors in the pixel driver circuit stabilizes through the data compensation process, and the thresholds reach their theoretical values. Therefore, during this phase, data writing and display driving can be performed using the pixel driver circuit with stable electrical performance. During this phase, the theoretical data voltage corresponding to the target brightness of the current frame update cycle is written into the pixel unit. Through normal driving of the pixel driver circuit, the pixel unit or display panel displays at the target brightness.

[0051] It is understood that the target data voltage in this stage can be a data voltage value within a certain range. For the display panel, its target brightness can actually be a brightness value within the allowable error range, and the corresponding theoretical data voltage can also be a data voltage value within the allowable range. After the data voltage within the allowable range is written, the brightness of the display screen reaches the expected brightness range.

[0052] Optionally, in the data holding phase, the data voltage is not written to the pixel unit. Specifically, a gate scan signal is provided to the pixel unit 110 without writing a data voltage signal. Figure 4 There are multiple data retention stages C, and the data retention stage is actually the picture retention stage. The data retention stage is consistent with the data voltage of the previous stage. In the pixel driving circuit, the storage capacitor of the data retention stage stores the data voltage of the previous stage, that is, the gate potential of the driving transistor maintains the data voltage of the previous stage. Therefore, when driving the light emission in the data retention stage, there is no need to rewrite the data voltage, and its brightness is theoretically the same as the brightness of the previous stage. Therefore, it can be understood that in this embodiment, the data retention stage should be set after the data writing stage or the data compensation stage. The data voltage written in the data writing stage or the data compensation stage can be saved in the capacitor of the pixel driving circuit, and the data voltage does not need to be rewritten in the data retention stage. In the process of refreshing the display of the pixel unit, it is only necessary to turn on and drive the pixel unit by providing a light-emitting control signal to enable the display panel to maintain the picture. It should be noted that, if Figure 4 As shown, the data voltage corresponding to the data holding phase C is not the written data voltage, but only a reference value of the data voltage, which is used to compare the compensated data voltage Vdata written in the data compensation phase A and the target data voltage Vdata0 written in the data writing phase B. For example, in the data holding phase, the pixel driving circuit controls the switch for inputting the data signal to be closed, and no data signal is input to the pixel driving circuit regardless of the signal on the data signal line; for example Figure 3 When the pixel driving circuit is in the data holding stage, the second transistor M2 (this circuit will be described in detail later) is in the off state.

[0053] An embodiment of the present invention provides a method for driving a display panel. The method includes configuring the display panel to include multiple frame update cycles during the display driving process, wherein at least one frame update cycle includes a data write phase, a data hold phase, and a data compensation phase. The data compensation phase is configured to precede the data write phase. In the data compensation phase, a gate scan signal is provided to a pixel unit and a compensation data voltage is written. The compensation data voltage is less than a target data voltage. The target data voltage is a theoretical data voltage corresponding to the target brightness of the current frame update cycle. In the data write phase, a gate scan signal is provided to the pixel unit and the target data voltage is written. In the data hold phase, no data voltage is written to the pixel unit. This method enables the display panel to perform data compensation in at least one frame update cycle, thereby rapidly improving the display brightness of the display panel during the data compensation process. The embodiment of the present invention can address the problem of image flicker caused by transistor hysteresis, compensate for the unstable electrical performance of transistors, ensure that the image reaches the target brightness of the current frame update cycle as quickly as possible during switching, reduce the brightness difference within the same frame update cycle, and thus improve the image display quality and effect. Furthermore, by ensuring that the compensation data voltage is less than the target data voltage, the frequency of data signal input can be further reduced, thereby reducing power consumption.

[0054] It should be noted that if Figure 4 Exemplarily, three data compensation phases A, one data writing phase B, and multiple data holding phases C are set, and the number of the above phases is not limited here. It is understandable that in the same picture update cycle, the data compensation phase needs to be set according to the specific hysteresis effect of the driving transistor of the pixel driving circuit in the display panel, and also needs to be set according to the effect of the compensation data actually written in the data compensation phase. Specifically, in the same picture update cycle, before the data writing phase, more than one and less than five data compensation phases can be set, and one data writing phase can be set at the same time. On the one hand, using a certain number of data compensation phases, the brightness of the picture can be effectively compensated, and the picture display brightness can be effectively increased before reaching the target brightness, so that the threshold of the driving transistor can be stabilized as soon as possible; on the other hand, using fewer data writing phases can reduce the data writing process of the display panel, which can reduce the driving frequency of the display panel, thereby reducing the power consumption of the display panel. Those skilled in the art can set the number of data compensation phases in the same picture update cycle according to the compensation effect of the actual panel. Figure 5 and Figure 6 4- Figure 6For example, for a display panel with a frame update period of 1s and a driving frequency of the light-emitting control signal Emit in the display panel of 60hz, it can be set that one to three data compensation stages A are included in the same frame update period, that is, one to three data compensation frames, and a data writing stage B is set immediately after the data compensation stage, that is, one data writing frame, and the stages after the data writing stage are all set as data holding stages C, that is, multiple data holding frames.

[0055] Furthermore, it should be noted that the data write phase is a crucial phase in the display panel's image display, determining the display brightness of the pixel units throughout the entire image update cycle. In addition to the data write phase, the image update cycle provided in the above embodiment also includes a data compensation phase and a data hold phase. The data hold phase can reduce the number of data write phases, primarily for reducing the drive frequency and panel power consumption. Furthermore, in embodiments of the present invention, one of the purposes of adding the data compensation phase before the data write phase is to improve the buffering process of the panel brightness within a single image update cycle. Those skilled in the art will appreciate that, during the entire drive process of the display panel, i.e., during multiple image update cycles, in addition to including the data compensation and data hold phases in at least one image update cycle, other image update cycles may also be configured to not include the data compensation and data hold phases. In this case, at least one image update cycle includes only the data write phase, and this image update cycle is driven in a high-frequency drive mode. As will be analyzed below, this image update cycle is referred to herein as a high-frequency drive image update cycle, and the frequency of the image update cycle also increases accordingly.

[0056] For example, if the frame update cycle frequency of a high-frequency drive is 60 Hz, there are 60 frames per second, each of which is a data writing phase. The frequency of the data writing phase is 60 Hz, and the frame update cycle frequency is also 60 Hz. However, in the embodiment provided in this application, when a low-frequency drive is used, although a frame update cycle still includes 60 frames, that is, 60 phases (i.e., the total number of data writing phases, data holding phases, and data compensation phases in a frame update cycle is 60), the target data voltage can be written only once. In this case, the frequency of the data writing phase is reduced to 1 Hz, and the frame update cycle frequency is equivalent to 1 Hz.

[0057] Furthermore, it should be noted that while the screen may change during the data hold phase in the embodiments of this application, the period of time encompassing the data hold phase alone is not considered a separate screen update cycle. A complete period encompassing the data write phase, data hold phase, and data compensation phase is considered a screen update cycle under the low-frequency drive conditions described herein.

[0058] Furthermore, unless otherwise specified, the image update period referred to below is the image update period under low-frequency driving.

[0059] Furthermore, the inventors have discovered through research that, in the actual display panel, during the screen switching process, although there is a hysteresis effect in the pixel driving circuit driving transistor, the extent of the hysteresis effect is related to the screen displayed by the display panel. Specifically, the time period significantly affected by the hysteresis effect of the driving transistor is when the brightness of the current screen update cycle is greater than the brightness of the previous screen update cycle. At this time, for the pixel unit and the pixel driving circuit, it is necessary to write a lower data voltage signal to the pixel driving circuit so that the driving transistor in the pixel driving circuit generates a higher driving current during the light-emitting process, thereby driving the light-emitting diode to emit light with a higher brightness. However, due to the hysteresis effect of the driving transistor, in the early data writing stage of the current screen update cycle, the threshold voltage Vth of the driving transistor is greatly offset, the generated driving current is small, and it cannot be driven normally. At this time, the brightness of the pixel unit will be lower than the target brightness, which will cause the screen display brightness of the current screen update cycle to be unsatisfactory and the display effect to be poor.

[0060] Based on this, optionally, in the driving method of the display panel provided in an embodiment of the present invention, the multiple picture update cycles include at least one first picture update cycle and at least one second picture update cycle; the brightness of the first picture update cycle is greater than the brightness of the previous picture update cycle, and the first picture update cycle includes the data writing stage, the data holding stage, and the data compensation stage; the brightness of the second picture update cycle is less than or equal to the brightness of the previous picture update cycle, and the first picture update cycle includes the data writing stage and the data holding stage. In other words, when the brightness of the current picture update cycle is greater than the brightness of the previous picture update cycle, the current picture update cycle includes the data compensation stage, the data writing stage, and the data holding stage; when the brightness of the current picture update cycle is less than or equal to the brightness of the previous picture update cycle, the current picture update cycle includes the data writing stage and the data holding stage.

[0061] When the brightness of a first frame update cycle is greater than that of a previous frame update cycle, the display panel's brightness switches. Due to the hysteresis effect of the drive transistor, the actual brightness is lower than the target brightness when writing data at the target voltage. Therefore, in addition to the data writing phase and the data holding phase, a data compensation phase is also provided in the first frame update cycle. Through data compensation, a higher brightness can be achieved during the data compensation phase, resulting in a significant brightness improvement during the frame switching process and achieving the target brightness more quickly. When the brightness of a second frame update cycle is less than or equal to that of the previous frame update cycle, the second frame update cycle only includes the data writing phase and the data holding phase, and the data compensation phase is omitted. Conversely, when the display screen switches from high brightness to low brightness, that is, in the adjacent nth frame update cycle and the n+1th frame update cycle, the nth frame update cycle is a high brightness screen and the n+1th frame update cycle is a low brightness screen, the drive current of the pixel drive circuit is relatively high during the nth frame update cycle, and the gate-source voltage of the drive transistor is relatively high. During the n+1th image update cycle, the pixel driver circuit's drive current decreases, and the gate-source voltage of the driver transistor decreases. That is, the gate-source voltage of the driver transistor decreases. At this time, the driver transistor's current decreases, and the driver transistor's threshold voltage Vth does not significantly shift. The driver transistor's electrical performance remains relatively stable, eliminating the need for data compensation.

[0062] Through this embodiment, brightness compensation can be performed in a targeted manner on each picture update cycle of the display panel to ensure that the actual brightness of the display panel in each picture update cycle meets the target brightness requirements, thereby improving the display effect of the display panel and avoiding flickering of the display panel; at the same time, by selectively adding a data compensation stage in a specific picture update cycle, the number of times the data writing unit writes data signals in other picture update cycles can be reduced, thereby reducing the power consumption of the entire display panel.

[0063] The present invention provides a variety of implementation methods for setting the compensation data voltage value in the data compensation phase of the image update cycle. Figure 4 Optionally, the same screen update cycle includes multiple data compensation stages A, the multiple data compensation stages A include a first data compensation stage A1 and a second data compensation stage A2, the first data compensation stage A1 is before the second data compensation stage A2; the compensation data voltage written in the second data compensation stage A2 is greater than the compensation data voltage written in the first data compensation stage A1.

[0064] like Figure 4As shown, at this time, the first data compensation stage A1 precedes the second data compensation stage A2, and the corresponding compensated data voltages Vdata1 and Vdata2 for these two stages are less than each other. It can be understood that as the data compensation stages progress, the electrical performance of the driving transistors in the pixel driving circuit gradually stabilizes, and the impact of transistor threshold drift on display brightness decreases. At this time, by setting the compensated data voltage in the second data compensation stage to be lower than the compensated data voltage in the first data compensation stage, the actual brightness of the screen can be guaranteed not to exceed the target brightness of the current screen update cycle, ensuring a stable and gradual brightness transition.

[0065] Optional, continue to refer to Figure 4 , the same frame update cycle includes multiple data compensation phases A, and the multiple data compensation phases A are arranged in chronological order; the compensation data voltages Vdata written in the multiple data compensation phases A increase in sequence. Figure 4 It can be seen from the brightness of the data compensation stage shown in the figure that by setting the compensation data voltages written corresponding to the multiple data compensation stages to increase in sequence, the theoretical corresponding screen display brightness gradually decreases, while the actual brightness will gradually increase with the data compensation. Finally, the compensation voltage increases to the target data voltage, and the screen brightness is also increased to the target brightness corresponding to the current screen update cycle.

[0066] Of course, considering that the actual impact of the hysteresis effect of the driving transistor needs to be determined based on simulation or experiment, when setting multiple data compensation stages, the compensation data voltage corresponding to individual local data compensation stages may also decrease. Under the condition of ensuring that the compensation data voltage of multiple data compensation stages shows an overall increasing trend, the increase of the compensation data voltage corresponding to any two adjacent data compensation stages can be unlimited.

[0067] Optionally, in another embodiment of the present invention, the same screen update cycle can be set to include multiple data compensation stages, the multiple data compensation stages include a third data compensation stage and a fourth data compensation stage, the third data compensation stage is before the fourth data compensation stage; the compensation data voltage written in the fourth data compensation stage is equal to the compensation data voltage written in the third data compensation stage. Figure 7 This is a timing diagram of another display panel driving method provided by an embodiment of the present invention, and the following reference is made to Figure 7 The compensated data voltage in the data compensation phase of this embodiment is specifically described. First, the same screen update cycle includes a data compensation phase A, a data writing phase B, and a data retention phase C. The data compensation phase A precedes the data writing phase B.

[0068] by Figure 7Taking the third data compensation phase A3 and the fourth data compensation phase A4 as an example, the third data compensation phase A3 is located before the fourth data compensation phase A4, and the compensation data voltages Vdata3 and Vdata4 corresponding to the two phases are respectively Figure 4 It can be seen from the embodiment shown that with the compensation in the data compensation stage, the electrical performance of the driving transistor in the pixel driving circuit gradually stabilizes. By setting the compensation data voltages corresponding to the multiple data compensation stages to be written in sequence, the theoretical corresponding screen display brightness gradually decreases, while the actual brightness will gradually increase with the data compensation, and finally the compensation voltage increases to the target data voltage. At the same time, the screen brightness is also increased to the target brightness corresponding to the current screen update cycle. Based on this, those skilled in the art can reasonably set the voltage value of the data compensation voltage written in the data compensation stage, so as to achieve the same compensation data voltage in multiple data compensation stages before the data writing stage, that is, to set Vdata3 to be equal to Vdata4. Figure 7 From the brightness of the data compensation stage shown in , it can be seen that, on the basis of ensuring that the voltage value of the data compensation voltage is less than the target data voltage, that is, on the basis of ensuring that the brightness corresponding to the data compensation voltage in theory is higher than the target brightness, the voltage values ​​of the data compensation voltages Vdata3 and Vdata4 can be reasonably increased, and the theoretically corresponding brightness can be reduced, so as to ensure that after the electrical performance of the driving transistor is stable, the brightness in the data compensation stage will not exceed or significantly exceed the target brightness, thereby ensuring the stable change of the brightness in the data compensation stage and avoiding flickering of the screen.

[0069] like Figure 7 In the third data compensation stage A3 and the fourth data compensation stage A4 shown, since the written compensation data voltage is the same, the data writing unit does not need to change the output value of the compensation data voltage during the process of writing the compensation data voltage in the two data compensation stages, which can reduce the complexity of the data writing unit outputting the data voltage and reduce the calculation amount of the data writing unit, thereby reducing the power consumption of the data writing unit to a certain extent.

[0070] Further optionally, at least one data hold phase can be provided between the third data compensation phase and the fourth data compensation phase. The data hold phase C is used to display the image according to the data voltage written in the previous data writing phase B or data compensation phase C. When at least one data hold phase C is provided between the third data compensation phase A3 and the fourth data compensation phase A4, the data hold phase C can maintain the brightness of the third data compensation phase A3 to maintain the image display. At this time, the driver transistor of the pixel driver circuit maintains the same external state, i.e., the gate-source voltage, during the data hold phase C as during the third data compensation phase A3. Therefore, the data hold phase C can not only compensate for the brightness of the pixel unit or display panel, but also reduce the offset of the threshold voltage Vth of the driver transistor, thereby stabilizing the electrical performance of the driver transistor. Furthermore, since the data hold phase C does not require the writing of the data compensation voltage, the number of data writes to the data write unit is reduced, thereby further reducing power consumption.

[0071] In some optional embodiments of the present application, various examples are provided regarding the relationship between the compensation data voltages during multiple data compensation phases within a single frame update cycle. Optionally, when a single frame update cycle includes multiple data compensation phases, the compensation data voltages corresponding to the multiple data compensation phases can be arranged to form an arithmetic progression, a geometric progression, or an exponential progression.

[0072] For compensation data voltages that follow an arithmetic, geometric, or exponential progression, the theoretical corresponding brightness over multiple data compensation stages also follows an arithmetic, geometric, or exponential progression. Simultaneously, due to data compensation, the hysteresis effect of the drive transistor gradually weakens, allowing the theoretical brightness during the data compensation stages to be set to a decreasing trend. By setting the compensation data voltage to follow an increasing trend, the theoretical corresponding brightness can be set to follow a decreasing trend. Ultimately, as the compensation data voltage reaches the target data voltage, the electrical performance of the drive transistor stabilizes, and the display panel achieves the target brightness.

[0073] Furthermore, on this basis, it is necessary to reasonably set the specific value of the compensation data voltage so that the appropriate compensation data voltage can be used to effectively buffer the hysteresis effect of the drive transistor and improve the brightness during the compensation phase. Specifically, optionally, the first data compensation phase of multiple data compensation phases in the same frame update cycle is used as the initial data compensation phase. The compensation data voltage written in the initial data compensation phase can be set to Vdata = Vdata0 × L1 / L2; where L2 is the target brightness of the frame update cycle, Vdata0 is the target data voltage corresponding to the target brightness of the frame update cycle, and L1 is the actual brightness when the target data voltage is written to the pixel unit during the initial data compensation phase.

[0074] It is understandable that in the initial data compensation stage, when the target data voltage is written to the pixel unit, the brightness of the pixel unit or display panel will not reach the target brightness corresponding to the target data voltage due to the hysteresis effect of the driving transistor, that is, the brightness L1 is significantly lower than the target brightness. From another perspective, the brightness L1 actually records the degree of the hysteresis effect of the driving transistor. Since the brightness and data voltage are negatively correlated, the ratio of the brightness L1 to the target brightness L2 is actually equal to the ratio of the target data voltage Vdata0 to the theoretical data voltage value Vdata1 of L1. Using this ratio as the ratio of the compensated data voltage Vdata written in the initial data compensation stage to the target data voltage Vdata0, we can obtain Vdata=Vdata0. 2 / Vdata1. Therefore, it can be understood that the compensation data voltage Vdata written in the initial data compensation stage can make the theoretical brightness in the data compensation stage greater than the target brightness, reducing the hysteresis effect that reduces the brightness of the picture while specifically compensating for the brightness impact caused by the hysteresis effect of the driving transistor.

[0075] In addition, optionally, the first data compensation stage among multiple data compensation stages of the same picture update cycle is the initial data compensation stage; the compensation data voltage Vdata written in the initial data compensation stage is Vdata=KVdata'; wherein Vdata' is the theoretical data voltage corresponding to the target brightness of the previous picture update cycle, 0<K<1.

[0076] As described in the above embodiment, the addition of a data compensation phase to a frame update cycle requires that the brightness of the previous frame update cycle be lower than that of the current frame update cycle. Therefore, to ensure that the data compensation process in the current frame update cycle is based on the brightness of the previous frame update cycle, the compensation data voltage written during the initial data compensation phase can be set to be proportional to the data voltage of the previous frame update cycle. The specific value of coefficient K needs to be determined based on the actual compensation effect of Vdata. Those skilled in the art can determine this through experiments and simulations based on this relationship, and no further limitations are imposed here.

[0077] Furthermore, if the same frame update cycle includes N data compensation stages, the data voltage corresponding to the nth data compensation stage can be set to Vdata_n=Vdata0-(N-n+1)*x, where Vdata0 is the target data voltage corresponding to the target brightness of the current frame update cycle, n and N are both positive integers, 1≤n≤N, and x=0.5V~2V.

[0078] At this time, the compensation data voltage corresponding to the N data compensation stages is actually an arithmetic progression, and the tolerance of the arithmetic progression is x. Setting the tolerance x in the range of 0.5V to 2V can ensure that the data voltage value compensated in the data compensation stage changes slowly, and according to Figure 3 As can be seen from the timing diagram shown, after providing the equidistant and increasing compensation data voltage, the brightness of the display panel can not only be gradually increased, but the brightness of its initial data compensation stage is also maintained at a high level, so that the picture brightness of the entire picture update cycle is relatively closer to the target display brightness, effectively avoiding the flicker of the picture.

[0079] Figure 8 This is a timing diagram of another display panel driving method provided by an embodiment of the present invention, referring to Figure 8 In another embodiment of the present invention, taking the example of a frame update cycle including multiple data compensation phases A, the frame update cycle sequentially includes the 1st to the Nth data compensation phases A. The difference between the compensation data voltages written corresponding to the ath data compensation phase A and the a+1th data compensation phase A can be set to ΔX1; the difference between the compensation data voltages written corresponding to the bth data compensation phase A and the b+1th data compensation phase A can be set to ΔX2. ΔX1>ΔX2, a and b are both positive integers greater than 0, and a+1≤b. Furthermore, a, a+1, b, and b+1 are all no greater than N.

[0080] The relationship between the a-th data compensation phase A and the a+1-th data compensation phase A is that the a+1-th data compensation phase is adjacent to the a-th data compensation phase and is located after the a-th data compensation phase. The a+1-th data compensation phase being adjacent to the a-th data compensation phase means that there are no other data compensation phases between the a-th and a+1-th data compensation phases, but at least one data hold phase may be provided. The data hold phase is used to display the data voltage written in the previous data writing phase or data compensation phase, during which the display image of the a-th data compensation phase is maintained. Furthermore, the compensation data voltage values ​​written in the a+1-th data compensation phase and the a-th data compensation phase referred to herein are gradually changing compensation data voltage values, and the compensation data voltage gradually increases during these two data compensation phases. Similarly, the relationship between the b-th data compensation phase and the b+1-th data compensation phase is that the b+1-th data compensation phase is adjacent to the b-th data compensation phase and is located after the b-th data compensation phase. Furthermore, taking the example of a frame update cycle including N data compensation phases, a+1≤N, b+1≤N. In this case, the compensation data voltage written during the data compensation phase not only increases, but also the difference between two adjacent compensation data voltages decreases. In other words, the theoretical brightness difference corresponding to the compensation data voltages decreases, and the brightness is getting closer and closer to the target brightness.

[0081] The inventors have discovered that over time, the drift of the threshold voltage of the drive transistor approaches stability, and the trend of change in electrical performance slows down. In the embodiments of the present invention, by providing a compensation data voltage with increasingly smaller differences during the data compensation phase, the trend of change slows down, thereby matching the decreasing hysteresis effect of the drive transistor and the decreasing change in the threshold voltage Vth of the drive transistor. This results in increasingly smaller brightness compensation, gradually approaching a normal state, and achieving normal drive display. This approach not only avoids insufficient brightness compensation during initial data compensation, resulting in a small increase in actual brightness, but also prevents excessive compensation in later data, resulting in actual brightness exceeding the target brightness.

[0082] In addition, considering the actual data compensation duration, there should be a certain upper limit on the proportion of the data compensation phase in a screen update cycle to ensure that it does not affect normal screen display. Specifically, the proportion of the data compensation phase can be appropriately reduced according to the degree of influence of the hysteresis effect of the driving transistor. In an embodiment of the present invention, the same screen update cycle can be set to include N data compensation phases, M data retention phases, and P data writing phases; where N / (N+M+P)≤1 / 6, and N, M, and P are all integers greater than or equal to 1.

[0083] At this point, for a 1s refresh cycle and a 60Hz drive frequency, the data compensation phase should account for less than or equal to 10 frames. Clearly, the data compensation phase does not affect the duration of the target brightness display. The human eye perceives a smaller difference between the perceived brightness and the target brightness, resulting in a more accurate display and better visual quality.

[0084] As shown above, in the image update cycle, the data compensation phase is centrally located before the data writing phase, while the data retention phase is located after the data writing phase. This is only one embodiment of the present invention. Regarding the actual location of the data compensation phase and the data retention phase during the driving process, the present invention also provides various implementations.

[0085] Optionally, the same screen update cycle includes N data compensation phases, M data retention phases, and P data writing phases; wherein N, M, and P are integers greater than or equal to 1; any two adjacent data compensation phases can be separated by n data retention phases, wherein 0≤n≤M.

[0086] The data hold phase is used to display the data voltage written in the previous data write phase or data compensation phase, thereby maintaining the display image of the previous data write phase or data compensation phase. It is understandable that by setting at least one data hold phase between two adjacent data compensation phases, the image displayed in the data compensation phase can be refreshed with a delay. During the display process at the compensated brightness, the electrical performance of the driving transistor can also gradually stabilize, thereby achieving brightness compensation. Specifically, when there is no data hold phase between any two data compensation phases, it is a solution in which the data compensation phase is concentrated before the data write phase, which is not described in detail here. Figure 9 This is a timing diagram of another display panel driving method provided by an embodiment of the present invention, referring to Figure 9 When the number of data hold stages C between any two data compensation stages A is greater than zero, due to the limited number of data hold stages, a maximum of M data hold stages can be set between two adjacent data compensation stages. Furthermore, considering that the brightness of the display panel during the data compensation stage is lower than the target brightness, the number of data hold stages between two adjacent data compensation stages can be appropriately set to ensure that the overall brightness of the entire screen update cycle is closer to the target brightness. Furthermore, at least some data hold stages should be placed after the data write stage. In this case, the image at the target brightness achieved during the data write stage can be delayed for display during the data hold stage, thereby ensuring that the entire screen update cycle is closer to the target brightness. In schemes where all data hold stages are placed after the data write stage, the data voltage signal written during the data write stage and stored in the pixel driver circuit may be lost due to the long data hold period without data voltage being written. Alternatively, due to signal crosstalk and other factors, the data voltage that actually activates the drive transistor to generate drive current during the data hold stage may be inaccurate or uncontrollable. This can cause the actual display image during the data hold stage to differ from the image displayed during the data write stage. In this embodiment, by inserting a data hold phase between data compensation phases, or between a data compensation phase and a data write phase, uncontrollable images caused by prolonged periods of continuous data hold phases can be avoided, ensuring that the display brightness throughout the entire image update cycle approaches the target brightness with relative accuracy. Furthermore, the data compensation phase and the data write phase can be more evenly distributed throughout the image update cycle, reducing the pressure of intensive data voltage writing in the early stages of the image update cycle.

[0087] Specifically, in embodiments of the present invention, a single screen update cycle can include multiple data compensation phases and multiple data retention phases, with at least one data retention phase separating at least two data compensation phases. Furthermore, embodiments of the present invention provide specific solutions for the number and location of data retention phases between data compensation phases.

[0088] Among them, continue to refer to Figure 9 Optionally, any two adjacent data compensation stages can be separated by the same number of data hold stages. In this case, the brightness compensated in each data compensation stage can be refreshed with the same degree of delay, meaning that the image can be displayed at the compensated brightness, thereby ensuring that the electrical performance of the drive transistor gradually stabilizes during this process. Furthermore, since the data hold stage is added after the data compensation stage, the data hold stage provides the compensated brightness without requiring the data voltage to be written to the pixel cell. This reduces the number of times the compensated data voltage is written, thereby reducing the power consumption of the display panel.

[0089] Figure 10 This is a timing diagram of another display panel driving method provided by an embodiment of the present invention. Figure 9 and Figure 10 The similarities between this embodiment and the above embodiment are not further described. In this embodiment, the number of data retention phases C between two adjacent data compensation phases A within the same frame update cycle can also be set to increase. In this embodiment, by gradually compensating data writing, the electrical performance of the drive transistor tends to stabilize in the later data compensation phases of the multiple data compensation phases, and the image brightness of the display panel tends to the target brightness. Taking the example of a frame update cycle including multiple data compensation phases, and the frame update cycle sequentially including the 1st to Nth data compensation phases, that is, the difference between the actual brightness of the pixel unit during the ath data compensation phase and the target brightness is greater than the difference between the actual brightness of the pixel unit during the a+1th data compensation phase and the target brightness. In this embodiment, by further reducing the number of data retention phases between the ath data compensation phase and the a-1th data compensation phase, it is possible to avoid excessive data retention phases holding images with a large difference from the target brightness. Instead, more data retention phases are set during the phases when the electrical performance of the drive transistor gradually stabilizes, so that the image of the entire frame update cycle is closer to the target display brightness. Moreover, with the compensation in the data compensation stage, the drift trend of the driving transistor threshold voltage Vth slows down. To match this slowing trend, the number of data compensation stages in the later stages of a picture update cycle can be appropriately reduced, and the arrangement density does not need to be very dense. At this time, the number of data writes in the data write unit can be appropriately reduced, thereby reducing the power consumption of the display device.

[0090] In addition, as described above, since the brightness of the display panel during the data compensation phase is lower than the target brightness, in order to ensure that the overall brightness of the entire screen update cycle is closer to the target brightness, the positions of the data compensation phase and the data writing phase in the entire screen update cycle can be reasonably set so that the brightness of the data compensation phase is effectively compensated and quickly reaches the target brightness. The target brightness image achieved during the data writing phase can also be maintained continuously during the screen update cycle, and a higher time percentage can be obtained. Based on this, in an embodiment of the present invention, the same screen update cycle can be set to include N data compensation phases, M data retention phases, and P data writing phases; wherein N, M, and P are all integers greater than or equal to 1; and between any data compensation phases, there are M*a% / N data retention phases, wherein 30%≤a%≤50%, M*a% is an integer greater than or equal to 1, and M*a% / N is an integer greater than or equal to 1.

[0091] The M*a% data hold phases are essentially the number of data hold phases preceding the data write phase. In other words, M*a% is evenly divided according to the number of data compensation phases, N, and distributed after each data compensation phase. In this case, a data hold phase follows each data compensation phase, and the brightness compensated in each data compensation phase can be refreshed with a delay. Simultaneously, the remaining data hold phases can also be evenly divided among the P data write phases, placing them after each data write phase, allowing for a delayed refresh of the image during each data write phase.

[0092] Of course, in the same screen update cycle, generally only one data writing phase can be set. Therefore, except for the data holding phase set before the data writing phase, the remaining data holding phases can simultaneously maintain and display the target brightness image of the data writing phase.

[0093] It should be noted that when a% is set to a small value, the data retention stages after each data compensation stage are fewer, and the compensated brightness cannot be maintained. At the same time, when a% is set to a large value, the target brightness of the screen during the data writing stage is maintained for a longer time, and the difference between the overall brightness of the screen and the maintained brightness during the entire screen update cycle is small. Another situation that needs to be explained here is that when a% is set to a large value, the difference between the overall brightness of the screen and the maintained brightness is small. However, when too many data retention stages are set to maintain the target brightness of the data writing stage, there is a certain leakage current in the driving transistor of the pixel driving circuit, which will cause the maintained screen brightness to decrease after multiple data retention stages, thus showing a certain difference from the target brightness. Based on the above reasons, the ratio value of a% can be specifically set within the range of 30% to 50%, and the specific value of a% can be set based on the actual brightness compensation situation and the overall brightness of the entire screen update cycle.

[0094] Through this embodiment, it is possible to add a data holding stage after the data compensation stage, so that the data holding stage has the compensation brightness while not needing to write the compensation data voltage to the pixel unit, thereby saving the number of times the compensation data voltage is written and reducing the power consumption of the display panel; it is also possible to appropriately distribute the data compensation stage and the data writing stage in the early and middle stages of the picture update cycle, thereby reducing the pressure of intensively writing data voltages in the early stage of the picture update cycle; and, by setting a relatively small number of data holding stages after the data writing stage, it is possible to avoid the uncontrollable picture that is maintained for too long during the data holding stage, thereby ensuring that the display brightness of the entire picture update cycle is relatively accurately closer to the target brightness; in addition, a relatively small number of data holding stages can ensure that the maintained picture brightness is closer to the picture brightness during the data writing stage.

[0095] Furthermore, the driving method of the display panel provided in an embodiment of the present invention also involves the design of a specific pixel driving circuit structure in the display panel. First, in the display panel, a pixel driving circuit is provided for each pixel unit, that is, the display panel includes multiple pixel driving circuits corresponding to the pixel units one by one; wherein the pixel driving circuit can be specifically provided to include a first pixel driving circuit and a second pixel driving circuit, the driving transistor of the first pixel driving circuit is a silicon-based transistor, and the driving transistor of the second pixel driving circuit is an oxide semiconductor transistor; in the same picture update cycle, the number of data compensation stages of the first pixel driving circuit can be set to be different from the number of data compensation stages of the second pixel driving circuit.

[0096] It is understandable that due to their different structures, silicon-based transistors and oxide semiconductor transistors have different electrical properties and different hysteresis effects. Based on this, for pixel driving circuits containing different driving transistors, it is necessary to set the number of data compensation stages to different proportions during the display driving process, so that differentiated data compensation can be performed for pixel driving circuits containing different driving transistors to ensure that the corresponding pixel units reach the target brightness as soon as possible, thereby making the picture brightness more uniform throughout the entire picture update cycle. Generally speaking, compared with oxide semiconductor transistors, silicon-based transistors have poor hysteresis characteristics. When performing data compensation, the number of data compensation stages can be set to a slightly larger proportion, thereby improving the degree of brightness compensation.

[0097] Similarly, for transistors made of the same material, their electrical properties can vary significantly due to the different transistor types, and the hysteresis effects can also differ. Based on this, in the following scenario, the display panel includes multiple pixel driving circuits corresponding one-to-one to the pixel units, the pixel driving circuits including driving transistors; the driving transistors including N-type silicon-based transistors and P-type silicon-based transistors; the pixel driving circuits including a third pixel driving circuit and a fourth pixel driving circuit, the third pixel driving circuit including an N-type silicon-based transistor and the fourth pixel driving circuit including a P-type silicon-based transistor; it can be configured that, in the same picture update cycle, the proportion of the number of data compensation stages of the third pixel driving circuit is different from the proportion of the number of data compensation stages of the fourth pixel driving circuit.

[0098] At this time, by performing differentiated data compensation for pixel driving circuits including different types of driving transistors, it is possible to ensure that the corresponding pixel units reach the target brightness as quickly as possible, thereby making the picture brightness more uniform throughout the entire picture update cycle.

[0099] Furthermore, it can be set that in the same picture update period, the number of data compensation phases of the third pixel driving circuit accounts for X, and the number of data compensation phases of the fourth pixel driving circuit accounts for Y, wherein X≥Y.

[0100] Taking low-temperature polysilicon transistors as an example, N-type silicon-based transistors have a more pronounced hysteresis effect. Therefore, when setting data compensation stages in the image update cycle, a larger number of data compensation stages can be set to improve the brightness compensation effect. P-type silicon-based transistors have relatively better electrical performance and a less pronounced hysteresis effect, so a smaller number of data compensation stages can be set in the image update cycle.

[0101] In another embodiment of the present invention, the display panel includes a plurality of pixel driving circuits corresponding one-to-one to the pixel units, the pixel driving circuits including driving transistors; the driving transistors including N-type silicon-based transistors. For the pixel driving circuits including N-type silicon-based transistors, in one image update cycle, the number of data compensation phases, data retention phases, and data writing phases satisfies: N / (N+M+P)≤1 / 6.

[0102] In another embodiment of the present invention, the display panel includes a plurality of pixel driving circuits corresponding one-to-one to the pixel units, the pixel driving circuits including driving transistors; the driving transistors including P-type silicon-based transistors. For the pixel driving circuits including P-type silicon-based transistors, in one image update cycle, the number of data compensation phases, data retention phases, and data writing phases satisfies: N / (N+M+P)≤1 / 12.

[0103] Similarly, N-type silicon-based transistors have poor electrical performance and a more pronounced hysteresis effect. Therefore, when setting data compensation stages in the picture update cycle, a larger number of data compensation stages can be set to improve the brightness compensation effect. For P-type silicon-based transistors, the hysteresis effect is relatively insignificant, and a smaller number of data compensation stages can be set in the picture update cycle. Taking 1s as a picture update cycle and a driving frequency of 60hz as an example, a picture update cycle includes 60 frames. For a pixel driving circuit of an N-type silicon-based transistor, the data compensation stage during the driving process can be set to include 10 frames. For a pixel driving circuit of a P-type silicon-based transistor, the data compensation stage during the driving process can be set to include 5 frames.

[0104] According to the above, based on the types of driving transistors in different pixel driving circuits, the number ratio of the data compensation stage is increased for driving transistors with more serious hysteresis effects, or the number ratio is set in a targeted manner. This can improve the degree of data compensation in the data compensation stage, so that each pixel unit in the display panel can obtain appropriate brightness compensation in the same picture update cycle, thereby avoiding the brightness difference of each pixel unit due to the influence of different degrees of hysteresis effects, making the brightness of the pixel unit more accurate, and ensuring the brightness uniformity of the display panel.

[0105] Furthermore, embodiments of the present invention also discuss and design the degree of data compensation within different screen update cycles. Specifically, any two adjacent screen update cycles include a first screen update cycle and a second screen update cycle; the first screen update cycle includes N1 data compensation phases, M1 data retention phases, and P1 data writing phases; the second screen update cycle includes N2 data compensation phases, M2 data retention phases, and P2 data writing phases; the first screen update cycle and the second screen update cycle can be configured to satisfy the following conditions: N1+M1+P1<N2+M2+P2, N1<N2.

[0106] Where N1+M1+P1 is the total number of phases in the first frame update cycle, and N2+M2+P2 is the total number of phases in the second frame update cycle. When N1+M1+P1 is less than N2+M2+P2, the total number of phases in the second frame update cycle is greater. Clearly, when the first and second frame update cycles include the same number of data compensation phases, the data compensation phases in the first frame update cycle account for a higher proportion of time. From the perspective of compensation time alone, the degree of data compensation in the first frame update cycle is higher than that in the second frame update cycle. To ensure the same degree of brightness compensation in each frame update cycle of the same display panel, and to achieve more uniform brightness compensation across all frame update cycles, the number of data compensation phases N2 in the second frame update cycle can be set to be greater than the number of data compensation phases N1 in the first frame update cycle. Furthermore, during the actual display panel image update process, the number of data compensation phases in the first and second frame update cycles can be set to satisfy N1 / (N1+M1+P1)=N1 / (N2+M2+P2).

[0107] Optionally, P1=P2=1.

[0108] The inventors further discovered that, due to differences in luminous efficiency, different color pixel units require different drive currents for the same target brightness during actual display driving. This means that different data voltages must be set and written. Based on this, in another embodiment of the present invention, the display panel includes a first color pixel unit and a second color pixel unit, and at the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is lower than the theoretical data voltage corresponding to the second color pixel unit.

[0109] Optionally, the compensation data voltage difference corresponding to two adjacent data compensation stages of the first color pixel unit may be set to be greater than the compensation data voltage difference corresponding to two adjacent data compensation stages of the second color pixel unit;

[0110] Alternatively, the compensation data voltage corresponding to the initial data compensation stage of the first color pixel is smaller than the compensation data voltage corresponding to the initial data compensation stage of the second color pixel;

[0111] Alternatively, the number of data compensation stages for the first color pixel is greater than the number of data compensation stages for the second color pixel.

[0112] It is understood that there is a first color pixel unit in the display panel whose luminous efficiency is lower than that of a second color pixel unit. For example, the first color pixel unit may be a blue pixel unit, and the second color pixel unit may be a red pixel unit or a green pixel unit. At the same target brightness, the driving current of the blue pixel unit needs to be higher than the driving current of the red or green pixel unit. Therefore, it is understood that the initial compensation data voltage of the blue pixel unit should be smaller. A smaller initial compensation data voltage corresponds to a higher theoretical brightness, thereby enabling the blue pixel unit to reach the target brightness faster.

[0113] On the other hand, it can be understood that the current variation of the blue pixel unit is relatively large. In order to stimulate the rapid stabilization of the threshold voltage of the blue pixel unit's drive transistor, the difference in the compensation data voltage of the blue pixel unit can be increased to match the variation trend of the blue pixel unit's current, thereby enabling the brightness of the blue pixel unit to change rapidly and achieve the same target brightness synchronously with the pixel units of other colors. Based on this, the rate of decrease of the compensation data voltage difference between two adjacent data compensation stages of the first color pixel unit can optionally be set to be greater than the rate of decrease of the compensation data voltage difference between two adjacent data compensation stages of the second color pixel unit, that is, the variation trend of the compensation data voltage of the blue pixel unit is made steeper.

[0114] On another level, it can be understood that the data compensation phase is primarily responsible for providing a compensated data voltage lower than the target data voltage, i.e., the corresponding theoretical brightness is higher, thereby improving the hysteresis of the threshold voltage of the driving transistor. Therefore, for blue pixel units, setting a greater number of data compensation phases can achieve a better burn-in effect on the hysteresis of the threshold voltage of the driving transistor of the blue pixel unit, allowing the threshold voltage of the driving transistor corresponding to the blue pixel unit to stabilize more quickly. Optionally, when the sum of the number of other phase sequences before the blue pixel data write phase is equal to the sum of the other frame sequences before the second color pixel data write phase, the number of data compensation frame sequences for the blue pixel unit can be set to be greater than the number of data compensation phase sequences for the second color pixel.

[0115] In some optional embodiments of the present application, similarities with the above-mentioned embodiments are not further described. However, to simplify the data compensation algorithm for different color pixel units and quantize the compensation data voltages written during the data compensation phase, embodiments of the present invention further employ an arithmetic progression relationship to quantify the magnitude relationship between the compensation data voltages written during multiple data compensation phases for different color pixel units. Specifically, during the data compensation phase, the compensation data voltages written to the first color pixel unit and the second color pixel unit corresponding to the data compensation phases are both arithmetic progressions, and are respectively a first arithmetic progression and a second arithmetic progression. The first arithmetic progression has a tolerance of d1, a number of terms of N1, and a first term of a1. The second arithmetic progression has a tolerance of d2, a number of terms of N2, and a first term of a2. Furthermore, the first and second arithmetic progressions may satisfy the following conditions: a1 = a2, d1 = d2, N1 < N2; or a1 = a2, d1 < d2, N1 = N2; or a1 < a2, d1 = d2, N1 = N2.

[0116] It is understandable that because the theoretical brightness during the data compensation phase is greater than the target brightness, the compensated data voltage is less than the target data voltage. Therefore, the first and second arithmetic progressions corresponding to the first and second color pixel units are both substantially increasing arithmetic progressions. Furthermore, because the theoretical data voltage of the first color pixel unit is less than the theoretical data voltage of the second color pixel unit at the same target brightness, the last term of the first arithmetic progression is less than the last term of the second arithmetic progression.

[0117] On this basis, to ensure that the compensation data voltages in the two arithmetic progressions synchronously reach the compensation data voltage of the last term and ensure uniform brightness across the display panel, the leading term and the tolerance can be set equal, i.e., a1 = a2, d1 = d2, and the number of terms in the first arithmetic progression can be set smaller than the number of terms in the second arithmetic progression, i.e., N1 < N2. In other words, when all other conditions are equal, the number of data compensation stages (N1) for the first color pixel can be set smaller than the number of data compensation stages (N2) for the second color pixel. This means that, in terms of the number of compensations alone, the first color pixel unit has a lower degree of data compensation. Because the target data voltage for the first color pixel unit is lower than that for the second color pixel unit, the first color pixel unit does not require excessive data compensation, while the second color pixel unit requires more data compensation. In this case, the first color pixel unit and the second color pixel unit can also synchronously reach their corresponding target data voltages and achieve the same target brightness.

[0118] Of course, in this embodiment, the first term and the number of terms can also be set to be equal, that is, a1 = a2, N1 = N2, and the tolerance of the first arithmetic progression can be set to be smaller than the tolerance of the second arithmetic progression, that is, d1 < d2. In other words, when other conditions are guaranteed to be equal, the compensation data voltage difference d1 corresponding to two adjacent data compensation stages of the first color pixel unit can be set to be smaller than the compensation data voltage difference d2 corresponding to two adjacent data compensation stages of the second color pixel unit. In other words, for the first color pixel unit, the compensation data voltage during its data compensation stage can increase faster. Because the target data voltage of the first color pixel unit is lower than the target data voltage of the second color pixel unit, it can be ensured that the first color pixel unit and the second color pixel unit reach the corresponding target data voltage synchronously and obtain the same target brightness.

[0119] Similarly, this embodiment can also set the tolerance and the number of terms to be equal, that is, d1=d2, N1=N2, and set the first term of the first arithmetic progression to be smaller than the first term of the second arithmetic progression, that is, a1<a2. In other words, when other conditions are guaranteed to be equal, the compensation data voltage a1 corresponding to the initial data compensation stage of the first color pixel can be set to be smaller than the compensation data voltage a2 corresponding to the initial data compensation stage of the second color pixel. That is, for the first color pixel unit, its initial compensation data voltage value in the data compensation stage is smaller. Since the target data voltage of the first color pixel unit is lower than the target data voltage of the second color pixel unit, setting the initial compensation data voltage value to be smaller can ensure that the first color pixel unit and the second color pixel unit synchronously reach the corresponding target data voltage and synchronously obtain the same target brightness.

[0120] It should be noted that the use of an arithmetic progression to quantify the magnitude relationship of the compensation data voltages of different color pixel units is based on the premise that the compensation data voltages are set as an arithmetic progression and that specific conditions in the arithmetic progression remain consistent. Only when the specific conditions are maintained the same can specific parameters in the arithmetic progression of the compensation data voltages of different color pixel units have a certain magnitude relationship. It is understandable that in other embodiments of the present invention, the compensation data voltages of different color pixel units may also satisfy other magnitude relationships, thereby adaptively adjusting and compensating for the hysteresis effect of the corresponding color pixel unit drive transistor, ensuring the stability of the drive transistor and the uniformity of the display. This will not be described in detail here.

[0121] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 2The display device includes: a display panel 100, the display panel includes a plurality of pixel units 110, the display panel 100 includes a plurality of picture update cycles, at least one picture update cycle includes a data writing phase, a data compensation phase and a data holding phase; the data compensation phase is located before the data writing phase; a scan driving unit 200, used to provide a gate scanning signal to each pixel unit in the data writing phase and the data compensation phase; a data writing unit 300, used to provide a gate scanning signal to the pixel unit and write a target data voltage in the data writing phase, the target data voltage being a theoretical data voltage corresponding to the target brightness of the current picture update cycle; and also used to provide a gate scanning signal to the pixel unit and write a compensation data voltage in the data compensation phase, the compensation data voltage being less than the target data voltage.

[0122] The display device is not limited to mobile phones, tablets and wearable products, but can also be used in computers, televisions, advertising screens, etc., which are not limited here. Among them, the display panel 100 generally needs to update the screen during the driving display process to present a continuous screen display. In the driving display process, multiple screen update cycles can be set, and each screen update cycle corresponds to displaying a screen with a certain brightness. In the display device of the embodiment of the present invention, a data writing phase, a data compensation phase and a data holding phase are set in at least one screen update cycle, wherein the data compensation phase is essentially a process of writing a compensation data voltage to the pixel unit. After the compensation data voltage is written in this process, the pixel unit is driven to display. However, the brightness of the pixel unit or display panel will be affected by the hysteresis effect of the driving transistor in the pixel driving circuit. At this time, the brightness of the pixel unit or display panel is actually inconsistent with the brightness corresponding to the compensation data voltage in theory. It can be understood by those skilled in the art that for an OLED display panel, the brightness of the pixel unit is positively correlated with the current flowing through the driving transistor in the pixel driving circuit, and the current flowing through the driving transistor is inversely proportional to the data voltage written to the pixel unit. Based on this, in the embodiment of the present invention, during the data compensation stage, the compensation data voltage written is set to be lower than the target data voltage. In theory, the brightness of the pixel unit or display panel will be greater than the target brightness of the current picture update cycle. Moreover, although the driving transistor of the pixel driving circuit also has a hysteresis effect, the actual brightness of the display panel can be improved by writing the data voltage according to the higher picture brightness. In other words, during the data compensation stage, a higher picture brightness can be obtained by writing a smaller compensation data voltage. Moreover, since the picture brightness is higher during the compensation stage, it is closer to the target brightness, and the time to reach the target brightness can be shortened to a certain extent. Therefore, in the picture update cycle, before reaching the target brightness, the difference in brightness change is relatively small, the brightness buffering time is shortened, and the target brightness can be reached faster, thereby ensuring the display effect of the picture.

[0123] The data writing stage refers to the process of writing the theoretical data voltage corresponding to the target brightness of the current picture update cycle into the pixel unit. Since the data writing stage needs to be set after the data compensation stage, through the data compensation process, the electrical performance of the driving transistor in the pixel driving circuit tends to be stable, and the threshold reaches the theoretical value. At this time, the data writing stage can realize the normal driving of the pixel driving circuit, and the pixel unit or display panel is displayed at the target brightness. The data holding stage is essentially to display with the target data voltage written in the data writing stage, or it can also be displayed with the compensated data voltage written in the data compensation stage. Therefore, the data holding stage should be set after the data writing stage or the data compensation stage. The data voltage written in the data writing stage or the data compensation stage can be stored in the capacitor of the pixel driving circuit, and there is no need to rewrite the data voltage in the data holding stage. In the process of refreshing the display of the pixel unit, it is only necessary to turn on and drive the pixel unit by providing a light-emitting control signal so that the display panel can maintain the picture.

[0124] A display device provided by an embodiment of the present invention comprises a display panel, a scan driver unit, and a data write unit. The display panel includes a plurality of pixel units. The display panel comprises a plurality of picture update cycles, wherein at least one picture update cycle comprises a data write phase, a data hold phase, and a data compensation phase. The data compensation phase is provided before the data write phase. The scan driver unit is configured to provide a gate scan signal to each pixel unit during the data write phase and the data compensation phase. The data write unit is configured to provide a gate scan signal to the pixel unit and write a target data voltage during the data write phase, wherein the target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle. The data write unit is further configured to provide a gate scan signal to the pixel unit and write a compensation data voltage during the data compensation phase, wherein the compensation data voltage is less than the target data voltage. This allows the display panel to implement a data compensation process in at least one picture update cycle, thereby improving the display brightness of the display panel during the data compensation process. The embodiment of the present invention can solve the problem of picture flicker caused by the hysteresis effect of transistors, compensate for the defect of unstable electrical performance of transistors, ensure that the picture reaches the target brightness of the current picture update cycle as soon as possible when switching, reduce the difference in picture brightness within the same picture update cycle, and thus improve the picture display quality and effect.

[0125] In the display device provided above, its display panel includes a plurality of pixel driving circuits corresponding one to one with the pixel units. The driving process of the display panel is essentially a process of driving each pixel driving circuit. The embodiment of the present invention also provides a variety of pixel driving circuits. In the display panel and the driving method thereof as above, a specific process including a data compensation phase, a data writing phase and a data holding phase can be set for the same picture update cycle, which will be introduced in detail below. First of all, each data compensation phase, data writing phase and data holding phase in the same picture update cycle can actually be equivalent to the driving process of one frame of the display panel. In the corresponding one-frame driving process, for each pixel unit and pixel driving circuit on the display panel, the driving process of the one-frame picture includes multiple driving periods. Figure 11 is a timing diagram of the data compensation phase provided by an embodiment of the present invention, Figure 12 is a timing diagram of the data writing phase provided by an embodiment of the present invention, Figure 13 This is a timing diagram of the data retention phase provided by an embodiment of the present invention, refer to Figure 11-13 Specifically, the data compensation phase includes at least the compensation data voltage writing period b1 and the luminous period c; the data writing phase includes at least the target data voltage writing period b2 and the luminous period c; and the data holding phase includes at least the luminous period c.

[0126] The following first takes the data writing stage as an example to explain the target data voltage writing period and the light emitting period. Figure 3 The pixel driving circuit includes: a driving transistor T, a data writing module 20, a light emitting control module (51 and 52) and a threshold compensation module 30; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor is connected to the second node N2, and the second terminal T2 of the driving transistor is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2; the threshold compensation module 30 is electrically connected between the first node N1 and the third node N3; the data writing module 20 is used to provide the data signal input by the data signal terminal Vdata to the driving transistor T; the threshold compensation module 30 is used to compensate the threshold voltage Vth of the driving transistor T to the first node N1; the light emitting control module (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light emitting element 60, and the light emitting control module (51 and 52) is used to control whether the driving current flows through the light emitting element 60.

[0127] Specifically, the pixel driving circuit also includes an initialization module 10, a reset module 70 and a storage capacitor Cst, wherein the initialization module 10 is electrically connected between the initialization signal terminal Vref and the first node N1; the initialization module 10 is used to provide an initialization signal of the initialization signal terminal Vref to the first node N1 during the initialization stage; the reset module 70 is electrically connected between the first scan signal terminal S1 and the anode of the light-emitting element 60, and the reset module 70 is used to provide a reset signal to the anode of the light-emitting element 60 during the reset stage; the gate G of the driving transistor T and the first plate a of the storage capacitor Cst are electrically connected to the first node N1; the second plate b of the storage capacitor Cst is electrically connected to the power signal terminal PVDD.

[0128] Reference below Figure 3 and Figure 12 The specific driving timing of the pixel driving circuit is introduced as follows:

[0129] During the initialization period a, the initialization module 10 is turned on, and the initialization module 10 provides the initialization signal of the initialization signal terminal Vref to the first node N1, so as to initialize the signal stored in the storage capacitor Cst and the gate G of the driving transistor T. This stage is actually a process of resetting the storage capacitor Cst and the gate G of the driving transistor T, which is used to eliminate the data voltage signal existing in the storage capacitor Cst and the gate G of the driving transistor T when the previous frame was displayed. Therefore, in each driving and emitting process of each light-emitting element 60, it is reset before being driven to emit light, thereby ensuring the uniformity of the light-emitting control of each light-emitting element 60 and ensuring the uniformity of the light-emitting brightness.

[0130] During the target data voltage writing period b2, the data writing module 20 and the threshold compensation module 30 are both turned on, and the data voltage signal of the data signal terminal Vdata is written into the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30 in sequence, so that the gate voltage of the driving transistor T gradually increases until the voltage difference between the gate voltage of the driving transistor T and the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, and the driving transistor T is turned off.

[0131] Under the control of the data writing module 20, the data voltage signal at the data signal terminal Vdata charges the first plate a of the storage capacitor Cst via the driving transistor T, ensuring that the voltage at the first node N1 reaches a preset, threshold-compensated value. At this point, the voltage V1 at the first node N1 = Vd - |Vth|, where Vd is the data voltage at the data signal terminal and Vth is the threshold voltage of the driving transistor.

[0132] During the light emitting period c, the light emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light emitting element 60, and the light emitting element 60 emits light in response to the driving current.

[0133] Among them, the light-emitting control module may include a first light-emitting control module 51 and a second light-emitting control module 52, and the first light-emitting control module 51 is electrically connected between the power signal terminal and the first terminal T1 of the driving transistor T; the second light-emitting control module 52 is electrically connected between the second electrode T2 of the driving transistor T and the first terminal of the light-emitting element 60; the second terminal of the light-emitting element 60 can be electrically connected to the low-level signal terminal PVEE, so that when the first light-emitting control module 51 and the second light-emitting control module 52 are turned on during the light-emitting period, a current loop can be formed to drive the light-emitting element 60 to emit light.

[0134] It should be noted that the embodiments of the present invention do not specifically limit the specific structures of the initialization module, data writing module, threshold compensation module and light emitting control module. Under the premise of being able to realize the compensation function of the threshold voltage of the driving transistor, the various modules of the pixel driving circuit can be designed according to actual needs. For ease of understanding, the specific structures of the initialization module, data writing module, threshold compensation module and light emitting control module in the embodiments of the present invention are exemplified below. Among them, the initialization module 10 can be provided with a first transistor M1, and the gate of the first transistor M1 is electrically connected to the first scan signal terminal S1. During the initialization period a, the first scan signal controls the first transistor M1 to turn on. At this time, the initialization signal terminal Vref initializes the potential of the first node N1 through the first transistor M1; during the non-initialization period, the first scan signal controls the first transistor M1 to turn off. The data writing module 20 includes a second transistor M2, and the threshold compensation module 30 includes a third transistor M3. The gates of the second transistor M2 and the third transistor M3 are both electrically connected to the second scan signal terminal S2. During the target data voltage writing period b2, the second scan signal S2 controls the second transistor M2 and the third transistor M3 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. During the non-data writing period, the second scan signal S2 controls the second transistor M2 and the third transistor M3 to turn off. In the light emission control module, the first light emission control module 51 may include a fourth transistor M4, and the second light emission control module 52 may include a fifth transistor M5. The gates of the fourth transistor M4 and the fifth transistor M5 are both electrically connected to the light emission control signal terminal Emit. During the light emission period, the light emission control signal controls the fourth transistor M4 and the fifth transistor M5 to turn on. At this time, the power supply signal terminal PVDD, the fourth transistor M4, the driving transistor T, the fifth transistor M5, and the light emitting element 60 form a conductive channel. The driving transistor T generates a driving current to drive the light emitting element 60 to emit light. During the non-light emission period, the light emission control signal controls the fourth transistor M4 and the fifth transistor M5 to turn off. It should be noted that the transistors and driving transistors of the above modules can be N-type transistors or P-type transistors, and the embodiment of the present invention does not limit this.

[0135] The above pixel driving circuit is essentially a 7T1C pixel driving circuit, and its driving process essentially includes an initialization period a, a data writing period b, and a light emitting period c. It is understood that in the data writing phase, the data compensation phase, and the data holding phase of the embodiment of the present invention, the data voltage value inputted by the data signal terminal can be changed to realize the turning off and on of each period. Specifically, referring to Figure 11 and Figure 12By adjusting the data signal from the target data voltage to the compensation data voltage, the data writing period b can be adjusted to the compensation data voltage writing period b1 in the data compensation stage. Figure 13 By controlling the relevant control signals, the initialization module 10, the data writing module 20 and the threshold compensation module 30 can all be turned off, and the light-emitting control modules (51 and 52) can be turned on, thereby turning off the initialization period a and the data writing period b during the data retention phase, and driving the light-emitting element 60 to emit light under the control of the light-emitting control signal Emit, entering the light-emitting period c.

[0136] It should be noted that, in the embodiment of the present invention, the initialization module 10 may be used to initialize the gate potential of the driving transistor T during the data holding stage, or the gate potential of the driving transistor T may not be initialized, so that the gate of the driving transistor T maintains the data voltage saved in the previous stage, such as the data writing stage, and the light-emitting element 60 is driven to emit light with the data voltage.

[0137] The embodiment of the present invention provides another implementation method for the pixel driving circuit in the display panel. In another pixel driving circuit provided by the embodiment of the present invention, a bias adjustment module is also included. Among them, the driving transistor of the pixel driving circuit has a threshold drift phenomenon, which affects the comprehensive characteristics of the driving transistor, and further affects the display uniformity pixel driving circuit. In view of this, the bias adjustment module added in the embodiment of the present invention can bias the driving transistor, thereby reducing the drift of the threshold and restoring the threshold to a normal level, ensuring the normal driving of the pixel driving circuit, and the pixel unit and the display panel can be displayed according to the target brightness, thereby ensuring the display quality. Specifically, the pixel driving circuit includes: a driving transistor, a data writing module, a light emitting control module, a threshold compensation module and a bias adjustment module;

[0138] The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node; the data writing module is electrically connected between the data signal terminal and the second node, and the data writing module is used to provide the data signal input by the data signal terminal to the driving transistor; the light control module and the driving transistor are electrically connected between the power signal terminal and the light emitting element, and the light control module is used to control whether the driving current flows through the light emitting element;

[0139] The threshold compensation module is electrically connected between the first node and the third node; the threshold compensation module is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor; the bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the second node or between the threshold bias adjustment signal terminal and the third node; the control terminal of the bias adjustment module is connected to the first control signal terminal, and the bias adjustment module is used to control the voltage bias of the driving transistor under the control of the first control signal input to the first control signal terminal and the threshold bias adjustment signal input to the threshold bias adjustment signal terminal.

[0140] Furthermore, the pixel driving circuit further includes an initialization module electrically connected between the initialization signal terminal and the first node; the initialization module is used to provide the first node with an initialization signal input from the initialization signal terminal.

[0141] It is understood that in the embodiments of the present invention, by providing a bias adjustment module in the pixel driving circuit and cooperating with the data compensation phase in the picture update cycle, the bias signal provided by the bias adjustment module can be used to reverse conduct the driving transistor, thereby reducing the drift of the threshold voltage of the driving transistor during forward conduction, making the threshold voltage of the driving transistor more stable and ensuring the driving accuracy of the driving transistor. At the same time, the theoretical brightness of the pixel unit is increased by using the data compensation phase, ensuring that the image reaches the target brightness of the current picture update cycle as soon as possible when switching, and making the pixel driving circuit drive the display brightness of the light-emitting element more accurately. In other words, the embodiments of the present invention can avoid brightness distortion caused by hysteresis and threshold shift of the driving transistor, ensure the accuracy and uniformity of the display of the display panel, and improve the picture display effect. In addition, by providing a period of time for the bias adjustment module to operate in the data compensation phase in this embodiment, the operation of the data compensation phase can be facilitated. In particular, when a picture update cycle includes multiple data compensation phases with different compensation data voltages, the influence of different data compensation voltages on the driving transistor can be avoided.

[0142] Several pixel driving circuits including bias adjustment modules provided by embodiments of the present invention are described in detail below. Figure 14 is a structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention. Figure 15 This is another timing diagram of the data writing phase provided by an embodiment of the present invention. First, refer to Figure 14The pixel driving circuit includes: a driving transistor T, a data writing module 20, a light emitting control module (51 and 52), a threshold compensation module 30 and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input by the data signal terminal Vdata to the driving transistor T;

[0143] The light emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light emitting element 60. The light emitting control modules (51 and 52) are used to control whether the driving current flows through the light emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate for the deviation of the threshold voltage Vth of the driving transistor T.

[0144] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the third node N3; the control terminal of the bias adjustment module 40 is connected to the first control signal terminal s1-p, and the bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the first control signal input to the first control signal terminal s1-p and the threshold bias adjustment signal input to the threshold bias adjustment signal terminal Vobs.

[0145] Optionally, in Figure 14 In the pixel driving circuit shown, in order to simplify its pixel driving circuit structure and improve the area utilization of the array substrate in the display panel, the driving transistor T can be set as a P-type transistor; and the threshold compensation module 30 and the bias adjustment module 40 are multiplexed as an initialization module for resetting the first node N1.

[0146] For the above-mentioned pixel driving circuit, its data writing stage and data compensation stage also include a first threshold bias period and / or a second threshold bias period; in the data writing stage, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light-emitting period; in the data compensation stage, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light-emitting period.

[0147] The following also takes the data writing stage as an example to introduce the specific driving timing. Figure 15 , as follows:

[0148] During the first threshold offset period d1, the offset adjustment module 40 is turned on, and the offset adjustment signal terminal Vobs simultaneously inputs the threshold offset adjustment signal Vobs to the third node N3. By appropriately setting the signal value of Vobs to the third node N3 and, based on the Vdata+Vth maintained at the first node N1 in the previous frame, Vdata+Vth < Vobs, the driving transistor T is turned on, and the Vobs signal is written to the second node N2, lowering the potential of the second node N2 below that of the first node N1. In another scenario, it can be understood that the driving transistor T is essentially a capacitor. Writing the threshold offset adjustment signal Vobs to the third node N3 can adaptively adjust the potential of the second node N2 to lower the potential of the second node N2 below that of the first node N1. For the driving transistor, the voltage at the first node N1 is lower than the voltage at the second node N2, causing the driving transistor T to conduct in reverse phase, thus achieving reverse bias. At this point, the threshold voltage drift of the driving transistor T is reduced, thereby ensuring normal light emission during the subsequent light emission period.

[0149] During the initialization period a, the threshold compensation module 30 and the bias adjustment module 40 are multiplexed into an initialization module. At this time, the threshold compensation module 30 and the bias adjustment module 40 are both turned on, and the bias adjustment signal terminal Vobs is multiplexed into the initialization signal terminal Vini. The initialization signal is written to the first node N1. At this time, Vobs / Vini is a low-level signal.

[0150] During the target data voltage writing period b2, the data writing module 20 and the threshold compensation module 30 are both turned on, and the data voltage signal of the data signal terminal Vdata is written into the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30 in sequence, so that the gate voltage of the driving transistor T gradually increases until the voltage difference between the gate voltage of the driving transistor T and the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, and the driving transistor T is turned off.

[0151] During the second threshold offset period d2, the bias adjustment module 40 is similarly turned on, and the bias adjustment signal terminal Vobs inputs the threshold offset adjustment signal Vobs to the third node N3. By properly setting the Vobs signal value, the voltage at the third node N3 is greater than the voltage at the first node N1, turning on the driving transistor T. The Vobs signal is then written to the second node N2, lowering the potential of the second node N2 below that of the first node N1. In another scenario, it can be understood that the driving transistor T is essentially a capacitor. Writing the threshold offset adjustment signal Vobs to the third node N3 can adaptively adjust the potential of the second node N2 to lower that of the first node N1. In this case, the potential of the first node N1 is lower than that of the second node N2, causing the driving transistor T to conduct in reverse phase, thus achieving reverse bias. This reduces the threshold voltage drift of the driving transistor T, thereby ensuring normal light emission during the subsequent light emission period.

[0152] During the light emitting period c, the light emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light emitting element 60, and the light emitting element 60 emits light in response to the driving current.

[0153] It should be noted that the embodiments of the present invention do not specifically limit the specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module. As long as the threshold voltage compensation function of the driving transistor can be achieved, the various modules of the pixel driving circuit can be designed according to actual needs. For ease of understanding, the specific structures of the initialization module, data writing module, threshold compensation module, bias adjustment module, and light emission control module in the embodiments of the present invention are exemplified below. The bias adjustment module 40 may include a fifth transistor M5, the gate of which is electrically connected to the second scan signal terminal s2-p1. During the first threshold offset period d1 and the second threshold offset period d2, the second scan signal terminal s2-p1 controls the bias adjustment module 40 to conduct. At this time, the threshold offset adjustment signal Vobs is input to the second node N3, causing the potential of the first node N1 to be lower than the potential of the second node N2, thereby achieving reverse conduction of the driving transistor M3. The threshold compensation module 30 and the bias adjustment module 40 are multiplexed into an initialization module. The threshold compensation module 30 can be configured as a fourth transistor M4, and specifically can be an N-type transistor. The gate of the fourth transistor M4 is electrically connected to the third scan signal terminal sn. During the initialization period a, the second scan signal terminal s2-p1 and the third scan signal terminal sn respectively control the bias adjustment module 40 and the threshold compensation module 30 to turn on, thereby writing a low-level initialization signal Vini to the first node N1. The data write module 20 includes a second transistor M2, the gate of which is electrically connected to the first scan signal terminal s1-p. During the target data voltage write period b2, the first scan signal s1-p controls the second transistor M2 to turn on, and the third scan signal sn controls the fourth transistor M4 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. The light-emitting control module may include a first transistor M1 and a sixth transistor M6. The gates of the first transistor M1 and the sixth transistor M6 are electrically connected to the light-emitting control signal terminal Emit. During a light-emitting period c, the light-emitting control signal Emit turns on the first transistor M1 and the sixth transistor M6. At this time, the power supply signal terminal PVDD, the first transistor M1, the driving transistor T, the sixth transistor M6, and the light-emitting element 60 form a conductive path. The driving transistor T generates a driving current that drives the light-emitting element 60 to emit light.

[0154] Similarly, as above Figure 14The provided pixel driving circuit has a driving process that essentially includes an initialization period a, a data writing period b, and a light-emitting period c. It is understood that in the data writing phase, the data compensation phase, and the data holding phase of the embodiment of the present invention, the data writing period b can be adjusted to the compensation data voltage writing period b1 in the data compensation phase by changing the data voltage value input at the data signal terminal. At the same time, by controlling the relevant control signals, the data writing module 20 and the threshold compensation module 30 are both turned off, and the light-emitting control modules (51 and 52) are turned on, so that the initialization period a and the data writing period b can be turned off in the data holding phase, and the image display is performed in the light-emitting period c throughout the data holding phase. In addition, in addition to setting the first threshold offset period d1 and the second threshold offset period d2 in the data writing phase, the first threshold offset period d1 and the second threshold offset period d2 can also be set in the data compensation phase, without limitation here.

[0155] Figure 16 FIG17 is a structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention, FIG18 is a timing diagram of another data writing phase provided by an embodiment of the present invention, and FIG19 is a timing diagram of another data writing phase provided by an embodiment of the present invention, Figure 16 The pixel driving circuit includes: a driving transistor T, a data writing module 20, a light emitting control module (51 and 52), a threshold compensation module 30 and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input by the data signal terminal Vdata to the driving transistor T;

[0156] The light emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light emitting element 60. The light emitting control modules (51 and 52) are used to control whether the driving current flows through the light emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate for the deviation of the threshold voltage Vth of the driving transistor T.

[0157] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the third node N3; the control terminal of the bias adjustment module 40 is connected to the second control signal terminal s2-p1, and the bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the second control signal input by the second control signal terminal s2-p1 and the threshold bias adjustment signal input by the threshold bias adjustment signal terminal Vobs.

[0158] Likewise, optionally, the driving transistor T may be set as an N-type transistor; and the threshold compensation module 30 and the bias adjustment module 40 may be multiplexed into an initialization module for resetting the first node N1.

[0159] Furthermore, the NMOS driver transistor can be configured as a dual-gate transistor. This dual-gate transistor includes a first gate and a second gate. The first gate serves as the control terminal of the driver transistor, i.e., for receiving a data signal, and the second gate is connected to a threshold voltage feedback unit. Specifically, the first gate can be the bottom gate of the dual-gate transistor, and the second gate can be the top gate. By using multiple gate structures, the cutoff current of the driver transistor can be reduced, increasing the transistor's withstand voltage and improving reliability. Alternatively, even when the drain-source voltage fluctuates when the transistor operates in the saturation region, the drain-source current does not fluctuate significantly, thereby achieving a flat characteristic for the driver transistor. Furthermore, the second gate can be connected to a threshold voltage feedback unit. The threshold voltage feedback unit provides threshold voltage feedback information, which can adjust the operating state of the driver transistor and compensate for threshold voltage drift caused by aging of the driver transistor. Furthermore, the threshold voltage feedback unit can compensate for differences in the mobility of the driver transistor, resolving the problem of uneven brightness of the light-emitting element caused by threshold voltage drift and mobility differences of the driver transistor, further improving the uniformity of the display panel.

[0160] For Figure 16 The pixel driving circuit shown in the figure can also be set to include a first threshold bias period and / or a second threshold bias period in its data writing phase and data compensation phase; in the data writing phase, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light-emitting period; in the data compensation phase, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light-emitting period.

[0161] The following also takes the data writing stage as an example to introduce the specific driving timing. Figure 17 , as follows:

[0162] During the first threshold offset period d1, the offset adjustment module 40 is turned on, and the offset adjustment signal terminal Vobs simultaneously inputs the threshold offset adjustment signal Vobs to the third node N3. By properly setting the signal value of Vobs, the voltage at the third node N3 can be made lower than the voltage at the first node N1, thereby enabling the driving transistor T to conduct in reverse phase, thereby achieving reverse bias. It should be noted that during the light-emitting period of the previous frame, the storage capacitor Cst stores the Vdata signal, and the potential of the first node N1 is Vdata + Vth. By properly setting Vobs < Vdata + Vth, the driving transistor T can be reversed. At this point, the threshold voltage drift of the driving transistor T is reduced, thereby ensuring normal light emission during the subsequent light-emitting period.

[0163] During the initialization period a, the threshold compensation module 30 and the bias adjustment module 40 are multiplexed into an initialization module. At this time, the threshold compensation module 30 and the bias adjustment module 40 are both turned on, and the bias adjustment signal terminal Vobs is multiplexed into the initialization signal terminal Vini. The initialization signal is written to the first node N1. At this time, Vobs / Vini is a high-level signal.

[0164] During the target data voltage writing period b2, the data writing module 20 and the threshold compensation module 30 are both turned on, and the data voltage signal of the data signal terminal Vdata is written into the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30 in sequence, so that the gate voltage of the driving transistor T gradually increases until the voltage difference between the gate voltage of the driving transistor T and the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, and the driving transistor T is turned off.

[0165] During the light emitting period c, the light emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light emitting element 60, and the light emitting element 60 emits light in response to the driving current.

[0166] For ease of understanding, here we also Figure 16The specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module in the pixel driving circuit are illustrated. The bias adjustment module 40 may include a seventh transistor M7, the gate of which is electrically connected to the second scan signal terminal s2-p1. During the first threshold offset period d1, the second scan signal terminal s2-p1 controls the bias adjustment module 40 to conduct. At this time, the threshold offset adjustment signal Vobs is input to the third node N3, thereby achieving reverse conduction of the driving transistor M3. The threshold compensation module 30 and the bias adjustment module 40 are multiplexed into the initialization module. The threshold compensation module 30 may be configured as a fourth transistor M4, which may be an N-type transistor. The gate of the fourth transistor M4 is electrically connected to the third scan signal terminal sn. During the initialization period a, the second scan signal terminal s2-p and the third scan signal terminal sn respectively control the bias adjustment module 40 and the threshold compensation module 30 to conduct, thereby writing a high-level initialization signal Vini to the first node N1. The data writing module 20 includes a second transistor M2, the gate of which is electrically connected to the first scan signal terminal s1-p. During the target data voltage writing period b2, the first scan signal s1-p controls the second transistor M2 to conduct, and the third scan signal sn controls the fourth transistor M4 to conduct. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. The light emitting control module may include a first transistor M1 and a fifth transistor M5, the gates of which are both electrically connected to the light emitting control signal terminal Emit. During the light emitting period c, the light emitting control signal Emit controls the first transistor M1 and the fifth transistor M5 to conduct. At this time, the power signal terminal PVDD, the first transistor M1, the driving transistor T, the fifth transistor M5, and the light emitting element 60 form a conductive channel, and the driving transistor T generates a driving current to drive the light emitting element 60 to emit light.

[0167] Similarly, as above Figure 16The provided pixel driving circuit has a driving process that essentially includes an initialization period a, a data writing period b, and a light-emitting period c. It is understood that in the data writing phase, the data compensation phase, and the data holding phase of the embodiment of the present invention, the data writing period b can be adjusted to the compensation data voltage writing period b1 in the data compensation phase by changing the data voltage value input at the data signal terminal. At the same time, by controlling the relevant control signals, the data writing module 20 and the threshold compensation module 30 are both turned off, and the light-emitting control modules (51 and 52) are turned on, so that the initialization period a and the data writing period b can be turned off in the data holding phase, and the image display is performed in the light-emitting period c throughout the data holding phase. In addition, in addition to setting the first threshold offset period d1 and the second threshold offset period d2 in the data writing phase, the first threshold offset period d1 and the second threshold offset period d2 can also be set in the data compensation phase, without limitation here.

[0168] Figure 18 FIG19 is a structural diagram of a display panel pixel driving circuit provided by an embodiment of the present invention, FIG19 is a timing diagram of another data writing phase provided by an embodiment of the present invention, Figure 18 The pixel driving circuit includes: a driving transistor T, a data writing module 20, a light emitting control module (51 and 52), a threshold compensation module 30 and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input by the data signal terminal Vdata to the driving transistor T;

[0169] The light emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light emitting element 60. The light emitting control modules (51 and 52) are used to control whether the driving current flows through the light emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate for the deviation of the threshold voltage Vth of the driving transistor T.

[0170] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the second node N2; the control terminal of the bias adjustment module 40 is connected to the first control signal terminal s1-p, and the bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the first control signal input to the first control signal terminal s1-p and the threshold bias adjustment signal input to the threshold bias adjustment signal terminal Vobs.

[0171] Alternatively, the driving transistor T can be configured as an N-type transistor; the data writing module 20 can be multiplexed into the bias adjustment module 40, and the data signal terminal Vdata can be multiplexed into the threshold bias adjustment signal terminal Vobs. The data writing module 20 is further configured to provide the threshold bias adjustment signal Vobs inputted by the data signal terminal Vdata to the second node N2. Furthermore, the first light emission control module 51 and the threshold compensation module 30 in the light emission control module can be multiplexed into an initialization module, and the power signal terminal PVDD can be multiplexed into the initialization signal terminal.

[0172] For the above-mentioned pixel driving circuit, its data writing stage and data compensation stage may also include a first threshold bias period and / or a second threshold bias period; in the data writing stage, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light-emitting period; in the data compensation stage, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light-emitting period.

[0173] The following also takes the data writing stage as an example to introduce the specific driving timing. Figure 19 , as follows:

[0174] During the first threshold offset period d1, the offset adjustment module 40 is turned on, and the offset adjustment signal terminal Vobs simultaneously inputs the threshold offset adjustment signal Vobs to the second node N2. It should be noted that in this pixel driver circuit, the threshold offset adjustment signal Vobs input at this time is essentially the data signal Vdata' written by the pixel driver circuit located before the current pixel driver circuit on the display panel. Obviously, by writing the data signal Vdata' to the second node N2, the voltage at the second node N2 is substantially lower than the voltage at the first node N1, turning on the driver transistor T. The Vobs signal is written to the third node N3, thereby making the voltage at the third node N3 lower than the voltage at the first node N1. This causes the driver transistor T to be reverse-phased, i.e., reverse-biased. At this point, the threshold voltage drift of the driver transistor T is reduced, thereby ensuring normal light emission during the subsequent light emission period.

[0175] During the initialization period a, the first light-emitting control module 51 and the threshold compensation module 30 are multiplexed as the initialization module, and the power signal terminal PVDD is multiplexed as the initialization signal terminal. At this time, the first light-emitting control module 51 and the threshold compensation module 30 are turned on, and the power signal terminal PVDD writes the initialization signal to the first node N1, that is, writes a high-level signal to the first node N1 to achieve initialization.

[0176] During the target data voltage writing period b2, the data writing module 20 and the threshold compensation module 30 are both turned on, and the data voltage signal of the data signal terminal Vdata is written into the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30 in sequence, so that the gate voltage of the driving transistor T gradually increases until the voltage difference between the gate voltage of the driving transistor T and the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, and the driving transistor T is turned off.

[0177] During the light emitting period c, the light emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light emitting element 60, and the light emitting element 60 emits light in response to the driving current.

[0178] Similarly, for ease of understanding, Figure 18 The specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module in the pixel driving circuit are illustrated. The data writing module 20 includes a second transistor M2, the gate of which is electrically connected to the first scanning signal terminal s1-p. The data writing module 20 is multiplexed into the bias adjustment module 40. During the first threshold bias period d1, the first scanning signal terminal s1-p controls the bias adjustment module 40 to conduct. At this time, the threshold bias adjustment signal Vobs (Vdata') is input to the third node N3, thereby achieving reverse conduction of the driving transistor M3.

[0179] The threshold compensation module 30 and the first emission control module 51 in the emission control module are multiplexed into an initialization module. The threshold compensation module 30 can be configured as a fourth transistor M4, specifically an N-type transistor, with its gate electrically connected to the third scan signal terminal sn. The first emission control module 51 can be specifically configured as a first transistor M1, with its gate electrically connected to the first emission control signal Emit1. During the initialization period a, the third scan signal terminal sn and the first emission control signal Emit1 respectively turn on the fourth transistor M4 and the first transistor M1, thereby writing a high-level initialization signal Vini (substantially PVDD) to the first node N1.

[0180] During the target data voltage writing period b2, the first scan signal s1-p controls the second transistor M2 to turn on, and the third scan signal sn controls the fourth transistor M4 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T and the threshold compensation module 30.

[0181] The second light-emission control module 52 in the light-emission control module may include a fifth transistor M5, the gate of which is electrically connected to the second light-emission control signal terminal Emit2. During light-emission period c, the first light-emission control signal Emit1 and the second light-emission control signal Emit2 control the first transistor M1 and the fifth transistor M5 to conduct. At this time, the power supply signal terminal PVDD, the first transistor M1, the driving transistor T, the fifth transistor M5, and the light-emitting element 60 form a conductive channel, and the driving transistor T generates a driving current to drive the light-emitting element 60 to emit light.

[0182] Similarly, as above Figure 18 The provided pixel driving circuit has a driving process that essentially includes an initialization period a, a data writing period b, and a light-emitting period c. It is understood that in the data writing phase, the data compensation phase, and the data holding phase of the embodiment of the present invention, the data writing period b can be adjusted to the compensation data voltage writing period b1 in the data compensation phase by changing the data voltage value input at the data signal terminal. At the same time, by controlling the relevant control signals, the data writing module 20 and the threshold compensation module 30 are both turned off, and the light-emitting control modules (51 and 52) are turned on, so that the initialization period a and the data writing period b can be turned off in the data holding phase, and the image display is performed in the light-emitting period c throughout the data holding phase. In addition, in addition to setting the first threshold offset period d1 and the second threshold offset period d2 in the data writing phase, the first threshold offset period d1 and the second threshold offset period d2 can also be set in the data compensation phase, without limitation here.

[0183] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for driving a display panel, characterized in that: It includes a plurality of picture update cycles, at least one of which includes a data writing phase, a data holding phase and a data compensation phase; The data compensation phase is located before the data writing phase; the data holding phase is provided between at least two adjacent data compensation phases, or the data holding phase is provided between adjacent data compensation phases and the data writing phase; During the data compensation phase, a gate scan signal is provided to the pixel unit and a compensation data voltage is written. The compensation data voltage is less than the target data voltage and less than the data voltage corresponding to the previous picture update cycle. The target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle. In the data writing phase, a gate scanning signal is provided to the pixel unit and the target data voltage is written; During the data holding phase, no data voltage is written into the pixel unit.

2. The method for driving a display panel according to claim 1, wherein: The same screen update cycle includes multiple data compensation stages, and the multiple data compensation stages include a first data compensation stage and a second data compensation stage, the first data compensation stage is before the second data compensation stage; the compensation data voltage written in the second data compensation stage is greater than the compensation data voltage written in the first data compensation stage.

3. The method for driving a display panel according to claim 1, wherein: The same screen update cycle includes multiple data compensation stages, and the multiple data compensation stages include a third data compensation stage and a fourth data compensation stage, and the third data compensation stage is before the fourth data compensation stage; the compensation data voltage written in the fourth data compensation stage is equal to the compensation data voltage written in the third data compensation stage.

4. The method for driving a display panel according to claim 1, wherein: The plurality of picture update cycles include at least one first picture update cycle and at least one second picture update cycle; The brightness of the first picture update period is greater than the brightness of the previous picture update period, and the first picture update period includes the data writing phase, the data holding phase and the data compensation phase; The brightness of the second picture update period is less than or equal to the brightness of the previous picture update period, and the first picture update period includes the data writing phase and the data holding phase.

5. The method for driving a display panel according to claim 1, wherein: The same frame update cycle includes a plurality of data compensation phases; the compensation data voltages written corresponding to the plurality of data compensation phases are in an arithmetic progression, a geometric progression or an exponential progression.

6. The method for driving a display panel according to claim 5, wherein: The first data compensation phase in the plurality of data compensation phases of the same frame update cycle is an initial data compensation phase; the compensation data voltage Vdata written in the initial data compensation phase is Vdata0×L1 / L2; Wherein, L2 is the target brightness of the picture update period, Vdata0 is the target data voltage corresponding to the target brightness of the picture update period, and L1 is the actual brightness when the target data voltage is written into the pixel unit in the initial data compensation stage.

7. The method for driving a display panel according to claim 5, wherein: The same picture update cycle includes N data compensation stages, wherein the data voltage corresponding to the nth data compensation stage is Vdata_n=Vdata0-(N-n+1)*x, wherein Vdata0 is the target data voltage corresponding to the target brightness of the current picture update cycle, n and N are both positive integers, 1≤n≤N, and x=0.5V~2V.

8. The method for driving a display panel according to claim 1, wherein: The same picture update cycle includes N data compensation phases, M data holding phases, and P data writing phases; Wherein, N / (N+M+P)≤1 / 6, and N, M and P are all integers greater than or equal to 1.

9. The method for driving a display panel according to claim 1, wherein: The same frame update cycle includes a plurality of data compensation stages, wherein the difference between the compensation data voltages written in the a-th data compensation stage and the a+1-th data compensation stage is △X1; the difference between the compensation data voltages written in the b-th data compensation stage and the b+1-th data compensation stage is △X2; Wherein, △X1>△X2, a and b are both positive integers greater than 0, and a+1≤b.

10. The method for driving a display panel according to claim 1, wherein: The same frame update cycle includes a plurality of the data compensation phases and a plurality of the data holding phases; at least two of the data compensation phases are separated by at least one data holding phase.

11. The method for driving a display panel according to claim 10, wherein: Any two adjacent data compensation phases are separated by the same number of data holding phases.

12. The method for driving a display panel according to claim 10, wherein: The number of the data holding phases between two adjacent data compensation phases increases gradually.

13. The method for driving a display panel according to claim 1, wherein: The same picture update cycle includes N data compensation phases, M data holding phases, and P data writing phases; Wherein, N, M and P are integers greater than or equal to 1; There are n data holding phases between any two adjacent data compensation phases, where 0≤n≤M.

14. The method for driving a display panel according to claim 13, wherein: There are M*a% / N data retention stages between any two adjacent data compensation stages, wherein 30%≤a%≤50%, M*a% is an integer greater than or equal to 1, and M*a% / N is an integer greater than or equal to 1.

15. The method for driving a display panel according to claim 13, wherein: The display panel includes a plurality of pixel driving circuits corresponding one-to-one to the pixel units; The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit, wherein the driving transistor of the first pixel driving circuit is a silicon-based transistor, and the driving transistor of the second pixel driving circuit is an oxide semiconductor transistor; In the same frame update cycle, the proportion of the number of data compensation phases of the first pixel driving circuit is different from the proportion of the number of data compensation phases of the second pixel driving circuit.

16. The method for driving a display panel according to claim 13, wherein: The display panel includes a plurality of pixel driving circuits corresponding to the pixel units one by one, and the pixel driving circuits include driving transistors; The driving transistor includes an N-type silicon-based transistor, and the number of the data compensation phase, the data holding phase, and the data writing phase satisfies: N / (N+M+P)≤1 / 6.

17. The method for driving a display panel according to claim 13, wherein: The display panel includes a plurality of pixel driving circuits corresponding to the pixel units one by one, and the pixel driving circuits include driving transistors; The driving transistor includes a P-type silicon-based transistor, and the number of the data compensation phase, the data holding phase, and the data writing phase satisfies: N / (N+M+P)≤1 / 12.

18. The method for driving a display panel according to claim 13, wherein: The display panel includes a plurality of pixel driving circuits corresponding to the pixel units one by one, and the pixel driving circuits include driving transistors; the driving transistors include N-type silicon-based transistors and P-type silicon-based transistors; The pixel driving circuit includes a third pixel driving circuit and a fourth pixel driving circuit, the third pixel driving circuit includes the N-type silicon-based transistor, and the fourth pixel driving circuit includes the P-type silicon-based transistor; In the same frame update cycle, the proportion of the number of data compensation phases of the third pixel driving circuit is different from the proportion of the number of data compensation phases of the fourth pixel driving circuit.

19. The method for driving a display panel according to claim 18, wherein: In the same frame update cycle, the number of data compensation phases of the third pixel driving circuit accounts for X, and the number of data compensation phases of the fourth pixel driving circuit accounts for Y, where X≥Y.

20. The method for driving a display panel according to claim 13, wherein: Any two adjacent picture update cycles include a first picture update cycle and a second picture update cycle; the first picture update cycle includes N1 data compensation phases, M1 data holding phases, and P1 data writing phases; the second picture update cycle includes N2 data compensation phases, M2 data holding phases, and P2 data writing phases; The first picture update period and the second picture update period satisfy: N1+M1+P1<N2+M2+P2, N1<N2.

21. The method for driving a display panel according to claim 5, wherein: The display panel includes a first color pixel unit and a second color pixel unit, and under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is smaller than the theoretical data voltage corresponding to the second color pixel unit; In the data compensation stage, the compensation data voltages corresponding to the first color pixel unit and the second color pixel unit written in the multiple data compensation stages are both in an arithmetic progression, and are respectively a first arithmetic progression and a second arithmetic progression; the tolerance of the first arithmetic progression is d1, the number of terms is N1, and the first term is a1; the tolerance of the second arithmetic progression is d2, the number of terms is N2, and the first term is a2; the first arithmetic progression and the second arithmetic progression satisfy: a1=a2, d1=d2, N1<N2; or, a1=a2, d1<d2, N1=N2; or, a1<a2, d1=d2, N1=N2.

22. The method for driving a display panel according to claim 5, wherein: The display panel includes a first color pixel unit and a second color pixel unit, and under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is smaller than the theoretical data voltage corresponding to the second color pixel unit; A compensation data voltage difference corresponding to two adjacent data compensation stages of the first color pixel unit is greater than a compensation data voltage difference corresponding to two adjacent data compensation stages of the second color pixel unit; Alternatively, the compensation data voltage corresponding to the initial data compensation stage of the first color pixel is smaller than the compensation data voltage corresponding to the initial data compensation stage of the second color pixel; Alternatively, the number of data compensation stages for the first color pixel is greater than the number of data compensation stages for the second color pixel.

23. The method for driving a display panel according to claim 1, wherein: The data writing phase at least includes a target data voltage writing period and a light emitting period; The data compensation phase at least includes a compensation data voltage writing period and a light emitting period; The data holding phase at least includes a light emitting period.

24. The method for driving a display panel according to claim 23, wherein: The data writing phase and the data compensation phase further include a first threshold bias period and / or a second threshold bias period; In the data writing phase, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light emitting period; In the data compensation phase, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light emitting period.

25. A display device, characterized in that: include: A display panel comprising a plurality of pixel units, the display panel comprising a plurality of picture update cycles, at least one of the picture update cycles comprising a data writing phase, a data compensation phase, and a data holding phase, and at least one of the picture update cycles further comprising the data compensation phase preceding the data writing phase; the data holding phase being interposed between at least two adjacent data compensation phases, or the data holding phase being interposed between adjacent data compensation phases and the data writing phase; A scan driving unit, configured to provide a gate scan signal to each pixel unit during the data writing phase and the data compensation phase; The data writing unit is used to provide a gate scanning signal to the pixel unit and write a target data voltage during the data writing phase, where the target data voltage is a theoretical data voltage corresponding to the target brightness of the current picture update cycle; and is also used to provide a gate scanning signal to the pixel unit and write a compensation data voltage during the data compensation phase, where the compensation data voltage is less than the target data voltage and less than the data voltage corresponding to the previous picture update cycle.

26. The display device according to claim 25, wherein: The display panel includes a plurality of pixel driving circuits corresponding one-to-one to the pixel units; The pixel driving circuit includes: Driving transistor, data writing module, light emitting control module and threshold compensation module; The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node; The data writing module is electrically connected between the data signal terminal and the second node; the threshold compensation module is electrically connected between the first node and the third node; the data writing module is used to provide the data signal input from the data signal terminal to the driving transistor; The threshold compensation module is used to compensate the threshold voltage of the driving transistor to the first node; The light emitting control module and the driving transistor are electrically connected between the power signal terminal and the light emitting element. The light emitting control module is used to control whether the driving current flows through the light emitting element.

27. The display device according to claim 25, wherein: The display panel includes a plurality of pixel driving circuits corresponding one-to-one to the pixel units; The pixel driving circuit includes: Driving transistor, data writing module, light emitting control module, threshold compensation module and bias adjustment module; The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node; The data writing module is electrically connected between the data signal terminal and the second node, and is used to provide the driving transistor with the data signal inputted from the data signal terminal; The light emitting control module and the driving transistor are electrically connected between the power signal terminal and the light emitting element, and the light emitting control module is used to control whether the driving current flows through the light emitting element; The threshold compensation module is electrically connected between the first node and the third node; the threshold compensation module is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor; The bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the second node or between the threshold bias adjustment signal terminal and the third node; the control terminal of the bias adjustment module is connected to the first control signal terminal, and the bias adjustment module is used to control the voltage bias of the driving transistor under the control of the first control signal input by the first control signal terminal and the threshold bias adjustment signal input by the threshold bias adjustment signal terminal.

28. The display device according to claim 27, wherein: The driving transistor is an N-type transistor; The threshold compensation module and the bias adjustment module are multiplexed into an initialization module for resetting the first node.

29. The display device according to claim 27, wherein The driving transistor is an N-type transistor; The data writing module is multiplexed into the bias adjustment module, and the data signal terminal is multiplexed into the threshold bias adjustment signal terminal; The data writing module is further configured to provide the second node with a threshold offset adjustment signal inputted from the data signal terminal.

30. The display device according to claim 27, wherein The driving transistor is a P-type transistor; The threshold compensation module and the bias adjustment module are multiplexed into an initialization module for resetting the first node.

Images