semiconductor structure

Abstract

A semiconductor structure includes: source / drain components disposed in a semiconductor layer; a metal gate stack disposed in and adjacent to the source / drain components in a first interlayer dielectric layer; a second interlayer dielectric layer disposed above the metal gate stack; and source / drain contacts disposed above the source / drain components. The semiconductor structure further includes an air gap disposed between the bottom sidewall of the source / drain contacts and the first interlayer dielectric layer, wherein the top sidewall of the source / drain contacts is in direct contact with the second interlayer dielectric layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to a semiconductor device including an air gap and a method for forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth. Technological advancements in semiconductor materials and design have resulted in several generations of semiconductor devices, each with smaller and more complex circuitry than the previous generation. During the evolution of integrated circuits, functional density (i.e., the number of interconnects per unit chip area) typically increases while geometry (i.e., the smallest element (or line) that can be manufactured using a process) decreases. This miniaturization process usually provides benefits such as increased production efficiency and reduced associated costs.

[0003] For example, many methods have been developed to reduce parasitic capacitance. One example involves forming air gaps between adjacent conductive components. While existing methods generally meet the requirements, they are not satisfactory in every aspect. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including: a source / drain component disposed in a semiconductor layer; a metal gate stack disposed in a first interlayer dielectric layer and adjacent to the source / drain component; a second interlayer dielectric layer disposed above the metal gate stack; a source / drain contact disposed above the source / drain component; and an air gap disposed between a bottom sidewall of the source / drain contact and the first interlayer dielectric layer, wherein a top sidewall of the source / drain contact is in direct contact with the second interlayer dielectric layer.

[0005] This disclosure provides a semiconductor structure including: a plurality of metal gate stacks disposed in a first interlayer dielectric layer; source / drain components disposed between the metal gate stacks; a second interlayer dielectric layer disposed above the metal gate stacks; contact components disposed above the source / drain components, wherein the contact components extend through the first and second interlayer dielectric layers; air gaps disposed on a plurality of sidewalls of the contact components, wherein the second interlayer dielectric layer seals the air gaps; and an etch stop layer disposed above the second interlayer dielectric layer, wherein the etch stop layer and the air gaps are partially separated by the second interlayer dielectric layer.

[0006] This disclosure provides a method for forming a semiconductor structure, comprising: providing a metal gate stack disposed in a first interlayer dielectric layer, source / drain components disposed adjacent to the metal gate stack, and a second interlayer dielectric layer disposed above the metal gate stack; forming contact trenches in the first and second interlayer dielectric layers to expose the source / drain components; forming a sacrificial layer in the contact trenches; forming source / drain contacts above the sacrificial layer; removing the sacrificial layer to form air gaps on a plurality of sidewalls of the source / drain contacts; and filling the top of the air gaps disposed above the metal gate stack, such that the bottom of the air gaps is sealed by the second interlayer dielectric layer. Attached Figure Description

[0007] The embodiments of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure.

[0008] Figure 1 This is a flowchart illustrating exemplary methods of manufacturing a semiconductor device according to various embodiments of the present disclosure.

[0009] Figure 2A This is a three-dimensional perspective view of an example semiconductor device according to various embodiments of the present disclosure.

[0010] Figure 2B Various embodiments of the present disclosure are shown. Figure 2A A top plan view of the semiconductor device shown.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A and Figure 9B Various embodiments of the present disclosure are shown in Figure 1 During the intermediate stage of the method shown, Figure 2A and Figure 2B The diagram shows a cross-sectional view of the semiconductor device along line AA'.

[0012] Figure 10 A schematic diagram showing the dopant particle concentration as a function of depth in an example device fabricated according to various embodiments of the present disclosure.

[0013] Explanation of reference numerals in the attached figures:

[0014] 100: Method

[0015] 102, 104, 106, 108, 110, 112A, 112B, 114A, 114B, 116: Operation

[0016] 200: Device

[0017] 202: Base

[0018] 204: Fins

[0019] 208: Isolation Structure

[0020] 210: High dielectric constant metal gate structure

[0021] 212: Gate spacer

[0022] 214: Source / Drain Components

[0023] 218: Interlayer dielectric layer

[0024] 220: Etching Stop Layer

[0025] 222: Interlayer dielectric layer

[0026] 230: Trench

[0027] 232: Sacrificial Layer

[0028] 234: Silicide layer

[0029] 235: Barrier Layer

[0030] 236: Conductive layer

[0031] 238: Source / Drain Contacts

[0032] 240: Air gap

[0033] 240a: upper part

[0034] 240b: Lower part

[0035] 250: Etching stop layer

[0036] 250a: Partial

[0037] 310: Fabric implantation technology

[0038] 320, 350: Beam

[0039] 330°, 360°: Angle

[0040] D, d, T, t: Thickness

[0041] w: width Detailed Implementation

[0042] The following disclosure provides numerous embodiments or examples of different elements for implementing the embodiments of this disclosure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of the embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0043] Furthermore, in subsequent embodiments of this disclosure, forming a component on another component, connecting and / or coupling this component to another component may include embodiments where these components are in direct contact, or embodiments where additional components are inserted between these components, such that these components may not be in direct contact. Additionally, spatially relative terms, such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc., and their derived terms (e.g., “horizontally,” “downward,” “upward,” etc.), are used to simplify the relationship between some components and other components in embodiments of this disclosure. Spatially relative terms are used to cover different orientations of devices containing components. Furthermore, when terms such as “about,” “approximately,” and similar terms are used to describe numbers or ranges of numbers, these terms are used to cover numbers within a reasonable range, including the described numbers, such as within + / - 10% of the described numbers or other values ​​understood by those skilled in the art to which this disclosure pertains. For example, the term “about 5nm” covers a size range of 4.5nm to 5.5nm.

[0044] This disclosure generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to forming air gaps between source / drain contacts and adjacent metal gate structures. During the fabrication of integrated circuits, a common method for reducing parasitic capacitance in a device includes inserting an insulating (or dielectric) material having a relatively low dielectric constant (k-value) between device components, such as a low-dielectric-constant dielectric and / or air (e.g., by forming an air gap). In this disclosure, a “low-k” dielectric material refers to a dielectric material whose dielectric constant is less than that of silicon oxide, with a value of approximately 3.9. Therefore, conversely, a “high-k” dielectric material refers to a dielectric material whose dielectric constant is greater than that of silicon oxide. While an air gap is generally sufficient to reduce parasitic capacitance, it can become a source of structural defects in subsequent process steps. In one example, unintentional over-etching when forming via contacts on source / drain contacts can open a sealed air gap and damage surrounding dielectric components. Furthermore, during wet etching, chemical etchants may penetrate the opened air gap and damage the underlying source / drain components and / or metal gate structure. For the aforementioned and other reasons, there is a need to improve the air gap formation method.

[0045] Reference Figure 1 The following flowchart illustrates a method 100 for forming a semiconductor device 200 (hereinafter referred to as device 200) according to various aspects of embodiments of the present disclosure. Method 100 is merely an example and is not intended to limit the present disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, and after method 100, and some of the operations may be replaced, omitted, or rescheduled in additional embodiments of the method. Method 100 is described below with reference to Figures 2A-9B, which show a portion of device 200 during an intermediate stage of method 100. Figures 3-9B In an intermediate step of method 100, device 200 moves along... Figure 2A and Figure 2BThe cross-sectional view shown is based on the dashed line AA'. Semiconductor device 200 may be an intermediate device manufactured during the process of an integrated circuit or a portion thereof, and may include static random access memory (SRAM) and / or other logic circuitry, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), fin field-effect transistors (FinFETs), gate-all-around (GAA) field-effect transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells). Embodiments of this disclosure are not limited to any particular number of devices or device regions, or any particular device configuration. For example, although device 200 is shown as a three-dimensional fin field-effect transistor device, embodiments of this disclosure may also provide embodiments for manufacturing planar field-effect transistor devices. Additional components may be added to semiconductor device 200, and in other embodiments of semiconductor device 200, some of the components described below may be replaced, modified, or removed.

[0046] Reference Figure 2A , Figure 2B and Figure 3 In operation 102 of method 100, an apparatus 200 is provided, comprising: a substrate 202 having at least one semiconductor layer 204 (e.g., an active region, such as a three-dimensional fin; hereinafter referred to as fin 204) deposited thereon; a high-k dielectric metal gate (HKMG) structure 210 disposed on the fin 204; an isolation structure 208 disposed on the substrate 202 and separating various elements of the apparatus 200; a source / drain component 214 disposed on the fin 204 and inserted into the high-k dielectric gate structure 210; and an interlayer dielectric layer 218 disposed on the source / drain component 214. As used herein, "high-k dielectric" refers to a dielectric material with a dielectric constant greater than that of silicon oxide, and its value is approximately 3.9. As shown, the device 200 may include a plurality of fins 204 oriented along the X direction and a plurality of high-dielectric-constant metal gate structures 210 oriented along the Y direction, i.e., the aforementioned high-dielectric-constant metal gate structures 210 are generally perpendicular to the fins 204. (Refer to...) Figure 3 The apparatus 200 includes additional components, such as gate spacers 212 disposed on the sidewalls of the high-dielectric-constant metal gate structure 210, an etch stop layer (ESL) 220 disposed above the high-dielectric-constant metal gate structure 210, and many other components. For simplicity, the intermediate steps of method 100 are described below with reference to a cross-sectional view of the apparatus 200 along the length of the fin 204 (i.e., line AA' in the X direction).

[0047] Substrate 202 may include: elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 may be a single-layer material having a uniform composition. Alternatively, substrate 202 may include multiple material layers having similar or different compositions suitable for manufacturing integrated circuit devices. In one example, substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof.

[0048] The fin 204 can be manufactured using suitable processes including photolithography and etching. The photolithography process may include: forming a photoresist layer (impedance layer) on a substrate 202, exposing the impedance layer to a pattern, performing a post-exposure baking process, and developing the aforementioned impedance layer to form a mask element (not shown) including the aforementioned impedance layer. The mask element is then used to etch grooves into the substrate 202, leaving the fin 204 on the substrate 202. The aforementioned etching process may include: dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0049] Many other implementations are applicable to forming the fin 204. For example, the fin 204 can be patterned using a double-patterning or multi-patterning process. Generally, compared to a single, direct lithography process, double-patterning or multi-patterning processes combine lithography and self-aligned processes, for example, resulting in a pattern with a smaller pitch. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Using a self-aligned process, spacers are formed along the sidewalls of the aforementioned patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers, or mandrels, can then be used to pattern the fin.

[0050] The isolation structure 208 may include silicon oxide, silicon nitride, silicon oxynitride, a low-dielectric-constant dielectric material, and / or other suitable materials. The isolation structure 208 may include shallow trench isolation (STI) components. In one embodiment, the isolation structure 208 is formed by etching trenches in the substrate 202 during the formation of the fin 204. The trenches are then filled with the aforementioned isolation material by a deposition process, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, localized oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 208. Alternatively, the isolation structure 208 may include a multilayer structure, for example, having one or more thermal oxide substrates. The isolation structure 208 may be deposited by any suitable method, such as chemical vapor deposition, flow-through chemical vapor deposition (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.

[0051] Still refer to Figure 2A , Figure 2B and Figure 3 The device 200 includes source / drain components 214 disposed within or above fins 204 and adjacent to a high-dielectric-constant metal gate structure 210. The source / drain components 214 can be formed using any suitable technique, such as an etching process, followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of the fins 204 to form a trench (not shown). A cleaning process can be performed to clean the trench with a hydrofluoric acid (HF) solution and / or other suitable solutions. Subsequently, one or more epitaxial growth processes are performed to grow the epitaxial components in the trenches. Each source / drain component 214 can be adapted to form a p-type fin field-effect transistor device (e.g., including p-type epitaxial material) or alternatively, an n-type fin field-effect transistor device (e.g., including n-type epitaxial material). The p-type epitaxial material may include one or more silicon-germanium epitaxial layers (epi SiGe), wherein the silicon-germanium is doped with a p-type dopant, such as boron, germanium, indium, and / or other p-type dopant. n-type epitaxial materials may include one or more silicon (epi Si) or silicon-carbon (epi SiC) epitaxial layers, wherein the silicon or silicon-carbon is an n-type dopant, such as arsenic, phosphorus, and / or other n-type dopant.

[0052] The device 200 further includes a high-dielectric-constant metal gate structure 210 disposed above a portion of the fins 204. The high-dielectric-constant metal gate structure 210 includes a high-dielectric-constant dielectric layer (not shown) disposed above the fins 204 and a metal gate electrode (not shown) disposed above the high-dielectric-constant dielectric layer. The metal gate electrode may further include at least one work function metal layer and a bulk conductive layer disposed thereon. The work function metal layer may be a p-type or n-type work function metal layer. Example work function materials include: TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The bulk conductive layer may include: Cu, W, Al, Co, Ru, other suitable materials, or combinations thereof. The high-dielectric-constant metal gate structure 210 may further include other layers (not shown), such as an interface layer, capping layer, barrier layer, other suitable layers, or combinations thereof disposed between the fin 204 and the high-dielectric-constant dielectric layer. Various layers of the high-dielectric-constant metal gate structure 210 can be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition (PVD), electroplating, other suitable methods, or combinations thereof.

[0053] The device 200 may further include a gate spacer 212 disposed on the sidewall of the high-dielectric-constant metal gate structure 210. In some embodiments, the gate spacer 212 includes one or more of the following elements: silicon, oxygen, nitrogen, and carbon. For example, the gate spacer 212 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, other suitable dielectric materials, or combinations thereof. It is worth noting that the gate spacer 212, the interlayer dielectric layer 218, and the etch stop layer 220 in the embodiments of this disclosure have different compositions, allowing them to be etched at different rates during the etching process. The gate spacer 212 can be formed on the sidewall of the high-dielectric-constant metal gate structure 210 by first depositing spacer material onto the device 200 and then performing an anisotropic etching process to remove part of the spacer material.

[0054] Still refer to Figure 3In some embodiments, the high-k dielectric metal gate structure 210 is formed after other components of the fabrication apparatus 200 (e.g., source / drain components 214). Such a process, commonly referred to as a gate replacement process, includes: forming a dummy gate structure (not shown) as a placeholder for the high-k dielectric metal gate structure 210; forming the source / drain components 214; forming an interlayer dielectric layer 218 over the source / drain components 214; planarizing the interlayer dielectric layer 218 to expose the top surface of the dummy gate structure; removing the dummy gate structure to form a trench exposing the channel region of the fins 204; and forming the high-k dielectric metal gate structure 210 in the trench to complete the gate replacement process. Subsequently, a polishing process, such as a chemical mechanical polishing process, can be performed to remove excess material from the top surface of the high-k dielectric metal gate structure 210 to planarize the top surface of the apparatus 200. In some embodiments, the interlayer dielectric layer 218 comprises a dielectric material, such as silicon oxide, a low dielectric constant dielectric material, tetraethylorthosilicate (TEOS), doped silicon oxide (e.g., borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), other suitable dielectric materials, or combinations thereof. The interlayer dielectric layer 218 may comprise a multilayer or monolayer structure and may be formed by a deposition process, such as chemical vapor deposition, flow-through chemical vapor deposition, spin-coating, other suitable methods, or combinations thereof. The etch stop layer 220 may comprise silicon nitride, silicon oxynitride, oxygen-containing silicon nitride, and / or carbon, aluminum oxide, aluminum nitride, other suitable materials, or combinations thereof, and may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.

[0055] Reference Figure 4 In method 100, trench 230 (i.e., source / drain contact trench) is formed in operation 104 to expose source / drain components 214. In embodiments of this disclosure, method 100 first forms an interlayer dielectric layer 222 over an etch stop layer 220, and then removes portions of the interlayer dielectric layer 222, the etch stop layer 220, and the interlayer dielectric layer 218 to form the trench 230. In embodiments of this disclosure, the interlayer dielectric layer 222 includes silicon oxide, a low-dielectric-constant dielectric material, or a combination thereof. In some embodiments, the low-dielectric-constant dielectric material is a silicon-containing low-dielectric-constant dielectric material. In some embodiments, the interlayer dielectric layer 222 includes a dielectric material with a density equal to or less than that of silicon oxide, having a density of approximately 2.1 g / cm³. 3 Approximately 2.6 g / cm³ 3In some embodiments, the interlayer dielectric layer 222 does not include a nitrogen-containing dielectric material, such as silicon nitride, having a density of about 2.8 g / cm³. 3 Approximately 3.2 g / cm³ 3 The following will discuss in detail that, to accommodate subsequent process steps, the interlayer dielectric layer 222 comprises a low-density (e.g., porous) dielectric material. The process for forming the interlayer dielectric layer 222 can be similar to the process discussed above regarding the interlayer dielectric layer 218.

[0056] Subsequently, method 100 can form the trench 230 in a series of patterning and etching processes. For example, a mask element (not shown) including photoresist as a top layer can be formed on the interlayer dielectric layer 222, and then patterned to expose the portion of the interlayer dielectric layer 222 to be removed. The patterning process may include: exposing the mask element to a radiation source through a patterned mask to form a latent image in the mask element, developing the latent image to form the patterned mask element, and optionally baking the patterned mask element. Thereafter, method 100 performs an appropriate etching process, using the patterned mask element as an etching mask, to anisotropically remove portions of the material layers (e.g., interlayer dielectric layer 222, interlayer dielectric layer 218, and etch stop layer 220) disposed on the source / drain components 214, thereby creating the trench 230. In an example embodiment, method 100 uses an etchant to perform a dry etching process, the etchant including: fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), H2, O2, other suitable gases, or combinations thereof. The patterned masking elements are then removed from apparatus 200 by any suitable method (e.g., impedance stripping or plasma ashing).

[0057] Reference Figure 5In method 100, a sacrificial layer 232 is formed in trench 230 in operation 106. In embodiments of this disclosure, the sacrificial layer 232 comprises a dielectric material whose composition differs from the surrounding material layers, so that in subsequent process steps, the sacrificial layer 232 can be selectively etched relative to interlayer dielectric layer 222, etch stop layer 220, and interlayer dielectric layer 218. In some embodiments, the sacrificial layer 232 comprises silicon, oxygen, nitrogen, carbon, other suitable materials, or combinations thereof. In an example embodiment, the sacrificial layer 232 comprises silicon, for example, in the form of amorphous silicon. The sacrificial layer 232 can be formed by any suitable method, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or combinations thereof. In some embodiments, as shown, the sacrificial layer 232 is formed on the bottom and sidewall surfaces of trench 230. In some embodiments, the sacrificial layer 232 is selectively formed on the sidewalls of the trench 230 (for example, on a portion of the interlayer dielectric layer 222, the etch stop layer 220, and the interlayer dielectric layer 218) rather than on the source / drain components 214. In embodiments of this disclosure, the sacrificial layer 232 is subsequently removed from the device 200, thereby forming an air gap between the source / drain contacts formed in the trench 230 and the portion of the interlayer dielectric layer 222, the etch stop layer 220, and the interlayer dielectric layer 218. Thus, the thickness t of the sacrificial layer 232 defines the width of the air gap. In some embodiments, the thickness t is from about 1 nm to about 5 nm. It should be noted that, on the one hand, if the thickness t is less than about 1 nm, it may be impossible to reduce the parasitic capacitance in the device 200; on the other hand, a measured width of the air gap greater than about 5 nm (i.e., a thickness t greater than about 5 nm) may hinder the execution of subsequent process steps.

[0058] Reference Figure 6 In method 100, in operation 108, source / drain contacts 238 are formed over a sacrificial layer 232 in trench 230. The source / drain contacts 238 include a conductive layer 236 disposed over a barrier layer 235. The barrier layer 235 may include titanium nitride, tantalum nitride, tungsten nitride, other suitable materials, or combinations thereof, and may be formed over the sacrificial layer 232 using any suitable method, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable methods, or combinations thereof. In some embodiments, the barrier layer 235 is omitted from the device 200. The conductive layer 236 may include Cu, W, Al, Co, Ru, other suitable materials, or combinations thereof. The conductive layer 236 may be formed using any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, other suitable methods, or combinations thereof.

[0059] Reference Figure 6Before forming the source / drain contacts 238, method 100 may form a silicide layer 234 over the source / drain components 214. If, as described above, a portion of the sacrificial layer 232 is formed over the source / drain components 214, the formation of the silicide layer 234 may remove this portion of the sacrificial layer 232, allowing the silicide layer 234 to directly contact the source / drain components 214. In some embodiments, the silicide layer 234 includes: nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. After performing an optional cleaning process to remove any residue remaining over the source / drain components 214 and / or any portion of the sacrificial layer 232, the silicide layer 234 may be formed by a deposition process, such as: chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations thereof. As an example, a metal layer (e.g., titanium) can be deposited over the source / drain component 214, and the device 200 can be annealed to react the metal layer with the semiconductor material of the source / drain component 214. Afterward, the unreacted metal layer is removed, leaving a silicide layer 234 over the source / drain component 214. Alternatively, the silicide layer 234 can be deposited directly over the source / drain component 214 using a suitable deposition process.

[0060] Reference Figure 7 In method 100, operation 110 selectively removes the sacrificial layer 232 to form an air gap 240 comprising an upper portion 240a and a lower portion 240b. In embodiments of this disclosure, the upper portion 240a is disposed within the interlayer dielectric layer 222, while the lower portion 240b is disposed below the upper portion 240a. That is, the upper portion 240a is defined by the source / drain contacts 238 and the interlayer dielectric layer 222, while the lower portion 240b is defined by the source / drain contacts 238, a portion of the etch stop layer 220, and the interlayer dielectric layer 218. As described above, the resulting air gap 240 can be defined by a width w, which is substantially equal to the thickness t of the sacrificial layer 232. In some examples, the width w is greater than 0 but less than approximately 4 nm, with 4 nm being a critical value above which the merging of the upper portion 240a may require more than one implantation process and / or a higher dose of dopant particles. In these embodiments, during operation 110, the sacrificial layer 232 is selectively etched such that portions of the interlayer dielectric layer 222, etch stop layer 220, interlayer dielectric layer 218, and barrier layer 235 that contact the sacrificial layer 232 are not etched, or are substantially not etched. In some embodiments, method 100 uses an etchant comprising H2 and / or NF3 to perform a dry etching process to selectively remove the sacrificial layer 232.

[0061] Backward reference Figure 1 Method 100 can proceed from operation 110 to one of the two alternative paths, path A and path B. In the following embodiments of this disclosure, reference will be made to... Figure 8A and Figure 8B Discuss path A, and refer to Figure 9A and Figure 9B Path B will be discussed. It should be understood that this disclosure does not require method 100 to be performed in any particular path; that is, the embodiments described in both path A and path B are equally applicable. Path A is an embodiment where a placement process is first performed on the interlayer dielectric layer 222, and then an etch stop layer is formed above the interlayer dielectric layer 222. On the other hand, path B is an embodiment where an etch stop layer is first formed on the interlayer dielectric layer 222, and then a placement process is performed on the underlying interlayer dielectric layer 222. Thus, for the purposes of this disclosure, path A is referred to as the "etch stop layer last (ESL last)" process, and path B is referred to as the "etch stop layer first (ESL first)" process.

[0062] Regarding path A, refer to... Figure 8A Method 100 performs a implantation (or ion implantation) process 310 on device 200 in operation 112a. In these embodiments, the implantation process 310 is configured to fill the upper portion 240a of the air gap 240, but not the lower portion 240b of the air gap 240, by introducing dopant into the interlayer dielectric layer 222. That is, the implantation process 310 expands a portion of the interlayer dielectric layer 222 (schematically indicated by the dashed arrow), reducing the width w of the air gap 240 to approximately 0 in the upper portion 240a, but substantially remaining unchanged in the lower portion 240b. In other words, the implantation process 310 is configured to merge a portion of the interlayer dielectric layer 222 with the sidewall portion of the source / drain contact 238, thereby filling the upper portion 240a of the air gap 240. To describe it in another way, the implantation process 310 seals the top opening of the air gap 240 with the interlayer dielectric layer 222, and allows the remaining part of the air gap 240 (i.e., the lower part 240b) to extend from the source / drain component 214 through the interlayer dielectric layer 218 and the etch stop layer 220, but not through the interlayer dielectric layer 222.

[0063] The implantation process 310 is typically implemented in an ion implantation apparatus, which includes: at least one ion source configured to generate a beam 320 containing ions of the desired element (hereinafter referred to as dopant particles); a device for selecting ions from the beam having a specific beam energy; and an accelerator configured to accelerate the beam toward a target (e.g., a device 200 having an interlayer dielectric layer 222 disposed on its top surface); other components may also be included in the ion implantation apparatus. In embodiments of this disclosure, as the beam 320 accelerates toward and penetrates the device 200, the dopant particles of the beam 320 are introduced into the interlayer dielectric layer 222. By adjusting various process parameters of the implantation process 310 (discussed in detail below), the penetration of the beam 320 can be confined within the interlayer dielectric layer 222, rather than within the etch stop layer 220 or other underlying material layers. Due to the size difference between the dopant particles and the main component (i.e., silicon) of the interlayer dielectric layer 222, the dopant particles create strain in the molecular structure of the interlayer dielectric layer 222, causing it to expand and occupy any available free space, i.e., the upper portion 240a of the air gap 240. In other words, the dopant particles increase the volume of the interlayer dielectric layer 222, thereby causing it to merge with the sidewalls of the source / drain contact 238 and close the upper portion 240a. In some embodiments, as described above, the low density (e.g., porosity) of the interlayer dielectric layer 222 also has a positive effect on the expansion of the interlayer dielectric layer 222 caused by the implantation process 310.

[0064] In embodiments of this disclosure, the implantation process 310 can be controlled by adjusting one or more of the following parameters: the composition of the dopant particles, the dosage of the dopant particles, the energy of the beam 320, or the angle 330 of the beam 320. As mentioned above, it is important that the dopant particles have an atomic radius (i.e., atomic number) different from the main component of the interlayer dielectric layer 222. In embodiments of this disclosure, the dopant particles have a larger atomic radius (i.e., number of atoms) compared to silicon present in the interlayer dielectric layer 222 in the form of silicon oxide and / or silicon-containing low-dielectric-constant dielectric materials as described above. In some embodiments, the dopant particles belong to the same group or period (e.g., group IV or period III) as silicon. In some embodiments, the dopant particles belong to an adjacent group (e.g., group V) or period (e.g., period IV) of silicon. Furthermore, in embodiments of this disclosure, because the interlayer dielectric layer 222 provides insulation for subsequently formed device components (e.g., interconnect components), the dopant particles do not contain any metallic (i.e., conductive) elements. In some examples, the dopant particles include elements such as germanium and / or arsenic.

[0065] In this embodiment of the disclosure, the dopant particle dose describes the number of dopant particles (unit: atoms / cm) per unit area impacting the interlayer dielectric layer 222.2 The total amount of dopant particles. This is a parameter that roughly reflects the amount of dopant particles required to expand the interlayer dielectric layer 222 and eliminate the upper portion 240a. Therefore, as provided herein, the dopant particle dosage is based on the thickness D of the interlayer dielectric layer 222 and / or Figure 7 The width w of the upper portion 240a varies. In one example, increasing the thickness D typically increases the dose of dopant particles. In another example, increasing the width w of the upper portion 240a also typically increases the dose of dopant particles. In some examples, if the thickness D exceeds approximately 25 nm, method 100 may perform operation 112a more than once, i.e., repeat the implantation process 310 at least once, to provide a sufficient dose of dopant particles for incorporating the upper portion 240a. On the other hand, if the thickness D is less than approximately 25 nm, method 100 may perform the implantation process 310 only once and form as shown in the image. Figure 8A The structure is shown. In embodiments of this disclosure, the dose of dopant particles is from about 1E14 to about 5E16 atoms / cm². 2 In some embodiments, if the dose is less than about 1E14 atoms / cm 2 If the dopant particles provided by the implantation process 310 are insufficient, the upper portion 240a may not be completely filled. In some embodiments, if the dose is greater than about 5E16 atoms / cm 2 Excessive dopant particles may penetrate and unintentionally bombard other device components, such as the high-dielectric-constant metal gate structure 210, fins 204, and / or other device components. In some examples, the dopant particle concentration obtained in the interlayer dielectric layer 222 is approximately 1E19 atoms / cm². 3 Approximately 1E22 atoms / cm 3 Of course, depending on specific design requirements and the dosage implemented during the implantation process 310, other concentrations of dopants may also be applicable to the embodiments of this disclosure.

[0066] In this embodiment of the disclosure, with other factors remaining constant, the maximum energy of beam 320 determines the maximum depth to which dopant particles can penetrate. In some embodiments, any additional material layer disposed above interlayer dielectric layer 222 typically increases the energy required for beam 320 to penetrate interlayer dielectric layer 222, although the dose of dopant particles may remain substantially constant. In some embodiments, keeping the dose constant, a change in beam angle (discussed in detail below) results in a change in the energy of beam 320.

[0067] The beam 320 may strike the device 200 at an angle 330 (relative to the normal to the surface of the interlayer dielectric layer 222). In embodiments of this disclosure, the angle 330 is not limited to any specific value, provided it remains within the permissible range of the ion implantation apparatus. In some examples of embodiments of this disclosure, the angle 330 is approximately 0° (i.e., the beam 320 is perpendicular to the interlayer dielectric layer 222) to approximately 60°. Holding other factors constant, increasing the angle 330 generally reduces the penetration depth of the dopant particles. Therefore, to maintain the overall implantation result, increasing the angle 330 increases the energy required for the beam 320 to penetrate the interlayer dielectric layer 222. Conversely, decreasing the angle 330 reduces the energy required for the beam 320 to penetrate the interlayer dielectric layer 222. Therefore, the angle 330 can be adjusted according to the energy of the beam 320 to achieve the desired implantation result. For path A, which forms the etch stop layer 250 after the implantation process 310, the angle 330 can be adjusted to be greater than about 15° to minimize the potential damage of the beam 320 to the source / drain components 214.

[0068] In this embodiment of the disclosure, the filling of the upper portion 240a leaves a partial air gap (i.e., the lower portion 240b) between a portion of the source / drain contact 238 and the high-dielectric-constant metal gate structure 210. That is, after performing operation 112a, method 100 seals the air gap 240 by expanding the interlayer dielectric layer 222 to merge with the sidewall portion of the source / drain contact 238 (e.g., barrier layer 235), effectively confining the air gap 240 between the interlayer dielectric layer 222 and the source / drain component 214. Since the dielectric constant of air is lower than that of most dielectric materials, the presence of the air gap generally reduces parasitic capacitance between conductive components; however, the air gap may introduce unintentional structural defects in some field-effect transistors. In one such example, due to the lack of etch-stopping power, the presence of an air gap may cause over-etching of the interlayer dielectric layer 222 (e.g., opening an already sealed air gap) when forming via contacts above the source / drain contacts 238. Furthermore, any subsequent wet etching processes (e.g., to remove photolithography mask elements) may allow wet chemicals to flow into the air gap, potentially damaging the source / drain components 214, the high-dielectric-constant metal gate structure 210, and / or other device components. Embodiments of this disclosure provide a partial air gap, preserving the effectiveness of reducing parasitic capacitance while protecting the device structure from unintentional damage during subsequent process steps. Regardless of whether method 100 is performed via path A or path B (discussed in detail below), the method described in this disclosure is to first form an air gap 240 extending from the source / drain component 214 to the top surface of the interlayer dielectric layer 222, and then fill the upper portion 240a of the air gap 240 disposed in the interlayer dielectric layer 222, leaving the lower portion 240b disposed between the source / drain contact 238 and the high dielectric constant metal gate structure 210.

[0069] Reference Figure 8BIn method 100, in operation 114a, an etch stop layer 250 is deposited over the interlayer dielectric layer 222. The etch stop layer 250 comprises one or more dielectric materials, such as silicon nitride, silicon oxynitride, oxygen-containing silicon nitride, and / or carbon, aluminum oxide, aluminum nitride, other suitable materials, or combinations thereof. It is noteworthy that, in order to provide etch selectivity relative to the interlayer dielectric layer 222, the composition of the etch stop layer 250 is significantly different from the composition of the interlayer dielectric layer 222. In some embodiments, the composition of the etch stop layer 250 is similar to that of the aforementioned etch stop layer 220. The etch stop layer 250 can be formed to any suitable thickness T by any suitable method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. In one example embodiment, the thickness T is from about 5 nm to about 15 nm. Of course, embodiments of this disclosure are not limited to such dimensions.

[0070] Since the upper portion 240a has been filled in a previous operation, the bottom surface of the etch stop layer 250 is disposed above the top surface of the interlayer dielectric layer 222 and the source / drain contacts 238. In some embodiments, the entire etch stop layer 250 is located above the top surface of the interlayer dielectric layer 222, and the etch stop layer 250 does not penetrate into the interlayer dielectric layer 222. In some examples, the etch stop layer 250 penetrates the interlayer dielectric layer 222 to a depth of approximately less than 3 nm.

[0071] Regarding path B, refer to... Figure 9A Method 100 proceeds from operation 110 to operation 112b, forming an etch stop layer 250 on the interlayer dielectric layer 222 to seal the air gap 240 (i.e., the upper portion 240a). As discussed above with respect to operation 114a, the composition of the etch stop layer 250 differs from that of the interlayer dielectric layer 222 and may include one or more dielectric materials, such as silicon nitride, silicon oxynitride, oxygen-containing silicon nitride, and / or carbon, aluminum oxide, aluminum nitride, other suitable materials, or combinations thereof. As mentioned above, the etch stop layer 250 can be formed to any suitable thickness T by any suitable method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. Although, as discussed above with respect to operation 114a, the embodiments disclosed herein do not limit the composition or thickness T of the etch stop layer 250, which will be discussed in detail below relative to the energy of the beam 320 (compare). Figure 8A and Figure 9B In some embodiments of the etch stop layer 250, the energy of the implemented beam 350 can be altered in a subsequent implantation process 340. Figure 8BIn contrast, since an air gap 240a exists in the interlayer dielectric layer 222, an etch stop layer 250 is formed in the air gap 240, forming a portion 250a. In other words, the etch stop layer 250 formed on the interlayer dielectric layer 222 partially fills the upper portion 240a. In some examples, the portion 250a has a thickness d of about 3 nm to about 8 nm. The thickness d can vary with the width w of the air gap 240. For example, the ratio of thickness d to width w can be about 0.8 to about 3, and the ratio of thickness d to thickness D can be about 0.1 to about 0.4. Of course, the embodiments disclosed herein are not limited to such dimensions.

[0072] Reference Figure 9B In method 100, a placement process 340 is performed on device 200 in operation 114b. Similar to placement process 310, placement process 340 is configured to fill upper portion 240a by bombarding interlayer dielectric layer 222 with a beam 350 of energetic dopant particles. However, because etch stop layer 250 is formed above interlayer dielectric layer 222 before placement process 340 is performed, placement process 340 is configured to pass through etch stop layer 250 before penetrating interlayer dielectric layer 222 and causing interlayer dielectric layer 222 to expand.

[0073] In this embodiment, the implementation of the implantation process 340 is similar to that of the implantation process 310 discussed above. For example, the implantation process 340 is typically implemented in an ion implantation apparatus, which generates, filters, and accelerates a beam 350 of charged ions (i.e., dopant particles) toward the device 200. Furthermore, similar to what has been discussed above regarding the implantation process 310, the implantation process 340 can be adjusted by changing process factors, such as the composition of the dopant particles, the dosage of the dopant particles, the energy of the beam 350, and / or the angle 360 ​​of the beam 350. However, unlike the implantation process 310, the implantation process 340 is configured to introduce dopant particles into the interlayer dielectric layer 222 through ion bombardment, passing through the etch stop layer 250. In other words, Figure 9B The beam 350 shown is configured to penetrate the etch stop layer 250 and the interlayer dielectric 222 to fill the upper portion 240a. Therefore, in this embodiment of the present disclosure, although most of the dopant particles can be found in the interlayer dielectric layer 222, a relatively small portion of the dopant particles can also be found in the etch stop layer 250, which will be discussed in detail below.

[0074] In embodiments of this disclosure, the presence of an additional material layer typically increases the energy of the beam 350 used to penetrate the interlayer dielectric layer 222, while the dose of dopant particles can remain substantially constant. Therefore, in embodiments of this disclosure, the energy of beam 350 is greater than the energy of beam 320 when other factors (e.g., the dose of dopant particles and the angle 360 ​​of beam 350) remain substantially constant. In embodiments of this disclosure, the thickness T is from approximately 5 nm to approximately 15 nm as described above, and the energy variation of beam 350 can be proportional to the thickness T. In an example embodiment, if the thickness T is approximately 10 nm, the energy of beam 350 is approximately 4 to 5 times higher than the energy of beam 320. Furthermore, if the etch stop layer 250 comprises particles larger than silicon (the main component of interlayer dielectric layer 222), the energy of beam 350 may also be increased. Because the etch stop layer 250 is formed as a protective layer for the underlying components before the implantation process 340 is performed, the angle 360 ​​can be implemented at any suitable angle, as discussed in detail above, without damaging the underlying source / drain components 214.

[0075] Reference Figure 10 This is a schematic diagram illustrating the relationship between the dopant concentration and the depth below the top surface of device 200. For clarity, the area marked "250" corresponds to the etch stop layer 250, and the area marked "222" corresponds to the interlayer dielectric layer 222. In embodiments of this disclosure, by adjusting various parameters discussed herein, the implantation process 340 is configured to provide the highest number of dopant particles in the interlayer dielectric layer 222 relative to other material layers to expand the interlayer dielectric layer 222 and fill the upper portion 240a. For example, as... Figure 10 As shown, the concentration of dopants, expressed on a logarithmic scale along the y-axis, increases from A at depth 0 (located at the surface) to a maximum value B in the interlayer dielectric layer 222. In embodiments of this disclosure, this increase is typically about one to two orders of magnitude. In some examples, the ratio of the dopant concentration in the interlayer dielectric layer 222 to the dopant concentration in the etch stop layer 250 can be about 5 to about 500. Of course, embodiments of this disclosure are not limited to this range, and the concentration of dopants can be adjusted using the methods provided herein. Figure 10 Three curves representing different doses of doped particles and / or beam energies are also shown, where an upward shift of the curve indicated by the dashed arrow represents an increase in dose at a given depth.

[0076] Subsequently, method 100 performs additional process steps on device 200 in operation 116. In some examples, method 100 may form additional contact features, such as gate contacts, on the high-dielectric-constant metal gate 210. Alternatively or additionally, method 100 may form interconnect structures, such as vias and / or wires, on device 200.

[0077] Not limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their formation. For example, the semiconductor structure provided in embodiments of this disclosure has an air gap disposed on a sidewall at the bottom of a source / drain contact, but not on a sidewall at the top of the source / drain contact, with the top opening of the air gap sealed by an interlayer dielectric layer disposed on a metal gate stack adjacent to the source / drain contact. In some embodiments, a method of forming this semiconductor structure includes: forming source / drain contacts embedded in a first interlayer dielectric layer and a second interlayer dielectric layer disposed above the first interlayer dielectric layer; forming an air gap on the sidewall of the source / drain contact extending through the first and second interlayer dielectric layers; and subsequently filling a portion of the air gap disposed in the second interlayer dielectric layer. In some embodiments, filling this portion of the air gap includes bombarding the second interlayer dielectric layer with dopant particles containing Ge and / or As, causing the dopant particles to expand the second interlayer dielectric layer and thus seal this portion of the air gap disposed therein. In this embodiment, the partial air gap remaining on the sidewall at the bottom of the source / drain contact reduces the parasitic capacitance between the source / drain contact and the adjacent metal gate stack. Simultaneously, sealing the air gap using an ion-implantation process prevents it from reopening during subsequent processes, thus preventing structural damage to the device.

[0078] In one aspect, embodiments of this disclosure provide a semiconductor structure comprising: source / drain components disposed in a semiconductor layer; a metal gate stack disposed in and adjacent to the source / drain components in a first interlayer dielectric layer; a second interlayer dielectric layer disposed above the metal gate stack; and source / drain contacts disposed above the source / drain components. The semiconductor structure further includes an air gap disposed between the bottom sidewall of the source / drain contacts and the first interlayer dielectric layer, wherein the top sidewall of the source / drain contacts is in direct contact with the second interlayer dielectric layer.

[0079] In some embodiments, the semiconductor structure further includes an etch stop layer disposed above the second interlayer dielectric layer. In some embodiments, the bottom of the etch stop layer extends below the top surface of the second interlayer dielectric layer. In some embodiments, the bottom of the etch stop layer is located above the top surface of the second interlayer dielectric layer. In some embodiments, the semiconductor structure further includes an etch stop layer disposed between the first and second interlayer dielectric layers. In some embodiments, an air gap extends vertically through the etch stop layer. In some embodiments, the first interlayer dielectric layer comprises a dielectric material free of germanium and arsenic, and the second interlayer dielectric layer comprises a dielectric material doped with germanium, arsenic, or a combination thereof.

[0080] On the other hand, embodiments of this disclosure provide a semiconductor structure comprising: a plurality of metal gate stacks disposed in a first interlayer dielectric layer; source / drain components disposed between the metal gate stacks; a second interlayer dielectric layer disposed above the metal gate stacks; and contact components disposed above the source / drain components and extending through the first and second interlayer dielectric layers. The semiconductor structure further comprises: an air gap disposed on a plurality of sidewalls of the contact components, wherein the second interlayer dielectric layer seals the air gap; and an etch stop layer disposed above the second interlayer dielectric layer, wherein the etch stop layer and the air gap are partially separated by the second interlayer dielectric layer.

[0081] In some embodiments, the second interlayer dielectric layer comprises a germanium-doped silicon-containing dielectric material, and the etch stop layer comprises a germanium-free silicon-containing dielectric material. In some embodiments, the second interlayer dielectric layer comprises an arsenic-doped silicon-containing dielectric material, and the etch stop layer comprises an arsenic-free silicon-containing dielectric material. In some embodiments, the second interlayer dielectric layer and the etch stop layer comprise germanium, arsenic, or a combination thereof, and the concentration of germanium, arsenic, or the combination thereof in the second interlayer dielectric layer is greater than the concentration in the etch stop layer. In some embodiments, the etch stop layer is a first etch stop layer, and the semiconductor structure further includes a second etch stop layer disposed between the first and second interlayer dielectric layers, wherein the composition of the first etch stop layer differs from the composition of the second etch stop layer. In some embodiments, a portion of the etch stop layer is disposed between the second interlayer dielectric layer and a contact component. In some embodiments, the etch stop layer comprises silicon nitride, and the second interlayer dielectric layer does not contain silicon nitride.

[0082] In another aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: firstly, providing a metal gate stack disposed in a first interlayer dielectric layer, source / drain components disposed adjacent to the metal gate stack, and a second interlayer dielectric layer disposed above the metal gate stack; forming contact trenches in the first and second interlayer dielectric layers to expose the source / drain components; forming a sacrificial layer in the contact trenches; and forming source / drain contacts above the sacrificial layer. The method for forming the semiconductor structure further comprises: subsequently removing the sacrificial layer to form air gaps on a plurality of sidewalls of the source / drain contacts, and filling the top of the air gaps disposed above the metal gate stack, such that the bottom of the air gaps is sealed by the second interlayer dielectric layer.

[0083] In some embodiments, removing the top of the air gap includes performing an ion implantation process on the second interlayer dielectric layer to expand the second interlayer dielectric layer and seal the air gap. In some embodiments, performing the ion implantation process includes bombarding the second interlayer dielectric layer with particles, said particles including germanium, arsenic, or combinations thereof. In some embodiments, the method of forming the semiconductor structure further includes forming an etch stop layer over the second interlayer dielectric layer after removing the top of the air gap. In some embodiments, removing the top of the air gap includes forming an etch stop layer over the second interlayer dielectric layer, such that the etch stop layer partially fills the air gap; and thereafter bombarding the second interlayer dielectric layer with particles, said particles including germanium, arsenic, or combinations thereof. In some embodiments, the bombardment of the second interlayer dielectric layer leaves some of the particles in the etch stop layer.

[0084] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily utilize this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the concept and scope of this disclosure, and that various changes, substitutions, and replacements can be made therein without departing from the concept and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: A source / drain component is disposed in a semiconductor layer; A first interlayer dielectric layer is disposed above the source / drain component; A second interlayer dielectric layer is disposed above the first interlayer dielectric layer; A source / drain contact is disposed in the first interlayer dielectric layer and the second interlayer dielectric layer to contact the source / drain component; An air gap is disposed between a bottom sidewall of the source / drain contact and the first interlayer dielectric layer, wherein a top sidewall of the source / drain contact is in direct contact with the second interlayer dielectric layer, and wherein the air gap is exposed on a top surface of the source / drain component. as well as An etch stop layer is disposed above the second interlayer dielectric layer, wherein the etch stop layer is a first etch stop layer, and the semiconductor structure further includes a second etch stop layer disposed between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein one bottom surface of the second interlayer dielectric layer is a plane that covers the second etch stop layer and seals a top opening of the air gap.

2. The semiconductor structure of claim 1, wherein a bottommost part of the etch stop layer extends below a top surface of the second interlayer dielectric layer and directly contacts the sidewall of the top of the source / drain contact.

3. The semiconductor structure of claim 1, wherein a bottom layer of the etch stop layer is located above a top surface of the second interlayer dielectric layer.

4. The semiconductor structure of claim 1, wherein the air gap extends vertically through the second etch stop layer.

5. The semiconductor structure of claim 1, wherein the first interlayer dielectric layer comprises a dielectric material free of germanium and arsenic, and wherein the second interlayer dielectric layer comprises a dielectric material doped with germanium, arsenic, or a combination thereof.

6. A semiconductor structure, comprising: A source / drain component is disposed in a semiconductor fin; A first interlayer dielectric layer is disposed above the semiconductor fin; A second interlayer dielectric layer is disposed above the first interlayer dielectric layer; A contact component is disposed above the source / drain component, wherein the contact component extends through the first interlayer dielectric layer and the second interlayer dielectric layer; An air gap is provided along multiple sidewalls of the contact component, wherein a top surface of the source / drain component seals a bottom opening of the air gap; as well as An etch stop layer is disposed above the second interlayer dielectric layer, wherein the etch stop layer and the air gap are partially separated by the second interlayer dielectric layer, wherein the etch stop layer is a first etch stop layer, and the semiconductor structure further includes a second etch stop layer disposed between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein one bottom surface of the second interlayer dielectric layer is a plane that covers the second etch stop layer and seals a top opening of the air gap.

7. The semiconductor structure of claim 6, wherein the second interlayer dielectric layer comprises a germanium-doped silicon dielectric material, and wherein the etch stop layer comprises a germanium-free silicon dielectric material.

8. The semiconductor structure of claim 6, wherein the second interlayer dielectric layer comprises an arsenic-doped silicon dielectric material, and wherein the etch stop layer comprises an arsenic-free silicon dielectric material.

9. The semiconductor structure of claim 6, wherein the second interlayer dielectric layer and the etch stop layer comprise germanium, arsenic, or a combination thereof, and wherein the concentration of germanium, arsenic, or a combination thereof in the second interlayer dielectric layer is greater than the concentration in the etch stop layer.

10. The semiconductor structure of claim 6, wherein the composition of the first etch stop layer is different from the composition of the second etch stop layer.

11. The semiconductor structure of claim 6, wherein a portion of the etch stop layer directly contacts one sidewall of the contact member.

12. The semiconductor structure of claim 6, wherein the etch stop layer comprises silicon nitride, and wherein the second interlayer dielectric layer does not contain silicon nitride.

13. A semiconductor structure comprising: A source / drain component is disposed in a semiconductor fin; A first interlayer dielectric layer is disposed above the semiconductor fin; A second interlayer dielectric layer is disposed above the first interlayer dielectric layer; A source / drain contact is disposed in the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the source / drain contact is electrically coupled to the source / drain component; An air gap is disposed in the first interlayer dielectric layer, wherein multiple sidewalls of the air gap are defined by the source / drain contact and the first interlayer dielectric layer, and a bottom opening of the air gap exposes the source / drain component; as well as An etch stop layer is disposed above the second interlayer dielectric layer, wherein the etch stop layer is a first etch stop layer, and the semiconductor structure further includes a second etch stop layer disposed between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein one bottom surface of the second interlayer dielectric layer is a plane that covers the second etch stop layer and seals a top opening of the air gap.

14. The semiconductor structure of claim 13, wherein the sidewalls of the air gap are further defined by the second interlayer dielectric layer.

15. The semiconductor structure of claim 13, further comprising a silicide layer disposed between the source / drain component and the source / drain contact, wherein the sidewalls of the air gap are further defined by the silicide layer.

16. The semiconductor structure of claim 13, wherein a separation distance between a bottom surface of the etch stop layer and the top opening of the air gap is defined by a thickness of the second interlayer dielectric layer.

17. The semiconductor structure of claim 13, wherein the second interlayer dielectric layer comprises a dielectric material doped with germanium, arsenic, or a combination thereof.

18. The semiconductor structure of claim 13, wherein a portion of the etch stop layer directly contacts one sidewall of the source / drain contact.

19. A method for forming a semiconductor structure, comprising: A metal gate stack is provided in a first interlayer dielectric layer, a source / drain component is provided adjacent to the metal gate stack, a second interlayer dielectric layer is provided above the metal gate stack, and a bottom etch stop layer is provided between the first interlayer dielectric layer and the second interlayer dielectric layer; A contact trench is formed in the first interlayer dielectric layer and the second interlayer dielectric layer to expose the source / drain component; A sacrificial layer is formed in the contact groove; A source / drain contact is formed above the sacrificial layer; Remove the sacrificial layer to form an air gap on multiple sidewalls of the source / drain contact; as well as The top of the air gap disposed above the metal gate stack is filled, such that the bottom of the air gap is sealed by the second interlayer dielectric layer, wherein one bottom surface of the second interlayer dielectric layer is a plane that covers the underlying etch stop layer and seals the top opening of the air gap.

20. The method of forming a semiconductor structure as claimed in claim 19, wherein filling the top of the air gap includes performing an ion implantation process on the second interlayer dielectric layer to expand the second interlayer dielectric layer to seal the air gap.

21. The method of forming a semiconductor structure as claimed in claim 20, wherein the ion implantation process includes bombarding the second interlayer dielectric layer with a plurality of particles, the particles including germanium, arsenic, or a combination thereof.

22. The method for forming a semiconductor structure as described in claim 19, further comprising: After filling the top of the air gap, an upper etch stop layer is formed above the second interlayer dielectric layer.

23. The method of forming a semiconductor structure as claimed in claim 19, wherein the top filling the air gap comprises: An upper etch stop layer is formed above the second interlayer dielectric layer, such that the upper etch stop layer partially fills the air gap; as well as Subsequently, the second interlayer dielectric layer is bombarded with multiple particles, including germanium, arsenic, or combinations thereof.

24. The method of forming a semiconductor structure as claimed in claim 23, wherein the bombardment of the second interlayer dielectric layer leaves some of the particles in the upper etch stop layer.

25. The method of forming a semiconductor structure as claimed in claim 19, wherein the sacrificial layer comprises silicon in the form of amorphous silicon, and the second interlayer dielectric layer comprises silicon oxide.

26. A method for forming a semiconductor structure, comprising: A source / drain component is formed on a semiconductor substrate; A first interlayer dielectric layer is formed above the source / drain component; A second interlayer dielectric layer is formed above the first interlayer dielectric layer and a lower etch stop layer, wherein the lower etch stop layer is disposed between the first interlayer dielectric layer and the second interlayer dielectric layer; An opening is formed in the second interlayer dielectric layer to expose the source / drain component; A sacrificial layer is deposited along multiple sidewalls of the opening; A source / drain contact is formed above the sacrificial layer; Remove the sacrificial layer to form an air gap, wherein the air gap extends from the second interlayer dielectric layer to expose the source / drain component; as well as The second interlayer dielectric layer is processed such that one of the bottom surfaces of the second interlayer dielectric layer is a plane that covers the etch stop layer below and seals the top of the air gap disposed in the second interlayer dielectric layer, but does not seal the bottom of the air gap disposed in the first interlayer dielectric layer.

27. The method of forming a semiconductor structure as claimed in claim 26, wherein processing the second interlayer dielectric layer includes bombarding the second interlayer dielectric layer with a plurality of particles, causing the second interlayer dielectric layer to merge with a sidewall of the source / drain contact, thereby sealing the top of the air gap.

28. The method of forming a semiconductor structure as claimed in claim 27, wherein the particles comprise germanium, arsenic, or a combination thereof.

29. The method of forming a semiconductor structure as claimed in claim 27, wherein the bombardment of the second interlayer dielectric layer is carried out at an angle relative to a direction perpendicular to a top surface of the second interlayer dielectric layer.

30. The method of forming a semiconductor structure as claimed in claim 26, further comprising forming an upper etch stop layer above the second interlayer dielectric layer after processing the second interlayer dielectric layer.

31. The method of forming a semiconductor structure as claimed in claim 26, further comprising forming an upper etch stop layer above the second interlayer dielectric layer before processing the second interlayer dielectric layer, such that the etch stop layer partially seals the air gap.

32. A method for forming a semiconductor structure, comprising: A semiconductor structure is provided, the semiconductor structure including a source / drain component disposed adjacent to a gate structure, wherein the gate structure is disposed in a first interlayer dielectric layer; A second interlayer dielectric layer is formed above the gate structure and a lower etch stop layer, wherein the lower etch stop layer is disposed between the first interlayer dielectric layer and the second interlayer dielectric layer; Remove part of the first interlayer dielectric layer and part of the second interlayer dielectric layer to expose the source / drain component in a first opening; A sacrificial layer is formed in the first opening; A conductive component is formed above the sacrificial layer to fill the first opening; The sacrificial layer is etched to form a second opening, wherein the second opening includes a top separating the conductive component from the second interlayer dielectric layer, and a bottom separating the conductive component from the first interlayer dielectric layer; and The second interlayer dielectric layer is merged with one sidewall of the conductive component, such that one bottom surface of the second interlayer dielectric layer is a plane relative to the top of the bottom that covers the underlying etch stop layer and seals the second opening.

33. The method of forming a semiconductor structure as claimed in claim 32, wherein the sacrificial layer comprises silicon in the form of amorphous silicon.

34. The method of forming a semiconductor structure as claimed in claim 32, wherein incorporating the second interlayer dielectric layer includes implanting a plurality of particles into the second interlayer dielectric layer, thereby causing the second interlayer dielectric layer to expand toward the sidewall of the conductive component.

35. The method of forming a semiconductor structure as claimed in claim 34, wherein the particles comprise germanium, arsenic, or a combination thereof.

36. The method of forming a semiconductor structure as claimed in claim 32, further comprising forming an upper etch stop layer above the second interlayer dielectric layer, such that a portion of the upper etch stop layer extends into the second opening.

37. The method of forming a semiconductor structure as claimed in claim 32, further comprising forming an upper etch stop layer over the merged second interlayer dielectric layer.

38. The method of forming a semiconductor structure as claimed in claim 32, wherein the sacrificial layer comprises silicon in the form of amorphous silicon, and the second interlayer dielectric layer comprises silicon oxide.

Images