Display device

Abstract

A display device includes a substrate; a pixel circuit; a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a signal line; a first voltage supply line overlapping with the signal line, configured to supply a first voltage to the pixel circuit, and including a first lower conductive layer and a first upper conductive layer; a second voltage supply line overlapping with the signal line, configured to supply a second voltage to the second electrode, and including a second lower conductive layer in the same layer as the first lower conductive layer and a second upper conductive layer in the same layer as the first upper conductive layer on the second lower conductive layer; an encapsulating layer over the second electrode and the first voltage supply line and the second voltage supply line; and a sensing signal line over the encapsulating layer, the first lower conductive layer and the second upper conductive layer overlapping with each other.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the present application relate to a display apparatus. More particularly, exemplary embodiments of the present application relate to a display apparatus including a sensing layer. BACKGROUND

[0002] A display apparatus is an output apparatus for presenting information in a visual form, for example. Various display apparatuses have been developed for multimedia apparatuses such as televisions, mobile phones, tablet computers, navigation systems, and game consoles. Keyboards, mice, and the like are used as input apparatuses for display apparatuses. In recent years, display apparatuses can include a sensing unit as an input tool. The sensing unit can include, for example, a touch screen. SUMMARY

[0003] A display apparatus according to an exemplary embodiment of the present application can include a substrate; a pixel circuit disposed on the substrate; a light emitting element including a first electrode electrically connected to the pixel circuit, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer; a plurality of signal lines disposed on the substrate; a first voltage supply line overlapping the signal lines, configured to supply a first voltage to the pixel circuit, and including a first lower conductive layer and a first upper conductive layer disposed on the first lower conductive layer; a second voltage supply line overlapping the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer disposed in the same layer as the first lower conductive layer and a second upper conductive layer disposed in the same layer as the first upper conductive layer on the second lower conductive layer; an encapsulation layer disposed on the second electrode, the first voltage supply line, and the second voltage supply line; and a plurality of sensing signal lines disposed on the encapsulation layer, wherein the first lower conductive layer and the second upper conductive layer overlap each other.

[0004] At least one of the first lower conductive layer and the second upper conductive layer can be located in an area in which the signal lines and the sensing signal lines overlap each other.

[0005] At least a portion of the sensing signal lines can not overlap the second electrode.

[0006] An end portion of the first lower conductive layer can extend beyond an end portion of the second electrode in a direction parallel to a surface of the substrate.

[0007] An end portion of the second electrode can extend beyond an end portion of the first lower conductive layer in a direction parallel to a surface of the substrate.

[0008] The pixel circuit can include a transistor, and at least one of the signal lines can be disposed in the same layer as a gate electrode of the transistor.

[0009] The pixel circuit can further include a capacitor, and at least one of the signal lines can be disposed in the same layer as an electrode of the capacitor.

[0010] The display apparatus can further include a data line configured to supply a data signal to the pixel circuit, wherein the first lower conductive layer and the second lower conductive layer can be arranged in the same layer as the data line.

[0011] The display apparatus can further include a first voltage line connecting the first voltage supply line to the pixel circuit, wherein the first upper conductive layer and the second upper conductive layer can be arranged in the same layer as the first voltage line.

[0012] The display apparatus can further include a plurality of dams arranged between the second voltage supply line and the encapsulation layer.

[0013] The encapsulation layer can include at least one inorganic encapsulation layer and at least one organic encapsulation layer, and an end portion of the at least one organic encapsulation layer can be adjacent to a side of at least one of the dams.

[0014] The display apparatus can further include an organic insulating layer arranged between the first lower conductive layer and the first upper conductive layer and between the second lower conductive layer and the second upper conductive layer.

[0015] A plurality of vias can be provided in the second upper conductive layer.

[0016] The via can overlap the first lower conductive layer.

[0017] The via can overlap the second electrode.

[0018] A display apparatus according to an exemplary embodiment of the present application can include a substrate; a pixel circuit arranged on the substrate; a light emitting element including a first electrode electrically connected to the pixel circuit, a light emitting layer arranged on the first electrode, and a second electrode arranged on the light emitting layer; a plurality of signal lines arranged on the substrate; a first voltage supply line overlapping the signal lines, configured to supply a first voltage to the pixel circuit, and including a first lower conductive layer and a first upper conductive layer arranged on the first lower conductive layer; a second voltage supply line overlapping the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer arranged in the same layer as the first lower conductive layer and a second upper conductive layer arranged in the same layer as the first upper conductive layer on the second lower conductive layer; an encapsulation layer arranged on the second electrode, the first voltage supply line, and the second voltage supply line; and a plurality of sensing signal lines arranged on the encapsulation layer, wherein the first upper conductive layer and the second lower conductive layer overlap each other.

[0019] At least one of the first upper conductive layer and the second lower conductive layer can be located in a region in which the signal lines and the sensing signal lines overlap each other.

[0020] At least a portion of the sensing signal lines can not overlap the second electrode.

[0021] The end of the first upper conductive layer may extend beyond the end of the second electrode in a direction parallel to the surface of the substrate.

[0022] Multiple vias overlapping the second lower conductive layer can be provided in the first upper conductive layer.

[0023] A display device according to an exemplary embodiment of the present invention may include: a substrate; a pixel circuit disposed on the substrate; a light-emitting element including a first electrode and a second electrode, wherein the first electrode is electrically connected to the pixel circuit; a plurality of signal lines disposed on the substrate; a first voltage supply line overlapping the signal lines, configured to supply a first voltage to the pixel circuit, and including a first conductive layer; a second voltage supply line overlapping the signal lines, configured to supply a second voltage to a second electrode, and including a second conductive layer; an encapsulation layer disposed on the second electrode, the first voltage supply line and the second voltage supply line; and a plurality of sensing signal lines disposed on the encapsulation layer, wherein the first conductive layer and the second conductive layer overlap the signal lines. Attached Figure Description

[0024] The above and other features of the present invention will be more clearly understood by referring to the accompanying drawings and detailed description of exemplary embodiments of the invention.

[0025] Figure 1 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

[0026] Figure 2 It shows Figure 1 The equivalent circuit diagram of the pixels.

[0027] Figure 3 It shows Figure 1 A block diagram of the scan driver.

[0028] Figure 4 This is a cross-sectional view showing a display device according to an exemplary embodiment of the present invention.

[0029] Figure 5 It shows Figure 4 A plan view of the overlapping area OA.

[0030] Figure 6 This is a cross-sectional view illustrating a display device according to another exemplary embodiment of the present invention.

[0031] Figure 7 It shows Figure 6 A plan view of the overlapping area OA.

[0032] Figure 8 This is a cross-sectional view showing a display device according to yet another exemplary embodiment of the present invention.

[0033] Figure 9is a plan view showing an overlapping area OA of Figure 8 DETAILED DESCRIPTION

[0034] Hereinafter, a display apparatus according to exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a plan view showing a display apparatus according to exemplary embodiments of the present application.

[0036] Referring to Figure 1 , a display apparatus according to exemplary embodiments of the present application can include a display panel DP and a flexible printed circuit board FPCB.

[0037] The display panel DP can include a display area DA and a peripheral area PA. The peripheral area PA can be disposed outside the display area DA. In exemplary embodiments of the present application, the peripheral area PA can surround the display area DA.

[0038] A plurality of pixels PX can be disposed in the display area DA. Each of the pixels PX can be connected to a scan line SCL extending in a first direction DR1 and a data line DL and a first voltage line VL1 extending in a third direction DR3 intersecting the first direction DR1.

[0039] The first scan driver SD1, the second scan driver SD2, the pads, the signal lines SL, the connection lines CL, the first voltage supply line VSL1, and the second voltage supply line VSL2 can be disposed in the peripheral area PA.

[0040] In exemplary embodiments of the present application, the first scan driver SD1 can be disposed in the first direction DR1 from the display area DA, and the second scan driver SD2 can be disposed in a second direction DR2 opposite the first direction DR1 from the display area DA, but the present application is not limited thereto. In another exemplary embodiment of the present application, the first scan driver SD1 and the second scan driver SD2 can be disposed in the first direction DR1 or the second direction DR2 from the display area DA. The first scan driver SD1 and the second scan driver SD2 can generate scan signals based on signals transmitted from the signal lines SL, and the scan signals can be sequentially transmitted to the pixels PX through the scan lines SCL.

[0041] The pads can be disposed in the third direction DR3 from the display area DA and aligned along the first direction DR1. The pads can include a signal pad PS, a data pad PD, a first voltage pad PV1, and a second voltage pad PV2. The data pad PD can be disposed, for example, between two first voltage pads PV1.

[0042] ​The signal line SL can connect the signal pad PS to the first scan driver SD1 and the second scan driver SD2. The signal line SL can supply a signal transmitted from the signal pad PS to the first scan driver SD1 and the second scan driver SD2.

[0043] The connection line CL can connect the data pad PD to the data line DL. For example, the connection line CL can extend from the data pad PD in the peripheral area PA to the data line DL in the display area DA. The connection line CL can transmit a data signal transmitted from the data pad PD to the data line DL to supply the data signal to the pixel PX.

[0044] The first voltage supply line VSL1 can connect the first voltage pad PV1 to the first voltage line VL1. The first voltage supply line VSL1 can supply a first voltage transmitted from the first voltage pad PV1 to the first voltage line VL1.

[0045] The second voltage supply line VSL2 can connect the second voltage pad PV2 to the pixel PX. The second voltage supply line VSL2 can supply a second voltage transmitted from the second voltage pad PV2 to the pixel PX.

[0046] The flexible printed circuit board FPCB can electrically connect the control unit CTL to the pads. For example, the flexible printed circuit board FPCB can include pads corresponding to the pads of the display panel DP. A signal or a voltage transmitted from the control unit CTL can be transmitted to the pads through the flexible printed circuit board FPCB.

[0047] In an exemplary embodiment of the present application, the data driver DD can be disposed on the flexible printed circuit board FPCB, but the present application is not limited thereto. In another exemplary embodiment of the present application, the data driver DD can be disposed in the peripheral area PA of the display panel DP. The data driver DD can generate a data signal to provide the data signal to the pixel PX.

[0048] Figure 2 is a circuit diagram illustrating Figure 1 a pixel PX.

[0049] Referring to Figure 2 , the pixel PX can include a pixel circuit PC and a light emitting element EL connected to the pixel circuit PC. The pixel circuit PC can generate a driving current DC by receiving a scan signal SS, a data signal DS, and a first voltage VDD to provide the driving current DC to the light emitting element EL. The light emitting element EL can receive a second voltage VSS to emit light based on the driving current DC provided from the pixel circuit PC. The pixel circuit PC can include at least one transistor and at least one capacitor to generate the driving current DC.

[0050] In an exemplary embodiment of the present invention, the pixel circuit PC can include a first transistor TR1, a second transistor TR2, and a capacitor CAP.

[0051] A gate electrode of the first transistor TR1 can be connected to the first node N1. A first voltage VDD can be applied to a source electrode of the first transistor TR1, and a drain electrode of the first transistor TR1 can be connected to the light emitting element EL. The first transistor TR1 can generate a driving current DC based on a voltage between its gate electrode and source electrode to transmit the driving current DC to the light emitting element EL.

[0052] A scan signal SS can be applied to a gate electrode of the second transistor TR2. A data signal DS can be applied to a source electrode of the second transistor TR2, and a drain electrode of the second transistor TR2 can be connected to the first node N1. The second transistor TR2 can transmit the data signal DS to the first node N1 based on the scan signal SS.

[0053] The first voltage VDD can be applied to a first electrode of the capacitor CAP, and a second electrode of the capacitor CAP can be connected to the first node N1. The capacitor CAP can maintain a voltage between the gate electrode and the source electrode of the first transistor TR1 even when the second transistor TR2 is turned off, so that the light emitting element EL can emit light.

[0054] A first electrode of the light emitting element EL can be connected to the pixel circuit PC, and a second voltage VSS can be applied to a second electrode of the light emitting element EL. In an exemplary embodiment of the present invention, the second voltage VSS can be less than the first voltage VDD. The light emitting element EL can emit light based on the driving current DC transmitted from the pixel circuit PC.

[0055] Figure 3 is a block diagram illustrating Figure 1 For example, Figure 3 The first scan driver SD1 can be illustrated. A configuration of the second scan driver SD2 can be substantially the same as or similar to that of the first scan driver SD1.

[0056] Referring to Figure 3The first scan driver SD1 can include a plurality of stages ST1, ST2, …, and STn. A scan control signal can be provided to the stages ST1, ST2, …, and STn through a signal line SL. The signal line SL can include a first clock signal line CL1, a second clock signal line CL2, a third voltage line VL, a fourth voltage line VH, and an enable signal line EF. The first clock signal line CL1, the second clock signal line CL2, the third voltage line VL, the fourth voltage line VH, and the enable signal line EF can transmit a first clock signal CLK1, a second clock signal CLK2, a third voltage VGL, a fourth voltage VGH, and an enable signal FLM, respectively.

[0057] Each of the stages ST1, ST2, …, and STn can include a first clock terminal CK1, a second clock terminal CK2, a third voltage input terminal VPL, a fourth voltage input terminal VPH, an input terminal IN, and an output terminal OUT.

[0058] The first clock terminal CK1 can receive the first clock signal CLK1, and the second clock terminal CK2 can receive the second clock signal CLK2. A phase of the first clock signal CLK1 and a phase of the second clock signal CLK2 can be different from each other. For example, the phase of the second clock signal CLK2 can be opposite to the phase of the first clock signal CLK1, or the phase of the second clock signal CLK2 can be delayed from the phase of the first clock signal CLK1.

[0059] The third voltage input terminal VPL can receive the third voltage VGL, and the fourth voltage input terminal VPH can receive the fourth voltage VGH. A voltage level of the third voltage VGL can be lower than a voltage level of the fourth voltage VGH.

[0060] The input terminal IN of the first stage ST1 of the stages ST1, ST2, …, and STn can receive the enable signal FLM, and the remaining stages ST2, …, and STn of the stages ST1, ST2, …, and STn can receive an output signal of a previous stage. For example, the second stage ST2 can receive an output signal of the first stage ST1. The output terminal OUT can provide a scan signal generated from the stage to a scan line and an input terminal IN of a next stage. For example, the output terminal OUT of the first stage ST1 can provide a scan signal to a first scan line SL1, the output terminal OUT of the second stage ST2 can provide a scan signal to a second scan line SL2, and so on.

[0061] Figure 4 is a cross-sectional view illustrating a display apparatus according to an exemplary embodiment of the present application. Figure 4 illustrates an example of a display apparatus taken along Figure 1 line I-I’ of

[0062] Referring toFigure 4 The pixel circuit PC including the transistor TR and the capacitor CAP, the data line 143, the first voltage line 153, and the light-emitting element EL can be arranged on the substrate 100 in the display region DA. The transistor TR, the data line 143, and the first voltage line 153 can be, respectively, Figure 2 the first transistor TR1 of the Figure 1 the data line DL of the Figure 1 the first voltage line VL1 of the. The first signal line 121, the second signal line 131, the first voltage supply line VSL1, and the second voltage supply line VSL2 can be arranged on the substrate 100 in the peripheral region PA.

[0063] The substrate 100 can be an insulating substrate including glass, quartz, plastic, or the like. In an exemplary embodiment of the present application, the substrate 100 can include a first flexible layer, a first barrier layer arranged on the first flexible layer, a second flexible layer arranged on the first barrier layer, and a second barrier layer arranged on the second flexible layer. The first flexible layer and the second flexible layer can include an organic insulating material such as polyimide (PI), and the first barrier layer and the second barrier layer can include an inorganic insulating material such as silicon oxide, silicon nitride, and amorphous silicon.

[0064] A buffer layer BUF can be arranged on the substrate 100. The buffer layer BUF can prevent impurities such as oxygen and moisture from diffusing through the substrate 100 to an upper portion of the substrate 100. In addition, the buffer layer BUF can provide a flat top surface on the upper portion of the substrate 100. The buffer layer BUF can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0065] An active layer 110 can be arranged on the buffer layer BUF. The active layer 110 can be formed of amorphous silicon, polysilicon, an oxide semiconductor, or the like. The active layer 110 can include a source region, a drain region, and a channel region arranged between the source region and the drain region. The source region and the drain region can be doped with a P-type or N-type impurity.

[0066] A first insulating layer 101 can be arranged on the active layer 110. The first insulating layer 101 can be arranged on the buffer layer BUF to cover the active layer 110. The first insulating layer 101 can insulate a gate electrode 122 arranged on the active layer 110 from the active layer 110. The first insulating layer 101 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0067] The gate electrode 122 can be arranged on the first insulating layer 101. The gate electrode 122 can overlap the channel region of the active layer 110. The gate electrode 122 can include a conductive material such as molybdenum (Mo) and copper (Cu). The active layer 110 including the source region, the drain region, and the channel region and the gate electrode 122 can form a transistor TR.

[0068] A second insulating layer 102 can be disposed on the gate electrode 122. The second insulating layer 102 can be disposed on the first insulating layer 101 to cover the gate electrode 122. The second insulating layer 102 can insulate the capacitor electrode 132 disposed on the gate electrode 122 from the gate electrode 122. In an exemplary embodiment of the present application, the second insulating layer 102 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0069] The capacitor electrode 132 can be disposed on the second insulating layer 102. The capacitor electrode 132 can overlap the gate electrode 122. The capacitor electrode 132 can include a conductive material such as molybdenum (Mo) and copper (Cu). The gate electrode 122 and the capacitor electrode 132 can form a capacitor CAP. For example, the gate electrode 122 can be one of the electrodes of the capacitor CAP.

[0070] A third insulating layer 103 can be disposed on the capacitor electrode 132. The third insulating layer 103 can be disposed on the second insulating layer 102 to cover the capacitor electrode 132. The third insulating layer 103 can insulate the data line 143 disposed on the capacitor electrode 132 from the capacitor electrode 132. In an exemplary embodiment of the present application, the third insulating layer 103 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0071] The data line 143 can be disposed on the third insulating layer 103. The data line 143 can be located in the display area DA. The data line 143 can include a conductive material such as aluminum (Al), titanium (Ti), and copper (Cu).

[0072] A fourth insulating layer 104 can be disposed on the data line 143. The fourth insulating layer 104 can be disposed on the third insulating layer 103 to cover the data line 143. The fourth insulating layer 104 can include an organic insulating material such as polyimide (PI).

[0073] A first voltage line 153 can be disposed on the fourth insulating layer 104. The first voltage line 153 can be located in the display area DA. The first voltage line 153 can include a conductive material such as aluminum (Al), titanium (Ti), and copper (Cu). As Figure 4 indicated in FIG. 1B, the first voltage line 153 can partially overlap the data line 143.

[0074] A fifth insulating layer 105 can be disposed on the first voltage line 153. The fifth insulating layer 105 can be disposed on the fourth insulating layer 104 to cover the first voltage line 153. The fifth insulating layer 105 can include an organic insulating material such as polyimide (PI).

[0075] The first electrode 160 can be disposed on the fifth insulating layer 105. The first electrode 160 can be electrically connected to the transistor TR. The first electrode 160 can include a conductive material such as a metal, an alloy, and a transparent conductive oxide. For example, the first electrode 160 can include silver (Ag), indium tin oxide (ITO), or the like.

[0076] The sixth insulating layer 106 can be disposed on the first electrode 160. The sixth insulating layer 106 can be disposed on the fifth insulating layer 105 to cover the first electrode 160. The sixth insulating layer 106 can have a pixel opening that exposes at least a portion of the first electrode 160. In an exemplary embodiment of the present disclosure, the pixel opening can expose a central portion of the first electrode 160, and the sixth insulating layer 106 can cover a peripheral portion of the first electrode 160. In other words, the sixth insulating layer 106 can cover an edge of the first electrode 160. The sixth insulating layer 106 can include an organic insulating material such as polyimide (PI).

[0077] The light emitting layer 170 can be disposed on the first electrode 160. The light emitting layer 170 can be disposed on the first electrode 160 exposed through the pixel opening. The light emitting layer 170 can include at least one of an organic light emitting material and a quantum dot.

[0078] In an exemplary embodiment of the present disclosure, the organic light emitting material can include a low molecular weight organic compound or a high molecular weight organic compound. For example, the low molecular weight organic compound can include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, or the like, and the high molecular weight organic compound can include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylene vinylene, polyfluorene, or the like.

[0079] In an exemplary embodiment of the present disclosure, the quantum dot can include a core including a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and a combination thereof. In an exemplary embodiment of the present disclosure, the quantum dot can have a core-shell structure including the core and a shell surrounding the core. The shell can serve as a protective layer for preventing chemical denaturation of the core to maintain a semiconductor property, and can serve as a charging layer for imparting electrophoretic properties to the quantum dot.

[0080] The second electrode 180 can be disposed on the light-emitting layer 170. In an exemplary embodiment of the present invention, the second electrode 180 can also be disposed on the sixth insulating layer 106. For example, the second electrode 180 can directly contact the sixth insulating layer 106. The second electrode 180 can include conductive materials such as metals, alloys, and transparent conductive oxides. For example, the second electrode 180 can include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode 160, the light-emitting layer 170, and the second electrode 180 can form a light-emitting element EL.

[0081] The first signal line 121 and the second signal line 131 can be arranged outside the pixel circuit PC on the substrate 100.

[0082] The first signal line 121 can be disposed on the substrate 100 in the peripheral region PA. In an exemplary embodiment of the present invention, the first signal line 121 may include a material substantially the same as that of the gate electrode 122 and may be disposed on the same layer as the gate electrode 122. In this case, the first signal line 121 may be disposed on the first insulating layer 101.

[0083] The second signal line 131 may be arranged on the first signal line 121 within the peripheral region PA. In an exemplary embodiment of the invention, the second signal line 131 may not overlap with the first signal line 121. For example, the second signal line 131 and the first signal line 121 may be arranged alternately along a third direction DR3. In an exemplary embodiment of the invention, the second signal line 131 may comprise a material substantially the same as that of the capacitor electrode 132 and may be arranged in the same layer as the capacitor electrode 132. In this case, the second signal line 131 may be arranged on the second insulating layer 102.

[0084] The first signal line 121 and the second signal line 131 may include Figure 1 The signal line SL and the connecting line CL. In other words, the first signal line 121 and the second signal line 131 may include the connecting line CL and the first clock signal line (SL). Figure 3 CL1), second clock signal line ( Figure 3 CL2), the third voltage line ( Figure 3 VL), fourth voltage line ( Figure 3 VH) and start signal line ( Figure 3 Therefore, the first signal line 121 and the second signal line 131 can transmit data signals (EF). Figure 2 DS), first clock signal ( Figure 3 CLK1), second clock signal ( Figure 3 CLK2), third voltage ( Figure 3 VGL), fourth voltage (Figure 3 VGH) and startup voltage ( Figure 3 (FLM).

[0085] In an exemplary embodiment of the present invention, the first signal line 121 may include a first clock signal line CL1, a second clock signal line CL2, a third voltage line VL, a fourth voltage line VH, a start signal line EF, and a portion of the connection line CL, and the second signal line 131 may include another portion of the first clock signal line CL1, the second clock signal line CL2, the third voltage line VL, the fourth voltage line VH, the start signal line EF, and the connection line CL.

[0086] The first voltage supply line VSL1 and the second voltage supply line VSL2 can be arranged on the first signal line 121 and the second signal line 131. The first voltage supply line VSL1 can deliver a first voltage ( Figure 2 The second voltage supply line VSL2 can be arranged outside the first voltage supply line VSL1 to supply the second voltage (VDD) to the pixel circuit PC. Figure 2 The voltage supply line VSL2 is supplied to the second electrode 180. For example, the second voltage supply line VSL2 may be located on a third direction DR3 from the first voltage supply line VSL1. In other words, the second voltage supply line VSL2 is spaced apart from the first voltage supply line VSL1 along the third direction DR3.

[0087] The first voltage supply line VSL1 may include a first lower conductive layer 141 and a first upper conductive layer 151 disposed on the first lower conductive layer 141. The first lower conductive layer 141 and the first upper conductive layer 151 may be electrically connected to each other. For example, the first lower conductive layer 141 and the first upper conductive layer 151 may be electrically connected to each other through a path in the fourth insulating layer 104.

[0088] The second voltage supply line VSL2 may include a second lower conductive layer 142 and a second upper conductive layer 152 disposed on the second lower conductive layer 142. The second lower conductive layer 142 may be disposed substantially on the same layer as the first lower conductive layer 141, and the second upper conductive layer 152 may be disposed substantially on the same layer as the first upper conductive layer 151. The second lower conductive layer 142 and the second upper conductive layer 152 may be electrically connected to each other. For example, the second lower conductive layer 142 and the second upper conductive layer 152 may be electrically connected to each other through a path in the fourth insulating layer 104.

[0089] In an exemplary embodiment of the present invention, the first lower conductive layer 141 and the second lower conductive layer 142 may comprise substantially the same material as the data line 143 and may be disposed on substantially the same layer as the data line 143. In this case, the first lower conductive layer 141 and the second lower conductive layer 142 may be disposed on the third insulating layer 103.

[0090] In an exemplary embodiment of the present disclosure, the first upper conductive layer 151 and the second upper conductive layer 152 can include substantially the same material as the first voltage line 153, and can be arranged in substantially the same layer as the first voltage line 153. In this case, the first upper conductive layer 151 and the second upper conductive layer 152 can be arranged on the fourth insulating layer 104.

[0091] The first lower conductive layer 141 and the first upper conductive layer 151 can be connected to each other through a contact hole formed in the fourth insulating layer 104. The second lower conductive layer 142 and the second upper conductive layer 152 can be connected to each other through a contact hole formed in the fourth insulating layer 104.

[0092] The second electrode 180 can extend to the outside of the display area DA. In other words, the second electrode 180 can extend from the display area DA to the peripheral area PA. For example, the second electrode 180 can extend in the third direction DR3. In this case, an end portion 180E of the second electrode 180 can be located in the peripheral area PA. The end portion 180E of the second electrode 180 can overlap with portions of the first voltage supply line VSL1 and the second voltage supply line VSL2.

[0093] In an exemplary embodiment of the present disclosure, the end portion 141E of the first lower conductive layer 141 can be located outside the end portion 180E of the second electrode 180. In other words, the end portion 180E of the second electrode 180 can be located inside the end portion 141E of the first lower conductive layer 141. For example, the end portion 141E of the first lower conductive layer 141 can be located in the third direction DR3 from the end portion 180E of the second electrode 180. In this case, the end portion 141E of the first lower conductive layer 141 and the end portion 180E of the second electrode 180 do not overlap with each other.

[0094] The encapsulation layer 190 can be arranged on the second electrode 180, the first voltage supply line VSL1, and the second voltage supply line VSL2. The encapsulation layer 190 can cover the light emitting element EL to protect the light emitting element EL from impurities such as oxygen and moisture.

[0095] The encapsulation layer 190 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer can include silicon nitride, silicon oxynitride, or the like, and the organic encapsulation layer can include an epoxy-based resin, an acrylic-based resin, a polyimide-based resin, or the like.

[0096] In an exemplary embodiment of the present application, the encapsulation layer 190 can include a first inorganic encapsulation layer 191, an organic encapsulation layer 192, and a second inorganic encapsulation layer 193. The first inorganic encapsulation layer 191 can be disposed on the second electrode 180, the first voltage supply line VSL1, and the second voltage supply line VSL2. The first inorganic encapsulation layer 191 can be formed along a lower profile of the encapsulation layer 190 such that the first inorganic encapsulation layer 191 can have a non-flat top surface. The first inorganic encapsulation layer 191 can extend to an outer side of the second voltage supply line VSL2.

[0097] The organic encapsulation layer 192 can be disposed on the first inorganic encapsulation layer 191. The organic encapsulation layer 192 can have a flat top surface. The organic encapsulation layer 192 can be located at least in the display area DA. For example, the organic encapsulation layer 192 can also be located in the peripheral area PA.

[0098] The second inorganic encapsulation layer 193 can be disposed on the organic encapsulation layer 192. The second inorganic encapsulation layer 193 can be formed along an upper profile of the encapsulation layer 190 such that the second inorganic encapsulation layer 193 can have a flat top surface. The second inorganic encapsulation layer 193 can extend to an outer side of the second voltage supply line VSL2. Accordingly, the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can contact each other at an outer side of the second voltage supply line VSL2.

[0099] A plurality of dams can be disposed between the second voltage supply line VSL2 and the encapsulation layer 190. For example, the dams can be disposed between the second upper conductive layer 152 and the first inorganic encapsulation layer 191. In an exemplary embodiment of the present application, the dams can include a first dam DM1, a second dam DM2, and a third dam DM3. The second dam DM2 can be disposed at an outer side of the first dam DM1, and the third dam DM3 can be disposed at an outer side of the second dam DM2.

[0100] Each of the first dam DM1, the second dam DM2, and the third dam DM3 can include substantially the same material as the fifth insulating layer 105 and substantially the same material as the sixth insulating layer 106, respectively. For example, the first dam DM1, the second dam DM2, and the third dam DM3 can be formed substantially simultaneously with the fifth insulating layer 105 and the sixth insulating layer 106.

[0101] The first dam DM1, the second dam DM2, and the third dam DM3 can prevent the organic encapsulation layer 192 from being formed at an outer side of the second voltage supply line VSL2 during a process of forming the organic encapsulation layer 192. Accordingly, an end portion 192E of the organic encapsulation layer 192 can be located at an inner side of at least one of the dams DM1, DM2, and DM3. In an exemplary embodiment of the present application, as Figure 4As illustrated in FIG. 1, the end portion 192E of the organic encapsulation layer 192 can be located inside the first dam DM1, but the present application is not limited thereto. In another exemplary embodiment of the present application, the end portion 192E of the organic encapsulation layer 192 can be located inside the second dam DM2 or the third dam DM3. In addition, the first dam DM1, the second dam DM2, and the third dam DM3 can provide a concave-convex top surface on the lower portion of the encapsulation layer 190, such that the contact area between the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be increased on the first dam DM1, the second dam DM2, and the third dam DM3. Accordingly, the adhesion between the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 can be increased.

[0102] The sensing layer 200 can be disposed on the encapsulation layer 190. The sensing layer 200 can obtain coordinate information of an external input. In this case, the external input can be contact or proximity of a user, an external object, or the like with respect to the display apparatus. In an exemplary embodiment of the present application, the sensing layer 200 can sense the external input in a capacitive scheme, but the operation scheme of the sensing layer 200 is not limited thereto. In another exemplary embodiment of the present application, the sensing layer 200 can sense the external input through an electromagnetic induction scheme, a pressure sensing scheme, or the like.

[0103] The sensing layer 200 can include a sensing signal line 201 and a sensing electrode 202. The sensing signal line 201 can be disposed in the peripheral area PA, and the sensing electrode 202 can be disposed in the display area DA. The sensing signal line 201 can transmit a driving signal to the sensing electrode 202, or receive a sensing signal from the sensing electrode 202.

[0104] In an exemplary embodiment of the present application, the sensing signal line 201 and the sensing electrode 202 can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowire, graphene, or the like. In another exemplary embodiment of the present application, the sensing signal line 201 and the sensing electrode 202 can include a metal such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), and aluminum (Al), or an alloy thereof.

[0105] In an exemplary embodiment of the present application, at least a portion of the sensing signal line 201 can be located outside the end portion 180E of the second electrode 180. When at least a portion of the sensing signal line 201 is located outside the end portion 180E of the second electrode 180, the area in which the sensing signal line 201 is disposed can be increased, such that the width of the sensing signal line 201 can be increased, or the interval between the sensing signal lines 201 can be increased. When the width of the sensing signal line 201 is increased, the resistance of the sensing signal line 201 can be reduced, and when the interval between the sensing signal lines 201 is increased, the sensing signal lines 201 can be prevented from being short-circuited.

[0106] The overlapping region OA in which the first signal line 121 and the second signal line 131 and the sensing signal line 201 overlap each other can be located in the peripheral region PA. Noise can be propagated upward from the first signal line 121 and the second signal line 131 within the overlapping region OA, and the noise can affect the sensing signal line 201. For example, when there is no structure for shielding the noise propagation between the first signal line 121 and the second signal line 131 and the sensing signal line 201, there is a risk of reducing the sensing sensitivity of the sensing layer 200.

[0107] To prevent the noise from being propagated from the first signal line 121 and the second signal line 131 to the sensing signal line 201, the first lower conductive layer 141 of the first voltage supply line VSL1 and the second upper conductive layer 152 of the second voltage supply line VSL2 can be extended to overlap each other. For example, the first lower conductive layer 141 can be extended in the third direction DR3, and the second upper conductive layer 152 can be extended in the fourth direction DR4 opposite to the third direction DR3. In this case, the noise generated by the first signal line 121 and the second signal line 131 can be blocked.

[0108] Figure 5 is a plan view illustrating Figure 4 an overlapping region OA of Figure 5 the first voltage supply line VSL1 and the second voltage supply line VSL2.

[0109] Referring to Figure 4 and Figure 5 at least one of the first lower conductive layer 141 and the second upper conductive layer 152 can be located in the overlapping region OA in which the first signal line 121 and the second signal line 131 overlap each other with the sensing signal line 201. For example, the first lower conductive layer 141 and the second upper conductive layer 152 can be located in a region in which the first lower conductive layer 141 and the second upper conductive layer 152 overlap each other. In this case, the first lower conductive layer 141 can be located in the fourth direction DR4 from the region in which the first lower conductive layer 141 and the second upper conductive layer 152 overlap each other, and the second upper conductive layer 152 can be located in the third direction DR3 from the region in which the first lower conductive layer 141 and the second upper conductive layer 152 overlap each other. At least one of the first lower conductive layer 141 and the second upper conductive layer 152 is located in the overlapping region OA so that the first lower conductive layer 141 and the second upper conductive layer 152 can form a shield between the first signal line 121 and the second signal line 131 and the sensing signal line 201.

[0110] In the display device of the related art, the second electrode 180 can be used to shield the propagation of noise between the first and second signal lines 121 and 131 and the sensing signal line 201. In this case, when viewed in a plan view, the area in which the sensing signal line 201 is formed can be limited to an area overlapping the second electrode 180. However, in the display device according to the embodiment of the present application shown in Figure 4 and Figure 5 In the display device according to the embodiment of the present application shown in

[0111] As described above, the fourth insulating layer 104 disposed between the first lower conductive layer 141 and the first upper conductive layer 151 of the first voltage supply line VSL1 and between the second lower conductive layer 142 and the second upper conductive layer 152 of the second voltage supply line VSL2 can be an organic insulating layer including an organic insulating material. Since the organic insulating material included in the organic insulating layer can be chemically decomposed over a long period of time, gas can be generated, and when the gas does not escape but moves to the display area DA, the gas can affect the light emitting element EL, thereby deteriorating the light emitting element EL.

[0112] To smoothly escape the gas generated in the fourth insulating layer 104, a plurality of through holes TH can be provided in the first upper conductive layer 151 of the first voltage supply line VSL1 and the second upper conductive layer 152 of the second voltage supply line VSL2. The gas generated in the fourth insulating layer 104 can be smoothly escaped upward through the through holes TH.

[0113] In the exemplary embodiment of the present application, the through holes TH can overlap the first lower conductive layer 141 of the first voltage supply line VSL1 and the second lower conductive layer 142 of the second voltage supply line VSL2. In other words, the through holes TH can be formed in an area overlapping the first lower conductive layer 141 or the second lower conductive layer 142. For example, the through holes TH can be formed in an area of the first upper conductive layer 151 overlapping the first lower conductive layer 141 and an area of the second upper conductive layer 152 overlapping the first lower conductive layer 141 or the second lower conductive layer 142. In addition, the through holes TH can not be formed in an area of the second upper conductive layer 152 not overlapping the first lower conductive layer 141 or the second lower conductive layer 142. The through holes TH are not formed in the area of the second upper conductive layer 152 not overlapping the first lower conductive layer 141 or the second lower conductive layer 142, so that the propagation of noise from the first and second signal lines 121 and 131 to the sensing signal line 201 through the through holes TH can be prevented.

[0114] Figure 6 is a cross-sectional view showing a display device according to another exemplary embodiment of the present application. Figure 6 shows another example of the display device taken along Figure 1 line I-I' of

[0115] In the display device of Figure 6 and Figure 7 , the description of the components substantially the same as or similar to the components of the display device described with reference to Figure 4 and Figure 5 may be omitted.

[0116] With reference to Figure 6 , the end portion 1180E of the second electrode 1180 can be located outside the end portion 141E of the first lower conductive layer 141. For example, the end portion 1180E of the second electrode 1180 can be located in the third direction DR3 from the end portion 141E of the first lower conductive layer 141. Since the end portion 1180E of the second electrode 1180 is located outside the end portion 141E of the first lower conductive layer 141, the second electrode 1180 can also form a shield together with the first lower conductive layer 141 of the first voltage supply line VSL1 and the second upper conductive layer 152 of the second voltage supply line VSL2 between the first signal line 121 and the second signal line 131 and the sensing signal line 201.

[0117] Figure 7 is a plan view showing an overlap region OA of Figure 6 . Figure 7 shows the first upper conductive layer 151 of the first voltage supply line VSL1, the second upper conductive layer 152 of the second voltage supply line VSL2, and the second electrode 1180.

[0118] With reference to Figure 6 and Figure 7 , the through hole TH can overlap the second electrode 1180. In other words, the through hole TH can be formed in a region overlapping the second electrode 1180. The through hole TH is formed in a region of the first upper conductive layer 151 and a region of the second upper conductive layer 152 overlapping the second electrode 1180. Thus, the second electrode 1180 can prevent noise from propagating from the first signal line 121 and the second signal line 131 to the sensing signal line 201 through the through hole TH.

[0119] Figure 8 is a cross-sectional view showing a display device according to another exemplary embodiment of the present application. Figure 8 shows another example of the display device taken along Figure 1 line I-I' of

[0120] In the display device of Figure 8 andFigure 9 In the display device of Figure 4 and Figure 5 the display device described in

[0121] In Figure 8 , the end portion 1151E of the first upper conductive layer 1151 can be positioned outside the end portion 180E of the second electrode 180. In other words, the end portion 180E of the second electrode 180 can be positioned inside the end portion 1151E of the first upper conductive layer 1151. For example, the end portion 1151E of the first upper conductive layer 1151 can be positioned on the third direction DR3 from the end portion 180E of the second electrode 180.

[0122] To prevent noise from propagating from the first signal line 121 and the second signal line 131 to the sensing signal line 201, the first upper conductive layer 1151 of the first voltage supply line VSL1 and the second lower conductive layer 1142 of the second voltage supply line VSL2 can be extended to overlap each other. For example, the first upper conductive layer 1151 can be extended on the third direction DR3, and the second lower conductive layer 1142 can be extended on the fourth direction DR4.

[0123] Figure 9 is a plan view that shows the overlapping region OA of Figure 8 . Figure 9 The first lower conductive layer 1141 and the first upper conductive layer 1151 of the first voltage supply line VSL1 and the second lower conductive layer 1142 and the second upper conductive layer 1152 of the second voltage supply line VSL2 are shown.

[0124] Referring to Figure 8 and Figure 9 , at least one of the first upper conductive layer 1151 and the second lower conductive layer 1142 can be positioned in the overlapping region OA in which the first signal line 121 and the second signal line 131 overlap each other with the sensing signal line 201. For example, the first upper conductive layer 1151 and the second lower conductive layer 1142 can be positioned in a region in which the first upper conductive layer 1151 and the second lower conductive layer 1142 overlap each other. For example, the first upper conductive layer 1151 can be positioned on the fourth direction DR4 from the region in which the first upper conductive layer 1151 and the second lower conductive layer 1142 overlap each other, and the second lower conductive layer 1142 can be positioned on the third direction DR3 from the region in which the first upper conductive layer 1151 and the second lower conductive layer 1142 overlap each other. At least one of the first upper conductive layer 1151 and the second lower conductive layer 1142 being positioned in the overlapping region OA allows the first upper conductive layer 1151 and the second lower conductive layer 1142 to function as a shield between the first signal line 121 and the second signal line 131 and the sensing signal line 201.

[0125] To smoothly discharge the gas generated in the fourth insulating layer 104, a plurality of through holes TH can be provided in the first upper conductive layer 1151 of the first voltage supply line VSL1 and the second upper conductive layer 1152 of the second voltage supply line VSL2. The gas generated in the fourth insulating layer 104 can be smoothly discharged upward through the through holes TH.

[0126] As shown in FIGS. 1A and 1B, the through holes TH can overlap the first lower conductive layer 1141 of the first voltage supply line VSL1 and the second lower conductive layer 1142 of the second voltage supply line VSL2. In other words, the through holes TH can be formed in regions overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. For example, the through holes TH can be formed in regions of the first upper conductive layer 1151 overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142 and regions of the second upper conductive layer 1152 overlapping the second lower conductive layer 1142. In addition, the through holes TH can not be formed in regions of the first upper conductive layer 1151 not overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. The through holes TH are not formed in regions of the first upper conductive layer 1151 not overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. Accordingly, it is possible to prevent noise from being propagated from the first signal line 121 and the second signal line 131 to the sensing signal line 201 through the through holes TH. Figure 8 Figure 9 As shown in FIGS. 1A and 1B, the through holes TH can overlap the first lower conductive layer 1141 of the first voltage supply line VSL1 and the second lower conductive layer 1142 of the second voltage supply line VSL2. In other words, the through holes TH can be formed in regions overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. For example, the through holes TH can be formed in regions of the first upper conductive layer 1151 overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142 and regions of the second upper conductive layer 1152 overlapping the second lower conductive layer 1142. In addition, the through holes TH can not be formed in regions of the first upper conductive layer 1151 not overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. The through holes TH are not formed in regions of the first upper conductive layer 1151 not overlapping the first lower conductive layer 1141 or the second lower conductive layer 1142. Accordingly, it is possible to prevent noise from being propagated from the first signal line 121 and the second signal line 131 to the sensing signal line 201 through the through holes TH.

[0127] The display apparatus according to an exemplary embodiment of the present application can be applied to a display apparatus included in a computer, a notebook, a mobile phone, a smart phone, a smart pad, a portable media player (PMP), a personal digital assistant (PDA), an MP3 player, etc.

[0128] An exemplary embodiment of the present application provides a display apparatus for improving sensitivity of a sensing layer.

[0129] For example, in the display apparatus according to an exemplary embodiment of the present application, a first voltage supply line configured to supply a first voltage and including a first lower conductive layer and a first upper conductive layer and a second voltage supply line configured to supply a second voltage and including a second lower conductive layer and a second upper conductive layer can be disposed between a plurality of signal lines and a sensing signal line. The first lower conductive layer and the second upper conductive layer can be extended to overlap each other, or the first upper conductive layer and the second lower conductive layer can be extended to overlap each other. Accordingly, the first voltage supply line and the second voltage supply line can prevent noise from being propagated from the plurality of signal lines to the plurality of sensing signal lines, and can improve sensitivity of the sensing signal line.

[0130] ​While the application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit of the application.

Claims

1. A display device comprising: a substrate; a pixel circuit arranged over the substrate; a light-emitting element including a first electrode electrically connected to the pixel circuit, a light-emitting layer arranged over the first electrode, and a second electrode arranged over the light-emitting layer; a plurality of signal lines arranged over the substrate; a first voltage supply line overlapping with the signal lines, configured to supply a first voltage to the pixel circuit, and including a first lower conductive layer and a first upper conductive layer arranged over the first lower conductive layer; a second voltage supply line overlapping with the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer arranged in the same layer as the first lower conductive layer, and a second upper conductive layer arranged in the same layer as the first upper conductive layer over the second lower conductive layer; an encapsulation layer arranged over the second electrode, the first voltage supply line, and the second voltage supply line; and a plurality of sensing signal lines arranged over the encapsulation layer, wherein the first lower conductive layer and the second upper conductive layer overlap with each other.

2. The display device according to claim 1, wherein at least one of the first lower conductive layer and the second upper conductive layer is positioned in a region where the signal lines and the sensing signal lines overlap with each other.

3. The display device according to claim 1, wherein at least a portion of the sensing signal lines does not overlap with the second electrode.

4. The display device according to claim 1, wherein an end portion of the first lower conductive layer extends beyond an end portion of the second electrode in a direction parallel to a surface of the substrate.

5. The display device according to claim 1, wherein an end portion of the second electrode extends beyond an end portion of the first lower conductive layer in a direction parallel to a surface of the substrate.

6. A display device comprising: a substrate; a pixel circuit arranged over the substrate; a light-emitting element including a first electrode electrically connected to the pixel circuit, a light-emitting layer arranged over the first electrode, and a second electrode arranged over the light-emitting layer; a plurality of signal lines arranged over the substrate; a first voltage supply line overlapping with the signal lines, configured to supply a first voltage to the pixel circuit, and including a first lower conductive layer and a first upper conductive layer arranged over the first lower conductive layer; a second voltage supply line overlapping with the signal lines, configured to supply a second voltage to the second electrode, and including a second lower conductive layer arranged in the same layer as the first lower conductive layer, and a second upper conductive layer arranged in the same layer as the first upper conductive layer over the second lower conductive layer; an encapsulation layer arranged over the second electrode, the first voltage supply line, and the second voltage supply line; and a plurality of sensing signal lines arranged over the encapsulation layer, wherein the first upper conductive layer and the second lower conductive layer overlap with each other.

7. The display device according to claim 6, wherein at least one of the first upper conductive layer and the second lower conductive layer is positioned in a region where the signal lines and the sensing signal lines overlap with each other. ​ ​ 8.The display device of claim 6, wherein at least a portion of the sensing signal line does not overlap the second electrode. 9.The display device of claim 6, wherein an end portion of the first upper conductive layer extends beyond an end portion of the second electrode in a direction parallel to a surface of the substrate.

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