Tamper Detection in Integrated Circuits

Abstract

A system with tamper detection may include at least one ring oscillator and a detection circuit coupled to the at least one ring oscillator to detect a frequency change greater than a tolerance. Each ring oscillator may include a plurality of inverters, wherein at least one intermediate node coupling an output of one of the plurality of inverters and an input of another of the plurality of inverters is a sensing node of a plurality of sensing nodes of the system. The outputs from two or more ring oscillators may be compared, and when the outputs have a difference greater than a tolerance value, a signal for initiating a countermeasure response may be generated.

Description

Background Art

[0001] An integrated circuit (IC) may include a design that contains sensitive information. An example of such sensitive information is secret key information used in a cryptographic engine implementation (such as AES). Attempts may be made to gain access to secure or sensitive information (passwords or other information) on the IC by dropping a measurement probe on the IC and / or physically modifying the IC and generating an unauthorized or unexpected response. Summary of the invention

[0002] Tamper detection in an integrated circuit is described herein. The described tamper detection and corresponding circuit can detect tampering by identifying changes in the frequency characteristics of a ring oscillator.

[0003] One implementation of a system incorporating tamper detection may include at least one ring oscillator and a detection circuit coupled to the at least one ring oscillator to detect frequency variations greater than a tolerance. Each ring oscillator is formed by a plurality of inverters, wherein at least one intermediate node coupling the output of one of the plurality of inverters and the input of another of the plurality of inverters is a sensing node among a plurality of sensing nodes of the system. In some cases, at least half of the intermediate nodes coupling the output of the inverter to the corresponding input of the inverter are sensing nodes. The sensing nodes may be disposed in a top metal line. The sensing nodes may be shaped as lines or large pads to cover an area above a circuit block of an IC.

[0004] In some cases, the detection circuit includes one or more comparators.The two or more ring oscillators can be coupled to a comparator that detects when at least one of the two or more ring oscillators has a frequency variation that is greater than a tolerance.

[0005] In some cases, the sensing nodes may cover the chip or a portion of the chip in such a way that the probe will contact at least one sensing node, or portions of the sensing node will have to be removed to avoid touching the sensing node. The sensing nodes may be disposed at the topmost metal level, at the top metal level, interspersed in lower metal layers, on a back metal layer, or a combination thereof. The inverters of at least one ring oscillator may be dispersed throughout the chip, around or between functional circuits or logic blocks.

[0006] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1BAn example schematic diagram of a sensor for tamper detection is shown. Figure 1A A normal state without tampering is shown. Figure 1B The effects of tampering are shown.

[0008] Figure 2A A conceptual representation of a sensor for tamper detection is shown.

[0009] Figure 2B and Figure 2C An example layout diagram of sensing nodes of a sensor for tamper detection is shown.

[0010] Figure 2D A cross-sectional view of the layers of an IC incorporating a sensor for tamper detection is shown.

[0011] Figure 3A A simplified view of an IC with various blocks is shown.

[0012] Figure 3B An example of a sensor node on an IC is shown.

[0013] Figure 4A and Figure 4B An example detector configuration for detecting changes in the frequency characteristics of a ring oscillator of a sensor is shown. DETAILED DESCRIPTION

[0014] Tamper detection in an integrated circuit is described herein. The described tamper detection and corresponding circuitry can protect secure or sensitive information that may be contained on the IC by identifying changes in the frequency characteristics of a ring oscillator.

[0015] Figure 1A to Figure 1B An example schematic diagram of a sensor for tamper detection is shown. Figure 1A A normal state without tampering is shown. Figure 1B The effects of tampering are shown.

[0016] refer to Figure 1A , the sensor 100 for tamper detection may include a ring oscillator. The ring oscillator may include a plurality of inverters connected in series to form a closed loop having a certain oscillation frequency in a normal state. For example, a sensor 100 implemented with 56 inverters (7FF node) may have an oscillation frequency of 653 MHz. A probe may be placed on the chip to measure the signal.

[0017] refer to Figure 1B When the probe contacts the area of ​​the pad of the node of the sensor 100, the contact of the probe generates a voltage modeled as C on the node of the sensor 100. L The additional capacitance C L, the oscillation frequency of the sensor 100 drops, for example, from 653 MHz to 283 MHz. This drop in frequency is significant (e.g., in addition to typical drifts that may occur due to process, temperature, and voltage) and can be easily detected. In addition to probe contact, the described sensor can also detect tampering due to frequency changes caused by changes in capacitance or resistance, which includes cutting a pad / wire or removing a portion of a pad (and applying a conductive material to mimic the original connection), the above-mentioned change in capacitance or resistance is due to the removal (and possible addition of conductive material, which is generally different from the material used for the pad).

[0018] The inverters of the ring oscillator sensor may be formed in the active layer of the chip. In some cases, the inverters may be dispersed throughout the chip, distributed around or between the functional circuits or logic blocks of the chip. In some cases, two or more ring oscillators may be provided.

[0019] Figure 2A A conceptual representation of a sensor for tamper detection is shown; Figure 2B to Figure 2C An example layout diagram of sensing nodes of a sensor for tamper detection is shown; and Figure 2D A cross-sectional view showing the layers of an IC incorporating a sensor for tamper detection. Figure 2A , the sensor 200 includes a plurality of inverters 210. The inverters 210 may be distributed around or between functional circuits or logic blocks of the chip. Figure 1A The ring oscillator configuration described herein provides one or more intermediate nodes (eg, N1, N2, ..., N n The corresponding intermediate node) can rise to the metal line 220. The output of each inverter (e.g., 221) and the input of each inverter (e.g., 222) are coupled to each other via the intermediate node (e.g., N3). At least one intermediate node is a sensing node (which may also be referred to as an intermediate sensing node or simply a "sensing node") disposed in one of the metal layers 220 of the IC chip.

[0020] like Figure 2D As shown, the sensing node can be set at the top metal level (see, for example Figure 2B 225), which may be the topmost 230 or just the high metal layer 240; interspersed in the lower layers of metal 250 (e.g., in the middle layers); on the back metal layer 260; or a combination thereof (e.g., see Figure 2C arrangement shown).

[0021] The sensing nodes form sensor pads and can be shaped as lines or large pads to cover an area of ​​underlying circuitry fabricated in device layer 215 of an IC chip (which may include IC circuitry and one or more detector ring oscillators). For example, the sensing nodes can each have a size greater than or equal to the contact pad width (defined by the layout technology minimum width of the metal contact coupled to the via (which may depend on the foundry and process)). In addition, the size and shape of the sensing nodes can be the same or different between the same ring oscillator or between different ring oscillators (when multiple ring oscillators are formed for tamper detection of the IC). The sensing nodes (e.g., N1, N2, ..., and N2) can be configured to have a plurality of sensing nodes, each of which has ... n One or more of ) may produce a covering layer which, when removed, cut or contacted by a probe, results in a change in the oscillation frequency of a ring oscillator formed by the connected inverters.

[0022] For example, refer to Figure 2B , sensing nodes (N1, N2, ..., N n ) may be disposed in the top metal 230. Although the sensing nodes are shown in rows and have different sizes, the pads forming the sensing nodes may be disposed in any suitable arrangement. It should also be understood that the top metal layer may not be the topmost metal of the chip.

[0023] As another example, refer to Figure 2C , the sensing nodes may be arranged in multiple metal layers. In the illustrative example, the intermediate nodes N1, N2, ..., and N n Includes sensing nodes in two layers of metal as well as some intermediate nodes that do not rise to higher metal layers (and in some cases may not be provided as "sensing nodes" in terms of size and shape). Here, intermediate nodes N1...N R is a sensing node set in the top metal 230, and the intermediate nodes N4, N8...N s The sensing node is disposed in the metal layer 240 below the top metal layer 230. The metal layer 240 may be a layer directly below the top metal layer 230, or a layer one layer below the top metal layer 230. T ) can be set in the intermediate layer. In some cases, some intermediate nodes can be set on the device layer 215 in the polysilicon layer. Figure 2C It can be seen that the shape and size of the sensing nodes can vary.

[0024] Figure 3A shows a simplified view of an IC having various blocks; and Figure 3B An example of a sensor node on an IC is shown. Figure 3A, a chip 300 implementing an IC may include a plurality of different circuit blocks and sub-blocks, including but not limited to a processor 302, a memory 304, an analog circuit 306, an interface circuit and other blocks 308, and a block 310 for sensitive operations (e.g., a cryptographic block). The described sensing nodes may be arranged on the IC 300 so as to cover the various blocks. For example, Figure 3B As shown, the sensing nodes 350 may be arranged above the IC in any suitable pattern, including but not limited to random, patchwork, mosaic, array, and checkerboard. In some cases, a higher density of sensing nodes 350 may be arranged in areas where it is expected that measurement probes may be placed, such as in area 360, which may correspond to the area above the sensitive operation block 310. The chip 300 may have multiple areas where measurement probes may be placed, which may exist within the IC, and different countermeasure responses may be required depending on where the probes are placed. Figure 3B Each node shown may be an intermediate node of a ring oscillator. In some cases, dummy nodes may be included to obfuscate which nodes are sensing nodes.

[0025] Figure 4A and Figure 4B An example detector configuration for detecting changes in the frequency characteristics of a ring oscillator of a sensor is shown. Multiple ring oscillators may be placed in an IC to provide a sensor for tamper detection. Tampering of the IC, such as by removing or cutting material from the IC or applying a probe, may be detected by the detector comparing the oscillation frequencies of the multiple ring oscillators and monitoring if there is one or more oscillation frequencies that deviate from the other oscillation frequencies by more than a threshold amount.

[0026] refer to Figure 4A and Figure 4B , there may be N ring oscillators in the sensor group (where N is a natural number). Each oscillator may be configured such as about FIG. 2A to FIG. 2D The frequency value of each ring oscillator (eg, from ring oscillator 1 401) can be "measured" by a readout circuit that includes a counter (eg, counter 411) coupled to each ring oscillator.

[0027] Each counter (eg, 411) can count the rising or falling edges of the corresponding ring oscillator output to determine the frequency value. Figure 4A of 420; Figure 4B430) can compare the counts of two or more ring oscillators to determine whether there is a significant difference in frequency (e.g., greater than a threshold) between the two or more ring oscillators. If the difference is greater than a certain tolerance value, the difference is considered significant. Multiple ring oscillators can be provided, where each ring oscillator is arranged similarly to the other ring oscillators so as to have similar frequencies.

[0028] The oscillation frequencies can be compared to each other in various combinations. In some cases, changes in frequency can be detected by comparing the frequencies of the ring oscillators two by two. In some cases, changes in frequency can be detected by comparing each ring oscillator to the other ring oscillators.

[0029] For example, if there are 20 ring oscillators in a sensor, the oscillation frequency of one ring oscillator can be compared to one of the other ring oscillators in the sensor group, thereby providing 10 pairs for comparison, or compared to one of the other sensor groups or a reference oscillator, thereby providing 20 pairs for comparison (where the second of the pair can be the same reference oscillator). As another example, the oscillation frequency of each ring oscillator can be compared to the other 19. As another example, the oscillation frequencies of the ring oscillators in a group of less than 20 sensors are compared to each other.

[0030] like Figure 4A As shown, when the oscillator frequencies are compared two by two, each oscillator pair can be coupled to a corresponding comparator 420. Figure 4B As shown, a single comparator 430 can be used with a switch network 440 to select which pairs of ring oscillators are being compared. The outputs of the ring oscillators can be selectively coupled to the comparators 430 in pairs. The signals 445 output by the comparators (e.g., comparators 420, 430) can be used to initiate a countermeasure / mediation response. For example, if the comparator determines that the difference between the frequencies is greater than a tolerance value, an error signal can be output. An error output from any comparator can initiate a countermeasure response. As described with respect to Figure 3A and Figure 3B As explained, different sensor groups can be used to initiate different responses.

[0031] A method of defending against tampering attacks may include: comparing outputs from two or more ring oscillators; and generating a signal for initiating a countermeasure response when the outputs have a difference greater than a tolerance value. For example, the method may include: receiving a first output of a first ring oscillator in a set of ring oscillators, each ring oscillator such as about Figure 2A and Figure 2BThe method of claim 1, wherein the first output is compared to the second output of the ring oscillator. ...

[0032] In some cases, a significant deviation in the oscillation frequency of one or more ring oscillators can trigger a reset of the system to prevent the adversary from making more interesting measurements or influencing the behavior of the circuit. The specific countermeasure response implemented by the system can be to reset, stop or disable the system, obfuscate data operations, or perform another appropriate countermeasure response. For example, an IC designer can determine a countermeasure response that obfuscates or changes data in some way. One such approach can be to switch from performing an appropriate response to performing an inappropriate response. An inappropriate response refers to a response that is intended to create power signatures that indicate different keys or random keys.

[0033] In some cases, the comparator may compare the ring oscillator frequency to a value stored in a register rather than comparing two ring oscillators.

[0034] Any reference in this specification to "one embodiment," "an embodiment," "an example embodiment," "an example," "some examples," etc., indicates that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. The appearances of such phrases in various places in the specification do not necessarily all refer to the same embodiment. In addition, any element or limitation of any invention or embodiment thereof disclosed herein may be combined with any and / or all other elements or limitations disclosed herein (alone or in any combination) or any other invention or embodiment thereof, and all such combinations are contemplated for the scope of the present invention without limitation thereto.

[0035] Although the subject matter has been described in language specific to structural features and / or acts, it will be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as examples of implementing the claims, and other equivalent features and acts are intended to be within the scope of the claims.

Claims

1. A system with tamper detection, comprising: a plurality of sensing nodes, each of the plurality of sensing nodes being disposed in the metal layer, wherein each of the plurality of sensing nodes has a size greater than or equal to a width of a contact pad; at least one ring oscillator, each ring oscillator comprising a plurality of inverters coupled to each other in a ring via intermediate nodes, wherein at least one intermediate node coupling an output of one of the plurality of inverters and an input of another of the plurality of inverters is a sensing node of the plurality of sensing nodes; and A detection circuit is coupled to the at least one ring oscillator to detect a frequency variation greater than a tolerance.

2. The system of claim 1, wherein: The plurality of sensing nodes are disposed in a top metal layer.

3. The system of claim 1 or claim 2, further comprising an integrated circuit, the integrated circuit comprising a circuit block on a chip, wherein the sensing node is disposed above the circuit block on the chip.

4. The system of claim 3, wherein: The plurality of inverters are distributed throughout and between circuit blocks of the chip.

5. The system of claim 3, wherein: The sensing nodes are arranged in a random pattern.

6. The system of claim 3, wherein: The sensing nodes are arranged in a patchwork or checkerboard pattern.

7. The system of claim 1, wherein: The detection circuit includes a comparator.

8. The system of claim 7, further comprising at least one counter, the output of the ring oscillator being coupled to the comparator through one of the at least one counter.

9. A system with tamper detection, comprising: a plurality of sensing nodes, each of the plurality of sensing nodes being disposed in the metal layer, wherein each of the plurality of sensing nodes has a size greater than or equal to a width of a contact pad; two or more ring oscillators, each ring oscillator comprising a plurality of inverters coupled to each other in a ring via intermediate nodes, wherein at least one intermediate node coupling an output of one of the plurality of inverters and an input of another of the plurality of inverters is a sensing node of the plurality of sensing nodes; and a detection circuit coupled to the two or more ring oscillators to detect a frequency variation greater than a tolerance, wherein the detection circuit comprises a comparator, Wherein, a first ring oscillator of the two or more ring oscillators has a first output coupled to the comparator, and a second ring oscillator of the two or more ring oscillators has a second output coupled to the comparator, so that the first output and the second output are compared with each other via the comparator.

10. A system with tamper detection, comprising: a plurality of sensing nodes, each of the plurality of sensing nodes being disposed in the metal layer, wherein each of the plurality of sensing nodes has a size greater than or equal to a width of a contact pad; two or more ring oscillators, each ring oscillator comprising a plurality of inverters coupled to each other in a ring via intermediate nodes, wherein at least one intermediate node coupling an output of one of the plurality of inverters and an input of another of the plurality of inverters is a sensing node of the plurality of sensing nodes; and a detection circuit coupled to the two or more ring oscillators to detect a frequency variation greater than a tolerance, wherein the detection circuit comprises a comparator, The outputs of the two or more ring oscillators are selectively coupled to the comparator, so that at least two outputs of the two or more ring oscillators are compared with each other via the comparator.

11. The system of claim 10, wherein: The outputs of the two or more ring oscillators are selectively coupled in pairs to the comparators.

12. A method for tamper detection, comprising: receiving a first output of a first ring oscillator in a set of ring oscillators; receiving a second output of a second ring oscillator in the set of ring oscillators; comparing the first output to the second output; and generating a signal for initiating a first countermeasure response when the first output differs from the second output by more than a tolerance value, wherein each ring oscillator in the group of ring oscillators including the first ring oscillator and the second ring oscillator comprises a plurality of inverters, Wherein, for each ring oscillator in the group of ring oscillators including the first ring oscillator and the second ring oscillator, At least one intermediate node coupling an output of one of the plurality of inverters and an input of another of the plurality of inverters is a sensing node of a plurality of sensing nodes, each of the plurality of sensing nodes being disposed in a metal layer, wherein each of the plurality of sensing nodes has a size greater than or equal to a width of a contact pad.

13. The method of claim 12, wherein: Comparing the first output to the second output includes: retrieving a first value from the first counter, the first value representing a first frequency of the first ring oscillator; retrieving a second value from the second counter, the second value representing a second frequency of the second ring oscillator; and The first value is compared to the second value using a comparator.

14. The method of claim 12 or claim 13, further comprising: Pairs of ring oscillators in the set of ring oscillators are compared sequentially.

15. The method of claim 14, further comprising: The pair of ring oscillators are selectively coupled to a comparator.

16. The method of claim 12, further comprising: When the first output and the second output are continuously received, the first output is periodically compared with the second output.

17. The method of claim 12, further comprising: comparing two outputs received from the second set of ring oscillators; and When the two outputs received from the second set of ring oscillators have a difference greater than a tolerance value, a signal for initiating a second countermeasure response is generated.

18. The method of claim 17, wherein: The second countermeasure response is different from the first countermeasure response.

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