Integrated circuit with thin film resistors having metal walls

Abstract

An integrated circuit (IC) (100) includes a substrate having a semiconductor surface layer (102) having a functional circuit system for implementing at least one circuit function, and an inter-layer dielectric (ILD) layer on a metal layer (118) above the semiconductor surface layer (102). A TFR including a thin-film resistor (TFR) layer is on the ILD layer. At least one vertical metal wall (108) is on at least two sides of the TFR. The metal wall includes at least two metal levels coupled by filled vias (126). The functional circuit system is outside the metal wall.

Description

Technical Field

[0001] This invention relates to semiconductor integrated circuit (IC) devices having thin-film resistors (TFRs). Background Technology

[0002] Some IC devices include TFRs. TFRs are typically on the order of 0.1 μm or less thick, while thick-film resistors are often 1000 times thicker. Silicon-chromium (SiCr) and nickel-chromium (NiCr) have been used as TFRs for many years due to their high resistance in thin-film form, relatively low temperature coefficient of resistance (TCR), and ability to reliably carry relatively high current densities. TFRs can be laser-trimmed, especially for precision ICs, such as for setting the offset voltage of operational amplifiers or the output voltage of voltage regulators.

[0003] Laser trimming is accomplished by ablating a portion of the TFR structure using a laser beam. As the effective cross-sectional area of ​​the TFR decreases, its resistance increases. Laser trimming is typically performed in conjunction with wafer probing. Summary of the Invention

[0004] This synopsis is provided to present a simplified selection of the disclosed concepts, which are further described below in a detailed description including the provided drawings. This synopsis is not intended to limit the scope of the claimed subject matter.

[0005] An IC includes a substrate having a semiconductor surface layer having a functional circuit system for implementing at least one circuit function, and an interlayer dielectric (ILD) layer on a metal layer above the semiconductor surface layer. A transducer frame (TFR) including a transducer frame (TFR) layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal wall includes at least two metal layers coupled together by filled vias. The functional circuit system is outside the metal wall. Attached Figure Description

[0006] Now refer to the attached diagram, which is not necessarily drawn to scale, in which:

[0007] Figure 1A A cross-sectional view is depicted of a portion of an example IC having a TFR, which includes an exposed metal wall that at least partially surrounds the TFR.

[0008] Figure 1B This is a top view of the disclosed TFR, which has metal walls that at least partially surround the TFR by enclosing three of the four sides of the TFR.

[0009] Figure 1C This is a cross-sectional view of the IC shown, which has at least partially surrounded by Figure 1BThe TFR of the three metal walls shown.

[0010] Figures 2A to 2J This is a cross-sectional view illustrating the process progress of an example method for forming an IC having a metal wall that at least partially surrounds the TFR, according to an example aspect. Detailed Implementation

[0011] Referring to the accompanying drawings, examples are described, in which similar reference numerals are used to denote similar or equivalent elements. The illustrated order of actions or events should not be considered limiting, as some actions or events may occur in a different order and / or simultaneously with other actions or events. Furthermore, some illustrated actions or events may not be necessary to implement the method according to this disclosure.

[0012] Furthermore, the terms “coupled to” or “coupled with” (and the like) used herein are intended to describe indirect or direct electrical connections without further limitation. Thus, if a first device is “coupled” to a second device, the connection can be a direct electrical connection where only parasites exist in the path, or an indirect electrical connection via an intermediary that includes other devices and connections. For indirect coupling, the intermediary typically does not modify the information of the signal, but may adjust its current level, voltage level, and / or power level.

[0013] This disclosure recognizes that potential dielectric damage generated during laser trimming of the TFR can lead to quality and reliability risks for the IC, such as increased leakage current and reduced mechanical strength. The disclosed IC has a TFR having at least partially surrounded by a metal wall that can reduce or eliminate the effects of dielectric damage caused by laser trimming by suppressing dielectric damage, thereby preventing it from extending beyond the metal wall. The disclosed metal wall comprises a metal layer and a filled via (e.g., filled with tungsten) coupling at least two different metal layers together.

[0014] Figure 1A A cross-sectional view depicting a portion of an example IC 100 having a TFR 290, the TFR 290 including surrounding metal walls 108a and 108b that at least partially surround the TFR 290. The IC 100 is formed on a substrate 102, such as a silicon wafer. The substrate 102 may include a bulk substrate material such as silicon or an epitaxial layer on a bulk substrate material. Alternatively, the substrate may include silicon-germanium, other Group 4 materials, or other semiconductor materials including III-V and II-VI compound semiconductor materials.

[0015] IC 100 includes at least one TFR, shown as TFR 290, whose respective ends are connected to a first node and a second node on IC 100. Figure 1AIn the view shown, metal walls 108a and 108b are shown as bimetallic walls on both sides of TFR 290.

[0016] TFR 290 may comprise chromium or doped polysilicon and is shown on an interlayer dielectric (ILD) layer 122a. TFR 290 is typically 1 nm to 100 nm thick and typically has a sheet resistance of 100 to 1000 Ω / □ (ohms / square). TFR 290 is contacted via through-hole pads as shown in 126a.

[0017] A field oxide (FOX) layer or FOX region 112 is formed in the substrate 102 (e.g., near or adjacent to the top surface of the substrate 102) to laterally electrically isolate the components of the IC 100. A pre-metal dielectric (PMD) layer 114 is formed over the substrate 102 prior to the deposition of subsequent metal layers 118-1 to 118-N, including over any FOX region 112, where 118-1 may be referred to as metal 1 (M1), and in this example, the top metal layer 118-N is M5. Metal layers 118-1 to 118-N may comprise aluminum or copper or their respective alloys. Contacts 116 may be disposed through the PMD layer 114 to provide electrical connections to IC components, such as a metal-oxide-semiconductor (MOS) transistor 106 including a gate 111, a source 107, and a drain 109 on a gate dielectric 110. Although metal walls 108a and 108b are shown to be electrically isolated from the semiconductor surface layer of substrate 102, contacts for grounding metal walls 108a and 108b to substrate 102 may be present.

[0018] The plurality of metal levels 118-1 to 118-N disposed above the PMD layer 114 may include metal interconnects 120, which include functional circuitry connected to the MOS transistor 106 and metal walls 108a, 108b, as well as any additional components, devices, or circuit portions. ILD layers (e.g., dielectric materials or compositions of materials such as silicon dioxide) shown as 122a-e are disposed between the metal interconnects 120 in each metal level and between the individual metal levels.

[0019] The corresponding via level 124 is disposed between metal levels 118-1 to 118-N, wherein the example via level 124 may include a metal via 126 that provides a connection between metal interconnects 120 in adjacent levels. In one arrangement, various dielectric layers can be formed using similar materials in a similar process flow. It should be understood that other dielectric materials used for ILD layers (e.g., low dielectric constant (k) materials) are within the scope of this example, such as FSG (k = 3.6 fluorinated silicate glass), OSG (k = 2.9 organosilicon glass), and ULK (k = 2.5 ultra-low k dielectric material). The ILD layer may include capping layers and etch stop layers of different dielectric materials (e.g., silicon nitride and silicon carbide).

[0020] The disclosed metal walls 108a and 108b can be single metal walls, double metal walls, or three or more metal walls and corresponding rows of vias. Metal walls 108a and 108b can comprise any or all metal layers on IC 100, such that they can comprise aluminum or copper, or their respective alloys. The vias 126 used in the metal walls can comprise any via level or combination of via levels. The width of the metal in the disclosed metal walls 108a and 108b can be, but is not limited to, the minimum size of a metal layer. The size of the via 126 can also be, but is not limited to, the minimum size of a via on IC. The metal on the metal levels for the metal walls 108a and 108b can comprise metal islands such that they are not connected to each other.

[0021] Figure 1B This is a top view of a disclosed TFR 290, which has metal walls as shown in 108a, 108b, and 108c, which at least partially surround the TFR 290 by surrounding three of its four sides. Each metal wall includes multiple metal islands, as shown in 158, which may include M1, M2, M3, M4, and M5 connected by through-holes 126 arranged in two rows with staggered metal islands 158. Metal arrangements at the top level (e.g., M5) have metal islands 158, each with two or three metal through-holes 126, from which the metal walls can be accessed. Figure 1A The M1 corresponding to 118-1 extends to the top metal layer (e.g.) Figure 1A The M5 shown corresponds to 118-N. The metal island 158 can be isolated from the substrate 102. Figure 1A (as shown) or alternatively connected to substrate 102, isolated from the functional circuitry on the IC, close to TFR 290 without having any intermediate structure between TFR 290 and metal island 158.

[0022] Figure 1CThis is a cross-sectional view of an IC, shown as 170, which has a TFR 290, which at least partially surrounds... Figure 1B The three metal walls 108a, 108b, and 108c are shown. Damage 167, representing laser-trimmed cracks 122b, 112c, and 122d, is contained within metal walls 108a and 108b.

[0023] The disclosed aspect includes a method for manufacturing an IC comprising a TFR having a metal wall that at least partially surrounds the TFR. Figure 2A The illustration depicts an in-process IC (IC) after depositing an ILD layer, as shown in 122a, on a substrate 102 comprising a semiconductor surface layer 103 having multiple IC dies (e.g., wafers) formed therein. Each IC die includes a functional circuit system 180, which includes multiple interconnect transistors, such as... Figure 1A The MOS transistor 106 is shown. Metal layer 118-1 is on PMD 114 and below the ILD layer shown in 122a. Functional circuit system (see description below) Figures 2A to 2I The functional circuit system 180 is typically formed in the substrate 102 prior to the formation of the TFR. The functional circuit system used herein implements and performs desired functions, such as those of a digital IC (e.g., a digital signal processor) or analog IC (e.g., an amplifier or power converter), and in one aspect, the functions of a BiCMOS (MOS and bipolar) IC. The capabilities of the functional circuit system provided on the disclosed IC can vary, for example, from simple devices to complex devices. Specific functions contained in the functional circuit system are not critical to the disclosed IC.

[0024] ILD layer 222a may include a silicon oxide layer derived from tetraethoxysilane (TEOS). However, other dielectric films may also be used for the disclosed ILD layer, which includes deposited silicon oxide, such as organosilicon glass (OSG), low-k dielectric (i.e., a smaller dielectric constant relative to silicon dioxide), doped dielectric layer (e.g., fluorine-doped silicon dioxide glass (FSG) or SiN layer or variants thereof (e.g., SiON)).

[0025] Figure 2BThe diagram shows a work-in-progress IC after a TFR layer 161 has been deposited on the ILD layer 122a. The deposition process may include direct current (DC) or radio frequency (RF) sputtering. The TFR layer 161 may contain SiCr or alloys thereof, such as carbon-containing SiCr, SiCOCr (where C may be 1% to 50% atomic percentage), or NiCr or alloys thereof (e.g., NiCrFe 61% Ni, 15% Cr, 24% Fe (all atomic percentages)) or doped polysilicon. The thickness of the TFR layer 161 is typically from 1 nm to 50 nm (e.g., 2 nm to 10 nm), or approximately 3 nm to 5 nm in a particular aspect.

[0026] Figure 2C The image shows a work-in-progress IC after depositing a hard mask layer, such as HM 162 (e.g., a TEOS-derived HM layer), and then patterning is formed on the HM layer 162. Photoresist 163 can be used to form the pattern. For a TEOS-based deposition process, this deposition process may include low-pressure CVD (LPCVD) at a pressure of approximately 300 mtorr and a temperature of approximately 700 °C. The thickness of the HM layer 162 may range from 20 Å to 300 Å.

[0027] Figure 2D The diagram illustrates a work-in-process IC where etching of the HM layer 162 and TFR layer 161 is stopped at ILD layer 122a to form at least one TFR 290 including the TFR layer, followed by stripping of PR layer 163. In the case of silicon oxide, the etching gas used for etching the HM layer can be Ar and CF4, with optional Cl2. The etching gas used for etching the TFR layer 161 typically includes flowing O2, Cl2, and at least one carbon halide gas. For example, O2, Cl2, and CF4 with optional Ar can be used to etch SiCr. Furthermore, other gases can also be used to etch the TFR layer, such as CHF3 or CH2F2, as alternatives to or complements to CF4, and / or N2 may also be used.

[0028] Figure 2E The image shows a work-in-process IC after the deposition of a second ILD layer, as shown in ILD layer 122b. ILD layer 122b typically comprises deposited silicon oxide. Figure 2FThe diagram illustrates a work-in-process IC after vias 126 are formed through ILD 122b and HM layer 162 to expose contacts on TFR layer 161, followed by deposition and patterning of another metal layer, exemplified by a thick SiCr layer 270 (thicker than TFR layer 161, for example at least 10 times thicker, e.g., 50 Å to 600 Å thick). The thick SiCr layer 270 may be referred to as the TFR head formed in ILD layer 122b. Vias 126 for the TFR head can be formed in ILD layer 122b using plasma etching or wet etching. Metal interconnects 120 contact vias 126 and the thick SiCr layer 270.

[0029] Figure 2G The image shows a work-in-progress IC after a metal layer 118-2 (M2) is deposited and then defined, an ILD layer 122c is deposited, and a via 126 is formed in the ILD layer 122c. Figure 2H The image shows a work-in-process IC after depositing and defining a metal layer 118-3 (M3), depositing an ILD layer 122d, and forming a via 126 in the ILD layer 122d. Figure 2I The image shows a work-in-progress IC after depositing and defining a metal layer 118-4 (M4), depositing an ILD layer 122e, and forming a via 126 in the ILD layer 122e. Figure 2J The in-process IC is shown after a metal layer 118-5 (M5) has been deposited and defined on a via 126 in an ILD layer 122e.

[0030] The IC can then be completed using known conventional line-back-of-line (BEOL) processing, which includes optionally forming one or more additional metal levels, including filled vias thereon, to add metal walls to optionally include metal levels up to the top metal level. Like the other metal layers, the top metal layer may comprise aluminum or copper or alloys thereof. A passivation coating (PO) is typically then applied, followed by patterning of the PO. The PO layer includes at least one dielectric layer, such as silicon oxide, silicon nitride, or SiON. As described below, in the final IC, the TFR 290 is connected within the functional circuit system 180, for example via M2, which reaches nodes within the circuit system in the semiconductor surface layer 103 through vias and contacts.

[0031] The disclosed aspects can be used to form semiconductor dies, which can be integrated into various assembly processes to form a variety of different devices and related products. The semiconductor die may include various components therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active components, and passive components, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Furthermore, the semiconductor die can be formed using various processes, including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS, and MEMS.

[0032] Those skilled in the art to which this disclosure pertains will understand that many other aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions, and modifications can be made to the described aspects without departing from the scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit, i.e., an IC, the method comprising: A substrate having a semiconductor surface layer is provided, the semiconductor surface layer having a functional circuit system for implementing at least one circuit function, and having an inter-layer dielectric layer, i.e., an ILD layer, on a metal layer above the semiconductor surface layer; A thin film resistor, namely a TFR, is formed on the ILD layer, and the TFR includes a TFR layer; At least one vertical metal wall is formed on at least two sides of the TFR to reduce or eliminate the effect of dielectric damage by suppressing dielectric damage; The metal wall comprises at least two metal layers coupled by filled through-holes, and The functional circuit system is located outside the metal wall.

2. The method according to claim 1, wherein the TFR layer comprises silicon-chromium (SiCr) or nickel-chromium (NiCr).

3. The method of claim 2, wherein the TFR layer comprises doped polysilicon.

4. The method according to claim 1, wherein the thickness of the TFR layer is from 1 nm to 100 nm.

5. The method according to claim 1, further comprising laser trimming of the TFR.

6. The method of claim 1, wherein each of the metal walls comprises at least two of the metal walls.

7. The method of claim 1, wherein the at least two metal levels of the metal wall comprise a plurality of staggered metal islands.

8. The method of claim 1, wherein the at least two metal layers of the metal wall share a minimum width on the IC.

9. The method of claim 1, wherein the metal wall is electrically isolated from the semiconductor surface layer.

10. The method of claim 1, wherein the sheet resistance of the TFR is 100 to 1000 Ω / □.

11. An integrated circuit, i.e., an IC, said IC comprising: A substrate having a semiconductor surface layer having a functional circuit system for implementing at least one circuit function, and having an interlayer dielectric layer, i.e., an ILD layer, on a metal layer above the semiconductor surface layer. The thin-film resistor, or TFR, on the ILD layer includes a TFR layer and... At least one vertical metal wall on at least two sides of the TFR, The metal wall comprises at least two metal layers coupled by filled vias, and the metal wall is configured to reduce or eliminate the effect of dielectric damage by suppressing dielectric damage. The functional circuit system is located outside the metal wall.

12. The IC of claim 11, wherein the TFR layer comprises silicon-chromium (SiCr) or nickel-chromium (NiCr).

13. The IC of claim 11, wherein the TFR layer comprises doped polysilicon.

14. The IC according to claim 11, wherein the thickness of the TFR layer is from 1 nm to 100 nm.

15. The IC of claim 11, wherein each of the metal walls comprises at least two of the metal walls.

16. The IC of claim 11, wherein the at least two metal levels of the metal wall comprise a plurality of staggered metal islands.

17. The IC of claim 11, wherein the at least two metal layers of the metal wall share a minimum width on the IC.

18. The IC of claim 11, wherein the metal wall is electrically isolated from the semiconductor surface layer.

19. The IC of claim 11, wherein the sheet resistance of the TFR is 100 to 1000 Ω / □.

20. The IC of claim 11, wherein the IC comprises an analog IC.

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