Memory controller and memory data receiving method

Abstract

A memory controller and a memory data receiving method, the memory controller comprising: a delay circuit, used to use a first delay value and a second delay value to delay a sampling clock signal respectively to generate a first and a second delayed sampling clock signal; a sampling circuit, used to sample a data signal using a first edge of the first delayed sampling clock signal to generate a first sampling value, and used to sample the data signal using a second edge of the second delayed sampling clock signal to generate a second sampling value; and a correction circuit, used to generate a sampling delay value based on the first sampling value and the second sampling value and according to the first delay value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal, and the sampling circuit samples the data signal with the adjusted sampling clock signal.

Description

Technical Field

[0001] The present invention relates to a memory controller and a memory data receiving method, and in particular to a memory controller and a memory data receiving method capable of generating a better sampling clock signal. Background Art

[0002] When receiving a data signal, a conventional memory controller uses a sampling clock signal from a memory to sample the data signal. However, if the sampled data signal is not properly selected, an erroneous sampled value may be obtained. Summary of the invention

[0003] Therefore, an object of the present invention is to provide a memory controller which can sample memory data using a sampling clock signal with a suitable sampling phase.

[0004] Another object of the present invention is to provide a memory control method, which can sample memory data using a sampling clock signal with a suitable sampling phase.

[0005] An embodiment of the present invention discloses a memory controller, comprising: a delay circuit, for receiving a sampling clock signal from a memory, delaying the sampling clock signal using a first delay value to generate a first delayed sampling clock signal, and delaying the sampling clock signal using a second delay value to generate a second delayed sampling clock signal; a sampling circuit, for receiving a data signal from the memory, sampling the data signal using a first edge of the first delayed sampling clock signal to generate a first sampling value, and sampling the data signal using a second edge of the second delayed sampling clock signal to generate a second sampling value; and a correction circuit, for generating a sampling delay value based on the first sampling value and the second sampling value and according to the first delay value; wherein the delay circuit generates an adjusted sampling clock signal using the sampling delay value, and the sampling circuit samples the data signal using the adjusted sampling clock signal.

[0006] Another embodiment of the present invention discloses a memory data receiving method, comprising: (a) delaying a sampling clock signal from a memory by a first delay value to generate a first delayed sampling clock signal; (b) delaying the sampling clock signal by a second delay value to generate a second delayed sampling clock signal; (c) sampling the data signal by a first edge of the first delayed sampling clock signal to generate a first sampling value; (d) sampling the data signal by a second edge of the second delayed sampling clock signal to generate a second sampling value; (e) generating a sampling delay value based on the first sampling value and the second sampling value and according to the first delay value; and (f) generating an adjusted sampling clock signal by the sampling delay value, and sampling the data signal by the adjusted sampling clock signal.

[0007] According to the aforementioned embodiments, a sampling clock signal with a better phase may be used to receive memory data to ensure that the sampled memory data is correct data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a block diagram showing a memory controller according to an embodiment of the present invention.

[0009] Figure 2 , Figure 3 and Figure 4 To illustrate the different embodiments of the present invention Figure 1 A schematic diagram of the operation of the memory controller.

[0010] Figure 5 FIG. 4 is a circuit diagram of a sampling circuit according to an embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a block diagram showing a memory controller according to another embodiment of the present invention.

[0012] Figure 7 To illustrate the embodiment of the present invention Figure 6 A schematic diagram of the operation of the memory controller.

[0013] Figure 8 FIG. 4 is a flow chart showing a method for receiving memory data according to an embodiment of the present invention.

[0014] Explanation of symbols

[0015] 100, 600 memory controller

[0016] 101 Delay Circuit

[0017] 103 Sampling Circuit

[0018] 105 Correction Circuit

[0019] 601 Delay Detection Circuit

[0020] MD Memory

[0021] SU_1, SU_2, SU_3 sampling units DETAILED DESCRIPTION

[0022] The concept of the present invention will be described below with multiple embodiments. Please also note that the "first", "second" or similar descriptions in the following description are only used to define different elements or signals, but not to limit their order.

[0023] Figure 1 FIG. 2 is a block diagram of a memory controller according to an embodiment of the present invention. Figure 1 As shown, the memory controller 100 includes a delay circuit 101, a sampling circuit 103 and a correction circuit 105. The delay circuit 101 receives a sampling clock signal SC from the memory MD, and uses different delay values ​​to delay the sampling clock signal SC to generate delayed sampling clock signals DSC_1, DSC_2...DSC_m, where m is a positive integer. The sampling circuit 103 receives a data signal DQ from the memory MD, and uses different edges of the delayed sampling clock signal to sample the data signal DQ to generate different sampling values ​​SV_1, SV_2...SV_n, where n is a positive integer. m and n can be the same or different. The correction circuit 105 adjusts the delay value of the delay circuit 101 according to at least two of the sampling values ​​SV_1, SV_2...SV_n.

[0024] Figure 2 , Figure 3 and Figure 4 To illustrate the different embodiments of the present invention Figure 1 Schematic diagram of the operation of the memory controller. Figure 2 and Figure 3 In the embodiment, the above m and n are 2. In addition, Figure 4 In the embodiment, the above m and n are 3. However, m and n can be any positive integer except 2 and 3.

[0025] exist Figure 2 In the embodiment of the present invention, the delay circuit 101 delays the sampling clock signal DSC by a delay value DV_1 to generate a delayed sampling clock signal DSC_1, and delays the sampling clock signal SC by another delay value DV_2 to generate a delayed sampling clock signal DSC_2. The delay value DV_1 is greater than the delay value DV_2. That is, the phase of the delayed sampling clock signal DSC_2 is ahead of the phase of the delayed sampling clock signal DSC_1. In addition, as Figure 2 As shown, the delayed sampling clock signal DSC_1 has an edge E_1, and the delayed sampling clock signal DSC_2 has an edge E_2. Figure 2 In the embodiment of , the edges E_1 and E_2 are rising edges, but at least one of the edges E_1 and E_2 may be a falling edge. Figure 2 In the embodiment of the present invention, the edge E_2 is the edge closest to the edge E_1 among all the edges of the delayed sampling clock signal DSC_2.

[0026] The sampling circuit 103 samples the data signal DQ with edge E_1 to generate a sampling value SV_1, and samples the data signal DQ with edge E_2 to generate a sampling value SV_2. If the sampling values ​​SV_1 and SV_2 are the same, it means that the edge E_1 is near the center of the data signal DQ, so the delayed sampling clock signal DSC_1 has a good sampling phase, and the correction circuit 105 does not adjust the delay value DV_1. In other words, the correction circuit 105 directly uses the delay value DV_1 as the sampling delay value, and the delay circuit 101 uses the sampling delay value to generate an adjusted sampling clock signal to sample the data signal DQ. On the contrary, if the sampling values ​​SV_1 and SV_2 are different, it means that the edge E_1 is close to the data edge DE_1 of the data signal DQ, so the delayed sampling clock signal DSC_1 has a poor sampling phase, and the correction circuit 105 adjusts the delay value DV_1. In detail, the correction circuit 105 adjusts the delay value DV_1 to generate a sampling delay value, and the delay circuit 101 uses the sampling delay value to generate an adjusted sampling clock signal, and the sampling circuit samples the data signal DQ with the adjusted sampling clock signal. For example, if the sampling values ​​SV_1 and SV_2 are different, it means that the edge E_1 is close to the data edge DE_1, so the delay value DV_1 is increased, so that the edge E_1 is closer to the center of the data signal DQ. Please also note that if the delay value DV_1 is not adjusted, the first delayed clock signal DSC_1 is used as the adjusted sampling clock signal.

[0027] exist Figure 3 In the embodiment of the present invention, the delay circuit 101 delays the sampling clock signal DSC by a delay value DV_1 to generate a delayed sampling clock signal DSC_1, and delays the sampling clock signal SC by another delay value DV_3 to generate a delayed sampling clock signal DSC_3. The delay value DV_1 is smaller than the delay value DV_3. That is, the phase of the delayed sampling clock signal DSC_1 is ahead of the phase of the delayed sampling clock signal DSC_3. Figure 2 The sampling circuit 103 samples the data signal DQ at edge E_1 to generate a sampled value SV_1, and samples the data signal DQ at edge E_3 to generate a sampled value SV_3. Figure 3 In the embodiment of FIG. 5 , the edge E_3 is the edge closest to the edge E_1 among all the edges of the delayed sampling clock signal DSC_3 .

[0028] If the sampling values ​​SV_1 and SV_3 are the same, the correction circuit 105 directly uses the delay value DV_1 as the sampling delay value, and the delay circuit 101 uses the sampling delay value to generate an adjusted sampling clock signal to sample the data signal DQ. On the contrary, if the sampling values ​​SV_1 and SV_2 are different, the correction circuit 105 adjusts the delay value DV_1 to generate the sampling delay value, and the delay circuit 101 uses the sampling delay value to generate an adjusted sampling clock signal to sample the data signal DQ. For example, if the sampling values ​​SV_1 and SV_3 are different, it means that the edge E_1 is close to the data edge DE_2 of the data signal DQ, so the delay value DV_1 will be reduced, so that the edge E_1 is closer to the center of the data signal DQ.

[0029] for Figure 2 and Figure 3 An embodiment of Figure 1 In this case, m and n are both 2. In addition, for Figure 4 An embodiment of Figure 1 The m and n in are 3. Figure 4 An embodiment can be considered as Figure 2 and Figure 3 A combination of embodiments.

[0030] exist Figure 4 In the embodiment of the present invention, the delay circuit 101 delays the sampling clock signal DSC by a delay value DV_1 to generate a delayed sampling clock signal DSC_1, delays the sampling clock signal SC by another delay value DV_2 to generate a delayed sampling clock signal DSC_2, and uses another delay value DV_3 to delay the sampling clock signal SC to generate a delayed sampling clock signal DSC_3. The delay value DV_1 is greater than the delay value DV_2 but less than the delay value DV_3. That is, the phase of the delayed sampling clock signal DSC_1 leads the phase of the delayed sampling clock signal DSC_3 but lags behind the phase of the delayed sampling clock signal DSC_2. The sampling circuit 103 samples the data signal DQ by edges E_1, E_2, and E_3, respectively, to generate sampling values ​​SV_1, SV_2, and SV_3.

[0031] If the sampling values ​​SV_1, SV_2 and SV_3 are the same, the correction circuit 105 directly uses the delay value DV_1 as the sampling delay value, and the delay circuit 101 generates the adjusted sampling clock signal with the sampling delay value to sample the data signal DQ. On the contrary, if the sampling values ​​SV_1 and SV_3 are the same, but the sampling values ​​SV_1 and SV_2 are different, it means that the edge E_1 is close to the data edge DE_1, so the correction circuit 105 increases the delay value DV_1 so that the edge E_1 is closer to the center of the data signal DQ. Moreover, if the sampling values ​​SV_1 and SV_2 are the same, but the sampling values ​​SV_1 and SV_3 are different, it means that the edge E_1 is close to the data edge DE_2, so the correction circuit 105 reduces the delay value DV_1 so that the edge E_1 is closer to the center of the data signal DQ.

[0032] The correction action described in the above embodiment can be performed periodically and before each data receiving action. In addition, in one embodiment, multiple correction actions can be performed for each data receiving action, and the best delay value DV_1 is selected from multiple delay values ​​DV_1 obtained in these correction actions.

[0033] Figure 1 The delay circuit 101 in the embodiment may be a delay chain including a plurality of delay stages connected in series. Furthermore, the correction circuit 105 may be a circuit including a plurality of logic gates, which may compare the sample values ​​SV_1 ... SV_n and output signals accordingly to control the delay circuit 101. Furthermore, the correction circuit 105 may be a processor installed with at least one program, so that the sample values ​​SV_1 ... SV_n may be compared and signals may be output accordingly to control the delay circuit 101.

[0034] In addition, the sampling circuit 103 may include various circuits. Figure 5 FIG. 4 shows a circuit diagram of a sampling circuit according to an embodiment of the present invention. Figure 5 As shown, the sampling circuit 103 includes a plurality of sampling units SC_1, SC_2, ..., which may be triggers or any other elements that can sample the data signal DQ according to the delayed sampling clock signals DSC_1, DSC_2, ...DSC_n. In this example, the number of sampling units is 3, which corresponds to Figure 4 Embodiment of the invention.

[0035] like Figure 5As shown, the sampling unit SU_1 samples the data signal DQ with the delayed sampling clock signal DSC_1 to generate the sampled value SV_1, the sampling unit SU_2 samples the data signal DQ with the delayed sampling clock signal DSC_2 to generate the sampled value SV_2, and the sampling unit SU_3 samples the data signal DQ with the delayed sampling clock signal DSC_3 to generate the sampled value SV_3. However, the circuit of the sampling circuit 103 is not limited to Figure 5 The embodiment shown.

[0036] Since the delay value provided to each delay stage of the delay circuit 101 may be affected by various factors such as temperature or voltage, the memory controller provided by the present invention may also provide a compensation mechanism. Figure 6 FIG. 1 is a block diagram of a memory controller 600 according to another embodiment of the present invention. In addition to the delay circuit 101, the sampling circuit 103 and the correction circuit 105, the memory controller 600 further includes a delay detection circuit 601, which can detect whether at least one of the delay intervals between the edges of different delayed clock signals falls within a predetermined interval. Therefore, the delay interval can be controlled within the predetermined interval.

[0037] Figure 7 To illustrate the embodiment of the present invention Figure 6 A schematic diagram of the operation of the memory controller, which corresponds to Figure 3 Examples of Figure 7 As shown, the delay detection circuit 601 detects the delay interval DI_1 between the edges E_1 and E_2 and the delay interval DI_2 between the edges E_1 and E_3. In addition, the delay detection circuit 601 controls the delay interval DI_1 to fall within the first predetermined interval, and controls the delay interval DI_2 to fall within the second predetermined interval. Many methods can be used to change the delay interval. For example, the delay detection circuit 601 can change the number of delay stages used to generate the delayed sampling clock signal DSC_1, or can change the number of delay stages used to generate the delayed sampling clock signal DSC_2 to adjust the delay interval DI_1.

[0038] The first predetermined interval and the second predetermined interval may be the same or different. In this way, the changes in the delay interval DI_1 and the delay interval DI_2 caused by the changes in the delay value provided by the delay stage can be compensated. If the delay value provided by the delay stage is not compensated, the delay intervals D1 and D2 may be too large or too small to affect the judgment of the correction circuit 105. Please also understand that in Figure 6 and Figure 7 The concepts disclosed in the Figure 2 and Figure 3 The embodiments shown can be implemented in any other memory controller provided in the present invention.

[0039] According to the above embodiments, it can be obtained Figure 8 The memory data receiving method shown comprises the following steps:

[0040] Step 801

[0041] A sampling clock signal from a memory is delayed by a first delay value to generate a first delayed sampling clock signal (eg: Figure 2 or Figure 3 DSC_1 in ).

[0042] Step 803

[0043] The sampling clock signal is delayed by a second delay value to generate a second delayed sampling clock signal (eg: Figure 2 DSC_2 or Figure 3 DSC_3 in ).

[0044] Step 805

[0045] A first edge of the sampling clock signal is sampled with a first delay (eg: Figure 2 or Figure 3 E_1 in the example) to sample the data signal to generate a first sample value (for example: Figure 2 or Figure 3 SV_1 in ).

[0046] Step 807

[0047] A second edge of the sampling clock signal is sampled with a second delay (eg: Figure 2 or Figure 3 E_2 in the example is used to sample the data signal to generate a second sample value (for example: Figure 2 or Figure 3 SV_2 in ).

[0048] Step 809

[0049] A sampling delay value is generated based on the first sampling value and the second sampling value and according to the first delay value. If the first delay value is not adjusted, the first delay value itself is used as the sampling delay value.

[0050] Step 811

[0051] An adjusted sampling clock signal is generated by the sampling delay value, and the data signal is sampled by the adjusted sampling clock signal. If the first delay value is not adjusted, the first delayed clock signal itself is used as the adjusted sampling clock signal.

[0052] Other detailed steps of the memory data receiving method provided by the present invention have been described in detail in the aforementioned embodiment, and thus will not be repeated here.

[0053] According to the aforementioned embodiments, memory data may be received using a sampling clock signal having a preferred phase to ensure that the sampled memory data is correct data.

[0054] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller comprising: a delay circuit for receiving a sampling clock signal from a memory, delaying the sampling clock signal using a first delay value to generate a first delayed sampling clock signal, and delaying the sampling clock signal using a second delay value to generate a second delayed sampling clock signal; a sampling circuit for receiving a data signal from the memory, sampling the data signal using a first edge of the first delayed sampling clock signal to generate a first sampled value, and sampling the data signal using a second edge of the second delayed sampling clock signal to generate a second sampled value; and a calibration circuit for generating a sampling delay value based on the first sampling value and the second sampling value and according to the first delay value; The delay circuit generates an adjusted sampling clock signal using the sampling delay value, and the sampling circuit samples the data signal using the adjusted sampling clock signal. wherein the second edge is an edge of all edges of the second delayed sampling clock signal that is closest to the first edge; When the first sampling value and the second sampling value are different, the correction circuit adjusts the first delay value to generate the sampling delay value; When the first sampling value and the second sampling value are the same, the calibration circuit uses the first delay value as the sampling delay value. 2 . The memory controller of claim 1 , wherein the first delay value is greater than the second delay value. 3 . The memory controller of claim 1 , wherein the first delay value is smaller than the second delay value.

4. The memory controller according to claim 1, wherein the delay circuit further uses a third delay value to delay the sampling clock signal to generate a third delayed sampling clock signal, and the sampling circuit samples the data signal with a third edge of the third delayed sampling clock signal to generate a third sampling value; wherein the first delay value is greater than the second delay value and less than the third delay value; The correction circuit generates the sampling delay value based on the first sampling value, the second sampling value, and the third sampling value and according to the first delay value.

5. The memory controller according to claim 4, When the first sampling value is different from the second sampling value or the third sampling value, the correction circuit adjusts the first delay value to generate the sampling delay value; When the first sampling value, the second sampling value and the third sampling value are the same, the calibration circuit uses the first delay value as the sampling delay value.

6. The memory controller according to claim 4, wherein the second edge is an edge of all edges of the second delayed sampling clock signal that is closest to the first edge, and the third edge is an edge of all edges of the third delayed sampling clock signal that is closest to the first edge; The memory controller further comprises a delay detection circuit for making the delay interval between the first edge and the second edge fall within a first predetermined interval, and making the delay interval between the first edge and the third edge fall within a second predetermined interval.

7. The memory controller according to claim 1, wherein the second edge is an edge of all edges of the second delayed sampling clock signal that is closest to the first edge; The memory controller further comprises a delay detection circuit for making the delay interval between the first edge and the second edge fall within a predetermined interval.

8. A memory data receiving method, comprising: Step (a) delaying a sampling clock signal from a memory by a first delay value to generate a first delayed sampling clock signal; Step (b) delaying the sampling clock signal by a second delay value to generate a second delayed sampling clock signal; Step (c) sampling the data signal with a first edge of the first delayed sampling clock signal to generate a first sampled value; Step (d) sampling the data signal with a second edge of the second delayed sampling clock signal to generate a second sampled value; Step (e) generates a sampling delay value based on the first sampling value and the second sampling value and according to the first delay value; and Step (f) generates an adjusted sampling clock signal using the sampling delay value, and samples the data signal using the adjusted sampling clock signal. wherein the second edge is an edge of all edges of the second delayed sampling clock signal that is closest to the first edge; When the first sampling value and the second sampling value are different, the step (e) adjusts the first delay value to generate the sampling delay value; When the first sampling value and the second sampling value are the same, the first delay value is used as the sampling delay value in step (e).

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