Chip package and manufacturing method thereof

Abstract

The present invention provides a chip package and a manufacturing method thereof. The chip package includes a semiconductor substrate, a support member, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad protruding from the inclined sidewall. The support member is positioned on the semiconductor substrate and has a top surface facing away from the semiconductor substrate and an inclined sidewall adjacent to the top surface. The antenna layer is positioned on the top surface of the support member. The redistribution layer is positioned on the inclined sidewall of the support member and contacts the sidewall of the conductive pad and one end of the antenna layer. This achieves miniaturization of the antenna and a chip package containing the antenna.

Description

Technical Field

[0001] The present invention relates to a chip package and a method for manufacturing the chip package. Background Art

[0002] In wireless communication devices, antennas, as the components that transmit and receive radio signals, are crucial components. With the advancement of wireless communication technology, wireless communication devices are being designed to be lightweight and compact. However, antennas typically require an external electrical connection to the chip on the circuit board. Therefore, they still occupy a considerable amount of space within electronic devices (such as mobile phones), hindering miniaturization. Summary of the Invention

[0003] A technical aspect of the present invention is a chip package.

[0004] According to one embodiment of the present invention, a chip package includes a semiconductor substrate, a support member, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad protruding from the inclined sidewall. The support member is positioned on the semiconductor substrate and has a top surface facing away from the semiconductor substrate and an inclined sidewall adjacent to the top surface. The antenna layer is positioned on the top surface of the support member. The redistribution layer is positioned on the inclined sidewall of the support member and contacts the sidewall of the conductive pad and one end of the antenna layer.

[0005] In one embodiment of the present invention, the chip package further includes a shielding layer located between the semiconductor substrate and the support member.

[0006] In one embodiment of the present invention, the support member has a bottom surface opposite to the top surface, and the shielding layer contacts the bottom surface.

[0007] In one embodiment of the present invention, the antenna layer contacts the top surface of the support member.

[0008] In one embodiment of the present invention, the semiconductor substrate has a bottom surface adjacent to the inclined sidewall, and the chip package further includes a planar layer. The planar layer covers the inclined sidewall and bottom surface of the semiconductor substrate and the bottom surface of the conductive pad. The planar layer has a bottom surface and an inclined sidewall adjacent to the bottom surface, and the slope of the inclined sidewall of the planar layer is substantially the same as the slope of the inclined sidewall of the support member.

[0009] In one embodiment of the present invention, the redistribution layer is located on the inclined sidewalls and bottom surface of the planar layer.

[0010] In one embodiment of the present invention, the transmission frequency of the antenna layer is in the range of 20 GHz to 60 GHz, and the semiconductor substrate is a radio frequency device.

[0011] In one embodiment of the present invention, the chip package further includes a protection layer that covers the support component, the antenna layer, and an end of the redistribution layer away from the semiconductor substrate.

[0012] In one embodiment of the present invention, the material of the protective layer includes glass, fused silica, quartz glass, sapphire, or a combination of these materials.

[0013] In one embodiment of the present invention, the protective layer is adhesive.

[0014] In one embodiment of the present invention, a cavity is formed between the support member, the semiconductor substrate and the protective layer, and the support member surrounds the cavity.

[0015] In one embodiment of the present invention, the semiconductor substrate has a top surface. The top surface of the semiconductor substrate is adjacent to the inclined sidewall of the semiconductor substrate. The chip package further includes a shielding layer. The shielding layer is located on the top surface of the semiconductor substrate.

[0016] In one embodiment of the present invention, the chip package further includes a bonding layer located between the support member and the semiconductor substrate.

[0017] A technical aspect of the present invention is a method for manufacturing a chip package.

[0018] According to one embodiment of the present invention, a method for manufacturing a chip package includes forming an antenna layer on the top surface of a support member; joining the support member to the top surface of a semiconductor substrate, wherein the top surface of the semiconductor substrate has a conductive pad; etching the bottom surface of the semiconductor substrate so that the semiconductor substrate has an inclined sidewall, and the conductive pad protrudes from the inclined sidewall; performing a cutting process so that the support member has an inclined sidewall; and forming a redistribution layer on the inclined sidewall of the support member so that the redistribution layer contacts the sidewall of the conductive pad and one end of the antenna layer.

[0019] In one embodiment of the present invention, the forming of the antenna layer includes sputtering a conductive layer on the top surface of the support member; and patterning the conductive layer to form the antenna layer.

[0020] In one embodiment of the present invention, the method for manufacturing the chip package further includes forming a shielding layer on the bottom surface of the support member.

[0021] In one embodiment of the present invention, the forming of the shielding layer includes sputtering a conductive layer on the bottom surface of the support member; and patterning the conductive layer to form the shielding layer.

[0022] In one embodiment of the present invention, the method for manufacturing the chip package further includes forming a planar layer on the inclined sidewalls and bottom surface of the semiconductor substrate and the bottom surface of the conducting pad.

[0023] In one embodiment of the present invention, the cutting process is performed so that the planar layer is simultaneously formed with an inclined sidewall, wherein the slope of the inclined sidewall of the planar layer is substantially the same as the slope of the inclined sidewall of the support member.

[0024] In one embodiment of the present invention, the method for manufacturing the chip package further includes disposing a protection layer on the support member and the antenna layer.

[0025] In the above-described embodiment of the present invention, the chip package includes a support member and an antenna layer located on the top surface of the support member, and the semiconductor substrate has a conductive pad protruding from its inclined sidewall. Therefore, the redistribution layer can be formed on the inclined sidewall of the support member, thereby contacting the sidewall of the conductive pad and one end of the antenna layer. Furthermore, the antenna layer is formed on the top surface of the support member and integrated into the chip package by bonding the support member to the top surface of the semiconductor substrate. This achieves a miniaturized antenna and a chip package incorporating an antenna.

[0026] According to one embodiment of the present invention, a chip package includes a first substrate, an antenna layer, a first passivation layer, and a redistribution layer. The first substrate has a first surface and a second surface facing each other. The antenna layer is located on the first surface of the first substrate. The first passivation layer covers the antenna layer. The redistribution layer is located on the second surface of the first substrate and is electrically connected to the antenna layer. The redistribution layer further includes a shielding section separate from the antenna layer. The shielding section overlaps with the antenna layer.

[0027] In one embodiment of the present invention, the redistribution layer extends to a side surface of the first substrate and a side surface of the first passivation layer.

[0028] In one embodiment of the present invention, the chip package further includes a second substrate. The first passivation layer is located between the first substrate and the second substrate, and the redistribution layer extends to the recessed portion of the second substrate.

[0029] In one embodiment of the present invention, the chip package further includes a metal layer and a second passivation layer. The metal layer is located on a surface of the second substrate facing away from the first passivation layer. The second passivation layer covers the metal layer.

[0030] In one embodiment of the present invention, the second substrate is made of glass, fused silica, or quartz glass.

[0031] In one embodiment of the present invention, the chip package further includes a second passivation layer covering the redistribution layer.

[0032] In one embodiment of the present invention, the chip package further includes an integrated circuit element having a conductive structure located on the redistribution layer.

[0033] In one embodiment of the present invention, the first substrate is made of glass, fused silica, or quartz glass.

[0034] In one embodiment of the present invention, the chip package further includes a conductive channel located in the first substrate, with two ends of the conductive channel contacting the antenna layer and the redistribution layer respectively.

[0035] According to one embodiment of the present invention, a method for manufacturing a chip package includes forming an antenna layer on a first surface of a first substrate, wherein the first substrate has a second surface opposite to the first surface; forming a first passivation layer to cover the antenna layer; and forming a redistribution layer on the second surface of the first substrate, wherein the redistribution layer is electrically connected to the antenna layer. The redistribution layer further includes a shielding section separated from the antenna layer. The shielding section overlaps the antenna layer.

[0036] In one embodiment of the present invention, the method for manufacturing the chip package further includes bonding the second substrate to the first substrate, such that the first passivation layer is located between the first substrate and the second substrate.

[0037] In one embodiment of the present invention, the method for manufacturing the chip package further includes forming a metal layer on a surface of the second substrate facing away from the first passivation layer; and forming a second passivation layer to cover the metal layer.

[0038] In one embodiment of the present invention, the manufacturing method of the chip package further includes removing edge portions of the first substrate and the first passivation layer to form a groove, wherein a side surface of the antenna layer is exposed from the groove, and the groove extends into the second substrate, so that the second substrate has a recess.

[0039] In one embodiment of the present invention, forming a redistribution layer on the second surface of the first substrate further includes forming a redistribution layer on a side surface of the antenna layer and on the concave portion of the second substrate.

[0040] In one embodiment of the present invention, the method for manufacturing the chip package further includes forming a second passivation layer to cover the redistribution layer.

[0041] In one embodiment of the present invention, the method for manufacturing the chip package further includes disposing an integrated circuit element having a conductive structure on the redistribution layer.

[0042] In one embodiment of the present invention, the manufacturing method of the chip package further includes forming a conductive channel in the first substrate, wherein two ends of the conductive channel contact the antenna layer and the redistribution layer respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The aspects of the present invention will be preferably understood from the following embodiments when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0044] Figure 1 A cross-sectional view of a chip package according to one embodiment of the present invention is shown.

[0045] Figures 2 to 9 Draw Figure 1 sectional views of various stages of a chip package manufacturing method.

[0046] Figure 10 Draw Figure 1 FIG. 1 is a top view of a chip package, wherein the protective layer and the bonding layer are omitted.

[0047] Figure 11 Draw Figure 1 A bottom view of a chip package is shown, with the passivation layer omitted.

[0048] Figure 12 FIG. 4 is a cross-sectional view of a chip package according to another embodiment of the present invention.

[0049] Figure 13 FIG. 4 is a cross-sectional view of a chip package according to another embodiment of the present invention.

[0050] Figures 14 to 25 1 and 2 are cross-sectional views of various stages of a method for manufacturing a chip package according to an embodiment of the present invention.

[0051] Figures 26 to 34 1 and 2 are cross-sectional views of various stages of a method for manufacturing a chip package according to an embodiment of the present invention.

[0052] Among them, the brief description of the symbols in the accompanying drawings is as follows:

[0053] 100, 100a, 100b: chip package; 102a, 102b: bonding layer; 110: semiconductor substrate; 111: inclined sidewall; 112: conductive pad; 113: bottom surface; 114: top surface; 115: functional layer; 116: insulating layer; 117: passivation layer; 120, 120a: support member; 121: inclined sidewall; 122: top surface; 123: bottom surface; 130, 130a: antenna layer; 132: one end; 140: redistribution layer; 142: one end; 150, 150a: shielding layer; 160: planar layer; 161: bottom surface; 162: inclined sidewall; 170, 170a: protective layer; 180: passivation layer; 190: conductive structure; 200, 200a: chip package; 210, 210a: first substrate; 211: first surface; 213: second surface; 220, 220a: antenna layer; 230, 230a: passivation layer; 240: second substrate; 242: recess; 250: metal layer; 260: passivation layer; 270, 270a: redistribution layer; 272, 272a: shielding segment; 275: metal surface layer; 280, 280a: passivation layer; 290: integrated circuit element; 292, 294: conductive structure; 295: filling layer; 1-1: line segment; C: cavity; L: line; O: notch; O1, O2: opening; H: perforation; T: groove; V: conductive channel; θ: obtuse angle. DETAILED DESCRIPTION

[0054] The following diagrams illustrate various embodiments of the present invention. For clarity, many practical details are included in the following description. However, it should be understood that these practical details are not intended to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not essential. Furthermore, to simplify the drawings, some commonly used structures and components are depicted in simplified schematic form.

[0055] Figure 1 A cross-sectional view of a chip package 100 according to one embodiment of the present invention is shown. Chip package 100 includes a semiconductor substrate 110, a support member 120, an antenna layer 130, and a redistribution layer 140. The semiconductor substrate 110 has a sloped sidewall 111 and a conductive pad 112, with the conductive pad 112 protruding from the sloped sidewall 121. The support member 120 is located on the semiconductor substrate 110 and has a top surface 122 facing away from the semiconductor substrate 110 and a sloped sidewall 121 adjacent to the top surface 122. The antenna layer 130 is located on the top surface 122 of the support member 120. The redistribution layer 140 is located on the sloped sidewall 121 of the support member 120 and contacts the sidewall of the conductive pad 112 and an end 132 of the antenna layer 130.

[0056] In this embodiment, the chip package 100 can be used for the transmission of high-frequency signals, such as 5G communication. The transmission frequency of the antenna layer 130 can be in the range of 20 GHz to 60 GHz, and the semiconductor substrate 110 can be a radio frequency device. The material of the semiconductor substrate 110 can include silicon and have a functional layer 115. For example, the material of the functional layer 115 can include gallium nitride (GaN). In addition, the top surface 114 of the semiconductor substrate 110 can also be covered with an insulating layer 116 and a passivation layer 117 (Passivation layer) in sequence, but this is not used to limit the present invention. The material of the redistribution layer 140 can include copper, silver or aluminum, and the material of the antenna layer 130 can include copper or silver, both of which can be formed by physical vapor deposition (such as sputtering). Therefore, the antenna layer 130 can directly contact the top surface 122 of the support 120.

[0057] Because the chip package 100 includes the support member 120 and the antenna layer 130 located on the top surface 122 of the support member 120, and the semiconductor substrate 110 has a conductive pad 112 protruding from its inclined sidewall 111, the redistribution layer 140 can be formed on the inclined sidewall 121 of the support member 120, thereby contacting the sidewall of the conductive pad 112 and one end 132 of the antenna layer 130. Furthermore, the antenna layer 130 is formed on the top surface 122 of the support member 120 and integrated into the chip package 100 by bonding the support member 120 to the top surface 114 of the semiconductor substrate 110. This achieves a miniaturized antenna and a chip package 100 containing an antenna.

[0058] In this embodiment, the chip package 100 further includes a shielding layer 150. The shielding layer 150 is located between the semiconductor substrate 110 and the support member 120. The support member 120 has a bottom surface 123 opposite the top surface 122. The shielding layer 150 can be formed on the bottom surface 123 of the support member 120 using a physical vapor deposition method (e.g., sputtering). Therefore, the shielding layer 150 can directly contact the bottom surface 123 of the support member 120. The shielding layer 150 can prevent radio frequency (RF) signals from interfering with the semiconductor substrate 110.

[0059] The semiconductor substrate 110 has a bottom surface 113 adjacent to the inclined sidewall 111 and opposite to the top surface 114. The chip package 100 further includes a planar layer 160. The planar layer 160 covers the inclined sidewall 111 and bottom surface 113 of the semiconductor substrate 110, and also covers the bottom surface of the conductive pad 112. The planar layer 160 has a bottom surface 161 and an inclined sidewall 162 adjacent to the bottom surface 161. The slope of the inclined sidewall 162 of the planar layer 160 is substantially the same as the slope of the inclined sidewall 121 of the support member 120. The redistribution layer 140 is located on the inclined sidewall 162 and bottom surface 161 of the planar layer 160. In other words, the redistribution layer 140 can extend from the inclined sidewall 121 of the support member 120 through the inclined sidewall 162 of the planar layer 160 to the bottom surface 161 of the planar layer 160, thereby forming an obtuse angle θ.

[0060] Furthermore, the chip package 100 may further include a passivation layer 180 and a conductive structure 190. The passivation layer 180 covers the redistribution layer 140 and the planarization layer 160 and may have an opening for disposing the conductive structure 190 on the bottom surface of the redistribution layer 140. The conductive structure 190 may be a solder ball or a conductive pillar, and is not intended to limit the present invention. The conductive structure 190 may be electrically connected to other electronic devices (such as a circuit board).

[0061] In this embodiment, the chip package 100 further includes a protective layer 170. The protective layer 170 covers the support member 120, the antenna layer 130, and an end 142 of the redistribution layer 140 away from the semiconductor substrate 110. The protective layer 170 may be made of glass, fused silica, quartz glass, sapphire, or a combination thereof.

[0062] In addition, the chip package 100 further includes bonding layers 102 a and 102 b. The bonding layer 102 a is located between the support member 120 and the semiconductor substrate 110 , and the bonding layer 102 b is located between the support member 120 and the protective layer 170 .

[0063] It should be understood that the connection relationship, materials, and functions of the components that have been described will not be repeated, and will be described first. In the following description, a method for manufacturing the chip package 100 will be described.

[0064] Figures 2 to 9 Draw Figure 1 The chip package 100 is a cross-sectional view at various stages of the manufacturing method. Figure 2, first, an antenna layer 130 is formed on the top surface 122 of the support member 120. The step of forming the antenna layer 130 may include first forming (for example, by sputtering) a conductive layer on the entire top surface 122 of the support member 120, and then patterning the conductive layer to form the antenna layer 130. The patterning step may include steps such as exposure, development, and etching. In addition, a shielding layer 150 may be formed on the bottom surface 123 of the support member 120. The step of forming the shielding layer 150 may include first forming (for example, by sputtering) a conductive layer on the entire bottom surface 123 of the support member 120, and then patterning the conductive layer to form the shielding layer 150. Through the above steps, a Figure 2 structure.

[0065] See Figure 3 The support member 120 is bonded to the top surface 114 of the semiconductor substrate 110 using the bonding layer 102a, and then the protective layer 170 can be disposed on the support member 120 and the antenna layer 130. For example, the protective layer 170 can be bonded to the top surface 122 of the support member 120 using the bonding layer 102b. In another embodiment, the protective layer 170 can be first bonded to the top surface 122 of the support member 120 using the bonding layer 102b, and then the support member 120 can be bonded to the top surface 114 of the semiconductor substrate 110 using the bonding layer 102a, which is not intended to limit the present invention. Figures 3 to 9 The semiconductor substrate 110 is a wafer that has not been cut into pieces, so as to facilitate manufacturing.

[0066] treat Figure 3 After the structure is completed, the semiconductor substrate 110 can be thinned, for example, by grinding the bottom surface 113 of the semiconductor substrate 110. In this way, Figure 4 structure.

[0067] See Figure 5 Then, the bottom surface 113 of the semiconductor substrate 110 is etched, so that the semiconductor substrate 110 has an inclined sidewall 111 facing the notch O, and the conducting pad 112 protrudes from the inclined sidewall 111 and is exposed from the notch O.

[0068] See Figure 6 ,treat Figure 5 After the structure is formed, a planar layer 160 may be formed on the inclined sidewalls 111 and the bottom surface 113 of the semiconductor substrate 110 and the bottom surface of the conducting pad 112 .

[0069] See Figure 7, then, a cutting process can be performed to make the support member 120 have an inclined sidewall 121. This cutting process can be performed by cutting with a tool. When the cutting process is performed, the planar layer 160 can simultaneously form an inclined sidewall 162. Since a single tool can be used to perform this cutting step, the slope of the inclined sidewall 162 of the planar layer 160 can be roughly the same as the slope of the inclined sidewall 121 of the support member 120. The sidewall of the conductive pad 112 of the semiconductor substrate 110 will also have a slope similar to the inclined sidewalls 121 and 162. Such a design is convenient for the subsequent redistribution layer 140 (see Figure 8 In addition, one end 132 of the antenna layer 130 will also be exposed during this cutting process.

[0070] See Figure 8 ,treat Figure 7 After the structure is formed, a redistribution layer 140 can be formed on the inclined side wall 121 of the support member 120, on the side wall of the conductive pad 112, on the inclined side wall 162 of the flat layer 160 and on the bottom surface 161 of the flat layer 160, so that the redistribution layer 140 contacts the side wall of the conductive pad 112 and one end 132 of the antenna layer 130, thereby realizing electrical connection between the semiconductor substrate 110 and the antenna layer 130.

[0071] See Figure 9 In the subsequent process, a passivation layer 180 may be formed to cover the redistribution layer 140 and the planar layer 160. Next, the passivation layer 180 may be patterned so that an opening is formed in the passivation layer 180 on the bottom surface 161 of the planar layer 160 to expose the redistribution layer 140. Next, a conductive structure 190 may be provided on the redistribution layer 140 in the opening. The conductive structure 190 may be used to electrically connect to other electronic devices (such as a circuit board). Afterwards, a cutting step may be performed along the line L to obtain Figure 1 Chip package 100.

[0072] Figure 10 Draw Figure 1 FIG. 1 is a top view of the chip package 100 , in which the protection layer 170 and the bonding layer 102 b are omitted. Figure 11 Draw Figure 1 FIG. 1 is a bottom view of the chip package 100 , in which the passivation layer 180 is omitted. Figure 1 Can be regarded as Figure 10 and Figure 11 Section along line 1-1. See also Figure 10 and Figure 11 , one end 132 of the antenna layer 130 is electrically connected to different redistribution layers 140 with the shielding layer 150, for example, one end 132 of the antenna layer 130 contacts Figure 10 The redistribution layer 140 on the left side and the shielding layer 150 contact Figure 10The redistribution layers 140 on the upper and lower sides. This configuration can utilize different redistribution layers 140 and the conductive structures 190 thereunder to operate the antenna layer 130 and the shielding layer 150. In addition, Figure 10 The pattern of the antenna layer 130 is for illustration only and is not intended to limit the present invention.

[0073] Figure 12 FIG. 1 is a cross-sectional view of a chip package 100a according to another embodiment of the present invention. The chip package 100a includes a semiconductor substrate 110, a support member 120, an antenna layer 130, a redistribution layer 140, and a protective layer 170a. Figure 1 The difference between the embodiments is that the protective layer 170a is adhesive, which can replace Figure 1 The protective layer 170 and the bonding layer 102b are formed to save materials and manufacturing costs.

[0074] Figure 13 FIG. 1 is a cross-sectional view of a chip package 100b according to another embodiment of the present invention. The chip package 100a includes a semiconductor substrate 110, a support member 120a, an antenna layer 130a, a redistribution layer 140, a shielding layer 150a, and a protective layer 170a. Figure 1 The difference between the embodiments is that a cavity C is formed between the support member 120a, the semiconductor substrate 110, and the protective layer 170a, and the support member 120a surrounds this cavity C. Furthermore, a portion of the antenna layer 130a faces the cavity C, while another portion faces the support member 120a. In this embodiment, the shielding layer 150a is located on the top surface 114 of the semiconductor substrate 110, so the cavity C is located between the shielding layer 150a and the antenna layer 130a.

[0075] Figures 14 to 25 A chip package 200 according to an embodiment of the present invention is shown (see FIG. Figure 25 ) manufacturing method at various stages of the cross-section. See also Figure 14 and Figure 15 The antenna layer 220 can be formed on the entire first surface 211 of the first substrate 210 by deposition and patterning. Figure 15 The antenna layer 220 is formed of copper. In this embodiment, the material of the antenna layer 220 may be copper, but is not limited thereto. The first substrate 210 may be made of glass, fused silica, or quartz glass, and may not have circuits or conductive contacts therein.

[0076] See Figure 16After the antenna layer 220 is formed, a passivation layer 230 can be formed to cover the antenna layer 230. During this step, the second substrate 240 can be bonded to the first substrate 210, with the passivation layer 230 positioned between the first and second substrates 210 and 240. The second substrate 240 can be made of the same material as the first substrate 210, such as glass, fused silica, or quartz glass. Furthermore, the passivation layer 230 can be formed on either the first or second substrate 210 before performing the bonding step, and this is not intended to limit the present invention.

[0077] See also Figure 17 and Figure 18 After the second substrate 240 is bonded to the first substrate 210, a metal layer 250 may be formed on the entire surface of the second substrate 240 facing away from the passivation layer 230, for example, by deposition. Figure 18 The metal layer 250 may be made of copper, but is not limited thereto. The provision of the metal layer 250 is optional. In some embodiments, the chip package may not have the metal layer 250.

[0078] See Figure 19 After the metal layer 250 is patterned, another passivation layer 260 may be formed to cover the metal layer 250 . The first substrate 210 has a second surface 213 facing away from the first surface 211 .

[0079] See also Figure 20 and Figure 21 , then, you can Figure 19 The structure is flipped 180 degrees, and the second surface 213 of the first substrate 210 is ground to thin the first substrate 210. After the first substrate 210 is thinned, the edges of the first substrate 210 and the passivation layer 230 are removed using a cutting tool to form a trench T. In this embodiment, the side of the antenna layer 220 is exposed through the trench T, and the trench T extends into the second substrate 240, forming a recessed portion 242 in the second substrate 240.

[0080] See Figure 22 Next, a redistribution layer 270 is formed on the second surface 213 of the first substrate 210, on the side surface of the antenna layer 220, and on the recess 242 of the second substrate 240. In this way, the redistribution layer 270 can be electrically connected to the antenna layer 220. In this embodiment, the redistribution layer 270 can be formed by sputtering and its material can be copper, but is not limited to this. The redistribution layer 270 can be patterned to have a shielding section 272 separated from the antenna layer 220. The shielding section 272 overlaps with the antenna layer 220 to provide a shielding effect.

[0081] See also Figure 23 and Figure 24After the redistribution layer 270 is formed, another passivation layer 280 may be formed to cover the redistribution layer 270. The passivation layer 280 surrounds the redistribution layer 270. The passivation layer 280 may be patterned to form an opening O1. A metal finish 275 may then be optionally formed on the redistribution layer 270 in the opening O1. In some embodiments, the metal finish 275 may be omitted.

[0082] Next see Figure 25 , a conductive structure 294 can be set on the passivation layer 280, and an integrated circuit element 290 with a conductive structure 292 can be set on the redistribution layer 270 in the opening O1. The integrated circuit element 290 can be electrically connected to the antenna layer 220 through the conductive structure 292 and the redistribution layer 270, and can also be electrically connected to the shielding section 272 of the redistribution layer 270 through the conductive structure 292. In addition, a filling layer 295 (under fill) can be set between the integrated circuit element 290 and the passivation layer 280 to provide insulation and protection functions. Through the above steps, a Figure 25 In one embodiment, the chip package 200 may omit the filling layer 295. In another embodiment, the chip package 200 may further omit the integrated circuit device 290.

[0083] In this embodiment, the redistribution layer 270 of the chip package 200 extends from the second surface 213 of the first substrate 210 to the side surfaces of the first substrate 210, the side surfaces of the first passivation layer 230, and the recess 242 of the second substrate 240. The chip package 200 can provide improved performance for millimeter-wave (mm-wave) devices, such as shorter transmission lines, integrated integrated circuit components 290 and antenna layers 220, and the ability to use a preferred substrate material (e.g., quartz glass) instead of a printed circuit board (PCB).

[0084] In another embodiment, Figure 16 The antenna layer 220 can be formed on the surface of the second substrate 240 facing the first passivation layer 230 rather than the first surface 211 of the first substrate 210. Figures 17 to 25 After the steps, Figure 25 The antenna layer 220 is located on the second substrate 240 .

[0085] The connection relationship, materials and functions of the components already described will not be repeated, but will be described first. In the following description, a method for manufacturing another type of chip package will be described.

[0086] Figures 26 to 34 A chip package 200a according to an embodiment of the present invention is shown (see FIG. Figure 34 ) is a cross-sectional view of the manufacturing method at various stages. Figure 26, a through hole H is formed in the first substrate 210a. The through hole H can be formed by drilling. Figure 27 Then, the first substrate 210a may be subjected to a metallization process to form an antenna layer 220a on the entire first surface 211 of the first substrate 210a, a conductive channel V in the first substrate 210a, and a redistribution layer 270a on the entire second surface 213 of the first substrate 210a. In this way, Figure 27 In this embodiment, the antenna layer 220a, the conductive channel V, and the redistribution layer 270a can be integrally formed and made of the same material (e.g., copper), but this is not intended to limit the present invention. The first substrate 210a can be made of glass, fused silica, or quartz glass, and may not have internal circuits or conductive contacts.

[0087] See also Figure 28 and Figure 29 After the aforementioned metallization process, the antenna layer 220a covering the entire first surface 211 of the first substrate 210a can be patterned to obtain Figure 28 The antenna layer 220a is formed, and then a passivation layer 230a may be formed to cover the antenna layer 220a.

[0088] See also Figure 30 and Figure 31 , then, you can Figure 29 The structure is flipped 180 degrees. The redistribution layer 270 can be patterned to include a shielding section 272a separated from the conductive path V. Shielding section 272a overlaps with antenna layer 220a, providing a shielding effect. After patterning the redistribution layer 270, another passivation layer 280a can be formed to cover the redistribution layer 270a. Passivation layer 280 can also be patterned to form openings O2.

[0089] See also Figure 32 and Figure 33 Then, a metal finish 275 may be selectively formed on the redistribution layer 270a in the opening O2. In some embodiments, the metal finish 275 may be omitted. After the metal finish 275 is formed, a conductive structure 294 may be disposed on the passivation layer 280a.

[0090] See Figure 34After the conductive structure 294 is set, the integrated circuit element 290 with the conductive structure 292 can be set on the redistribution layer 270a in the opening O2. The integrated circuit element 290 can be electrically connected to the antenna layer 220 through the conductive structure 292, the redistribution layer 270a and the conductive channel V, and can also be electrically connected to the shielding section 272a of the redistribution layer 270a through the conductive structure 292. The two ends of the conductive channel V can contact the antenna layer 220a and the redistribution layer 270a respectively. In addition, a filling layer 295 (Under fill) can be set between the integrated circuit element 290 and the passivation layer 280 to provide insulation and protection functions. Through the above steps, a Figure 34 In one embodiment, the chip package 200a may omit the filling layer 295. In another embodiment, the chip package 200a may further omit the integrated circuit device 290.

[0091] In this embodiment, the redistribution layer 270a of the chip package 200a is electrically connected to the antenna layer 220a on the first surface 211 of the first substrate 210 via the conductive vias V in the first substrate 210. The chip package 200a can provide improved performance for millimeter-wave (mm-wave) devices, such as shorter transmission lines, integrated integrated circuit device 290 and antenna layer 220a, and the ability to use a preferred substrate material (e.g., quartz glass) instead of a printed circuit board (PCB).

[0092] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Anyone familiar with this technology can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of this application.

Claims

1. A chip package, characterized in that: Include: A semiconductor substrate having an inclined sidewall, a bottom surface adjacent to the inclined sidewall, and a conductive pad protruding from the inclined sidewall; a planar layer covering the inclined sidewall and the bottom surface of the semiconductor substrate and the bottom surface of the conducting pad, the planar layer having adjacent bottom surface and inclined sidewall; a support member located on the semiconductor substrate and having a top surface facing away from the semiconductor substrate and an inclined sidewall adjacent to the top surface, wherein the slope of the inclined sidewall of the planar layer is the same as the slope of the inclined sidewall of the support member; an antenna layer, located on the top surface of the support member; as well as The redistribution layer is located on the inclined sidewall of the support component and contacts the sidewall of the conductive pad and one end of the antenna layer.

2. The chip package according to claim 1, wherein: Also includes: The shielding layer is located between the semiconductor substrate and the support member.

3. The chip package according to claim 2, wherein: The supporting component has a bottom surface opposite to the top surface, and the shielding layer contacts the bottom surface.

4. The chip package according to claim 1, wherein: The antenna layer contacts the top surface of the support member.

5. The chip package according to claim 1, wherein: The redistribution layer is located on the inclined sidewall and the bottom surface of the planar layer.

6. The chip package according to claim 1, wherein: The transmission frequency of the antenna layer is in the range of 20 GHz to 60 GHz, and the semiconductor substrate is a radio frequency device.

7. The chip package according to claim 1, wherein: Also includes: The protective layer covers the support component, the antenna layer and an end of the redistribution layer away from the semiconductor substrate.

8. The chip package according to claim 7, wherein: The protective layer is made of glass, sapphire or a combination of these materials.

9. The chip package according to claim 7, wherein: The protective layer is adhesive.

10. The chip package according to claim 7, wherein: A cavity is formed between the support member, the semiconductor substrate and the protection layer, and the support member surrounds the cavity.

11. The chip package according to claim 1, wherein The semiconductor substrate has a top surface, the top surface of the semiconductor substrate is adjacent to the inclined sidewall of the semiconductor substrate, and the chip package further includes: The shielding layer is located on the top surface of the semiconductor substrate.

12. The chip package according to claim 1, wherein Also includes: The bonding layer is located between the support component and the semiconductor substrate.

13. A method for manufacturing a chip package, characterized in that: Include: forming an antenna layer on the top surface of the support member; bonding the support member to a top surface of a semiconductor substrate, wherein the top surface of the semiconductor substrate has a conductive pad; Etching the bottom surface of the semiconductor substrate so that the semiconductor substrate has an inclined sidewall adjacent to the bottom surface, and the conducting pad protrudes from the inclined sidewall; forming a planar layer to cover the inclined sidewall and the bottom surface of the semiconductor substrate and the bottom surface of the conducting pad; Performing a cutting process so that the support member has an inclined sidewall, and the planar layer simultaneously forms an inclined sidewall, wherein the slope of the inclined sidewall of the planar layer is the same as the slope of the inclined sidewall of the support member; as well as A redistribution layer is formed on the inclined sidewall of the support component, so that the redistribution layer contacts the sidewall of the conductive pad and one end of the antenna layer.

14. The method for manufacturing a chip package according to claim 13, wherein: Forming the antenna layer includes: sputtering a conductive layer on the top surface of the support member; and The conductive layer is patterned to form the antenna layer.

15. The method for manufacturing a chip package according to claim 13, wherein: Also includes: A shielding layer is formed on the bottom surface of the support component.

16. The method for manufacturing a chip package according to claim 15, wherein: Forming the shielding layer includes: sputtering a conductive layer on the bottom surface of the support member; and The conductive layer is patterned to form the shielding layer.

17. The method for manufacturing a chip package according to claim 13, wherein: Also includes: A protection layer is disposed on the support component and the antenna layer.

18. A chip package, characterized in that: Include: A first substrate having a first surface and a second surface opposite to each other; an antenna layer, located on the first surface of the first substrate; a first passivation layer, covering the antenna layer; a redistribution layer located on the second surface of the first substrate and electrically connected to the antenna layer, wherein the redistribution layer further comprises a shielding section separated from the antenna layer, and the shielding section overlaps with the antenna layer; as well as The second substrate, wherein the first passivation layer is located between the first substrate and the second substrate, and the redistribution layer extends to the concave portion of the second substrate.

19. The chip package according to claim 18, wherein The redistribution layer extends to a side surface of the first substrate and a side surface of the first passivation layer.

20. The chip package according to claim 18, wherein Also includes: a metal layer located on a surface of the second substrate facing away from the first passivation layer; and A second passivation layer covers the metal layer.

21. The chip package according to claim 18, wherein The second substrate is made of glass.

22. The chip package according to claim 18, wherein Also includes: A second passivation layer covers the redistribution layer.

23. The chip package according to claim 22, wherein: Also includes: The integrated circuit element has a conductive structure, and the conductive structure is located on the redistribution layer.

24. The chip package according to claim 18, wherein The first substrate is made of glass.

25. The chip package according to claim 18, wherein Also includes: The conductive channel is located in the first substrate, and two ends of the conductive channel are respectively in contact with the antenna layer and the redistribution layer.

26. A method for manufacturing a chip package, characterized in that: Include: forming an antenna layer on a first surface of a first substrate, wherein the first substrate has a second surface facing away from the first surface; forming a first passivation layer to cover the antenna layer; bonding a second substrate to the first substrate so that the first passivation layer is located between the first substrate and the second substrate; as well as A redistribution layer is formed on the second surface of the first substrate, wherein the redistribution layer is electrically connected to the antenna layer and has a shielding section separated from the antenna layer, and the shielding section overlaps the antenna layer.

27. The method for manufacturing a chip package according to claim 26, wherein: Also includes: forming a metal layer on a surface of the second substrate facing away from the first passivation layer; and A second passivation layer is formed to cover the metal layer.

28. The method for manufacturing a chip package according to claim 26, wherein: Also includes: The edge portions of the first substrate and the first passivation layer are removed to form a groove, wherein the side surface of the antenna layer is exposed from the groove, and the groove extends into the second substrate so that the second substrate has a concave portion.

29. The method for manufacturing a chip package according to claim 28, wherein: Forming the redistribution layer on the second surface of the first substrate further comprises: The redistribution layer is formed on the side surface of the antenna layer and the concave portion of the second substrate.

30. The method for manufacturing a chip package according to claim 26, wherein: Also includes: A second passivation layer is formed to cover the redistribution layer.

31. The method for manufacturing a chip package according to claim 26, wherein: Also includes: An integrated circuit element with a conductive structure is arranged on the redistribution layer.

32. The method for manufacturing a chip package according to claim 26, wherein: Also includes: A conductive channel is formed in the first substrate, wherein two ends of the conductive channel contact the antenna layer and the redistribution layer respectively.

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