Semiconductor device and method of forming the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same. The method for forming the semiconductor device includes providing a substrate having scribe lines, forming a sensing pixel array in the substrate, forming a plurality of light-transmitting columns on the substrate, and forming a light-shielding layer on the substrate and the light-transmitting columns. The sensing pixel array includes a plurality of sensing pixels, and the light-transmitting columns are correspondingly disposed above the sensing pixels of the sensing pixel array. This method further includes performing a first cutting process to form an opening directly above the scribe line, and leaving a remaining material covering the scribe line, and performing an etching process to remove this remaining material to extend the opening until the scribe line is exposed. The present invention can reduce the risk of causing microcracks between material layers during the wafer dicing process or peeling due to poor adhesion between the substrate and other structures, so as to eliminate the delamination problem occurring at the corners or edges of the die during subsequent reliability tests, thereby further improving the reliability of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to a semiconductor device and a method for forming the same. Background Art

[0002] Today's mobile electronic devices (such as mobile phones, tablet computers, laptops, etc.) are usually equipped with a user identification system to protect personal data security. Since everyone's fingerprint is different, the fingerprint sensor is a common and reliable user identification system.

[0003] Fingerprint sensors on the market often use optical technology to sense the user's fingerprint. The optical elements of such fingerprint sensors based on optical technology may include a light collimator, a beam splitter, a focusing lens, and a linear sensor, etc. The collimator is used to make the light incident on the sensor travel in parallel to reduce the energy loss caused by light divergence.

[0004] However, although existing optical fingerprint sensors generally meet their intended purpose, they are not completely satisfactory in all aspects and still need further improvement to enhance product yield and reliability. Summary of the invention

[0005] An embodiment of the present invention provides a method for forming a semiconductor device. The method includes providing a substrate having a cutting path, forming a sensing pixel array in the substrate, forming a plurality of light-transmitting columns on the substrate, and forming a light-shielding layer on the substrate and the light-transmitting columns. The sensing pixel array includes a plurality of sensing pixels, and the light-transmitting columns are correspondingly arranged on the sensing pixels of the sensing pixel array. The method further includes performing a first cutting process to form an opening directly above the cutting path, leaving a residual material covering the cutting path, and performing an etching process to remove the residual material to extend the opening until the cutting path is exposed.

[0006] An embodiment of the present invention provides a semiconductor device. The device includes a sensing pixel array located in a substrate, wherein the sensing pixel array includes a plurality of sensing pixels, a plurality of light-transmitting columns located on the substrate and correspondingly arranged on the sensing pixels of the sensing pixel array, and a light-shielding layer located on the substrate and filled between the light-transmitting columns. The sidewall of the light-shielding layer and the edge of the substrate together form a stepped profile.

[0007] The present invention can reduce the risk of micro-cracks between material layers or peeling caused by poor adhesion between the substrate and other structures during the wafer cutting process, thereby eliminating the delamination problem occurring at the corners or edges of the die during the subsequent reliability test, thereby further improving the reliability of the semiconductor device.

[0008] The following embodiments and the accompanying reference drawings will provide a detailed description. Brief Description of the Drawings

[0009] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention.

[0010] Figures 1A - 1F is a cross-sectional schematic diagram showing various intermediate stages of an exemplary method for forming a Figure 1F semiconductor device according to some embodiments.

[0011] Figures 2A - 2F is a cross-sectional schematic diagram showing various intermediate stages of an exemplary method for forming a Figure 2F semiconductor device according to some other embodiments.

[0012] Figures 3A - 3C is a cross-sectional schematic diagram showing various intermediate stages of an exemplary method for forming a Figure 3C semiconductor device according to still some other embodiments.

[0013] Reference Numerals in the Drawings

[0014] 10, 20, 30 ~ Semiconductor Devices

[0015] 100, 100' ~ Substrates

[0016] 100E ~ Edges

[0017] 102 ~ Scribing Lanes

[0018] 200 ~ Sensing Pixel Arrays

[0019] 202 ~ Sensing Pixels

[0020] 300 ~ Light Transmitting Columns

[0021] 400 ~ Light Shielding Layers

[0022] 400A, 400B ~ Sidewalls

[0023] 402, 402' ~ Openings

[0024] 600 ~ Light Collimating Layers

[0025] W1, W2, W3 ~ Widths

[0026] T1 ~ Thickness Detailed Description of the Embodiments

[0027] The following disclosure provides many different embodiments or examples to illustrate different components of the embodiments of the present invention. Specific examples of the components of this specification and their arrangements will be disclosed below to simplify the description of this disclosure. Of course, these specific examples are not used to limit this disclosure. For example, if the following description of the invention in this specification states that a first component is formed on or above a second component, it means that it includes embodiments in which the formed first and second components are in direct contact, and also includes embodiments in which additional components can be formed between the above-mentioned first and second components, so that the first and second components are not in direct contact. In addition, various examples in this disclosure description may use repeated reference symbols and / or words. The purpose of these repeated symbols or words is to simplify and clarify, and not to limit the relationship between various embodiments and / or the described configurations.

[0028] Furthermore, for the convenience of describing the relationship between an element or component in a figure and another element or component(s), spatial relative terms may be used, such as "under", "below", "lower part", "above", "upper part" and the like. In addition to the orientations shown in the figures, spatial relative terms also cover different orientations of the device during use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatial relative adjectives used therein will also be interpreted according to the turned orientation. It should be understood that additional operations may be provided before, during, and / or after the methods described in the embodiments of the present invention, and in other embodiments of the methods, some of the described operations may be replaced or omitted.

[0029] Here, the terms "about", "approximately", "substantially" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meanings of "about", "approximately", "substantially" can still be implied even without specific mention of "about", "approximately", "substantially".

[0030] Some variations of the example methods and structures are described herein. Those skilled in the relevant art will readily understand that other modifications can be made within the scope of other embodiments. Although some of the method embodiments discussed are in a specific order, various other method embodiments can be in another logical order and can include fewer or more steps than those discussed herein. In some figures, the reference symbols of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting these figures.

[0031] Embodiments of the present invention provide a semiconductor device and a method of forming the same, which are particularly applicable to an optical sensor including an optical collimation layer. In some embodiments of the present invention, before dicing a wafer into dies, other materials covering the dicing streets are removed by using a dicing process in combination with an etching process to reduce defects caused during the wafer dicing process. In this way, the delamination problem occurring at the corners or edges of the dies during subsequent reliability tests can be eliminated.

[0032] Figures 1A - 1F In accordance with some embodiments, there are shown cross-sectional schematic views of various intermediate stages of an example method for forming Figure 1F a semiconductor device 10.

[0033] Figure 1A The starting steps of a method of forming a semiconductor device 10 are shown in accordance with an embodiment of the present invention. As Figure 1A shown, a substrate 100 is provided, which has dicing streets 102. In one embodiment, the substrate 100 may be a silicon substrate, a silicon germanium (SiGe) substrate, a compound semiconductor substrate, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, which may be doped (e.g., using a p-type or n-type dopant) or undoped. Generally, a semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on an insulator. For example, this insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or a similar layer. The above insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate may include an elemental semiconductor containing silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination of the above.

[0034] In some embodiments, the substrate 100 may include various isolation components (not shown) for defining active regions and electrically isolating the active region components in / on the substrate 100. In some embodiments, the isolation components include shallow trench isolation (STI) components, local oxidation of silicon (LOCOS) components, other suitable isolation components, or a combination of the above.

[0035] In some embodiments, the substrate 100 may include various device elements. These device elements are not shown for simplicity and clarity. These device elements may include transistors, diodes, other suitable elements, or a combination of the above. For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), and so on.

[0036] In some embodiments, the above-mentioned substrate 100 may include various conductive elements (e.g., wires or via holes) (not shown). For example, the above-mentioned conductive elements may be formed of aluminum, copper, tungsten, other suitable conductive materials, alloys of the above, or a combination of the above.

[0037] As Figure 1A shown, the dicing street 102 is drawn in dashed lines. In subsequent processes, the wafer will be diced along the dicing street 102 into individual dies. In some embodiments, the width W1 of the dicing street 102 may range from about 25 micrometers (μm) to about 500 micrometers. In some embodiments, the width W1 of the dicing street 102 may range from about 50 micrometers to about 150 micrometers, such as about 80 micrometers.

[0038] Next, as Figure 1AAs shown, in some embodiments, a sensing pixel array 200 is formed in a substrate 100, and the sensing pixel array 200 has a plurality of sensing pixels 202. The sensing pixels 202 can be connected to signal processing circuitry (not shown). In some embodiments, the number of sensing pixels 202 included in the sensing pixel array 200 depends on the area of the optical sensing region. Each sensing pixel 202 can include one or more photodetectors. In some embodiments, the photodetector can include a photodiode, where the photodiode can include a three-layer structure of a P-type semiconductor layer, an intrinsic layer, and an N-type semiconductor layer of a photoelectric material. The intrinsic layer absorbs light to generate excitons, and the excitons are separated into electrons and holes at the junction of the P-type semiconductor layer and the N-type semiconductor layer, thereby generating a current signal. In other embodiments, the photodetector can also include a charged coupling device (CCD) sensor, a complimentary metal-oxide-semiconductor (CMOS) image sensor, an active sensor, a passive sensor, other suitable sensors, or a combination of the above. In some embodiments, the sensing pixel 202 can convert the received optical signal into an electrical signal through the photodetector and process the electrical signal through the signal processing circuitry. It should be noted that in Figure 1A The number and arrangement of the illustrated sensing pixel arrays 200 are merely exemplary, and the embodiments of the present invention are not limited thereto. The sensing pixels 202 can be an array of any number of rows and columns or other arrangements.

[0039] Continuing to refer to Figure 1A , a plurality of light-transmitting columns 300 are formed on the sensing pixel array 200 and corresponding to the sensing pixels 202. In some embodiments, a light-transmitting material layer (not shown) can be formed blanketly on the substrate 100 to cover the sensing pixel array 200. In some embodiments, the light-transmitting material layer can include a light-transmitting material, and its light transmittance for light in the wavelength range of 300 nanometers to 1200 nanometers is greater than about 90%, thereby allowing part of the incident light to pass through the light-transmitting material layer and reach the sensing pixel 202.

[0040] In some embodiments, the above light-transmissive material layer may include a UV-curable material, a thermosetting material, or a combination of the above. For example, the light-transmissive material may include, for example, poly(methyl methacrylate) (PMMA), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), perfluorocyclobutyl (PFCB) polymer, polyimide (PI), acrylic resin, epoxy resins, polypropylene (PP), polyethylene (PE), polystyrene (PS), polyvinyl chloride (PVC), other suitable materials, or a combination of the above. The spin-coating method, casting, bar coating, blade coating, roller coating, wire bar coating, dip coating, chemical vapor deposition (CVD), other suitable methods, or a combination of the above can be used to deposit the above light-transmissive material layer on the substrate 100. In some embodiments, the thickness of the light-transmissive material layer formed by the above method ranges from about 10 to about 300 microns, for example, it can be 100 microns. In other embodiments, the thickness of the light-transmissive material layer ranges from about 100 to about 500 microns, for example, it can be 300 microns.

[0041] Next, the light-transmissive material layer formed on the substrate 100 is selectively removed to form the light-transmissive pillar 300, as Figure 1A shown. In some embodiments, since the above light-transmissive pillar 300 is correspondingly disposed above the sensing pixel 202, the light-transmissive pillar 300 correspondingly disposed above the sensing pixel 202 can protect the sensing pixel 202 and reduce or avoid the contamination and / or damage of the sensing pixel 202 during the process, thereby affecting the sensitivity of the semiconductor device 10. In some embodiments, each light-transmissive pillar 300 is correspondingly disposed above each sensing pixel 202, as Figure 1AAs shown. In other embodiments, at least one light-transmitting pillar 300 covers more than two sensing pixels 202 (not shown). In some embodiments, in a top view, the light-transmitting pillar 300 can be circular, rectangular, polygonal, of any shape, or a combination of the foregoing, and arranged in an array (not shown).

[0042] In some embodiments, a patterning process can be used to selectively remove the light-transmitting material layer to form the light-transmitting pillar 300. In some embodiments where the light-transmitting material layer is a non-photoresist material, the patterning process can include a photolithography process and an etching process. The photolithography process can include, for example, photoresist coating (such as spin coating), soft baking, exposure to a pattern, post-exposure baking, photoresist development, cleaning, and drying (such as hard baking), other suitable processes, or a combination of the foregoing. The etching process can include, for example, a wet etching process, a dry etching process (such as reactive ion etching (RIE), plasma etching, ion milling), other suitable processes, or a combination of the foregoing.

[0043] In other embodiments, the light-transmitting material layer can be a photoresist material. In this case, the light-transmitting material layer can be patterned by a photolithography process to directly form the patterned light-transmitting pillar 300 without the need for an additional etching process. The photolithography process is similar to the photolithography process mentioned above and will not be elaborated here.

[0044] In some embodiments, the thickness of the light-transmitting pillar 300 formed by the above method is in the range of about 5 to about 500 microns, for example, it can be 100 microns. In other embodiments, the thickness of the light-transmitting pillar 300 can be, for example, 60 microns. In some embodiments, the top surfaces of the light-transmitting pillars 300 are substantially aligned with each other. In some embodiments, the aspect ratio of the light-transmitting pillar 300 is in the range of about 2 to about 30, for example, it can be about 5, about 10, about 15, or about 20. If the light-transmitting pillar 300 is too high (i.e., the aspect ratio is too large), the light-transmitting pillar 300 is prone to deformation or collapse, resulting in increased process difficulty and relatively increased process cost. If the light-transmitting pillar 300 is too wide (i.e., the aspect ratio is too small), it is likely to receive unnecessary incident light, making it difficult to achieve a collimation effect, thus reducing the sensitivity of the semiconductor device 10.

[0045] Please refer to Figure 1B, a light-shielding layer 400 is formed on the substrate 100 and filled between the plurality of light-transmitting pillars 300 described above. In some embodiments, the material of the light-shielding layer 400 has a light transmittance of less than about 1% for light in the wavelength range of 300 nanometers to 1200 nanometers, so that light can accurately reach the corresponding sensing pixels 202 of the light-transmitting pillars 300. In subsequent processes, the combination of the light-transmitting pillars 300 disposed on the sensing pixels 202 and the light-shielding layer 400 filled between the light-transmitting pillars 300 together constitutes a light collimation layer 600 (to be described in detail later).

[0046] In some embodiments, the light-shielding layer 400 may include photoresist (such as black photoresist or other suitable non-transparent photoresist), ink (such as black ink or other suitable non-transparent ink), molding compound (such as black molding compound or other suitable non-transparent molding compound), solder mask (such as black solder mask or other suitable non-transparent solder mask), other suitable materials, or a combination of the above.

[0047] In some embodiments, the light-shielding layer 400 may be a light-curable material, a heat-curable material, or a combination of the above. In the above embodiments, a light-shielding material (not shown) may be coated or dispensed on the substrate 100 to completely cover the light-transmitting pillars 300 and fill between the plurality of light-transmitting pillars 300, and then a curing process is performed to cure the above light-shielding material to form the light-shielding layer 400. For example, the above curing process may be a light-curing process, a heat-curing process, or a combination of the above.

[0048] Figure 1C The formation of the opening 402 is illustrated. In some embodiments, a cutting process is performed on the light-shielding layer 400 to remove the main part of the light-shielding layer 400 directly above the cutting channel 102 to form an opening 402 directly above the cutting channel 102, and the remaining part of the light-shielding layer 400 covering the cutting channel 102 is left. The remaining part of the light-shielding layer 400 can protect the substrate 100 during the cutting process and prevent the substrate 100 from being damaged.

[0049] The formation of the opening 402 causes the light-shielding layer 400 to have sidewalls 400A. In some embodiments, the bottom of the opening 402 has a width W2, and the width W2 may be in the range of about 25 micrometers to about 600 micrometers. In some embodiments, the width W2 of the opening 402 may be in the range of about 20 micrometers to about 500 micrometers, such as about 80 micrometers. In some embodiments, the width W2 of the opening 402 is greater than the width W1 of the cutting channel 102.

[0050] Although in Figure 1CIn [the figure], the opening 402 has a generally vertical sidewall and a generally flat bottom surface, but the present invention is not limited thereto. For example, the opening 402 may have an inclined sidewall, a concave bottom surface, or other shapes. In some embodiments, the above cutting process may include laser cutting, ion beam cutting, wire saw, die saw, other suitable cutting techniques, or a combination of the above.

[0051] Next, as Figure 1D shown, an etching process is performed on the remaining portion of the light-shielding layer 400 directly above the cutting channel 102 through the opening 402 to extend the opening 402 until the cutting channel 102 is exposed, and an opening 402' is formed. The etching process can completely remove the remaining portion of the light-shielding layer 400 located directly above the cutting channel, while substantially not damaging the surface of the substrate 100.

[0052] Since there is no other structure (such as the light-shielding layer 400) covering above the cutting channel 102, in the cutting process of cutting the wafer along the cutting channel 102 into independent die, only the substrate 100 can be cut without touching other structures, thereby reducing the risk of causing micro-cracks between material layers during the cutting process or peeling due to poor adhesion between the substrate 100 and other structures. In this way, the delamination problem occurring at the corners or edges of the die during subsequent reliability tests can be eliminated.

[0053] In some embodiments, the formation of the opening 402' causes the sidewall 400A of the light-shielding layer 400 to extend from the substrate 100. In some embodiments, the bottom of the opening 402' has a width W3, and the width W3 can be in the range of about 20 micrometers to about 600 micrometers. In some embodiments, the width W3 of the bottom of the opening 402' can be in the range of about 25 micrometers to about 200 micrometers, such as about 90 micrometers. In some embodiments, the width W3 of the opening 402' is greater than the width W1 of the cutting channel 102. In some embodiments, the width W3 of the opening 402' is the same as the width W2 of the opening 402. Although in Figure 1D [the figure], the opening 402' has a generally vertical sidewall, but the present invention is not limited thereto. For example, the opening 402' may have an inclined sidewall or other shapes.

[0054] In some embodiments, the etching process may include a dry etching process, a wet etching process, other suitable processes, or a combination of the above. For example, the dry etching process may include reactive ion etching (RIE), inductive couple plasma (ICP) etching, neutral beam etching (NBE), electron cyclotron resonance (ECR) etching, other suitable processes, or a combination of the above. For example, the etchant used in the wet etching process may include hydrofluoric acid (HF), ammonium hydroxide (NH4OH), any suitable etchant, or a combination of the foregoing. In some embodiments, the material of the light-shielding layer 400 includes epoxy resin or other applicable materials, which can be etched by a dry etching process or other applicable etching methods.

[0055] According to some embodiments, in order to remove the material directly above the dicing street 102, compared with some embodiments that only use the dicing process, using the etching process will not damage the substrate 100. On the other hand, in order to avoid damaging the substrate 100 during the dicing process, in some embodiments that only use the dicing process, there may be residual material on the dicing street 102, and since the etching process will not damage the substrate 100, it can completely remove the residual material, thereby improving the reliability of the semiconductor device 10.

[0056] In the above embodiments, a dicing process and an etching process are performed on the light-shielding layer 400 directly above the dicing street 102. The dicing process can quickly remove the main part of the light-shielding layer 400 located on the dicing street 102, and then the etching process can completely remove the remaining part of the light-shielding layer 400 located on the dicing street 102 to expose the dicing street 102. The remaining part of this light-shielding layer 400 can protect the substrate 100 during the dicing process and prevent the substrate 100 from being damaged. The etching process can remove the remaining part of the light-shielding layer 400 remaining on the dicing street 102 without substantially damaging the surface of the substrate 100. In some embodiments, the thickness T1 of the remaining part of this light-shielding layer 400 may be in the range of about 5 microns to about 100 microns. In some embodiments, the thickness T1 of the remaining part of this light-shielding layer 400 may be in the range of about 10 microns to about 40 microns, such as about 20 microns to about 25 microns. In the foregoing thickness range, the remaining part has sufficient thickness to effectively protect the substrate 100 during the dicing process, and at the same time, it will not cause the etching time to be too long due to too thick a thickness. In some embodiments, the ratio of the thickness of the part removed by the dicing process to the thickness of the part removed by the etching process is in the range of about 20:1 to about 2:1.

[0057] Next, as Figure 1E shown, in some embodiments, a planarization process (such as a chemical mechanical polishing (CMP) process, a grinding process, other suitable processes, or a combination of the above) can be performed on the light-shielding layer 400 to planarize the light-shielding layer 400 so that the light-shielding layer 400 is flush with the top surface of the light-transmitting column 300. As previously mentioned, the combination of the light-transmitting columns 300 disposed on the sensing pixel 202 and the light-shielding layer 400 filled between the light-transmitting columns 300 together constitutes a light collimation layer 600. The function of this light collimation layer is to collimate light to reduce energy loss caused by light divergence. In some embodiments, other optical elements may be included above the light collimation layer, such as color filters, glass, lenses, etc. (not shown). In some embodiments, the incident light is guided to the sensing pixel 202 through the light collimation layer 600 after passing through the optical elements above the light collimation layer 600.

[0058] In some embodiments, a cover layer (not shown) disposed above the light collimation layer 600 may be included above the light collimation layer 600. The cover layer can be a hard light-transmitting material, such as calcium aluminosilicate glass, soda lime glass, sapphire, transparent polymer, or other suitable materials, so that at least part of the incident light can penetrate and reach the sensing pixel 202, and this hard cover plate can protect the semiconductor device 10 and other components thereunder.

[0059] As Figure 1F shown, a dicing process is performed to dice the substrate 100 along the dicing lane 102 to form the semiconductor device 10. Since the widths W2 and W3 of the openings 402 and 402' are greater than the width W1 of the dicing lane 102, during the dicing process, only the substrate 100 can be diced without touching other structures (such as the light-shielding layer 400), thereby reducing the risk of microcracks between material layers during the dicing process or peeling due to poor adhesion between the substrate 100 and other structures. In this way, the delamination problem occurring at the corners or edges of the die during subsequent reliability tests can be eliminated.

[0060] In some embodiments, after the above dicing process, the substrate 100 is diced into the substrate 100', and the sidewall 400A of the light-shielding layer 400 and the edge 100E of the substrate 100' together form a stepped profile, as Figure 1FAs shown. In some embodiments, the distance between the sidewall 400A of the light-shielding layer 400 and the edge 100E of the substrate 100' is greater than 0 micrometers to about 600 micrometers. In some embodiments, the distance between the sidewall 400A of the light-shielding layer 400 and the edge 100E of the substrate 100' is in the range of about 1 micrometer to about 500 micrometers, such as about 10 micrometers.

[0061] In some embodiments, the above cutting process may include laser cutting, ion beam cutting, wire saw, die saw, other suitable cutting techniques, or a combination of the above.

[0062] In the above embodiments, by performing a cutting process and an etching process on the light-shielding layer directly above the scribe line, the structure covering the scribe line is removed without damaging the surface of the substrate. Since there is no other structure (e.g., light-shielding layer) covering above the scribe line, during the cutting process of cutting the wafer into individual die along the scribe line, only the substrate can be cut without touching other structures, thereby reducing the risk of micro-cracking between material layers during the cutting process or peeling due to poor adhesion between the substrate and other structures. In this way, the delamination problem occurring at the corners or edges of the die during subsequent reliability tests can be eliminated.

[0063] Figures 2A - 2F is a cross-sectional schematic diagram showing various intermediate stages of another exemplary method for forming Figure 2F the semiconductor device 20 in accordance with some embodiments. For clarity, similar or identical elements and processes will be denoted by the same reference numerals. For the sake of brevity, the description of these processes and devices will not be repeated here.

[0064] In Figures 2A - 2F the described embodiments, the method of forming the semiconductor structure 20 is similar to the method of forming the semiconductor structure 10, except that an additional sacrificial structure 302 is formed directly above the scribe line 102 before forming the light-shielding layer 400.

[0065] Please refer to Figure 2A , first form the structure as Figure 1A described, and before forming the light-shielding layer 400, form a sacrificial structure 302 directly above the scribe line 102, and the sacrificial structure 302 covers the scribe line 102. In this embodiment, since the sacrificial structure 302 uses a material that is relatively easy to remove (e.g., by an etching process), the process time can be shortened. In some embodiments, the width of the sacrificial structure 302 can be in the range of about 25 micrometers to about 500 micrometers, such as about 100 micrometers. In some embodiments, the width of the sacrificial structure 302 is greater than the width W1 of the scribe line 102, as Figure 2A shown.

[0066] In some embodiments, a method similar to that described above may be used. Figure 1A The sacrificial structure 302 is formed by the process and material used to form the light-transmitting column 300, and the sacrificial structure 302 can be formed in the same step as the light-transmitting column 300, but the embodiments of the present invention are not limited thereto. In other embodiments, the process and / or material used to form the sacrificial structure 302 can be different from the process and / or material used to form the light-transmitting column 300, and the sacrificial structure 302 can be formed before, during or after the light-transmitting column 300. For example, in this embodiment, the material of the sacrificial structure 302 can be a photoresist material, and the material of the light-transmitting column 300 can be a transparent resin. In some embodiments, the sacrificial structure 302 and the light-transmitting column 300 can have different heights.

[0067] Then, if Figure 2B As shown, a light shielding layer 400 is formed on the substrate 100 and filled between the plurality of light-transmitting pillars 300 and the sacrificial structure 302. In some embodiments, a method similar to that described above can be used. Figure 1B The light shielding layer 400 is formed by the process and materials used to form the light shielding layer 400, and thus will not be described in detail herein.

[0068] Figure 2C The formation of the opening 402 is depicted. In some embodiments, the light shielding layer 400 and the sacrificial structure 302 are subjected to a cutting process to quickly remove the light shielding layer 400 and a portion of the sacrificial structure 302 located directly above the cutting street 102, so as to form the opening 402 directly above the cutting street 102, and leave a remaining sacrificial structure 302' covering the cutting street 102. The remaining sacrificial structure 302' can protect the substrate 100 during the cutting process to prevent the substrate 100 from being damaged. In some embodiments, the remaining sacrificial structure 302' has a thickness T1, and the thickness T1 can be in the range of about 1 micron to about 500 microns. In some embodiments, the thickness T1 of the remaining sacrificial structure 302' can be in the range of about 5 microns to about 100 microns, for example, about 20 microns. Within the aforementioned thickness range, the remaining sacrificial structure 302' can effectively protect the substrate 100 during the cutting process, and at the same time, the etching time will not be too long due to the thickness being too thick.

[0069] In addition, the sacrificial structure 302 may be made of a material having a different etching selectivity from the light shielding layer 400, so that the light shielding layer 400 is substantially not etched during the etching of the remaining sacrificial structure 302', so that the light shielding layer 400 after the etching process is easy to have a desired sidewall shape. In addition, compared with the material of the light shielding layer 400, the sacrificial structure 302 may include a material that is easily etched to shorten the time required for the etching process.

[0070] In other embodiments, the cutting process for forming the opening 402 only removes a part of the light-shielding layer 400 directly above the cutting channel 102, without removing the sacrificial structure 302 (not shown), so that the opening 402 exposes the top surface of the sacrificial structure 302.

[0071] The formation of the opening 402 makes the light-shielding layer 400 have an upper sidewall 400A. In some embodiments, the bottom of the opening 402 has a width W2, and the width W2 can range from about 25 micrometers to about 600 micrometers. In some embodiments, the width W2 can range from about 20 micrometers to about 500 micrometers, such as about 80 micrometers. In some embodiments, the width W2 of the opening 402 is greater than the width W1 of the cutting channel 102. In this embodiment, the width W2 of the opening 402 is greater than the width of the sacrificial structure 302, so that the opening 402 completely exposes the top surface of the remaining sacrificial structure 302'.

[0072] Although in Figure 2C , the opening 402 has substantially vertical sidewalls and a substantially flat bottom surface, the present invention is not limited thereto. For example, the opening 402 can have inclined sidewalls, a concave bottom surface, or other shapes. In some embodiments, the above cutting process can include laser cutting, ion beam cutting, wire saw, die saw, other suitable cutting techniques, or a combination of the above.

[0073] Next, as Figure 2D shown, an etching process is performed on the remaining sacrificial structure 302' directly above the cutting channel 102 through the opening 402 to extend the opening 402 until the cutting channel 102 is exposed, and an opening 402' is formed. The etching process can completely remove the remaining sacrificial structure 302', and substantially does not damage the surface of the substrate 100.

[0074] In some embodiments, the bottom of the opening 402' has a width W3, and the width W3 can range from about 20 micrometers to about 600 micrometers. In some embodiments, the width W3 can range from about 25 micrometers to about 200 micrometers, such as about 90 micrometers. The width W3 of the opening 402' is greater than the width W1 of the cutting channel 102. In this embodiment, the width W3 of the opening 402' is less than the width W2 of the opening 402.

[0075] In some embodiments, the formation of the opening 402' makes the light-shielding layer 400 have a lower sidewall 400B, so that the light-shielding layer 400 has a stepped sidewall. For example, the stepped sidewall of the light-shielding layer 400 includes an upper sidewall 400A away from the substrate 100 and a lower sidewall 400B adjacent to the substrate 100, as Figure 2DAs shown. In some embodiments, the minimum distance between the upper sidewall 400A of the light-shielding layer 400 and the light-transmitting column 300 is less than the minimum distance between the lower sidewall 400B of the light-shielding layer 400 and the light-transmitting column 300, such as Figure 2D As shown.

[0076] In some embodiments, a process and etchant similar to those described previously for Figure 1D etching the remaining portion of the light-shielding layer 400 can be used to etch the remaining sacrificial structure 302', and thus will not be elaborated here. In other embodiments, a rinsing process can be used to remove the remaining sacrificial structure 302', such as by deionised water (DI water).

[0077] Next, as Figure 2E shown, in some embodiments, a planarization process can be performed on the light-shielding layer 400 to planarize the light-shielding layer 400 such that the light-shielding layer 400 is flush with the top surface of the light-transmitting column 300. As previously mentioned, the combination of the light-transmitting columns 300 disposed on the sensing pixel 202 and the light-shielding layer 400 filled between the light-transmitting columns 300 together form a light collimation layer 600. In some embodiments, a process similar to that described previously for Figure 1E planarizing the light-shielding layer 400 can be used to planarize the above-mentioned light-shielding layer 400, and thus will not be elaborated here.

[0078] Please refer to Figure 2F , a dicing process is performed to dice the substrate 100 along the dicing street 102 to form the semiconductor device 20. Since there is no other structure (such as the light-shielding layer 400 and / or the sacrificial structure 302) covering above the dicing street 102, in the dicing process of dicing the wafer into individual dies along the dicing street 102, only the substrate 100 can be diced without touching other structures, thereby reducing the risk of microcracks between material layers during the wafer dicing process or peeling due to poor adhesion between the substrate 100 and other structures. In this way, delamination problems occurring at the corners or edges of the dies during subsequent reliability tests can be eliminated.

[0079] In some embodiments, after the above dicing process, the substrate 100 is diced into the substrate 100', and the sidewall 400B of the light-shielding layer 400 and the edge 100E of the substrate 100' together form a stepped profile, such as Figure 2F shown. In some embodiments, the distance between the sidewall 400B of the light-shielding layer 400 and the edge 100E of the substrate 100' is in the range of about 1 micron to about 600 microns, such as 90 microns. In some embodiments, the dicing process used here can be similar to the dicing process described previously for Figure 1F , and thus will not be elaborated here.

[0080] In the above embodiment, an additional sacrificial structure may be formed directly above the scribe line before forming the light-shielding layer, so as to shorten the time required for the subsequent etching process.

[0081] Figures 3A - 3C Some embodiments are illustrated in Figure 3C cross-sectional schematic views of various intermediate stages of another exemplary method for forming the semiconductor device 30 in

[0082] The dimensions of the sacrificial structure 302 may be adjusted so that the light-shielding layer 400 has a desired shape. In this embodiment, except that the stepped sidewalls of the light-shielding layer 400 are reverse-stepped, the semiconductor device 30 is similar to the semiconductor device 20.

[0083] Refer to Figure 3A , except that the sacrificial structure 302 is formed to have a width greater than the width W2 of the opening 402, the same or similar processes as those described above with respect to Figures 2A to 2C are performed to form a structure as in Figure 3A . In this embodiment, since the width of the sacrificial structure 302 is greater than the width of the opening 402, only a part of the top surface of the remaining sacrificial structure 302' is exposed by the opening 402.

[0084] Next, as shown in Figure 3B , an etching process is performed on the remaining sacrificial structure 302' directly above the scribe line 102 through the opening 402 to extend the opening 402 until the scribe line 102 is exposed, and an opening 402' is formed. The etching process may completely remove the remaining sacrificial structure 302' with substantially no damage to the surface of the substrate 100.

[0085] In some embodiments, the above remaining sacrificial structure 302' may be etched using a process and an etchant similar to those used for etching the remaining portion of the light-shielding layer 400 described above with respect to Figure 1D , and thus will not be described in detail herein. In other embodiments, a rinsing process may be used to remove the remaining sacrificial structure 302', such as by deionised water (DI water).

[0086] In some embodiments where the etching process is a dry etching process, the width W3 of the opening 402' is the same as the width W2 of the opening 402 (not shown). In some embodiments where the etching process is a wet etching process, the width W3 of the opening 402' is greater than the width W2 of the opening 402, as shown in Figure 3B .

[0087] In some embodiments where the width W3 of the opening 402' is greater than the width W2 of the opening 402, the formation of the opening 402' causes the light-shielding layer 400 to have a lower sidewall 400B, making the light-shielding layer 400 have a stepped sidewall with an inverted stepped shape, which includes an upper sidewall 400A away from the substrate 100 and a lower sidewall 400B adjacent to the substrate 100, as Figure 3B shown. For example, the minimum distance between the upper sidewall 400A of the light-shielding layer 400 and the light-transmitting column 300 is greater than the minimum distance between the lower sidewall 400B of the light-shielding layer 400 and the light-transmitting column 300, as Figure 3B shown.

[0088] In other embodiments, the width of the opening 402 can also be changed by adjusting the parameters of the cutting process, thereby adjusting the shape of the sidewall of the light-shielding layer 400. For example, without changing the size of the sacrificial structure 302 (i.e., the same as the size of the sacrificial structure 302 described above regarding Figures 2A - 2C ), by adjusting the parameters of the cutting process to adjust the width of the opening 402 to be greater than the width of the sacrificial structure 302, the light-shielding layer 400 can also have a stepped sidewall with an inverted stepped shape.

[0089] Next, as Figure 3C shown, then perform a planarization process and a cutting process that are the same as or similar to those described above regarding Figures 2E to 2F to form the semiconductor device 30. In some embodiments, after the above cutting process, the substrate 100 is cut into a substrate 100', and the sidewall 400B of the light-shielding layer 400 and the edge 100E of the substrate 100' together form a stepped profile, as Figure 3C shown. In some embodiments, the distance between the sidewall 400B of the light-shielding layer 400 and the edge 100E of the substrate 100' is in the range of greater than 0 microns to about 600 microns, for example, in the range of about 1 micron to about 500 microns.

[0090] In the above embodiments, the size of the sacrificial structure can be adjusted to make the light-shielding layer have a desired shape.

[0091] In summary, in the embodiments of the present invention, a cutting process and an etching process are performed on the material directly above the scribe line to expose the scribe line. The cutting process can quickly remove most of the material and leave a remaining material covering the scribe line to prevent the cutting process from damaging the substrate. Then, this remaining material is removed by the etching process, and the etching process can effectively remove this remaining material without damaging the substrate. Therefore, in the cutting process of cutting the wafer along the scribe line into individual die, the risk of causing microcracks between material layers during the wafer cutting process or peeling due to poor adhesion between the substrate and other structures can be reduced, so as to eliminate the delamination problem occurring at the corners or edges of the die during subsequent reliability tests, thereby further improving the reliability of the semiconductor device.

[0092] The features of several embodiments of the present invention are outlined above to make it easier for those skilled in the relevant art to understand this disclosure. Any person skilled in the relevant art should understand that this specification can easily be used as a basis for changes or designs of other structures or processes to achieve the same purposes as the embodiments of this disclosure and / or obtain the same advantages. Any person skilled in the relevant art can also understand that the equivalent structures or processes do not depart from the spirit and scope of this disclosure, and can be modified, substituted, and refined without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate, wherein the substrate has a scribe line; Forming a sensing pixel array in the substrate, wherein the sensing pixel array includes a plurality of sensing pixels; Forming a plurality of light-transmitting columns on the substrate, corresponding to being disposed above the plurality of sensing pixels of the sensing pixel array; Forming a light-shielding layer on the substrate and the plurality of light-transmitting columns; Performing a first cutting process to form an opening directly above the scribe line and leaving a remaining material covering the scribe line, wherein the width of the opening is greater than the width of the scribe line; And Performing an etching process to remove the remaining material and extend the opening until the scribe line is exposed.

2. The method for forming a semiconductor device according to claim 1, wherein, The thickness of the remaining material ranges from 5 micrometers to 100 micrometers.

3. The method for forming a semiconductor device according to claim 1, wherein The remaining material is the light-shielding layer.

4. The method for forming a semiconductor device according to claim 1, wherein, Further comprising forming a sacrificial structure above the scribe line before forming the light-shielding layer, wherein the remaining material is the sacrificial structure.

5. The method for forming a semiconductor device according to claim 4, wherein, The step of performing the first cutting process further comprises removing a part of the sacrificial structure.

6. The method for forming a semiconductor device according to claim 1, wherein, The scribe line has a first width, and the first width ranges from 25 micrometers to 500 micrometers.

7. The method for forming a semiconductor device according to claim 6, wherein, After performing the first cutting process and before performing the etching process, the bottom of the opening has a second width, and the second width ranges from 25 micrometers to 600 micrometers.

8. The method for forming a semiconductor device according to claim 7, wherein, After performing the etching process, the bottom of the opening has a third width, and the third width ranges from 25 micrometers to 200 micrometers.

9. The method for forming a semiconductor device according to claim 8, wherein, The second width is greater than the first width, and the third width is greater than the first width.

10. The method for forming a semiconductor device according to claim 8, wherein, The second width is the same as the third width.

11. The method for forming a semiconductor device according to claim 8, wherein The opening has a stepped sidewall.

12. The method for forming a semiconductor device according to claim 11, wherein, The second width is greater than the third width.

13. The method for forming a semiconductor device according to claim 11, wherein, The second width is less than the third width.

14. The method for forming a semiconductor device according to claim 4, wherein, The sacrificial structure and the plurality of light-transmitting columns are made of the same material.

15. The method for forming a semiconductor device according to claim 1, wherein, Further comprising performing a second cutting process to cut the substrate along the scribe line.

16. A semiconductor device, characterized in that, The semiconductor device is formed by the method according to any one of claims 1-15, comprising: A sensing pixel array located in a substrate, wherein the substrate has a scribe line, and wherein the sensing pixel array includes a plurality of sensing pixels; A plurality of light-transmitting columns located above the substrate and corresponding to being disposed above the plurality of sensing pixels of the sensing pixel array; and A light-shielding layer located above the substrate and filled between the plurality of light-transmitting columns, wherein the top surface directly above the scribe line in the substrate is exposed through an opening in the light-shielding layer, and a sidewall of the opening and the top surface directly above the scribe line in the substrate together form a stepped profile.

17. The semiconductor device according to claim 16, wherein The distance between the sidewall of the light-shielding layer and the edge of the substrate ranges from greater than 0 micrometers to 600 micrometers.

18. The semiconductor device according to claim 16, wherein, The sidewall of the light-shielding layer is a stepped sidewall, wherein the stepped sidewall has an upper sidewall away from the substrate and a lower sidewall adjacent to the substrate.

19. The semiconductor device according to claim 18, wherein, The distance between the upper sidewall of the light-shielding layer and the plurality of light-transmitting columns is less than the distance between the lower sidewall of the light-shielding layer and the plurality of light-transmitting columns.

20. The semiconductor device according to claim 18, characterized in that, The distance between the upper sidewall of the light-shielding layer and the plurality of light-transmitting columns is greater than the distance between the lower sidewall of the light-shielding layer and the plurality of light-transmitting columns.

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