Image sensor and method for manufacturing a pixel cell thereof

Abstract

This application is directed to backside illuminated sensor pixel structures. In one embodiment, an image sensor includes a plurality of photodiodes arranged as rows and columns of a pixel array disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. The individual photodiodes have a diffusion region formed in an epitaxial region and a plurality of storage nodes (SGs) disposed on a front side of the semiconductor substrate and formed in the epitaxial region. An opaque isolation layer having a plurality of opaque isolation elements is disposed proximate to the front side of the semiconductor substrate and proximate to the diffusion regions of the plurality of photodiodes. The opaque isolation elements are configured to block a path of incoming light from the backside of the semiconductor substrate toward the storage nodes.

Description

Technical Field

[0001] This invention generally relates to the design of image sensors, and more specifically to image sensors that reduce optical crosstalk. Background Technology

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technologies used to manufacture image sensors continue to advance rapidly. For example, the demand for higher image sensor resolution and lower power consumption is driving further miniaturization and integration of image sensors into digital devices.

[0003] As image sensor resolution increases, the spacing between photodiodes typically decreases, resulting in narrower and deeper photodiodes. These more densely packed photodiodes are more susceptible to optical noise caused by stray light. For example, after illuminating a target photodiode, incoming light can be reflected back to adjacent photodiodes, thus increasing the signal noise level of those photodiodes. Stray light can also be generated by reflections from the metallized layer.

[0004] In some applications, back-illuminated photodiodes are derived from semiconductor substrates on semiconductor dies. Noise generated by stray light can be even more significant for back-illuminated photodiodes because their semiconductor regions (which are less shielded by the wiring layers on the front side of the image sensor) are more exposed to stray light. Therefore, the accuracy or applicability of the image sensor can be limited. Summary of the Invention

[0005] In one aspect, this application relates to an image sensor comprising: a plurality of photodiodes arranged in rows and columns of a pixel array disposed in a semiconductor substrate, wherein individual photodiodes of the pixel array are configured to receive incoming light through a back side of the semiconductor substrate, wherein a front side of the semiconductor substrate is opposite to the back side, wherein each individual photodiode includes a diffusion region formed in an epitaxial region; a plurality of memory nodes (SGs) disposed on the front side of the semiconductor substrate and formed in the epitaxial region; a plurality of transfer gates (TXs) disposed proximately to the front side of the semiconductor substrate, the plurality of transfer gates being configured to couple the plurality of photodiodes to the plurality of memory nodes, each of the transfer gates being configured to operatively transfer an image charge generated by each coupled photodiode to each corresponding memory node; and an opaque isolation layer having a plurality of opaque isolation elements disposed proximately to the front side of the semiconductor substrate and proximate to the diffusion regions of the plurality of photodiodes, wherein the plurality of opaque isolation elements are configured to block at least a portion of the incoming light from the back side of the semiconductor substrate toward the plurality of memory nodes (SGs).

[0006] In another aspect, this application relates to a method for manufacturing a pixel unit of an image sensor, the method comprising: providing a semiconductor substrate having a first side and a second side, the second side being opposite to the first side; forming an opaque isolation element near the first side of the semiconductor substrate; growing an epitaxial layer near the first side of the semiconductor substrate, wherein the epitaxial layer is embedded in the opaque isolation element; and forming a photodiode between the opaque isolation element and the second side of the semiconductor substrate. Attached Figure Description

[0007] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein, unless otherwise specified, similar element symbols refer to similar parts throughout the views.

[0008] Figure 1 This is a block diagram of an example image sensor according to an embodiment of the present invention.

[0009] Figure 2 This is a partial exploded view of an example photodiode according to an embodiment of the technology of the present invention.

[0010] Figure 3 This is a partial exploded view of an example photodiode having an opaque isolation element according to an embodiment of the present invention.

[0011] Figure 4 A cross-sectional view of an opaque isolation element according to an embodiment of the present invention is shown.

[0012] Figure 5 This is a schematic diagram of the manufacturing process according to an embodiment of the present invention.

[0013] Figure 6 This is a flowchart of a manufacturing process according to an embodiment of the present invention.

[0014] Several views throughout the diagrams correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, the dimensions of some elements in the figures may be enlarged relative to others. Furthermore, common but well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a less obstructed view of these various embodiments of the invention. Detailed Implementation

[0015] This invention discloses an image sensor, and more specifically, an image sensor with reduced sensitivity to optical noise. Numerous specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the stated specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0016] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one embodiment of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same example. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0017] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., are used herein to describe the relationship of one element or feature to another, as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is rotated, an element described as being “below,” “under,” or “below” other elements or features will be oriented as being “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptions used herein will be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also exist.

[0018] Several terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0019] Briefly, examples of the teachings of the present invention pertain to photodiodes (also referred to as channels or pixels) that have improved immunity to stray light, reduced inter-channel noise, and / or reduced inter-channel crosstalk. Back-illuminated photodiodes can withstand stray light reflected from the metallized substrate or stray light arriving from adjacent diodes, referred to as reflected light or transmitted light. In some embodiments, an opaque insulating layer is disposed above the top side (or the side close to the front side of the semiconductor substrate) of the photodiode to limit the amount of stray light illuminating the diffusion region of the photodiode. In some embodiments, individual opaque insulating elements at least cover the breadth of the N-type diffusion region of the individual photodiode. In operation, the opaque insulating elements reflect or absorb at least a portion of the incoming stray light, thereby reducing optical noise at the semiconductor diffusion region of the photodiode.

[0020] In some embodiments, the opaque isolation layer may comprise a plurality of opaque isolation elements, each disposed between the front side of the semiconductor substrate and a corresponding photodiode. Each of the opaque isolation elements may comprise a metal (or metal alloy) layer coated in a dielectric layer. The metal layer is typically characterized by high light absorption, while the dielectric layer prevents or reduces electrical leakage into the semiconductor diffusion region. The opaque isolation layer may be fabricated as part of the manufacturing process of a sensor array. In some embodiments, the dielectric layer may also be opaque.

[0021] In some embodiments, individual photodiodes include light shielding elements (e.g., metallic light shielding elements) having centered openings above the N-type diffusion regions of the photodiode. These openings transmit incoming light toward the N-type diffusion regions while limiting undesired illumination of adjacent N-type diffusion regions.

[0022] In some embodiments, the semiconductor material of the photodiode (e.g., an N-type diffusion region) is electrically coupled to an associated transfer transistor to transfer accumulated charge to the floating diffusion region via vertical electrodes made of metal. Because these vertical electrodes extend relatively deep into the semiconductor material, the vertical gates further limit stray light noise in the photodiode of the image sensor.

[0023] Figure 1 This is a schematic diagram of an example image sensor 10 according to an embodiment of the present invention. The image sensor 10 includes pixels 11 arranged in rows (R) and columns (C) of a pixel array 12. In one embodiment, the pixel array 12 includes, for example, Bayer patterns or mosaic color filter patterns of additive red, green, and blue color filters (e.g., RGB, RGBG, or GRGB); color filter patterns of subtractive blue-green, magenta, yellow, and primary hue (black) color filters (e.g., CMYK); combinations of both; or others. When the image sensor 10 is exposed to light, individual pixels 11 (also referred to as channels or photodiodes) acquire certain voltage values. After each pixel has acquired its voltage value, image data is read out by readout circuitry 14 and then transferred to functional logic 18.

[0024] Individual pixels (P1-P) n The voltage value can be captured by the readout circuit 14. For example, the control circuit 16 can determine a specific row R of the pixel array 12 coupled to the readout circuit 14. i In the captured line R i After the pixel value is in the data, the control circuit 16 can adjust the row R. i+1 Coupled with readout circuit 14, the process is repeated until the voltage values ​​of all pixels in the column are captured. In other embodiments, readout circuit 14 may use various other techniques (not described in the text). Figure 1 (Illustrated in the diagram) to read out image data, such as serial readout or simultaneous parallel readout of all pixels. In different embodiments, the readout circuit 14 may include amplifier circuitry, analog-to-digital converter (ADC) circuitry, or other circuitry. In some embodiments, pixel values ​​are captured and processed by functional logic 18. Such processing may (for example) include image processing, image filtering, image extraction and manipulation, light intensity determination, etc.

[0025] Figure 2This is a partially exploded view of an example pixel (photodiode) according to an embodiment of the present invention. The illustrated pixel 11 may include a semiconductor substrate 36 having a P-type epitaxial region 34 and a photodiode formed in the P-type epitaxial region 34. In some embodiments, the P-type epitaxial region 34 is formed by an epitaxial growth process. The photodiode may include an N-type diffused region 32, and the N-type diffused region 32 may be formed by implanting N-type dopants, such as arsenic and phosphorus, into the P-type epitaxial region 34 during an ion implantation process. In some embodiments, the P-type epitaxial region 34 and the N-type diffused region 32 may be collectively referred to as the semiconductor substrate 36. In operation, during a global reset cycle, the photodiode is reset to a preset voltage by a global shutter gate 42 in response to a global shutter signal GS. During a global exposure or integration cycle, incoming light 20 irradiates the N-type diffused region 32, thereby generating free electrons that generate charge. During a global charge transfer cycle, this charge is transferred to a storage node (SG) 48 via, for example, a flat transfer channel, in response to a transfer signal TX received at the transfer gate 44. In response to the output signal node (OG) 46, charge is further transferred, for example, through the output gate 46 to the floating diffusion region (FD) 50 for subsequent readout operations. It is known, for example, in some embodiments, that the polarity may be reversed, and pixel 11 may include a P-type diffusion region formed in the N-type epitaxial region for accumulating holes as charge in response to incoming light 20.

[0026] In some embodiments, the exposure of the N-type diffusion region 32 to the incoming light 20 can be controlled by a light shield 52, which may be made of a metal such as, for example, tungsten or aluminum. The light shield 52 may include openings and can act as an aperture arranged to guide the incoming light 20 to illuminate the N-type diffusion region 32. Therefore, the light shield 52 can prevent unwanted illumination of the N-type diffusion regions 32 of adjacent pixels. In different embodiments, the light shield 52 may be fabricated during the manufacture of the image sensor by, for example, metal deposition. However, in addition to the incoming light 20, the N-type diffusion region 32 may still be exposed to stray light 63, 64 that generates cross-optical noise among adjacent pixels.

[0027] Figure 3 This is a partially exploded view of an instance pixel 110 (also referred to as pixel unit 110) having an opaque isolation element 82 according to an embodiment of the present invention. The image sensor containing the instance pixel 110 may be a global shutter back-side illuminated image sensor. An image sensor containing a pixel array includes a plurality of instance pixels 110 arranged in rows and columns. The plurality of instance pixels 110 may be arranged in rows and columns, such as by… Figure 1The pixel array 12 is illustrated. A plurality of instance pixels 110 can be brought into their initial state by a global shutter gate 62, which is turned on to reset the photodiodes of the pixels 110 in the pixel array to their initial values ​​in response to a global reset signal GS.

[0028] As the resolution of the image sensor is increased and / or the size of the image sensor is reduced, the spacing between pixels 110 is reduced, resulting in narrower and deeper photodiodes. Generally, these more densely packed pixels 110 are more susceptible to noise generated by stray light. In different embodiments, stray light can be generated at the front side 72 from adjacent pixels or from reflections from the metallized coating.

[0029] The floating diffusion region (FD) 50 and the storage node (SG) 48 may be positioned close to the front side 72. The floating diffusion region (FD) 50 and the storage node (SG) 48 may be non-contact and laterally spaced. The floating diffusion region (FD) 50 and the storage node (SG) 48 may be coupled to the output gate (OG) 46. Figure 3 In pixel 110, the N-type diffusion region 32 of the photodiode is deeply embedded in the semiconductor substrate 36, while the floating diffusion region 50 and the storage node (SG) 48 are disposed on the N-type diffusion region 32 to effectively utilize the pixel space and further minimize the size of pixel 110. Furthermore, pixel 110 may also include a vertical transfer gate 60, an output gate 46, and a vertical global shutter gate 62. The vertical transfer gate 60 may be a vertical transfer gate structure used to transfer accumulated charge from the deeply embedded N-type diffusion region 32 to the storage node 48 in response to a transfer signal TX.

[0030] Figure 3 The vertical transfer door 60 is different Figure 2The diagram illustrates the flat structure of transfer gate 44. For example, vertical transfer gate 60 includes an electrode 49 for transferring accumulated charge from N-type diffusion region 32. The electrode 49 of vertical transfer gate 60 is formed to extend from the front side 72 of semiconductor substrate 36 to one side (first side) of N-type diffusion region 32 in response to transfer signal TX, operatively transferring charge accumulated in the deeper N-type diffusion region 32 to storage node 48. Vertical global shutter gate 62 may also be in the form of a vertical gate structure including electrode 49, and vertical global shutter gate 62 is used to operatively reset N-type diffusion region 32 with a reset value (e.g., reset to power supply voltage) in response to global reset signal GS during a global reset cycle. The electrode 49 of the vertical global shutter gate 62 may be formed to extend from the front side 72 of the semiconductor substrate 36 into the semiconductor substrate 36 and close to the other side (second side) of the N-type diffusion region 32 to operatively reset the deeply applied N-type diffusion region 32 to a reset value in response to the global reset signal GS. The output gate 46 is configured to transfer accumulated charge from the storage node (SG) 48 to the floating diffusion region (FD) 50 in response to the output signal OG.

[0031] In some embodiments, the vertical transfer gate 60 and the vertical global shutter gate 62 may be arranged to extend from the front side 72 through the semiconductor substrate 36 such that a portion of the electrode 49 of the vertical transfer gate 60 and a portion of the electrode 49 of the vertical global shutter gate 62 overlaps with a portion of the N-type diffusion region 32 of the photodiode.

[0032] Pixel 110 may further include a microlens 22 and a color filter 24. Microlens 22 may be configured to have a first surface facing the color filter 24 and a second surface facing away from the first surface (opposite to the first surface). Color filter 24 may be configured to have a first side facing the light shield 52 and a second side facing away from the first side (opposite to the first side) and facing the buffer oxide layer 26. In some embodiments, microlens 22 may operatively focus incoming light 20 onto the N-type diffusion region 32 of a corresponding photodiode. Color filter 24 may operatively filter incoming light 20 passing through the first side of color filter 24 to allow selected wavelength range components (e.g., visible light components) of the incoming light 20 to pass through, thereby illuminating the N-type diffusion region 32.

[0033] In some embodiments, the light shield 52 may be formed in the buffer oxide layer 26. In some embodiments, the light shield 52 may be at least partially coplanar with the buffer oxide layer 26 disposed on the back side 74 of the semiconductor substrate 36.

[0034] In operation, incoming light 20 to individual photodiodes can pass through a microlens 22, a color filter 24, a buffer oxide layer 26, and a light shield 52 at the back side 74 of the semiconductor substrate 36 to illuminate the N-type diffusion region 32 of the corresponding photodiode during a global exposure or integration cycle. The resulting charge (illustrated as "e-") in response to the incoming light 20 accumulates in the N-type diffusion region 32 of the corresponding photodiode. The charge can be collected by the electrode 49 of the vertical transfer gate 60 disposed at the front side 72 of the semiconductor substrate 36 and transferred to the storage node 48 in response to the transfer signal TX during a global charge transfer cycle. Next, during the readout cycle, the charge is transferred, for example, line-by-line through the output gate 46 from the storage node (SG) 48 toward the associated floating diffusion region (FD) 50.

[0035] The N-type diffusion region 32 of pixel 110 is electrically connected to elements (e.g., global shutter (GS), vertical transfer gate (TX), etc.) at the front side 72 via a relatively deep electrode 49. In at least some embodiments, the presence of the electrode 49 extending into the depth of the semiconductor substrate 36 reduces stray light incident on the N-type diffusion region 32.

[0036] An opaque isolation layer can be used to prevent incoming light 20 from penetrating the N-type diffusion region 32 and illuminating the floating diffusion region (FD) 50 and / or the storage node (SG) 48. Otherwise, the incoming light could generate noise that hinders readout. In some embodiments, the pixel 110 has an opaque isolation layer comprising an opaque isolation element 82 formed between the N-type diffusion region 32 on one side of the opaque isolation element and the floating diffusion region (FD) 50 and the storage node (SG) 48 on the other side. The opaque isolation element 82 may be formed and arranged to extend within the span of the N-type diffusion region 32, thus blocking or at least reducing the incoming light 20 from illuminating the storage node (SG) 48 and the floating diffusion region (FD) 50 through the N-type diffusion region 32. In some embodiments, the opaque isolation element 82 may be arranged to optically isolate the floating diffusion region (FD) 50 and the storage node (SG) 48 from the incoming light 20. For example, during exposure or integration cycles, light incident on the storage node (SG) 48 and the floating diffusion region (FD) 50 can generate noise that hinders image readout. Furthermore, the opaque isolation element 82 can absorb or limit the amount of stray light incident on the N-type diffusion region 32, thus limiting optical noise. In some embodiments, the opaque isolation element 82 may extend beyond the span of the N-type diffusion region 32, or may extend only partially within the planar dimensions (X and Y dimensions) of the N-type diffusion region 32.

[0037] In some embodiments, the electrodes 49 of the vertical transfer gate 60 and the vertical global shutter gate 62 may be laterally spaced from the opaque isolation element 82.

[0038] In some embodiments, the N-type diffusion region 32 may be capped by a P-type implantation layer 33 that provides isolation between the opaque isolation element 82 and the N-type diffusion region 32. In some embodiments, the P-type implantation layer 33 may be formed by implanting a P-type dopant, such as boron, into the region between the opaque isolation element 82 and the N-type diffusion region 32.

[0039] Figure 4 A cross-sectional view of an opaque isolation element according to an embodiment of the present invention is shown. The opaque isolation element 82 may be fabricated as a deposited layer within a semiconductor substrate 30. In some embodiments, the opaque isolation element 82 may comprise multiple material layers. For example, the opaque isolation element 82 may comprise a metal layer 84 (e.g., copper, aluminum) at least partially encapsulated within a dielectric layer 86 (e.g., silicon dioxide, nitrogen oxides, organic dielectrics, etc.). In operation, the metal layer 84 blocks incoming light, while the dielectric layer 86 prevents or reduces electrical leakage into the semiconductor substrate 30. In some embodiments, the dielectric layer may also be opaque. For example, the dielectric layer may be formed of an opaque material having a suitable thickness for the desired opacity.

[0040] Figure 5 This is a schematic diagram of a manufacturing process 500 according to an embodiment of the present invention. In some embodiments, the process may include only some of the boxes in the schematic diagram, or may include additional steps not illustrated in the schematic diagram 500. For simplicity, the manufacturing process 500 depicts the formation of a single pixel or a single pixel unit, but the process can be adapted to form... Figure 1 The pixels of the pixel array 12 are similarly arranged multiple pixels (pixel units).

[0041] In block 510, the fabrication process 500 begins with a semiconductor substrate 30. As an example, the material of the semiconductor substrate is silicon. However, those skilled in the art will understand that any Group III element (B, Al, Ga, In, Tl), Group IV element (C, Si, Ge, Sn, Pb), Group V element (N, P, As, Sb, Bi), and suitable combinations of these elements can be used to form a semiconductor substrate.

[0042] In block 515, an opaque isolation element 82 is formed on the semiconductor substrate 30 as an opaque isolation layer. In different embodiments, forming the opaque isolation element 82 may include different manufacturing steps, such as mask deposition, optically exposing a mask, etching, material deposition, etc. A single opaque isolation element 82 is illustrated in block 515; however, semiconductor wafers typically contain multiple opaque isolation elements 82 for different pixels (e.g., one opaque isolation element 82 per pixel). The thickness of the opaque isolation element 82 may depend on the material used for the isolation element 82 and the required opacity to ensure that incoming light 20 or stray light from the back side of the semiconductor substrate 30 does not penetrate the opaque isolation element 82 and illuminate the diffusion region (e.g., floating diffusion region, memory node) formed above the optical isolation element 82 on the front side.

[0043] As explained above, the opaque insulating element 82 may comprise a metal layer (material) and a dielectric layer (material). In some instances, the dielectric material may comprise oxides / nitrides, such as silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y Tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium trioxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), etc. Furthermore, those skilled in the art will recognize that, according to the teachings of the present invention, other stoichiometric combinations of the above-mentioned metals / semiconductors and their oxides / nitrides / oxygen oxides can be used, provided that they have a refractive index lower than that of the semiconductor material.

[0044] In blocks 520 and 525, the growth of the semiconductor substrate 30 continues, for example, by epitaxial growth, to enclose the optical isolating element 82 within the semiconductor substrate 30. In block 530, the semiconductor substrate 30 is doped by an ion implantation process, thereby forming, for example, an N-type diffusion region 32 below or beneath the optical isolating element 82. In some embodiments, preferably, there may be a separation between the optical isolating element and the N-type diffusion region 32; for example, the N-type diffusion region 32 may be formed at a depth greater than that of the opaque isolating element 82. arrive Further preferably, the lateral width of the opaque isolating element 82 may be at least the same as the width of the photodiode (e.g., the N-type diffusion region 32) to ensure that the floating diffusion region and storage node formed on the opaque isolating element 82 at the front side are not exposed to incoming or stray light, thus preventing optical noise. In some embodiments, doping to form the N-type diffusion region 32 may be performed prior to the formation of the opaque isolating element 82, as doping through the opaque isolating element 82 can be challenging. The sequence of manufacturing steps may depend on the material selection and thickness of the opaque isolating element 82. In block 540, the fabrication of pixel 110 continues, by way of example, by forming a doped region comprising the floating diffusion region and storage node formed on the opaque isolating element 82 by corresponding ion implantation, and the N-type diffusion region 32 in the semiconductor substrate 30; forming a vertical transfer gate, an output gate, and a vertical global shutter gate; and forming a metallized layer on the front side of the semiconductor substrate 30 that electrically connects the semiconductor substrate 30 to the circuitry of an image sensor formed on the front side of the semiconductor substrate 30. In some embodiments, the floating diffusion region and the memory node may be formed close to a first side of the semiconductor substrate 30 and laterally spaced apart from each other within the semiconductor substrate 30. The floating diffusion region and the memory node may be doped with a dopant of the same conductivity type as the N-type diffusion region 32. In other words, both the floating diffusion region and the memory node may be N-type doped regions.

[0045] Figure 6 This is a flowchart of a manufacturing process 600 according to an embodiment of the present invention. In some embodiments, the method may include only some of the steps in the flowchart, or may include additional steps not illustrated in flowchart 600.

[0046] Method 600 can be used to make Figure 3 An exemplary pixel 110 is used, and method 600 begins in box 605. A semiconductor substrate 30 is provided in box 610. In box 615, the example referenced above is used... Figure 5 The fabrication steps described herein involve forming an opaque isolation element 82 (also referred to as an opaque isolation material or opaque isolation element) on a semiconductor substrate 30. An epitaxial layer is grown over the semiconductor substrate 30 in block 620, thus embedding the opaque isolation element 82.

[0047] In block 625, a photodiode region (e.g., an N-type diffusion region) for each individual pixel 110 is formed on the first side (front side) of the semiconductor substrate 30 and beneath the opaque isolation element 82. As explained above, the photodiode region can be formed by implanting the semiconductor substrate 30 with a suitable N-type dopant, such as arsenic (As) or phosphorus (P), and a suitable implantation energy. In block 630, other elements forming the pixel, for example, doped regions such as a floating diffusion region 50 storing accumulated charge for readout and a storage node 48 laterally spaced from the floating diffusion region 50 for temporary charge storage in global shutter operation, can be formed by implanting the semiconductor substrate 30 with a suitable N-type dopant and concentration; and a metallized layer electrically connecting the semiconductor material to the circuitry of the image sensor. The opaque isolation element 82 can be arranged to shield the floating diffusion region 50 and the storage node 48 from incoming light. In block 635, a light shield 52 is formed on the back side of the semiconductor substrate 30 to form an optical aperture. As explained above, the light shield 52 may be a metal layer containing an opening for allowing and guiding incoming light, which is centered on the back side of the semiconductor substrate 30, to the photodiode region (e.g., the N-type diffusion region).

[0048] Many embodiments of the techniques described above may take the form of computer or controller executable instructions, including routines executed by a programmable computer or controller. Those skilled in the art will understand that the techniques can be practiced on computer / controller systems other than those shown and described above. The techniques may be embodied in a special-purpose computer, application-specific integrated circuit (ASIC), controller, or data processor that is specifically programmed, configured, and / or constructed to execute one or more of the computer executable instructions described above. Of course, any logic or algorithm described herein may be implemented in software or hardware, or a combination of software and hardware.

[0049] The above description of the illustrated examples of the invention, including the content described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention.

[0050] These modifications can be made to the invention in light of the above detailed description. The terminology used in the following claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with the established principles of claim interpretation.

Claims

1. An image sensor, comprising: Multiple photodiodes arranged in rows and columns of a pixel array are disposed in a semiconductor substrate, wherein individual photodiodes of the pixel array are configured to receive incoming light through the back side of the semiconductor substrate, wherein the front side of the semiconductor substrate is opposite to the back side, and wherein each individual photodiode includes a diffusion region formed in an epitaxial region. Multiple memory nodes SG are disposed on the front side of the semiconductor substrate and formed in the epitaxial region; Multiple global shutter gates GS are disposed on the front side of the semiconductor substrate; A plurality of transfer gates TX are disposed close to the front side of the semiconductor substrate, the plurality of transfer gates being configured to couple the plurality of photodiodes to the plurality of memory nodes, each of the transfer gates being configured to operatively transfer image charge generated by each coupled photodiode to each corresponding memory node; An opaque isolation layer having a plurality of opaque isolation elements disposed close to the front side of the semiconductor substrate and close to the diffusion region of the plurality of photodiodes; and Multiple vertical electrodes are connected to the transfer gate TX and the global shutter gate GS. The vertical electrodes are laterally spaced from individual opaque isolation elements, and the vertical electrodes extend into the epitaxial region at the front side to a depth to be laterally spaced from the corresponding diffusion region. Individual opaque isolation elements are vertically stacked between the corresponding diffusion region and the memory node SG, and laterally disposed between the vertical electrodes, wherein the plurality of opaque isolation elements are configured to block at least a portion of the incoming light from the back side of the semiconductor substrate toward the plurality of memory nodes SG.

2. The image sensor of claim 1, further comprising a plurality of light shields disposed close to the back side of the semiconductor substrate and close to the diffusion region of the plurality of photodiodes, wherein individual light shields at least partially constrain the path of the incoming light toward the diffusion region of the photodiodes.

3. The image sensor of claim 1, wherein the opaque isolation element extends at least above the diffusion region of the corresponding photodiode.

4. The image sensor of claim 3, wherein the individual opaque isolation element comprises a metal layer encapsulated in a dielectric layer.

5. The image sensor according to claim 4, wherein the dielectric layer is opaque.

6. The image sensor according to claim 1, wherein the diffusion region is an N-type semiconductor material and the epitaxial region is a P-type semiconductor material.

7. The image sensor of claim 6, wherein each of the individual photodiodes comprises a P-type implant disposed between the diffusion region of the respective individual photodiode and the respective opaque isolation element.

8. The image sensor of claim 1, further comprising a vertical gate laterally spaced from the opaque isolation element and extending through the extensional region at the front side.

9. The image sensor of claim 2, further comprising a buffer oxide that is at least partially coplanar with the corresponding light shield.

10. The image sensor of claim 2, further comprising a color filter having a first side facing the light shield and a second side facing away from the first side.

11. The image sensor of claim 10, further comprising a microlens having a first surface facing the color filter and a second surface facing away from the first surface.

Images