Semiconductor device

Abstract

A semiconductor device includes: first and second active patterns on first and second active regions of a substrate, respectively; a pair of first source / drain patterns and a first channel pattern therebetween, wherein the pair of first source / drain patterns are in the upper portion of the first active patterns; a pair of second source / drain patterns and a second channel pattern therebetween, wherein the pair of second source / drain patterns are in the upper portion of the second active patterns; and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a corresponding adjacent first metal pattern in the first and second channel patterns. The first and second channel patterns comprise SiGe. The Ge concentration of the second channel pattern is higher than the Ge concentration of the first channel pattern. The thickness of the first metal pattern of the second gate electrode is greater than the thickness of the first metal pattern of the first gate electrode.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices can include integrated circuits containing metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices decrease, MOSFETs have been scaled down accordingly. The operating characteristics of semiconductor devices may deteriorate due to the reduction in MOSFET size. Therefore, various methods for fabricating semiconductor devices with excellent performance while overcoming the limitations of high integration have been investigated. Summary of the Invention

[0003] Embodiments of the present invention can provide semiconductor devices with improved electrical properties.

[0004] In some embodiments, the semiconductor device may include: a substrate including a first active region and a second active region; a first active pattern and a second active pattern, respectively, on the first active region and the second active region; a pair of first source / drain patterns and a first channel pattern between the pair of first source / drain patterns, wherein the pair of first source / drain patterns are in the upper portion of the first active pattern; a pair of second source / drain patterns and a second channel pattern between the pair of second source / drain patterns, wherein the pair of second source / drain patterns are in the upper portion of the second active pattern; and a first gate electrode and a second gate electrode, respectively, intersecting the first channel pattern and the second channel pattern. Each of the first gate electrode and the second gate electrode may include a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns may include silicon-germanium (SiGe). The concentration of germanium (Ge) in the second channel pattern may be higher than the concentration of germanium (Ge) in the first channel pattern, and the thickness of the first metal pattern of the second gate electrode may be greater than the thickness of the first metal pattern of the first gate electrode.

[0005] In some embodiments, the semiconductor device may include: a substrate including a first active region and a second active region; a first active pattern and a second active pattern, respectively, on the first active region and the second active region; a pair of first source / drain patterns and a first channel pattern between the pair of first source / drain patterns, wherein the pair of first source / drain patterns and the first channel pattern are in the upper portion of the first active pattern; a pair of second source / drain patterns and a second channel pattern between the pair of second source / drain patterns, wherein the pair of second source / drain patterns and the second channel pattern are in the upper portion of the second active pattern; first and second gate electrodes, respectively, intersecting the first and second channel patterns; a first gate dielectric pattern between the first gate electrode and the first channel pattern; and a second gate dielectric pattern between the second gate electrode and the second channel pattern. The concentration of germanium (Ge) in the first channel pattern may be different from the concentration of germanium (Ge) in the second channel pattern, and the first gate dielectric pattern may include lanthanum (La) or aluminum (Al).

[0006] In some embodiments, the semiconductor device may include: a substrate including P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) regions and N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) regions spaced apart from each other in a first direction; a first active pattern and a second active pattern on the PMOSFET regions and the NMOSFET regions, respectively; the first and second active patterns extending in a second direction intersecting the first direction; a device isolation layer on the substrate extending over a sidewall of the lower portion of each of the first and second active patterns, the first and second active patterns having an upper portion projecting upward from the top surface of the device isolation layer and the upper portion of the first active pattern including a semiconductor pattern; a pair of first source / drain patterns in the upper portion of the first active pattern; a pair of second source / drain patterns in the upper portion of the second active pattern; a gate electrode intersecting the first and second active patterns and extending in the first direction; a gate dielectric pattern between the gate electrode and the first and second active patterns; an active contact electrically connected to the first and second source / drain patterns; and an interconnect on the active contact and electrically connected to the active contact and the gate electrode. The semiconductor pattern of the first active pattern may include silicon germanium (SiGe). The semiconductor pattern of the first active pattern may also include nitrogen (N) as an impurity. The concentration of germanium (Ge) in the semiconductor pattern may increase from the top surface to the bottom surface of the semiconductor pattern. The concentration of nitrogen (N) in the semiconductor pattern may decrease from the top surface to the bottom surface of the semiconductor pattern. Attached Figure Description

[0007] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0008] Figure 1This is a plan view illustrating some embodiments of a semiconductor device according to the present invention.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0010] Figure 3 yes Figure 2A Enlarged cross-sectional view of the first active region.

[0011] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention.

[0012] Figure 5A , Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A They are along Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 A cross-sectional view taken from line A-A'.

[0013] Figure 5B , Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B They are along Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 The cross-sectional view taken by line B-B'.

[0014] Figure 15C and Figure 17C They are along Figure 14 and Figure 16 The cross-sectional view taken from line C-C'.

[0015] Figure 15D and Figure 17DThey are along Figure 14 and Figure 16 The cross-sectional view taken by line D-D'.

[0016] Figure 18 and Figure 19 It is along Figure 1 A cross-sectional view taken along line A-A' is provided to illustrate a semiconductor device according to some embodiments of the concept of the present invention.

[0017] Figure 20A , Figure 20B and Figure 20C They are along Figure 1 The cross-sectional views taken along lines A-A', C-C', and D-D' are used to illustrate a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0018] Figure 1 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 2A , Figure 2B , Figure 2C and Figure 2D They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'. Figure 3 yes Figure 2A Enlarged cross-sectional view of the first active region.

[0019] refer to Figure 1 and Figures 2A to 2D A substrate 100 comprising a PMOSFET region PR and an NMOSFET region NR can be provided. The substrate 100 may be a semiconductor substrate comprising silicon, germanium, or silicon-germanium, or it may be a compound semiconductor substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0020] In some embodiments, the PMOSFET region PR and the NMOSFET region NR may be included in a logic cell region, on which logic transistors constituting the logic circuit of the semiconductor device are disposed. For example, the logic transistors constituting the logic circuit may be disposed on the logic cell region of the substrate 100. Some of the logic transistors may be disposed on the PMOSFET region PR and / or the NMOSFET region NR.

[0021] The PMOSFET region PR and the NMOSFET region NR can be defined by a second trench TR2 formed in the upper portion of the substrate 100. The second trench TR2 can be disposed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR can be spaced apart from each other in a first direction D1 and the second trench TR2 is interposed therebetween. Each of the PMOSFET region PR and the NMOSFET region NR can extend in a second direction D2 that intersects the first direction D1. The first direction D1 can be perpendicular to the second direction D2.

[0022] The PMOSFET region PR may include a first active region PR1, a second active region PR2, and a third active region PR3. The first to third active regions PR1, PR2, and PR3 may be spaced apart from each other in the second direction D2. The absolute value of the threshold voltage of the PMOS transistor in the first active region PR1 may be higher than the absolute value of the threshold voltage of the PMOS transistor in the second active region PR2. The absolute value of the threshold voltage of the PMOS transistor in the second active region PR2 may be higher than the absolute value of the threshold voltage of the PMOS transistor in the third active region PR3.

[0023] A first active pattern AP1 can be provided on the PMOSFET region PR, and a second active pattern AP2 can be provided on the NMOSFET region NR. The first and second active patterns AP1 and AP2 can extend in a second direction D2. The first and second active patterns AP1 and AP2 can be vertically projecting portions of the substrate 100. A first trench TR1 can be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 can be shallower than the second trench TR2.

[0024] The device isolation layer ST can fill the first trench TR1 and the second trench TR2. For example, the device isolation layer ST can include a silicon oxide layer. The upper portions of the first and second active patterns AP1 and AP2 can protrude vertically from the device isolation layer ST (see [link to documentation]). Figure 2C Each of the upper portions of the first and second active patterns AP1 and AP2 may have a fin shape. The device isolation layer ST may not cover the upper portions of the first and second active patterns AP1 and AP2 or may not extend above the upper portions of the first and second active patterns AP1 and AP2. The device isolation layer ST may cover, overlap the sidewalls of the lower portions of the first and second active patterns AP1 and AP2 or extend above the sidewalls of the lower portions of the first and second active patterns AP1 and AP2.

[0025] The upper portion of the first active pattern AP1 of the first active region PR1 may include a first semiconductor pattern SP1. The upper portion of the first active pattern AP1 of the second active region PR2 may include a second semiconductor pattern SP2. The upper portion of the first active pattern AP1 of the third active region PR3 may include a third semiconductor pattern SP3. Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon germanium (SiGe). Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be used as a first channel pattern CH1, which will be described later. In other words, a PMOS transistor according to some embodiments of the present invention may have a channel formed of silicon germanium (SiGe).

[0026] Reference Figure 3 The first semiconductor pattern SP1 is described in detail. The first semiconductor pattern SP1 may also include nitrogen (N) as an impurity. Nitrogen (N) can be diffused into the first semiconductor pattern SP1 during the process of forming the first semiconductor pattern SP1.

[0027] The concentration of nitrogen (N) can gradually decrease from the top surface SP1t of the first semiconductor pattern SP1 to the bottom surface SP1b of the first semiconductor pattern SP1. The concentration of nitrogen (N) at the top surface SP1t of the first semiconductor pattern SP1 can range from 6 atomic percent (at%) to 8 at%, and the concentration of nitrogen (N) at the bottom surface SP1b of the first semiconductor pattern SP1 can be 1 at%. As the distance from the top surface SP1t to the bottom surface SP1b increases, the concentration of nitrogen (N) can decrease from 7 at% to 1 at%.

[0028] The concentration of germanium (Ge) in the first semiconductor pattern SP1 can gradually increase from the top surface SP1t to the bottom surface SP1b of the first semiconductor pattern SP1. The concentration of germanium (Ge) at the top surface SP1t of the first semiconductor pattern SP1 can range from 5 at% to 15 at%, and the concentration of germanium (Ge) at the bottom surface SP1b of the first semiconductor pattern SP1 can be approximately 30 at%. For example, as the distance from the top surface SP1t to the bottom surface SP1b increases, the concentration of germanium (Ge) can increase from 10 at% to 30 at%.

[0029] Refer again Figure 1 and Figures 2A to 2D The nitrogen (N) concentrations of the first to third semiconductor patterns SP1, SP2, and SP3 can be different from each other. Here, the nitrogen (N) concentration can be on the top surface of each of the first to third semiconductor patterns SP1, SP2, and SP3 (e.g., Figure 3 The concentration measured at SP1t.

[0030] Similar to the first semiconductor pattern SP1, the nitrogen (N) concentration in the second semiconductor pattern SP2 gradually decreases from its top surface to its bottom surface. The nitrogen (N) concentration at the top surface of the second semiconductor pattern SP2 can range from 3 at% to 6 at%, and the nitrogen (N) concentration at the bottom surface of the second semiconductor pattern SP2 can be 1 at%.

[0031] Like the first semiconductor pattern SP1, the nitrogen (N) concentration in the third semiconductor pattern SP3 can gradually decrease from its top surface to its bottom surface. The nitrogen (N) concentration at the top surface of the third semiconductor pattern SP3 can range from 0 at% to 4 at%. For example, the third semiconductor pattern SP3 may not contain nitrogen (N).

[0032] The germanium (Ge) concentrations of the first to third semiconductor patterns SP1, SP2, and SP3 can be different from each other. Here, the germanium (Ge) concentration can be on the top surface of each of the first to third semiconductor patterns SP1, SP2, and SP3 (e.g., Figure 3 The concentration measured at SP1(t). The concentration of germanium (Ge) in the first semiconductor pattern SP1 can be lower than the concentration of germanium (Ge) in the second semiconductor pattern SP2. The concentration of germanium (Ge) in the second semiconductor pattern SP2 can be lower than the concentration of germanium (Ge) in the third semiconductor pattern SP3. For example, the concentration of germanium (Ge) in the first semiconductor pattern SP1 can be in the range of 5 at% to 15 at%. The concentration of germanium (Ge) in the second semiconductor pattern SP2 can be in the range of 10 at% to 20 at%. The concentration of germanium (Ge) in the third semiconductor pattern SP3 can be in the range of 20 at% to 30 at%.

[0033] The first to third semiconductor patterns SP1, SP2, and SP3 may be provided in the upper part of the first active pattern AP1. The first to third semiconductor patterns SP1, SP2, and SP3 may not be provided in the upper part of the second active pattern AP2. Therefore, the upper part of the second active pattern AP2 may include silicon (Si).

[0034] A first source / drain pattern SD1 may be provided in the upper part of a first active pattern AP1. The first source / drain pattern SD1 may be a doped region having a first conductivity type (e.g., P-type). A first channel pattern CH1 may be disposed between a pair of first source / drain patterns SD1. The bottom surface of each of the first to third semiconductor patterns SP1, SP2, and SP3 may be lower than the bottom surface of each of the first source / drain patterns SD1. In some embodiments, for example... Figure 2D The first source / drain patterns SD1 adjacent in the first direction D1 can be merged together.

[0035] The second source / drain pattern SD2 can be provided in the upper part of the second active pattern AP2. The second source / drain pattern SD2 can be a doped region having a second conductivity type (e.g., N-type). The second channel pattern CH2 can be disposed between a pair of second source / drain patterns SD2. In some embodiments, such as Figure 2D The adjacent second source / drain patterns SD2 on the first direction D1 can be merged together.

[0036] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include epitaxial patterns formed by a selective epitaxial growth (SEG) process. In some embodiments, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be disposed at substantially the same height as the top surface of each of the first and second channel patterns CH1 and CH2.

[0037] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element of the substrate 100. Therefore, the first source / drain pattern SD1 can provide compressive stress to the first channel pattern CH1. The second source / drain pattern SD2 may include the same semiconductor element as the substrate 100 (e.g., silicon).

[0038] The gate electrode GE may extend in a first direction D1 to intersect with the first and second active patterns AP1 and AP2. The gate electrodes GE may be spaced apart from each other in a second direction D2. The gate electrode GE may perpendicularly overlap with the first and second channel patterns CH1 and CH2 in a third direction D3.

[0039] Refer again Figure 2C The gate electrode GE can be provided on the first top surface TS1 of the first channel pattern CH1 and at least one first sidewall SW1 of the first channel pattern CH1. The gate electrode GE can be provided on the second top surface TS2 of the second channel pattern CH2 and at least one second sidewall SW2 of the second channel pattern CH2. In other words, the transistor according to some embodiments can be a three-dimensional (3D) field-effect transistor (e.g., FinFET), wherein the gate electrode GE surrounds the channels CH1 and CH2 in three dimensions.

[0040] Refer again Figure 1 and Figures 2A to 2DA pair of gate spacers GS can be disposed on the two sidewalls of each gate electrode GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, which will be described later. The gate spacers GS can include at least one of SiCN, SiCON, and SiN. In some embodiments, each gate spacer GS can have a multilayer structure formed of at least two of SiCN, SiCON, and SiN.

[0041] A gate overlay pattern GP can be provided on each gate electrode GE. The gate overlay pattern GP can extend along the gate electrode GE in a first direction Dl. The gate overlay pattern GP can include a material that is etch-selective with respect to the first and second interlayer insulating layers 110 and 120, which will be described later. For example, the gate overlay pattern GP can include at least one of SiON, SiCN, SiCON, and SiN.

[0042] A gate dielectric pattern GI can be disposed between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend along the bottom surface of the gate electrode GE thereon. For example, the gate dielectric pattern GI can cover the top surface and two sidewalls of the first channel pattern CH1. The gate dielectric pattern GI can cover the top surface and two sidewalls of the second channel pattern CH2. The gate dielectric pattern GI can cover the top surface of the device isolation layer ST below the gate electrode GE (see...). Figure 2C ).

[0043] In some embodiments, the gate dielectric pattern GI may include a high-k dielectric material whose dielectric constant is higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0044] In some embodiments, the gate dielectric pattern GI may include a ferroelectric material. A gate dielectric pattern GI including a ferroelectric material can be used as a negative capacitor. Negative capacitance is generated when a change in charge causes a change in the net voltage across the material in the opposite direction. In other words, a decrease in voltage leads to an increase in charge. For example, when an external voltage is applied to a ferroelectric material, a negative capacitance effect caused by a phase transition from an initial polarity state to another state can be generated by the movement of dipoles within the ferroelectric material. In this case, the total capacitance of the transistor including the ferroelectric material in the embodiment can be increased, thus improving the subthreshold swing characteristics of the transistor and reducing the operating voltage of the transistor.

[0045] The ferroelectric material of the gate dielectric pattern GI may include hafnium oxide doped with (or containing) at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). Due to the doping of at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La) in a predetermined proportion, at least a portion of the ferroelectric material may have an orthorhombic crystal structure. When at least a portion of the ferroelectric material has an orthorhombic crystal structure, a negative capacitance effect can be generated. The volume fraction of the portion of the ferroelectric material having an orthorhombic crystal structure can range from 10% to 50%.

[0046] When the ferroelectric material includes zirconium-doped hafnium oxide (ZrHfO), the ratio of Zr atoms to the sum of Zr and Hf atoms (Zr / (Hf+Zr)) can range from 45 at% to 55 at%. When the ferroelectric material includes silicon-doped hafnium oxide (SiHfO), the ratio of Si atoms to the sum of Si and Hf atoms (Si / (Hf+Si)) can range from 4 at% to 6 at%. When the ferroelectric material includes aluminum-doped hafnium oxide (AlHfO), the ratio of Al atoms to the sum of Al and Hf atoms (Al / (Hf+Al)) can range from 5 at% to 10 at%. When the ferroelectric material includes lanthanum-doped hafnium oxide (LaHfO), the ratio of La atoms to the sum of La and Hf atoms (La / (Hf+La)) can range from 5 at% to 10 at%.

[0047] Each gate electrode GE may include a first metal pattern WF1, a second metal pattern WF2, and an electrode pattern EL. The first metal pattern WF1 may be provided on the gate dielectric pattern GI. For example, the gate dielectric pattern GI may be disposed between the first metal pattern WF1 and the first channel pattern CH1.

[0048] The gate dielectric pattern GI and the first metal pattern WF1 can be chamfered (i.e., cut at right angles or corners to form symmetrical sloping edges), so that their upper parts can be lower than the uppermost surface GEt of the gate electrode GE. For example, the first metal pattern WF1 can have a recessed top surface RSt, and the recessed top surface RSt can be lower than the uppermost surface GEt of the gate electrode GE.

[0049] The first metallic pattern WF1 may include a metal nitride with a relatively high work function. The work function is the minimum energy required for a free electron to escape from the surface of a metal. If the material has a high work function, a large amount of energy may be required for electrons to escape from the metal surface. The first metallic pattern WF1 may include a p-type work function metal. For example, the first metallic pattern WF1 may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxide nitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbide nitride (WCN), and / or molybdenum nitride (MoN).

[0050] A second metal pattern WF2 may be provided on a first metal pattern WF1. The second metal pattern WF2 may cover or extend above the recessed top surface RSt of the first metal pattern WF1. The second metal pattern WF2 may include a metal carbide having a relatively low work function. In other words, the second metal pattern WF2 may include an N-type work function metal. The second metal pattern WF2 may include metal carbides doped with (or containing) silicon and / or aluminum. For example, the second metal pattern WF2 may include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), and / or silicon-doped tantalum carbide (TaSiC). For other examples, the second metal pattern WF2 may include aluminum- and silicon-doped titanium carbide (TiAlSiC) or aluminum- and silicon-doped tantalum carbide (TaAlSiC). In yet another example, the second metallic pattern WF2 may include aluminum-doped titanium (TiAl).

[0051] In the second metal pattern WF2, the work function of the second metal pattern WF2 can be adjusted by regulating the doping concentration of silicon or aluminum corresponding to the dopant. For example, the concentration of the dopant (e.g., silicon or aluminum) in the second metal pattern WF2 can be in the range of 0.1 at% to 25 at%.

[0052] Electrode pattern EL can be provided on second metal pattern WF2. The resistance of electrode pattern EL can be lower than the respective resistances of first metal pattern WF1 and second metal pattern WF2. For example, electrode pattern EL can include a low-resistance metal, including at least one of aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

[0053] According to some embodiments of the present invention, the first and second metal patterns WF1 and WF2 may be adjacent to the first channel pattern CH1. The first and second metal patterns WF1 and WF2 can serve as work function metals for adjusting the threshold voltage of the PMOS transistor. In other words, the desired threshold voltage can be obtained by adjusting the thickness and / or composition of each of the first metal pattern WF1 and the second metal pattern WF2.

[0054] The thickness of the first metal pattern WF1 on the second active region PR2 can be greater than the thickness of the first metal pattern WF1 on the first active region PR1. The thickness of the first metal pattern WF1 on the third active region PR3 can be greater than the thickness of the first metal pattern WF1 on the second active region PR2. As discussed herein, the thickness of the first metal pattern WF1 can be the width of the upper portion of the first metal pattern WF1 adjacent to the gate spacer GS in the second direction D2.

[0055] The thickness of the first metal pattern WF1 can increase sequentially from the first active region PR1 to the third active region PR3. In other words, the effective work function (eWF) of the gate electrode GE can increase sequentially from the first active region PR1 to the third active region PR3. Therefore, the absolute value of the threshold voltage of the PMOS transistor can decrease sequentially from the first active region PR1 to the third active region PR3.

[0056] Furthermore, the effective work function of the gate electrode GE can also be adjusted by the concentration of germanium (Ge) in the first to third semiconductor patterns SP1, SP2, and SP3. As the concentration of germanium (Ge) in the semiconductor patterns SP1, SP2, and SP3 increases, the effective work function of the gate electrode GE can increase. Since the concentration of germanium (Ge) in the first to third semiconductor patterns SP1, SP2, and SP3 increases in the listed order, the effective work function of the gate electrode GE can increase sequentially from the first active region PR1 to the third active region PR3. Therefore, the absolute value of the threshold voltage of the PMOS transistor can decrease sequentially from the first active region PR1 to the third active region PR3.

[0057] Specifically, the concentration of germanium (Ge) in the third semiconductor pattern SP3 of the third active region PR3 can be greater than the concentration of germanium (Ge) in the first semiconductor pattern SP1 of the first active region PR1. Furthermore, the thickness of the first metal pattern WF1 on the third active region PR3 can be greater than the thickness of the first metal pattern WF1 on the first active region PR1. The combined effect of the thickness of the first metal pattern WF1 on the third active region PR3 and the concentration of germanium (Ge) in the third semiconductor pattern SP3 can relatively increase the effective work function of the gate electrode GE on the third active region PR3. Conversely, the combined effect of the thickness of the first metal pattern WF1 on the first active region PR1 and the concentration of germanium (Ge) in the first semiconductor pattern SP1 can relatively decrease the effective work function of the gate electrode GE on the first active region PR1. As a result, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 can be much lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.

[0058] A first interlayer insulating layer 110 may be provided on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2, or extend over the gate spacer GS and the first and second source / drain patterns SD1 and SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 and the gate overlay pattern GP. For example, each of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0059] The active contact AC can penetrate the second interlayer insulation layer 120 and the first interlayer insulation layer 110 to electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2. Each active contact AC can be provided between a pair of gate electrodes GE.

[0060] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed as self-aligned using a gate cover pattern GP and a gate spacer GS. For example, the active contact AC can cover, overlap, or extend over at least a portion of the sidewalls of the gate spacer GS. Although not shown in the figures, the active contact AC can also cover or extend over a portion of the top surface of the gate cover pattern GP.

[0061] The silicide pattern SC can be disposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can include metal silicides, and can include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0062] The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the bottom surface and sidewalls of the conductive pattern FM. The barrier pattern BM may include a metal layer / metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, and platinum nitride (PtN) layer.

[0063] A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A first metal layer may be provided in the third interlayer insulating layer 130. The first metal layer may include a first interconnect M1, a first path V1, and a second path V2. The first and second paths V1 and V2 may be provided below the first interconnect M1.

[0064] The first interconnects M1 may extend parallel to each other in the second direction D2. The first interconnects M1 may be arranged in the first direction D1. A first path V1 may be provided between an active contact AC and a corresponding one of the first interconnects M1 to electrically connect the active contact AC to the corresponding one of the first interconnects M1. A second path V2 may be provided between a gate electrode GE and a corresponding one of the first interconnects M1 to electrically connect the gate electrode GE to the corresponding one of the first interconnects M1.

[0065] For example, the first interconnect M1 and the first path V1 or the second path V2 disposed below it can be connected to each other to form a single integral conductive structure. In other words, the first interconnect M1 and the first path V1 or the second path V2 can be formed together. The first interconnect M1 and the first path V1 or the second path V2 can be formed into a single integral conductive structure using a dual damascene process. Although not shown in the figure, a stacked metal layer can additionally be disposed on the third interlayer insulating layer 130.

[0066] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Figure 5A , Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A They are along Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 A cross-sectional view taken from line A-A'. Figure 5B , Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B They are along Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 The cross-sectional view taken by line B-B'. Figure 15C and Figure 17C They are along Figure 14 and Figure 16 The cross-sectional view taken from line C-C'. Figure 15D and Figure 17D They are along Figure 14 and Figure 16 The cross-sectional view taken by line D-D'.

[0067] refer to Figure 4 , Figure 5A and Figure 5B A substrate 100 comprising a PMOSFET region PR and an NMOSFET region NR can be provided. A semiconductor layer SL can be formed on the PMOSFET region PR of the substrate 100. The formation of the semiconductor layer SL may include forming a trench on the PMOSFET region PR of the substrate 100, and performing a selective epitaxial growth (SEG) process on the PMOSFET region PR to form a semiconductor layer SL that fills the trench. The semiconductor layer SL may not be formed on the NMOSFET region NR.

[0068] The semiconductor layer SL may include silicon germanium (SiGe). The concentration of germanium (Ge) in the semiconductor layer SL may range from 20 at% to 30 at%.

[0069] refer to Figure 6 , Figure 7A and Figure 7B A first mask layer ML1 can be formed on the third active region PR3 of the NMOSFET region NR and the PMOSFET region PR. The first mask layer ML1 can expose the first and second active regions PR1 and PR2 of the PMOSFET region PR.

[0070] A first plasma treatment PA1 can be performed on the first and second active regions PR1 and PR2 exposed through the first mask layer ML1. The first plasma treatment PA1 may include an annealing process using hydrogen plasma. The hydrogen plasma can be provided to the semiconductor layer SL on the first active region PR1 and the second active region PR2, i.e., to the exposed semiconductor layer SL. At this time, the native oxide layer (e.g., germanium oxide (GeO) layer) formed on the exposed semiconductor layer SL can be volatilized by the hydrogen plasma treatment and thus removed. In other words, germanium (Ge) on the exposed surface of the semiconductor layer SL can be selectively removed during the first plasma treatment PA1. Although not shown in the figure, by removing germanium (Ge) from the exposed surface of the semiconductor layer SL, a silicon-rich layer can be formed on the exposed surface of the semiconductor layer SL.

[0071] Due to the first plasma treatment PA1, the concentration of germanium (Ge) in the semiconductor layers SL on the first and second active regions PR1 and PR2 can be reduced compared to the concentration of germanium (Ge) in the semiconductor layer SL on the third active region PR3. For example, during the first plasma treatment PA1, the concentration of germanium (Ge) on the exposed surface of the semiconductor layer SL can be reduced by approximately 5 at%. Through the first plasma treatment PA1, germanium (Ge) in the exposed semiconductor layer SL can have a concentration gradient (see...). Figure 3 ).

[0072] In the first plasma treatment PA1, nitrogen (N) can diffuse into the exposed semiconductor layer SL. Nitrogen (N) can be generated from a coating material inside the apparatus used to perform the first plasma treatment PA1. Because nitrogen (N) diffuses into the exposed semiconductor layer SL, a concentration gradient of nitrogen (N) can exist in the exposed semiconductor layer SL (see...). Figure 3 ).

[0073] refer to Figure 8 , Figure 9A and Figure 9B The first mask layer ML1 can be removed. A second mask layer ML2 can be formed on the second and third active regions PR2 and PR3 of the NMOSFET region NR and the PMOSFET region PR. The second mask layer ML2 can expose the first active region PR1 of the PMOSFET region PR.

[0074] A second plasma treatment PA2 can be performed on the first active region PR1 exposed through the second mask layer ML2. The second plasma treatment PA2 may include an annealing process using hydrogen plasma. The second plasma treatment PA2 may be substantially the same as the first plasma treatment PA1 described above.

[0075] Due to the second plasma treatment of PA2, the concentration of germanium (Ge) in the semiconductor layer SL on the first active region PR1 can be reduced compared to the concentration of germanium (Ge) in the semiconductor layer SL on the second active region PR2. For example, during the second plasma treatment of PA2, the concentration of germanium (Ge) on the exposed surface of the semiconductor layer SL can be reduced by approximately 5 at%.

[0076] As a result, the semiconductor layer SL of the first active region PR1, to which the first and second plasma treatments PA1 and PA2 were performed, can have the lowest germanium concentration. The semiconductor layer SL of the third active region PR3, to which the first and second plasma treatments PA1 and PA2 were not performed, can have the highest germanium concentration.

[0077] refer to Figure 10 , Figure 11A and Figure 11B The second mask layer ML2 can be removed. The substrate 100 can be patterned to form first and second active patterns AP1 and AP2. The first active pattern AP1 can be formed on the PMOSFET region PR, and the second active pattern AP2 can be formed on the NMOSFET region NR. A first trench TR1 can be formed between the first active pattern AP1 and between the second active pattern AP2.

[0078] The formation of the first active pattern AP1 may include a patterned semiconductor layer SL to form first to third semiconductor patterns SP1, SP2, and SP3 on the first to third active regions PR1, PR2, and PR3, respectively. In other words, the upper part of the first active pattern AP1 in the first active region PR1 may include the first semiconductor pattern SP1. The upper part of the first active pattern AP1 in the second active region PR2 may include the second semiconductor pattern SP2. The upper part of the first active pattern AP1 in the third active region PR3 may include the third semiconductor pattern SP3.

[0079] The substrate 100 can be patterned to form a second trench TR2 between the PMOSFET region PR and the NMOSFET region NR. The second trench TR2 can be deeper than the first trench TR1.

[0080] A device isolation layer ST may be formed on the substrate 100 to fill the first and second trenches TR1 and TR2. The device isolation layer ST may include an insulating material such as a silicon oxide layer. The device isolation layer ST may be recessed until the upper portions of the first and second active patterns AP1 and AP2 are exposed. Therefore, the upper portions of the first and second active patterns AP1 and AP2 may protrude vertically from the device isolation layer ST. The first to third semiconductor patterns SP1, SP2, and SP3 of the first active pattern AP1 may protrude vertically from the device isolation layer ST.

[0081] refer to Figure 12 , Figure 13A and Figure 13B The sacrificial pattern PP can be formed to intersect with the first and second active patterns AP1 and AP2. The sacrificial pattern PP can have a linear or stripe shape extending in a first direction D1. For example, forming the sacrificial pattern PP can include: forming a sacrificial layer on the entire top surface of the substrate 100; forming a hard mask pattern MA on the sacrificial layer; and using the hard mask pattern MA as an etch mask to pattern the sacrificial layer. The sacrificial layer can include polysilicon.

[0082] A pair of gate spacers GS can be formed on the two sidewalls of each sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer over the entire top surface of the substrate 100 and anisotropically etching the gate spacer layer. For example, the gate spacer layer may include at least one of SiCN, SiCON, and SiN. In some embodiments, the gate spacer layer may be formed from a multilayer comprising at least two of SiCN, SiCON, and SiN.

[0083] refer to Figure 14 and Figures 15A to 15D The first source / drain pattern SD1 can be formed in the upper part of the first active pattern AP1. A pair of first source / drain patterns SD1 can be formed on both sides of each sacrificial pattern PP.

[0084] Specifically, a hard mask pattern MA and a gate spacer GS can be used as an etching mask to etch the upper part of the first active pattern AP1 to form a first recessed region. The device isolation layer ST between the first active patterns AP1 can be recessed during the etching of the upper part of the first active pattern AP1.

[0085] The first source / drain pattern SD1 can be formed by performing a selective epitaxial growth (SEG) process using the inner surface of the first recessed region of the first active pattern AP1 as a seed layer. Since the first source / drain pattern SD1 is formed, a first channel pattern CH1 can be defined between a pair of first source / drain patterns SD1. For example, the SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 can include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element of the substrate 100. In some embodiments, each of the first source / drain patterns SD1 can be formed from multiple stacked semiconductor layers.

[0086] In some embodiments, dopant can be implanted in situ into the first source / drain pattern SD1 during the SEG process for forming the first source / drain pattern SD1. In some embodiments, dopant can be implanted or embedded into the first source / drain pattern SD1 after the SEG process for forming the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped with dopant to have a first conductivity type (e.g., P-type).

[0087] The second source / drain pattern SD2 can be formed in the upper part of the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed on both sides of each sacrificial pattern PP.

[0088] Specifically, the upper portion of the second active pattern AP2 can be etched using a hard mask pattern MA and a gate spacer GS as an etching mask to form a second recessed region. The second source / drain pattern SD2 can be formed by performing a SEG process using the inner surface of the second recessed region of the second active pattern AP2 as a seed layer. Since the second source / drain pattern SD2 is formed, a second channel pattern CH2 can be defined between a pair of second source / drain patterns SD2. For example, the second source / drain pattern SD2 may comprise the same semiconductor element as the substrate 100 (e.g., silicon). The second source / drain pattern SD2 may be doped with a dopant to have a second conductivity type (e.g., N-type).

[0089] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed sequentially using different processes. In other words, the first source / drain pattern SD1 may not be formed simultaneously with the second source / drain pattern SD2.

[0090] refer to Figure 16 and Figures 17A to 17DA first interlayer insulating layer 110 may be formed to cover, overlap, or extend over the first and second source / drain patterns SD1 and SD2, the hard mask pattern MA, and the gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0091] The first interlayer insulating layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. The planarization process of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MA can be completely removed during the planarization process. As a result, the top surface of the first interlayer insulating layer 110 can be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0092] The sacrificial pattern PP can be replaced by the gate electrode GE. More specifically, the exposed sacrificial pattern PP can be selectively removed. Empty spaces can be formed by removing the sacrificial pattern PP. A gate dielectric pattern GI, a gate electrode GE, and a gate cover pattern GP can be formed in each empty space. The gate electrode GE may include a first metal pattern WF1, a second metal pattern WF2, and an electrode pattern EL.

[0093] The first metal pattern WF1 on the second active region PR2 can be formed thicker than the first metal pattern WF1 on the first active region PR1. The first metal pattern WF1 on the third active region PR3 can be formed thicker than the first metal pattern WF1 on the second active region PR2.

[0094] Refer again Figure 1 and Figures 2A to 2D A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. Active contacts AC may be formed in the second and first interlayer insulating layers 120 and 110. The active contacts AC may penetrate the second and first interlayer insulating layers 120 and 110 to be electrically connected to the first and second source / drain patterns SD1 and SD2.

[0095] A third insulating layer 130 may be formed on the second insulating layer 120. A first metal layer may be formed in the third insulating layer 130. The first metal layer may include a first interconnect M1, a first path V1, and a second path V2.

[0096] Figure 18 and Figure 19 It is along Figure 1 A cross-sectional view taken along line A-A' is provided to illustrate a semiconductor device according to some embodiments of the present invention. In this embodiment, for ease of explanation, the details of the connection between the two devices will be omitted. Figure 1and Figures 2A to 2D The description of the same technical features as those in the embodiments is as follows. In other words, the following description will mainly focus on the technical features of this embodiment and... Figure 1 and Figures 2A to 2D Differences between implementation methods.

[0097] refer to Figure 18 The first to third gate dielectric patterns GI1, GI2, and GI3 can be respectively provided on the first to third active regions PR1, PR2, and PR3. The first gate dielectric pattern GI1 can be disposed between the gate electrode GE and the first semiconductor pattern SP1. The second gate dielectric pattern GI2 can be disposed between the gate electrode GE and the second semiconductor pattern SP2. The third gate dielectric pattern GI3 can be disposed between the gate electrode GE and the third semiconductor pattern SP3. The thickness of the first metal pattern WF1 on the first to third active regions PR1, PR2, and PR3 can be equal to each other.

[0098] The first gate dielectric pattern GI1 may include a first dipole. The first dipole may include lanthanum (La). For example, the first gate dielectric pattern GI1 may include a hafnium oxide containing lanthanum (La). The hafnium oxide containing lanthanum (La) in the first gate dielectric pattern GI1 may reduce the effective work function of the gate electrode GE.

[0099] The formation of the first gate dielectric pattern GI1 may include forming a first dipole layer comprising lanthanum oxide on the first gate dielectric pattern GI1, and performing an annealing process on the first dipole layer to diffuse lanthanum into the first gate dielectric pattern GI1. Therefore, a first dipole interface can be formed in the first gate dielectric pattern GI1.

[0100] The third gate dielectric pattern GI3 may include a second dipole. The second dipole may include aluminum (Al). For example, the third gate dielectric pattern GI3 may include a hafnium oxide containing aluminum (Al). The hafnium oxide containing aluminum (Al) in the third gate dielectric pattern GI3 may increase the effective work function of the gate electrode GE.

[0101] The formation of the third gate dielectric pattern GI3 may include forming a second dipole layer comprising aluminum oxide on the third gate dielectric pattern GI3 and performing an annealing process on the second dipole layer to diffuse aluminum into the third gate dielectric pattern GI3. Therefore, a second dipole interface can be formed in the third gate dielectric pattern GI3.

[0102] The second gate dielectric pattern GI2 may not include a dipole. In other words, the second gate dielectric pattern GI2 may include hafnium oxide. The second gate dielectric pattern GI2 may be related to the above-mentioned reference. Figure 1 and Figures 2A to 2DThe gate dielectric pattern GI described is basically the same.

[0103] The combined effect of the germanium (Ge) concentrations of the third gate dielectric pattern GI3 and the third semiconductor pattern SP3 on the third active region PR3 can relatively increase the effective work function of the gate electrode GE on the third active region PR3. Conversely, the combined effect of the germanium (Ge) concentrations of the first gate dielectric pattern GI1 and the first semiconductor pattern SP1 on the first active region PR1 can relatively decrease the effective work function of the gate electrode GE on the first active region PR1. As a result, without changing the thickness of the first metal pattern WF1, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 can be significantly lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.

[0104] refer to Figure 19 The thickness of the first metal pattern WF1 on the first to third active regions PR1, PR2 and PR3 can be equal to each other. However, the materials of the first metal pattern WF1 on the first to third active regions PR1, PR2 and PR3 can be different from each other.

[0105] Specifically, the first metal pattern WF1 on the first active region PR1 may include a first work function metal W1. The first work function metal W1 may be a metal with a relatively low work function. The first work function metal W1 may include titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), and / or tantalum nitride (TaN). The first metal pattern WF1 on the second active region PR2 may include a second work function metal W2. The second work function metal W2 may include titanium nitride (TiN). The first metal pattern WF1 on the third active region PR3 may include a third work function metal W3. The third work function metal W3 may be a metal with a relatively high work function. The third work function metal W3 may include titanium nitride oxide (TiON), tungsten carbide nitride (WCN), and / or molybdenum nitride (MoN).

[0106] The combined effect of the concentrations of the third work function metal W3 on the third active region PR3 and the germanium (Ge) in the third semiconductor pattern SP3 can relatively increase the effective work function of the gate electrode GE on the third active region PR3. Conversely, the combined effect of the concentrations of the first work function metal W1 on the first active region PR1 and the germanium (Ge) in the first semiconductor pattern SP1 can relatively decrease the effective work function of the gate electrode GE on the first active region PR1. As a result, without changing the thickness of the first metal pattern WF1, the absolute value of the threshold voltage of the PMOS transistor on the third active region PR3 can be significantly lower than the absolute value of the threshold voltage of the PMOS transistor on the first active region PR1.

[0107] Figure 20A , Figure 20B and Figure 20C They are along Figure 1 The cross-sectional views taken along lines A-A', C-C', and D-D' illustrate semiconductor devices according to some embodiments of the present invention. In this embodiment, for ease of explanation, details regarding... Figure 1 , Figures 2A to 2D and Figure 18 The description of the same technical features as those in the embodiments is as follows. In other words, the following description will mainly focus on the technical features of this embodiment and... Figure 1 , Figures 2A to 2D and Figure 18 Differences between implementation methods.

[0108] refer to Figure 1 and Figures 20A to 20C A substrate 100 may be provided, comprising a PMOSFET region PR and an NMOSFET region NR. A device isolation layer ST may be provided in the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 in the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be defined on the PMOSFET region PR and the NMOSFET region NR, respectively.

[0109] The upper part of the first active pattern AP1 may include first to third semiconductor patterns SP1, SP2 and SP3. The first to third semiconductor patterns SP1, SP2 and SP3 may be provided on the first to third active regions PR1, PR2 and PR3 of the PMOSFET region PR, respectively.

[0110] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include a vertically stacked first channel pattern CH1. The stacked first channel patterns CH1 may be spaced apart from each other on the third direction D3. The stacked first channel patterns CH1 may overlap each other perpendicularly.

[0111] The second active pattern AP2 may include a vertically stacked second channel pattern CH2. The stacked second channel patterns CH2 may be spaced apart from each other on a third direction D3. The stacked second channel patterns CH2 may overlap each other perpendicularly. The first and second channel patterns CH1 and CH2 may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0112] The first active pattern AP1 may further include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be disposed between a pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1 may connect the pair of adjacent first source / drain patterns SD1.

[0113] The second active pattern AP2 may further include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be disposed between a pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 may connect the pair of adjacent second source / drain patterns SD2.

[0114] The gate electrode GE may extend in a first direction D1 to intersect with the first and second channel patterns CH1 and CH2. The gate electrode GE may overlap perpendicularly with the first and second channel patterns CH1 and CH2. A pair of gate spacers GS may be disposed on the two sidewalls of each gate electrode GE, respectively. A gate overlay pattern GP may be provided on each gate electrode GE.

[0115] The gate electrode GE may be positioned around each of the first and second channel patterns CH1 and CH2 in the first direction D1 and / or the third direction D3 (see...). Figure 20B The gate electrode GE can be provided on a first top surface TS1, at least one first sidewall SW1, and a first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE can be provided on a second top surface TS2, at least one second sidewall SW2, and a second bottom surface BS2 of the second channel pattern CH2. In other words, the gate electrode GE can surround the top surface, bottom surface, and two sidewalls of each of the first and second channel patterns CH1 and CH2. According to some embodiments, the transistor can be a 3D field-effect transistor (e.g., MBCFET), wherein the gate electrode GE surrounds the channel patterns CH1 and CH2 in three dimensions.

[0116] A first gate dielectric pattern GI1 may be provided between the gate electrode GE and the first channel pattern CH1 on the first active region PR1. A second gate dielectric pattern GI2 may be provided between the gate electrode GE and the first channel pattern CH1 on the second active region PR2. A third gate dielectric pattern GI3 may be provided between the gate electrode GE and the first channel pattern CH1 on the third active region PR3. The first to third gate dielectric patterns GI1, GI2, and GI3 may be referenced above. Figure 18 The descriptions are basically the same.

[0117] A first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be provided on the entire top surface of substrate 100. Active contact AC may penetrate the second and first interlayer insulating layers 120 and 110 to connect to the first and second source / drain patterns SD1 and SD2. A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A first metal layer may be provided in the third interlayer insulating layer 130. The first metal layer may include a first interconnect M1, a first path V1, and a second path V2.

[0118] In semiconductor devices according to some embodiments of the present invention, the threshold voltage of a transistor can be adjusted by the combined effect of the thickness of a first metal pattern comprising a P-type work function metal and the concentration of germanium in the channel. According to some embodiments of the present invention, a sufficient difference between the threshold voltages of the transistor can be obtained. According to some embodiments of the present invention, the threshold voltage of the transistor can be adjusted by controlling the impurities in the gate dielectric pattern and / or the type of metal in the first metal pattern.

[0119] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but exemplary. Accordingly, the scope of the inventive concept will be determined by the widest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the above description.

[0120] This application claims priority to Korean Patent Application No. 10-2019-0114081, filed with the Korean Intellectual Property Office on September 17, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The substrate includes a first active region and a second active region; The first active pattern and the second active pattern are respectively located on the first active region and the second active region; A pair of first source / drain patterns and a first channel pattern between the pair of first source / drain patterns, wherein the pair of first source / drain patterns is in the upper part of the first active pattern; A pair of second source / drain patterns and a second channel pattern between the pair of second source / drain patterns, wherein the pair of second source / drain patterns are in the upper part of the second active pattern; as well as The first gate electrode and the second gate electrode intersect with the first channel pattern and the second channel pattern, respectively. Each of the first gate electrode and the second gate electrode includes a first metal pattern adjacent to a corresponding one of the first channel pattern and the second channel pattern. The first and second trench patterns include silicon germanium (SiGe). The germanium (Ge) concentration in the second channel pattern is higher than that in the first channel pattern. Wherein, the thickness of the first metal pattern of the second gate electrode is greater than the thickness of the first metal pattern of the first gate electrode, and The first channel pattern further includes nitrogen (N) as an impurity, and the concentration of nitrogen (N) in the first channel pattern gradually decreases from the top surface of the first channel pattern to the bottom surface of the first channel pattern.

2. The semiconductor device according to claim 1, wherein, The second absolute value of the threshold voltage of the second transistor on the second active region is less than the first absolute value of the threshold voltage of the first transistor on the first active region.

3. The semiconductor device according to claim 1, wherein, The first metal pattern includes a work function metal configured to regulate the threshold voltage of a transistor.

4. The semiconductor device according to claim 1, wherein the first metal pattern comprises titanium nitride (TiN), tantalum nitride (TaN), titanium oxide nitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbide nitride (WCN), and / or molybdenum nitride (MoN).

5. The semiconductor device according to claim 1, further comprising: A third active pattern on the N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region of the substrate; A pair of third source / drain patterns in the upper part of the third active pattern; as well as The third channel pattern between the pair of third source / drain patterns, The first active region and the second active region are included in the P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region of the substrate, and The third channel pattern includes silicon (Si).

6. The semiconductor device according to claim 1, wherein, The concentration of germanium (Ge) in the first channel pattern increases from the top of the first channel pattern to the bottom of the first channel pattern.

7. The semiconductor device according to claim 1, further comprising: Gate dielectric patterns respectively between the first channel pattern and the first gate electrode, and between the second channel pattern and the second gate electrode. The first metal pattern is in direct contact with the gate dielectric pattern.

8. The semiconductor device according to claim 1, further comprising: A device isolation layer in the substrate extends over the lower sidewalls of each of the first and second active patterns. The upper portion of each of the first active pattern and the second active pattern protrudes upward from the top surface of the device isolation layer.

9. The semiconductor device according to claim 1, in, The first channel pattern includes vertically stacked first channel patterns. The second channel pattern includes vertically stacked second channel patterns. The first gate electrode is located on the top surface, bottom surface, and two sidewalls of each first channel pattern, and... The second gate electrode is located on the top surface, bottom surface, and two sidewalls of each second channel pattern.

10. A semiconductor device, comprising: The substrate includes a first active region and a second active region; The first active pattern and the second active pattern are respectively located on the first active region and the second active region; A pair of first source / drain patterns and a first channel pattern between the pair of first source / drain patterns, wherein the pair of first source / drain patterns and the first channel pattern are in the upper part of the first active pattern; A pair of second source / drain patterns and a second channel pattern between the pair of second source / drain patterns, wherein the pair of second source / drain patterns and the second channel pattern are in the upper part of the second active pattern; The first gate electrode and the second gate electrode intersect with the first channel pattern and the second channel pattern, respectively; A first gate dielectric pattern is located between the first gate electrode and the first channel pattern; and A second gate dielectric pattern is located between the second gate electrode and the second channel pattern. The concentration of germanium (Ge) in the first channel pattern differs from the concentration of germanium (Ge) in the second channel pattern. The first gate dielectric pattern includes lanthanum (La) or aluminum (Al), and The first channel pattern further includes nitrogen (N) as an impurity, wherein the concentration of nitrogen (N) in the first channel pattern gradually decreases from the top surface of the first channel pattern to the bottom surface of the first channel pattern.

11. The semiconductor device according to claim 10, in, The first gate dielectric pattern comprises lanthanum (La), and The concentration of germanium (Ge) in the second channel pattern is higher than that in the first channel pattern.

12. The semiconductor device according to claim 10, in, The first gate dielectric pattern comprises aluminum (Al), and The concentration of germanium (Ge) in the first channel pattern is higher than that in the second channel pattern.

13. The semiconductor device according to claim 10, in, The first gate dielectric pattern comprises a hafnium oxide containing lanthanum (La) or aluminum (Al), and The second gate dielectric pattern includes hafnium oxide.

14. The semiconductor device according to claim 10, wherein, The first threshold voltage of the first transistor on the first active region is different from the second threshold voltage of the second transistor on the second active region.

15. A semiconductor device, comprising: The substrate includes P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) regions and N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) regions spaced apart from each other in a first direction; The first active pattern and the second active pattern are respectively on the P-type metal-oxide-semiconductor field-effect transistor region and the N-type metal-oxide-semiconductor field-effect transistor region, and the first active pattern and the second active pattern extend in a second direction that intersects the first direction. A device isolation layer on the substrate extends over the lower sidewall of each of the first active pattern and the second active pattern, wherein the upper portion of each of the first active pattern and the second active pattern protrudes upward from the top surface of the device isolation layer, and the upper portion of the first active pattern includes a semiconductor pattern. A pair of first source / drain patterns in the upper part of the first active pattern; A pair of second source / drain patterns in the upper part of the second active pattern; The gate electrode intersects the first active pattern and the second active pattern and extends in the first direction; A gate dielectric pattern is located between the gate electrode and the first active pattern and between the gate electrode and the second active pattern. Active contacts, electrically connected to the first source / drain pattern and the second source / drain pattern; and Interconnects are provided on the active contact and electrically connected to the active contact and the gate electrode. The semiconductor pattern of the first active pattern includes silicon germanium (SiGe). The semiconductor pattern of the first active pattern further includes nitrogen (N) as an impurity. The concentration of germanium (Ge) in the semiconductor pattern increases from the top surface to the bottom surface of the semiconductor pattern. The concentration of nitrogen (N) in the semiconductor pattern gradually decreases from the top surface of the semiconductor pattern to the bottom surface of the semiconductor pattern.

16. The semiconductor device according to claim 15, wherein, The upper portion of the second active pattern comprises silicon (Si).

17. The semiconductor device according to claim 15, wherein, The gate electrode includes: A first metal pattern is formed on the first active pattern and the second active pattern; A second metal pattern on the first metal pattern; and Electrode patterns on the second metal pattern The first metal pattern includes a P-type work function metal, and The second metal pattern includes an N-type work function metal.

18. The semiconductor device according to claim 15, wherein, The bottom surface of the semiconductor pattern is lower than the bottom surface of the first source / drain pattern.

19. The semiconductor device according to claim 15, wherein, The gate dielectric pattern is in direct contact with the top surface of the semiconductor pattern.

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