Level conversion circuit

Abstract

The present invention provides a level conversion circuit, comprising a level conversion unit and a duty cycle unit. The level conversion unit comprises an input node, an output node for outputting an output signal having a desired level, an adjustment input node, and an adjustment output node for adjusting the duty cycle of the output signal. The duty cycle unit is coupled between the adjustment input node and the adjustment output node. The duty cycle unit is configured to adjust the duty cycle of the output signal. In the level conversion circuit of the present invention, the level conversion unit is configured to output an output signal having a desired level. By coupling the duty cycle unit to the level conversion unit, the duty cycle of the output signal can be effectively adjusted without changing the size ratio of the level conversion unit, thereby improving the output signal quality.

Description

Technical field

[0001] The present invention relates to the technical field of integrated circuit chips, and in particular to a level conversion circuit. [Background Technology]

[0002] In semiconductor integrated circuits, circuit signals are not very stable during power-up or power-down. Especially when using multiple power domains, the asynchronous power-up or power-down timing of each power domain can easily lead to uncontrollable circuit signals. This situation is particularly obvious in level conversion circuits, which directly leads to errors in the output signal of the level conversion circuit and may cause large leakage problems, damaging related devices.

[0003] The level conversion circuit includes a high-voltage level conversion circuit and a low-voltage level conversion circuit. The high-voltage level conversion circuit converts the low-voltage signal into a high-voltage signal, thereby realizing the control of the low-voltage logic over the high-voltage logic; the low-voltage level conversion circuit converts the high-voltage signal into a low-voltage signal, thereby realizing the control of the high-voltage logic over the low-voltage logic.

[0004] The conventional level shifting circuit consists of four high-voltage transistors: two high-voltage PMOS transistors for pull-up and two high-voltage NMOS transistors for pull-down. The gates of the two high-voltage NMOS transistors serve as the two inputs of the level shifting circuit, with the input voltage at a low voltage potential. The drains of the two high-voltage PMOS transistors serve as the two outputs of the level shifting circuit, with the output voltage at a high voltage potential. Because the two high-voltage NMOS transistors operate at a low voltage, their pull-down capability is very weak. When the low voltage drops below a certain level, the level shifting circuit ceases to operate, meaning that the level shifting function cannot be achieved. Furthermore, the timing difference between the rising and falling edges of the converted signal is significant, resulting in an unreasonable duty cycle for the converted signal. [Summary of the invention]

[0005] The object of the present invention is to provide a level conversion circuit to improve the quality of output signals.

[0006] To achieve the above-mentioned objectives, the present invention provides a level conversion circuit, comprising a level conversion unit and a duty cycle unit; the level conversion unit comprises: an input node, an output node for outputting an output signal having a desired level, an adjustment input node, and an adjustment output node for adjusting the duty cycle of the output signal; the duty cycle unit is coupled between the adjustment input node and the adjustment output node; and the duty cycle unit is configured to adjust the duty cycle of the output signal.

[0007] Preferably, the system further comprises a feedback unit, which is coupled between the adjustment input node and the output node; the feedback unit is used to perform feedback compensation on the output signal.

[0008] Preferably, an enabling unit is further included, wherein the output end of the enabling unit is connected to the regulating input node; the enabling unit is used to control the operation of the level conversion unit.

[0009] Preferably, the system further comprises a second inverter and a third inverter; the input end of the second inverter is connected to the output node, and the output end of the second inverter is connected to the input end of the third inverter.

[0010] Preferably, the feedback unit includes an NMOS transistor.

[0011] Preferably, the enabling unit includes a PMOS transistor.

[0012] Preferably, the second inverter and the third inverter each include a PMOS transistor and an NMOS transistor connected in series between the first power supply and the ground terminal.

[0013] The beneficial effects of the present invention are as follows: providing a level conversion circuit, wherein the level conversion unit is used to output an output signal with a desired level, and by coupling a duty cycle unit in the level conversion unit, the duty cycle of the output signal is effectively adjusted without changing the size ratio of the level conversion unit, thereby improving the output signal quality.

Brief Description of the Drawings

[0014] Figure 1 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention;

[0015] Figure 2 1 is a circuit diagram of a level conversion circuit according to another embodiment of the present invention;

[0016] Figure 3 1 is a circuit diagram of a level conversion circuit according to another embodiment of the present invention;

[0017] Figure 4 FIG. 4 is a circuit diagram of a level conversion circuit according to another embodiment of the present invention. [Specific implementation method]

[0018] In order to make the purpose, technical solutions and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with the specific embodiments of this specification and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this specification. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0019] The terms "first," "second," and "third," etc., in the specification and claims of the present invention and the accompanying drawings are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "comprise," "comprising," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0020] An embodiment of the present invention provides a level conversion circuit, including a level conversion unit and a duty cycle unit.

[0021] The level conversion unit includes: an input node, an output node for outputting an output signal with a desired level, an adjustment input node, and an adjustment output node for adjusting the duty cycle of the output signal; the duty cycle unit is coupled between the adjustment input node and the adjustment output node.

[0022] The duty cycle unit is used to adjust the duty cycle of the output signal.

[0023] The level conversion circuit of the present invention has a level conversion unit for outputting an output signal having a desired level. By coupling a duty cycle unit in the level conversion unit, the duty cycle of the output signal is effectively adjusted without changing the size ratio of the level conversion unit, thereby improving the output signal quality.

[0024] In one embodiment, the level conversion unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter.

[0025] The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the input node, the source of the first PMOS transistor is connected to the first power supply, the drain of the first PMOS transistor is connected to the source of the third PMOS transistor, the gate of the third PMOS transistor is connected to the output node, the drain of the third PMOS transistor and the drain of the first NMOS transistor are connected to the regulation input node, and the source of the first NMOS transistor is connected to the ground terminal.

[0026] The gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the reverse input node, the source of the second PMOS transistor is connected to the first power supply, the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the regulation output node, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are connected to the output node, and the source of the second NMOS transistor is connected to the ground terminal.

[0027] The first inverter is connected in series between the input node and the reverse input node, and is powered by a second power supply. The first inverter includes a PMOS transistor and an NMOS transistor connected in series between the second power supply and a ground terminal.

[0028] In one embodiment, the duty cycle unit includes a first buffer, which adjusts the duty cycle of the output signal by delaying, wherein the first buffer is powered by a first power supply.

[0029] In one embodiment, the level conversion circuit further includes a feedback unit for performing feedback compensation on the output signal, and the feedback unit is coupled between the adjustment input node and the output node.

[0030] Preferably, the feedback unit includes a fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the regulation input node; the source of the fifth NMOS transistor is connected to the ground terminal; and the drain of the fifth NMOS transistor is connected to the output node. By providing the feedback unit, feedback compensation can be performed on the output signal when multiple power supplies are used, avoiding the phenomenon of incorrect high and low level outputs from the output node.

[0031] In one embodiment, the level conversion circuit further includes an enabling unit for controlling the operation of the level conversion unit, wherein an output terminal of the enabling unit is connected to the adjustment input node. When the enabling unit is valid, the input signal of the level conversion unit is shielded, thereby disabling the level conversion unit from operating.

[0032] Preferably, the enabling unit includes a seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the enable signal of the level conversion circuit, the source of the seventh PMOS transistor is connected to the first power supply, and the drain of the seventh PMOS transistor is connected to the regulation input node. When the enable signal is at a low level, the input signal of the level conversion unit is shielded, and the level conversion circuit cannot operate; when the enable signal is at a high level, the level conversion circuit operates normally.

[0033] Based on the above embodiments, the level conversion circuit further includes a second inverter and a third inverter; the input of the second inverter is connected to the output node, and the output of the second inverter is connected to the input of the third inverter. By adding two stages of inverters, the output signal can be shaped, further improving the output signal quality.

[0034] Preferably, the second inverter includes a fifth PMOS transistor and a third NMOS transistor connected in series between the first power supply and the ground terminal, the gate of the fifth PMOS transistor and the gate of the third NMOS transistor are connected as the input terminal of the second inverter connected to the output node, the drain of the fifth PMOS transistor and the drain of the third NMOS transistor are connected as the output terminal of the second inverter connected to the input terminal of the third inverter; the source of the fifth PMOS transistor is connected to the first power supply, and the source of the third NMOS transistor is connected to the ground terminal.

[0035] Preferably, the third inverter includes a sixth PMOS transistor and a fourth NMOS transistor connected in series between the first power supply and the ground terminal, the gate of the sixth PMOS transistor and the gate of the fourth NMOS transistor are connected as the input terminal of the third inverter and the output terminal of the second inverter, the drain of the sixth PMOS transistor and the drain of the fourth NMOS transistor are connected as the output terminal of the third inverter; the source of the sixth PMOS transistor is connected to the first power supply, and the source of the fourth NMOS transistor is connected to the ground terminal.

[0036] like Figure 1 As shown, the level conversion circuit provided by the embodiment of the present invention includes a level conversion unit and a duty cycle unit; the level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, an adjustment input node A and an adjustment output node B.

[0037] The level conversion unit is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2 and a first inverter I1.

[0038] The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the input node IN, the source of the first PMOS transistor P1 is connected to the first power supply VDDH, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3, the gate of the third PMOS transistor P3 is connected to the output node OUT, the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1 are connected to the regulation input node A, and the source of the first NMOS transistor N1 is connected to the ground terminal GND.

[0039] The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the inverting input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, the drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the regulated output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor P2 are connected to the output node OUT, and the source of the second NMOS transistor N2 is connected to the ground terminal GND.

[0040] The first inverter I1 is connected in series between the input node IN and the inverting input node INB, and the first inverter I1 is powered by the second power supply VDDL; wherein, the first inverter I1 includes a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are connected as the input end of the first inverter I1, and the input end of the first inverter I1 is connected to the input node IN; the drain of the PMOS transistor and the drain of the NMOS transistor are connected as the output end of the first inverter I1, and the output end of the first inverter I1 is connected to the inverting input node INB; the source of the PMOS transistor is connected to the second power supply VDDL, and the source of the NMOS transistor is connected to the ground end GND.

[0041] The duty cycle unit includes a first buffer BUF1 , which is coupled between an adjustment input node A and an adjustment output node B and is powered by a first power supply VDDH. The duty cycle of the output signal is adjusted by delaying the first buffer BUF1 .

[0042] Specifically, when the input node IN is at a high level, the first NMOS transistor N1 is turned on, and the drain of the first NMOS transistor N1 is at a low level. This low level is transmitted through the first buffer BUF1 to turn on the fourth PMOS transistor P4. Furthermore, the high level of the input node IN is inverted by the first inverter I1 (the inverted input node is at a low level), turning on the second PMOS transistor P2. Because the signal transmission path of the input signal to the gate of the second PMOS transistor P2 is shorter than the signal transmission path of the input signal to the gate of the fourth PMOS transistor P4, the low-level gate signal of the second PMOS transistor P2 arrives earlier than the low-level gate signal of the fourth PMOS transistor P4. Therefore, the rising edge time of the output signal at the output node OUT is controlled by the delay of the first buffer BUF1. The rising edge time of the output signal directly affects the duty cycle, thereby achieving the purpose of adjusting the duty cycle of the output signal and improving the output signal quality without changing the size of the transistors in the level conversion unit.

[0043] The output node OUT of the level conversion unit is the total output node of the level conversion circuit.

[0044] The first power supply VDDH can be configured to 3.3V or 5V according to circuit applications; the second power supply VDDL can be configured to 1.2V, 1.35V, 1.5V, or 1.8V according to circuit applications.

[0045] like Figure 2 As shown, the level conversion circuit provided by the embodiment of the present invention includes a level conversion unit, a duty cycle unit and a feedback unit; the level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, an adjustment input node A and an adjustment output node B.

[0046] The level conversion unit is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2 and a first inverter I1.

[0047] The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the input node IN, the source of the first PMOS transistor P1 is connected to the first power supply VDDH, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3, the gate of the third PMOS transistor P3 is connected to the output node OUT, the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1 are connected to the regulation input node A, and the source of the first NMOS transistor N1 is connected to the ground terminal GND.

[0048] The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the inverting input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, the drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the regulated output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2 are connected to the output node OUT, and the source of the second NMOS transistor N2 is connected to the ground terminal GND.

[0049] The first inverter I1 is connected in series between the input node IN and the inverting input node INB, and the first inverter I1 is powered by the second power supply VDDL; wherein, the first inverter I1 includes a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are connected as the input end of the first inverter I1, and the input end of the first inverter I1 is connected to the input node IN; the drain of the PMOS transistor and the drain of the NMOS transistor are connected as the output end of the first inverter I1, and the output end of the first inverter I1 is connected to the inverting input node INB; the source of the PMOS transistor is connected to the second power supply VDDL, and the source of the NMOS transistor is connected to the ground end GND.

[0050] The duty cycle unit includes a first buffer BUF1 , which is coupled between an adjustment input node A and an adjustment output node B and is powered by a first power supply VDDH. The duty cycle of the output signal is adjusted by delaying the first buffer BUF1 .

[0051] The feedback unit includes a fifth NMOS transistor N5 , a gate of the fifth NMOS transistor N5 is connected to the regulation input node A, a drain of the fifth NMOS transistor N5 is connected to the output node OUT, and a source of the fifth NMOS transistor N5 is connected to the ground terminal GND.

[0052] Specifically, the first PMOS transistor P1, the third PMOS transistor P3, and the first NMOS transistor N1 of the level conversion unit are symmetrical with the second PMOS transistor P2, the fourth PMOS transistor P4, and the second NMOS transistor N2. That is, the drain level of the first NMOS transistor N1 and the drain level of the second NMOS transistor N2 are opposite. When the power-on or power-off timing of multiple power supplies is asynchronous, the feedback unit will perform feedback compensation on the output signal so that the output node OUT outputs a level signal with a determined high or low state.

[0053] like Figure 3 As shown, the level conversion circuit provided by the embodiment of the present invention includes a level conversion unit, a duty cycle unit, a feedback unit and an enable unit; the level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, an adjustment input node A and an adjustment output node B.

[0054] The level conversion unit is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2 and a first inverter I1.

[0055] The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the input node IN, the source of the first PMOS transistor P1 is connected to the first power supply VDDH, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3, the gate of the third PMOS transistor P3 is connected to the output node OUT, the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1 are connected to the regulation input node A, and the source of the first NMOS transistor N1 is connected to the ground terminal GND.

[0056] The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the inverting input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, the drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the regulated output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2 are connected to the output node OUT, and the source of the second NMOS transistor N2 is connected to the ground terminal GND.

[0057] The first inverter I1 is connected in series between the input node IN and the inverting input node INB, and the first inverter I1 is powered by the second power supply VDDL; wherein, the first inverter I1 includes a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are connected as the input end of the first inverter I1, and the input end of the first inverter I1 is connected to the input node IN; the drain of the PMOS transistor and the drain of the NMOS transistor are connected as the output end of the first inverter I1, and the output end of the first inverter I1 is connected to the inverting input node INB; the source of the PMOS transistor is connected to the second power supply VDDL, and the source of the NMOS transistor is connected to the ground end GND.

[0058] The duty cycle unit includes a first buffer BUF1 , which is coupled between an adjustment input node A and an adjustment output node B and is powered by a first power supply VDDH. The duty cycle of the output signal is adjusted by delaying the first buffer BUF1 .

[0059] The feedback unit includes a fifth NMOS transistor N5 , a gate of the fifth NMOS transistor N5 is connected to the regulation input node A, a drain of the fifth NMOS transistor N5 is connected to the output node OUT, and a source of the fifth NMOS transistor N5 is connected to the ground terminal GND.

[0060] The enabling unit includes a seventh PMOS transistor P7 , a gate of the seventh PMOS transistor P7 connected to the enable signal EN, a source of the seventh PMOS transistor P7 connected to the first power supply VDDH, and a drain of the seventh PMOS transistor P7 connected to the regulation input node A.

[0061] When the enable signal EN is at a low level, the seventh PMOS transistor P7 is turned on and pulls up the gate of the fifth NMOS transistor N5, thereby pulling down the drain of the fifth NMOS transistor N5, and the output node OUT is at a low level. After passing through two stages of inverters, the output of the level conversion circuit is at a low level. At this time, regardless of whether the input node IN is at a high level or a low level, the output signal is always at a low level. When the enable signal EN is at a high level, the seventh PMOS transistor P7 is turned off and does not operate, and does not shield the input signal of the input node IN. At this time, the level conversion circuit operates normally.

[0062] like Figure 4 As shown, the level conversion circuit provided by the embodiment of the present invention includes a level conversion unit, a duty cycle unit, a feedback unit, an enabling unit, a second inverter and a third inverter;

[0063] The level conversion unit includes an input node IN, an inverting input node INB, an output node OUT, a regulation input node A, and a regulation output node B.

[0064] The level conversion unit is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2 and a first inverter I1.

[0065] The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the input node IN, the source of the first PMOS transistor P1 is connected to the first power supply VDDH, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3, the gate of the third PMOS transistor P3 is connected to the output node OUT, the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor N1 are connected to the regulation input node A, and the source of the first NMOS transistor N1 is connected to the ground terminal GND.

[0066] The gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are connected to the inverting input node INB, the source of the second PMOS transistor P2 is connected to the first power supply VDDH, the drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the regulated output node B, the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor N2 are connected to the output node OUT, and the source of the second NMOS transistor N2 is connected to the ground terminal GND.

[0067] The first inverter I1 is connected in series between the input node IN and the inverting input node INB, and the first inverter I1 is powered by the second power supply VDDL; wherein, the first inverter I1 includes a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are connected as the input end of the first inverter I1, and the input end of the first inverter I1 is connected to the input node IN; the drain of the PMOS transistor and the drain of the NMOS transistor are connected as the output end of the first inverter I1, and the output end of the first inverter I1 is connected to the inverting input node INB; the source of the PMOS transistor is connected to the second power supply VDDL, and the source of the NMOS transistor is connected to the ground end GND.

[0068] The duty cycle unit includes a first buffer BUF1 , which is coupled between an adjustment input node A and an adjustment output node B and is powered by a first power supply VDDH. The duty cycle of the output signal is adjusted by delaying the first buffer BUF1 .

[0069] The feedback unit includes a fifth NMOS transistor N5 , a gate of the fifth NMOS transistor N5 is connected to the regulation input node A, a drain of the fifth NMOS transistor N5 is connected to the output node OUT, and a source of the fifth NMOS transistor N5 is connected to the ground terminal GND.

[0070] The enabling unit includes a seventh PMOS transistor P7 , a gate of the seventh PMOS transistor P7 connected to the enable signal EN, a source of the seventh PMOS transistor P7 connected to the first power supply VDDH, and a drain of the seventh PMOS transistor P7 connected to the regulation input node A.

[0071] The input terminal of the second inverter is connected to the output node OUT, and the output terminal of the second inverter is connected to the input terminal of the third inverter. By adding two stages of inverters, the output signal can be shaped, further improving the output signal quality.

[0072] The second inverter I2 includes a fifth PMOS transistor P5 and a third NMOS transistor N3. The gate of the fifth PMOS transistor P5 is connected to the gate of the third NMOS transistor N3, serving as the input of the second inverter I2 and connected to the output node OUT. The drain of the fifth PMOS transistor P5 is connected to the drain of the third NMOS transistor N3, serving as the output of the second inverter I2 and connected to the input of the third inverter I3. The source of the fifth PMOS transistor P5 is connected to the first power supply VDDH, and the source of the third NMOS transistor N3 is connected to the ground terminal GND.

[0073] The third inverter I3 includes a sixth PMOS transistor P6 and a fourth NMOS transistor N4. The gate of the sixth PMOS transistor P6 and the gate of the fourth NMOS transistor N4 are connected to serve as the input of the third inverter I3 and are connected to the output of the second inverter I2. The drain of the sixth PMOS transistor P6 and the drain of the fourth NMOS transistor N4 are connected to serve as the output of the third inverter I3. The source of the sixth PMOS transistor P6 is connected to the first power supply VDDH, and the source of the fourth NMOS transistor N4 is connected to the ground GND.

[0074] The output end of the third inverter I3 is the total output node OUT′ of the level conversion circuit.

[0075] The level conversion unit working process of the embodiment of the present invention is as follows:

[0076] When the input signal at the input node IN is at a low level, the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off. The input signal (low level) becomes high level after passing through the first inverter I1. This high level turns off the second PMOS transistor P2 and turns on the second NMOS transistor N2. As a result, the drain of the second NMOS transistor N2 is at a low level (pulled low), which in turn turns on the third PMOS transistor P3. The drain of the third PMOS transistor P3 is at a high level (pulled high). After passing through the first buffer BUF1, the fourth PMOS transistor P4 is turned off, further ensuring that the drain of the second NMOS transistor N2 is at a low level. After passing through the two-stage inverter (I2, I3), the total output node OUT' is at a low level.

[0077] When the input signal at the input node IN is high, the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on. The input signal (high) is turned off after passing through the first inverter I1. This low level turns on the second PMOS transistor P2 and turns off the second NMOS transistor N2. The first NMOS transistor N1 is turned on, and the drain of the first NMOS transistor N1 is at a low level (pulled low), which in turn turns off the fifth NMOS transistor N5. The fourth PMOS transistor P4 is turned on through the first buffer BUF1, so that the drain of the fourth PMOS transistor P4 is at a high level (pulled high). This high level, in turn, turns off the third PMOS transistor P3 and ensures that the drain of the first NMOS transistor N1 is at a low level (pulled low). After the high level of the drain of the fourth PMOS transistor P4 passes through two stages of inverters (I2, I3), the overall output node OUT' is at a high level.

[0078] When the enable signal EN is at a low level, the seventh PMOS transistor P7 is turned on and pulls up the gate of the fifth NMOS transistor N5, thereby pulling down the drain of the fifth NMOS transistor N5, and the output node OUT is at a low level. After passing through two stages of inverters, the output of the level conversion circuit is at a low level. At this time, regardless of whether the input node IN is at a high level or a low level, the output signal is always at a low level. When the enable signal EN is at a high level, the seventh PMOS transistor P7 is turned off and does not operate, and does not shield the input signal of the input node IN. At this time, the level conversion circuit operates normally.

[0079] The first PMOS transistor P1, the third PMOS transistor P3, and the first NMOS transistor N1 of the level conversion unit are symmetrical with the second PMOS transistor P2, the fourth PMOS transistor P4, and the second NMOS transistor N2. That is, the drain level of the first NMOS transistor N1 and the drain level of the second NMOS transistor N2 are opposite. When the power-on or power-off timing of multiple power supplies is asynchronous, the feedback unit will perform feedback compensation on the output signal so that the output node OUT outputs a level signal with a determined high or low state.

[0080] When the input node IN is at a high level, the first NMOS transistor N1 is turned on, and the drain of the first NMOS transistor N1 is at a low level. This low level is transmitted through the first buffer BUF1 to turn on the fourth PMOS transistor P4. Furthermore, the high level of the input node IN is inverted by the first inverter I1 (the inverting input node is at a low level), turning on the second PMOS transistor P2. Because the signal transmission path of the input signal to the gate of the second PMOS transistor P2 is shorter than the signal transmission path of the input signal to the gate of the fourth PMOS transistor P4, the low-level gate signal of the second PMOS transistor P2 arrives earlier than the low-level gate signal of the fourth PMOS transistor P4. Therefore, the rising edge time of the output signal at the output node OUT is controlled by the delay of the first buffer BUF1. The rising edge time of the output signal directly affects the duty cycle, thereby achieving the purpose of adjusting the duty cycle of the output signal and improving the output signal quality without changing the size of the transistors in the level conversion unit.

[0081] The above description is only an embodiment of the present invention. It should be pointed out that those skilled in the art can make improvements without departing from the creative concept of the present invention, but these improvements all fall within the scope of protection of the present invention.

Claims

1. A level conversion circuit, characterized in that: including a level conversion unit and a duty cycle unit; The level conversion unit includes: an input node, an output node for outputting an output signal with a desired level, an adjustment input node, and an adjustment output node for adjusting a duty cycle of the output signal; The duty cycle unit is coupled between the regulation input node and the regulation output node; The duty cycle unit includes a first buffer for delaying the signal input from the adjustment input node and outputting it from the adjustment output node to adjust the duty cycle of the output signal; The level conversion unit further includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter and a reverse input node; The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the input node, the source of the first PMOS transistor is connected to a first power supply, the drain of the first PMOS transistor is connected to the source of a third PMOS transistor, the gate of the third PMOS transistor is connected to the output node, the drain of the third PMOS transistor and the drain of the first NMOS transistor are connected to the regulation input node, and the source of the first NMOS transistor is connected to the ground terminal; The gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the inverting input node, the source of the second PMOS transistor is connected to the first power supply, the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the regulated output node, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor are connected to the output node, and the source of the second NMOS transistor is connected to the ground terminal; The first inverter is connected in series between the input node and the inverting input node, and the first inverter is powered by a second power supply.

2. The level conversion circuit according to claim 1, wherein: Also included is a feedback unit, the feedback unit being coupled between the adjustment input node and the output node; The feedback unit is used to perform feedback compensation on the output signal.

3. The level conversion circuit according to claim 2, wherein: It also includes an enabling unit, wherein the output end of the enabling unit is connected to the regulating input node; The enabling unit is used to control the operation of the level conversion unit.

4. The level conversion circuit according to claim 3, wherein: It also includes a second inverter and a third inverter; the input end of the second inverter is connected to the output node, and the output end of the second inverter is connected to the input end of the third inverter.

5. The level conversion circuit according to claim 4, wherein: The feedback unit includes an NMOS tube.

6. The level conversion circuit according to claim 4, wherein: The enabling unit includes a PMOS tube.

7. The level conversion circuit according to claim 4, wherein: The second inverter and the third inverter each include a PMOS transistor and an NMOS transistor connected in series between the first power supply and the ground terminal.

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