Apparatus and method for chopper instrumentation amplifier

Abstract

Embodiments of the present invention relate to apparatus and methods for a chopper instrumentation amplifier. For various applications, such as testing the resistance of connections between layers of a memory, it may be desirable to provide a high gain instrumentation amplifier. A chopper instrumentation amplifier may provide high gain while allowing for a variety of common input voltages and canceling out offsets on the amplifier. An example chopper instrumentation amplifier of the present invention may include a plurality of amplifiers including a chopper amplifier and a non-chopper amplifier. The chopper amplifier may use a chopper circuit to cancel out the offset voltage of the amplifier. A low pass filter may be used to minimize the effects of the chopper amplifier.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 16 / 052,586, filed August 1, 2018, which is incorporated herein by reference in its entirety for all purposes. Background Art

[0003] A differential amplifier is a circuit used to amplify the difference between the two input voltages of the amplifier. An example of a differential amplifier is an operational amplifier ("op-amp") that receives a non-inverting input (V+) and an inverting input (V-) and outputs a single-ended output (Vout). Feedback between the output and the inverting input can be used to control the gain of the circuit.

[0004] An instrumentation amplifier may be a circuit that uses a main amplifier to amplify a differential signal and one or more additional amplifiers as input buffers. Instrumentation amplifiers may be used to test electronic devices. In one example application, an instrumentation amplifier may be used to measure the resistance of a connection between semiconductor dies or chips of a semiconductor memory device (e.g., through silicon / substrate vias, TSVs).

[0005] Figure 1 1 is a schematic diagram of a prior art instrumentation amplifier. The instrumentation amplifier 100 includes a first amplifier 102 coupled to a second amplifier 104. The first amplifier 102 includes two operational amplifiers OP1 and OP2. The outputs of OP1 and OP2 are coupled through resistors R21, R1, and R22, which are coupled in series from the output of OP1 to the output of OP2. The inverting input of OP1 is coupled between resistors R21 and R1, and the inverting input of OP2 is coupled between R1 and R22. The non-inverting input of OP1 is coupled to an input voltage INp, and the non-inverting input of OP2 is coupled to an input voltage INn. The output of OP1 serves as an input IA1p to the second amplifier 104, and the output of OP2 serves as an input IA1n to the second amplifier 104. The operational amplifiers OP1 and OP2 can serve as input buffers on the inputs INp and INn, respectively.

[0006] The second amplifier 104 includes an operational amplifier OP3. The input IA1p is coupled to ground via a resistor R31 and a variable resistor R41 coupled in series. The non-inverting input of OP3 is coupled between R31 and R41. The input IA1n is coupled to the output of OP3 via resistors R32 and R42 coupled in series. The inverting input of OP3 is coupled between R32 and R42. The resistors R21 and R22 have equal resistances to each other. The resistors R31 and R32 have equal resistances, and the variable resistor R41 has a default resistance equal to the resistor R42.

[0007] The first amplifier 102 receives voltages INp and INn as inputs and provides voltages IA1p and IA1n as outputs. The input voltages can be expressed as a common voltage Vcom (equal voltages across the differential inputs) and a differential signal amplitude Vin. Therefore, the input voltage INp can be expressed as Vcom+(1 / 2)*Vin, and the voltage at Inn can be expressed as Vcom-(1 / 2)*Vin. Based on this, the output voltages V(1A1p) and V(1A1n) can be calculated by the following equations 1 and 2:

[0008]

[0009] R2 is the value of resistors R21 and R22, which have equal resistance to each other. VOS1 and VOS2 are offset voltages that may be present on the input voltages INp and INn of the non-inverting inputs of the operational amplifiers OP1 and OP2, respectively. Figure 1 The voltages VOS1 and VOS2 shown in FIG. 1 may have opposite polarities to each other. The difference Vdif between the two outputs V(1A1p) and V(1A1n) may be derived by subtracting Equation 2 from Equation 1 to produce the following Equation 3:

[0010]

[0011] According to the above equations, the amplification factor (gain) Acom1 of the common voltage Vcom and the amplification factor A1 of the differential signal Vin can be determined by the following equations 4 and 5:

[0012] Acom1=1Equation 4

[0013]

[0014] Therefore, since the shared gain Acom1 is 1, the common voltage between the differential inputs INp and INn will not increase, while the differential voltage Vin will increase by a factor based on the values ​​of R2 and R1. The second amplifier 104 receives as input the amplified output provided by the first amplifier 102. The common input voltage between the inputs IA1p and IA1n remains at Vcom because Acom1 of the first amplifier 102 is 1. If the difference between the offset voltages VOS1 and VOS2 is assumed to be negligible (e.g., VOS1≈VOS2), then the voltage of IA1p is Vcom+(1 / 2)*Vdif, while the voltage of IA1n is Vcom-(1 / 2)*Vdif. Therefore, the voltage Vout provided by the second amplifier 104 can be estimated by the following equation 6:

[0015]

[0016] In Equation 6, the values ​​of resistors R31 and R32 are assumed to be equal to R3. The value of resistor R42 is equal to R4. The adjustable resistor R41 has an initial value R4 that is trimmed to offset the offset. The above equation assumes that resistor R41 is trimmed by a percentage Δ of its value, and that Δ is much less than 1. VOS3 is the offset voltage of the third operational amplifier OP3. By dividing the above equation, the common amplification Acom2 and the differential amplification A2 of the second amplifier 104 can be determined as:

[0017]

[0018]

[0019] Based on the above equations, the overall output of the instrumentation amplifier 100 can be determined by the following equation 9:

[0020] VOUT≈Vin·A1·A2+(VOS1+VOS2)A1·A2+VOS3(1+A2)+Vcom·Acom2

[0021] Equation 9

[0022] The output depends on the amplification of the signal (e.g., Vin*A1*A2) and the offset error term depends on VOS1, VOS2, and VOS3. The second and third terms of Equation 9 (e.g., the offset error term) can be offset by adjusting the trim percentage Δ to cancel the offset error in the output. However, in order to adjust the trim percentage, the input common mode voltage Vcom must be set to a known predetermined value.

[0023] Figure 2 A prior art adjustable resistor 200 is shown. In some embodiments, the adjustable resistor 200 can be used as Figure 1 The adjustable resistor 200 may include an input node IN, an output node OUT, a number of resistors R1 to R10 (labeled here using their resistance values, e.g., 200k, 300k, etc.), and switches SW0 to SW7. Although specific values ​​for the resistors are shown, it should be understood that the adjustable resistor 200 may be configured using many different values ​​of the resistors R1 to R10. Similarly, the adjustable resistor 200 may have more or fewer switches than the eight switches SW0 to SW7 shown.

[0024] Switches SW0 to SW7 may be sequentially activated by a counter (not shown) to reduce the resistance of the adjustable resistor 200. In the example adjustable resistor 200 shown, the adjustable resistor 200 has a default resistance of 500k due to the values ​​of R1 and R2 (e.g., 200k and 300k) in series between the input and output nodes (IN and OUT, respectively). As switches SW0 to SW7 are sequentially activated, the value of the adjustable resistor 200 may be reduced from -3% to -24% in eight stages. Although the example adjustable resistor 200 only shows a reduction in resistance from a default value, additional resistors and switches may be added in series between the input node IN and the output node OUT to allow the resistance of the adjustable resistor 200 to be increased.

[0025] The adjustable resistor 200 may be optimized for a particular application. For example, when used to fine-tune an instrumentation amplifier (e.g., Figure 1 When the amplifier 100 is used, the step width (e.g., the number of steps between the maximum resistance and the minimum resistance) and the value of the maximum resistance and the minimum resistance can be optimized. The adjustable resistor 200 can be operated by a counter, which can be responsive to the output of the amplifier 100 to automatically determine the amount of fine adjustment required to offset the offset error of the amplifier 100.

[0026] Figure 3 Shows a graph indicating the operating characteristics of an instrumentation amplifier. Figure 3 A diagram 300 is included that illustrates an instrumentation amplifier (eg Figure 1 The operating characteristics of the instrumentation amplifier 100 for two different gain configurations of the instrumentation amplifier are shown in FIG. The x-axis of the graph 300 is the output voltage Vout of the amplifier. The y-axis of the graph 300 is the common voltage Vcom between the differential inputs. The graph 300 illustrates the Figure 1 100 is configured to provide a high gain, in this case a gain of 100. The dashed line shows a scenario where a total gain of 100 is achieved by setting the gain of the first amplifier 102 and the second amplifier 104 to 10 (e.g., by selecting resistor values). The solid line shows a scenario where a total gain of 100 is achieved by setting the gain of the first amplifier 102 to 100 and the gain of the second amplifier 104 to 1.

[0027] Instrumentation amplifiers, such as amplifier 100, can be used to test various circuit components. If a known current is used, the instrumentation amplifier can measure the voltage in order to determine the resistance of the circuit component, for example, to check for manufacturing defects and / or damage to the component. The amplifier may need to have sensitivity to small resistance changes. While increasing the gain of the amplifier can increase small changes in the signal, it can also prevent easy cancellation of offsets and narrow the common voltage range in which the instrumentation amplifier can operate stably. There remains a need for a high gain instrumentation amplifier that can properly cancel offsets and operate stably while keeping the range of input common mode voltages wide. Summary of the invention

[0028] In at least one aspect, the present invention relates to an instrumentation amplifier comprising a pair of input terminals, first and second intermediate nodes, and an output terminal. The instrumentation amplifier further comprises a first amplifier stage coupled between the pair of input terminals and the first intermediate node. The first amplifier stage may comprise a first chopper amplifier. The instrumentation amplifier further comprises a second amplifier stage coupled between the first intermediate node and the second intermediate node. The second amplifier stage may comprise a second chopper amplifier. The instrumentation amplifier may further comprise a third amplifier stage coupled between the second intermediate node and the output terminal. The third amplifier stage may comprise a non-chopper amplifier. The gain of the first amplifier stage may be greater than the gain of the third amplifier stage, and the gain of the second amplifier stage may be greater than the gain of the third amplifier stage.

[0029] The gain of the third amplifier stage may be approximately 1. The first amplifier stage may also further include a first low pass filter (LPF) circuit coupled to the output of the first chopper amplifier, and the second amplifier stage may also further include a second LPF circuit coupled to the output of the second chopper amplifier. The pair of input terminals may include a first input terminal and a second input terminal, and the first chopper amplifier may include a first sub-chopper amplifier and a second sub-chopper amplifier. The first sub-chopper amplifier may be coupled to the first input terminal, and the second sub-chopper amplifier may be coupled to the second input terminal.

[0030] The instrumentation amplifier may also include at least one additional amplifier stage inserted between the second amplifier stage and the third amplifier stage. The at least one additional amplifier stage may include a third chopper amplifier. The gain of the at least one additional amplifier stage may be greater than the gain of the third amplifier stage. The gain of the third amplifier stage may be approximately 1 and the gains of the first amplifier stage, the second amplifier stage, and the at least one additional amplifier stage may be approximately equal to each other. The first chopper amplifier and the second chopper amplifier may each include at least one chopper circuit. The instrumentation amplifier may also include a buffer circuit that can provide a bias voltage coupled to the second amplifier stage and the third amplifier stage.

[0031] In at least one aspect, the present invention relates to an apparatus comprising a first input and a second input, a first chopper circuit, a main amplifier, a sub-amplifier, and an output stage. The first chopper circuit may be coupled to the first input and the second input and may provide a first chopped input and a second chopped input. The main amplifier may include a first main input coupled to the first chopped input, a second main input coupled to the second chopped input, a first main intermediate node and a second main intermediate node, a main amplifier output, and a second chopper circuit coupled between the output and the first main intermediate node and the second main intermediate node. The voltage at the first main intermediate node may be substantially equal to the voltage at the second main intermediate node. The sub-amplifier may be coupled to the first main intermediate node and the second main intermediate node. The sub-amplifier may include a first sub-intermediate node and a second sub-intermediate node and a third chopper circuit coupled to the first sub-intermediate node and the second sub-intermediate node. The voltage at the first sub-intermediate node may be substantially equal to the voltage at the second sub-intermediate node. The output of the third chopper circuit may be coupled to the main amplifier. The output stage may be coupled to the main amplifier output and configured to provide an output voltage.

[0032] The first chopper circuit, the second chopper circuit, and the third chopper circuit each include a chopper switch. The first chopper circuit, the second chopper circuit, and the third chopper circuit can each switch a pair of input signals between a pair of output terminals. The first chopper circuit, the second chopper circuit, and the third chopper circuit can each switch at a frequency determined by a clock signal coupled to the chopper circuit. The first chopper circuit can modulate the signal and the second chopper circuit and the third chopper circuit can demodulate the signal. The sub-amplifier can keep the voltage on the first main intermediate node substantially equal to the voltage on the second main intermediate node.

[0033] In at least one aspect, the invention relates to a method that may include: modulating a signal using a first chopper circuit; amplifying the modulated signal; demodulating the signal using a second chopper circuit; and filtering the demodulated signal using a low pass filter.

[0034] The method may also include synchronizing the first chopper circuit and the second chopper circuit with a clock signal. The method may also include synchronizing the low pass filter with a second clock signal based on the clock signal. The second clock signal may have a delayed activation compared to the clock signal. After filtering the demodulated signal, the method may also further include amplifying the filtered signal. The demodulating the signal may include canceling an offset of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a prior art instrumentation amplifier.

[0036] Figure 2 is a schematic diagram of an adjustable resistor in the prior art.

[0037] Figure 3 is a graphical representation of the operating characteristics of an instrumentation amplifier.

[0038] Figure 4 is a schematic diagram of a chopper instrumentation amplifier according to an embodiment of the present invention.

[0039] Figure 5 is a schematic diagram of a chopper instrumentation amplifier according to an embodiment of the present invention.

[0040] Figure 6 is a schematic diagram of a non-chopper amplifier according to an embodiment of the present invention.

[0041] Figure 7 is a schematic diagram of a chopper amplifier according to an embodiment of the present invention.

[0042] Figure 8 is a schematic diagram of a chopper circuit according to an embodiment of the present invention.

[0043] Fig. 9 is a schematic diagram of a low-pass filter according to an embodiment of the present invention.

[0044] Fig.10 is a timing diagram of signals used to operate a chopper instrumentation amplifier in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following description of specific embodiments is merely exemplary in nature and is not intended to limit the present invention or its application or use in any way. In the following implementation of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part of the present invention and are shown by the description of specific embodiments of the described system and method in which they can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments can be utilized and that structural and logical changes can be made without departing from the spirit and scope of the present invention. In addition, for the sake of clarity, when specific features are understood by those skilled in the art, detailed descriptions of specific features will not be discussed to avoid obscuring the description of embodiments of the present invention. Therefore, the following embodiments should not be understood in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0046] An example application of an instrumentation amplifier will be described in order to illustrate the advantages of the instrumentation amplifier of the present invention. Although a specific application will be described, it should be understood that the present invention can be used in many applications in various fields and that minimal changes can be made to optimize the amplifier for other applications without departing from the present invention.

[0047] In particular, an example application of the instrumentation amplifier of the present invention is to test the connection between layers of a semiconductor memory device. Different layers may be coupled through silicon / substrate through vias (TSVs), which may be conductive elements extending vertically between layers (e.g., stacked dies) of a semiconductor memory device (e.g., dynamic random access memory DRAM). The TSVs may be tested to determine whether they have sufficient conductivity (e.g., low resistance), and if they have a resistance below a threshold, they pass the test. A predetermined current Im may flow through one or more TSVs, which may produce a voltage drop Vm across the TSVs in response to the resistance along the TSVs. Because both the current Im and the potential resistance of the TSVs may be smaller, the voltage Vm may also be smaller. Therefore, it may be necessary to amplify the voltage for reliable measurement / detection.

[0048] Conventional instrumentation amplifiers (e.g. Figure 1The amplifier 100 of the instrumentation amplifier (100) may have several limitations when used in this application. As an example, if the current Im is 200 μA and the gain of the instrumentation amplifier is 25, then the amplifier may produce an output voltage of 1V based on a resistance of 200Ω on the TSV. If the pass / fail determination is set to an output level of 0.5V, then a maximum resistance of 100Ω or more along the TSV may be detected accordingly. However, it should be noted that the designed resistance of a single TSV may be about 0.1Ω. Therefore, even a large number (e.g., about 8) of stacked TSVs may still have a total resistance of less than 1Ω. Therefore, a conventional instrumentation amplifier with a detection limit of 100Ω may be too high for sensitive detection of resistance along the TSV. In this application (TSV testing), it may be impractical to increase the current Im because this will also increase the voltage Vm and the common-mode voltage on the amplifier. Therefore, it may be necessary to increase the gain of the amplifier. However, conventional instrumentation amplifiers may not be suitable for large gains (e.g., gains above about 25).

[0049] Conventional instrumentation amplifiers (e.g. Figure 1 The instrumentation amplifier 100 of FIG. 100 uses an adjustable resistor (eg, resistor 41) to cancel the offset voltage. If the gain of the amplifier is greatly increased, then the assumption Δ<<1 of equation 7 does not hold, and equation 8 becomes equation 10 again, as follows:

[0050]

[0051] Therefore, increasing the overall gain of the circuit results in a scenario where the adjustable resistor both cancels the offset and adjusts the gain of the circuit. This makes the circuit unsuitable for precise measurement of resistance. Furthermore, the offset cannot be precisely adjusted unless the common mode voltage Vcom is constant.

[0052] By reference Figure 3 Another problem with increasing the gain of a conventional instrumentation amplifier can be seen in the graph 300 of FIG. The solid and dashed lines each enclose a region of the operating range of the amplifier as the gain for a given configuration. The two configurations have the same overall gain, but have different distributions of gain between the two stages of the circuit (e.g., the first amplifier 102 and the second amplifier 104). Outside of the lines, the voltage between the first and second amplifiers (e.g., voltages IA1p and IA1n) will exceed the rail voltages (e.g., Vdd and Vss) supplied to the instrumentation amplifier. Any portion of the waveform that would exceed the rail voltages will be maximized and 'clipped' at these levels, distorting the waveform shape and resulting in undesirable output characteristics.

[0053] Conventional instrumentation amplifiers (e.g. Figure 1The instrumentation amplifier 1) is used to cancel the offset by introducing a chopper circuit. However, this can lead to a larger problem because the chopper circuit introduces a rectangular wave with an amplitude based on a gain factor multiplied by the offset source VOS. As an example, consider an amplifier with a total gain of 100, where both the first amplifier 102 and the second amplifier 104 have a gain of 10. If the input amplitude Vin=5mV and the input offset voltage VOS1=VOS2=VOS3=5mV, then both the outputs IA1p and IA1n have a rectangular wave superimposed with ±150mV. Since the amplification factor Acom2 is 2, the output of the second amplifier 104 can be a rectangular wave with an amplitude of 1.055V and a common voltage of 0.5V. However, since one of the rails of the system can be set to ground (e.g., 0V), it can be seen that the rectangular output wave will be severely deformed due to the rail voltage. This can lead to undesired changes in the output signal, even if the rectangular wave is removed later (e.g., using low-pass filtering).

[0054] The chopper instrumentation amplifier may be a high gain instrumentation amplifier that can cancel the offset voltage and still operate stably within a wide range of common mode input voltages. The chopper instrumentation amplifier may include multiple amplifier stages with chopper amplifiers. The chopper amplifier may include a chopper circuit to cancel the offset voltage by modulating the signal, and remove the square wave imposed by the chopper circuit by demodulating with subsequent switches. A low pass filter may be coupled to the output of one or more chopper amplifiers to remove the square wave that may be imposed by the chopper amplifier. The final amplifier stage may include a non-chopper amplifier without a chopper circuit.

[0055] Figure 4 A chopper instrumentation amplifier according to an embodiment of the present invention is shown. The chopper instrumentation amplifier 400 may include a first chopper amplifier 401 coupled to a pair of inputs IN1 and IN2. The first chopper amplifier 401 provides an output to a first intermediate node N1, which may be an input to a second chopper amplifier 402. The second chopper amplifier 402 provides an output to a second intermediate node N2, which may be an input to a non-chopper amplifier 404. The non-chopper amplifier 404 provides an output signal OUT. In some embodiments, the chopper instrumentation amplifier 400 may also include low pass filters (LPFs) 406a-b, which may be coupled between the outputs of the chopper amplifiers 401, 402 and their respective intermediate nodes N1 and N2. In some embodiments, the chopper instrumentation amplifier 400 may include additional amplifiers, such as a third chopper amplifier between the second chopper amplifier 402 and the non-chopper amplifier 404.

[0056] The chopper amplifier 401 can amplify the signal across inputs IN1 and IN2 to generate an output on a first node. The first chopper amplifier can include a chopper circuit to offset the offset between inputs IN1 and IN2. The chopper circuit can also impose a square wave on the output provided by the first chopper amplifier. The first chopper amplifier can be configured to amplify the signal instead of amplifying the imposed square wave so that the rectangular wave has a smaller effect on the amplified signal. The low-pass filter 406a can filter the signal to remove all or part of the imposed rectangular wave. The low-pass filter 406a can be a separate component between the first chopper amplifier 401 and the first intermediate node N1 or can be integrated in the first chopper amplifier 401.

[0057] The second chopper amplifier 402 and the low pass filter 406b can generally operate in the same manner as the first chopper amplifier 401 and the low pass filter 406a. Similar to the low pass filter 406a, the low pass filter 406a can be a separate component, or can be integrated into the second chopper amplifier 402. The chopper amplifier 402 can receive a second input from the first chopper amplifier 401, or can receive an external input. In one embodiment, the external input can be a constant voltage, such as a bias voltage. The first chopper amplifier 401 and the second chopper amplifier 402 can each include one or more chopper sub-amplifiers. The chopper sub-amplifier can include a chopper circuit.

[0058] The non-chopper amplifier 404 can amplify the signal provided on the second intermediate node N2 to provide an output signal OUT. The non-chopper amplifier 404 can be a differential amplifier and can receive a second input signal. The second input signal can be provided from the second chopper amplifier 402. In some embodiments, the second input signal can be an external input and can be the same external input as the external input of the second chopper amplifier 402. The non-chopper amplifier 404 can include one or more non-chopper sub-amplifiers. The non-chopper sub-amplifiers can be substantially similar to the chopper sub-amplifiers of the chopper amplifiers 401, 402, except that the non-chopper sub-amplifiers do not include chopper circuits.

[0059] Although Figure 4 4. The chopper amplifiers 401 and 402 and the non-chopper amplifier 404 may be coupled to a supply voltage. The supply voltage may be provided by components external to the chopper instrumentation amplifier 400. In some examples, the chopper instrumentation amplifier 400 may be coupled to a device for testing (e.g., a memory device for testing TSVs) and the supply voltage may be provided by a power supply for the device. The supply voltage may be a high voltage (e.g., Vdd) and a low voltage (e.g., Vss, ground). Each amplifier may be coupled to a supply voltage individually, or they may be coupled to a common rail.

[0060] The chopper circuits and low pass filters 406a-b of chopper amplifiers 401 and 402 may be coupled to a clock signal. Chopper amplifiers 401 and 402 may be coupled to the chopper clock signal, and the low pass filter may be coupled to the LPF clock signal. The chopper clock signal and the LPF clock signal may be synchronized with each other. The chopper clock signal may include a pair of complementary clock signals, and the LPF clock signal may include a pair of clock signals each synchronized to one of the complementary clock signals. The clock signal may be generated and provided externally from the chopper instrumentation amplifier 400 (e.g., by a clock circuit).

[0061] The chopper instrumentation amplifier 400 may have an overall gain A, which may be a combination of the individual gains of each of the amplifiers 401, 402, and 404. For example, the first chopper amplifier has a gain A1, the second chopper amplifier 402 has a gain A2, and the non-chopper amplifier 404 has a gain A4. Since the amplifiers are coupled in series, the overall gain may be the product of the gains (e.g., A=A1*A2*A4). In some examples, the gain of the non-chopper amplifier 404 may be less than the gains of the chopper amplifiers 401 and 402. In some embodiments, the gain of the non-chopper amplifier 404 may be approximately 1.

[0062] Figure 5 A chopper instrumentation amplifier 500 is shown in accordance with an embodiment of the invention. The chopper instrumentation amplifier (CIA) 500 may receive differential inputs INp and INn and provide an output OUT. The chopper instrumentation amplifier 500 may include a first amplifier 501, a second amplifier 502, a third amplifier 503, and a fourth amplifier 504. The chopper instrumentation amplifier 500 may also include a buffer circuit 508 that couples a bias voltage Vbiascom to the second, third, and fourth amplifiers 502-503. The first, second, and third amplifiers 501-503 may be chopper amplifiers, while the fourth amplifier may be a non-chopper amplifier. In some embodiments, the CIA 500 may be Figure 4 An implementation of a chopper instrumentation amplifier 400 is provided.

[0063] The first amplifier 501 receives input voltages INp and INn and provides differential outputs LP1p and LP1n to a first intermediate node. The second amplifier 502 is coupled to the first intermediate node and provides an output LP2out to a second intermediate node. The third amplifier 503 is coupled to the second intermediate node and provides an output LP3out to a third intermediate node. The fourth amplifier 504 is coupled to the third intermediate node and provides an output voltage OUT.

[0064] Each of the amplifiers 501 to 504 may include one or more sub-amplifiers. The fourth amplifier 504 and the buffer circuit 508 may include a symmetric operating point self-biased amplifier (SOS amplifier). The SOS amplifier is a differential amplifier similar to an operational amplifier and will Figure 6 The first, second, and third amplifiers 501 to 503 may include chopper switch SOS amplifiers (CSOS amplifiers), which may be generally similar to SOS amplifiers but include chopper circuits. The CSOS amplifiers and chopper circuits are respectively Figure 7 and 8 The CSOS amplifier may function similarly to an operational amplifier, however, a chopper circuit may be used to offset the input offset voltage to the CSOS amplifier. The CIA 500 may also include Fig. 9 The low pass filter (LPF) described in detail in FIG. 1 removes the rectangle superimposed by the chopper circuit. The LPF can act as Figure 4 Low pass filters 406a to b. Figure 5 In the example of FIG. 5 , the LPF is integrated into the amplifiers 501 to 503 rather than as Figure 4 The individual components shown in .

[0065] The first amplifier 501 is coupled to input voltages INp and INn. The input voltage INp is coupled to the non-inverting input of the CSOS amplifier CSOS1, and the input voltage INn is coupled to the non-inverting input of the amplifier CSOS2. The outputs of CSOS1 and CSOS2 may be coupled together through resistors R21, R1, and R22 coupled in series between the outputs. The inverting input of CSOS1 may be coupled between resistors R21 and R1, and the inverting input of CSOS2 may be coupled between R1 and R22. The output of CSOS1 is coupled in series to the non-inverting inputs of LPF1 and CSOS3. The output of CSOS2 is coupled in series to the non-inverting inputs of LPF2 and CSOS4. CSOS3 provides an output voltage LP1p, which is coupled to the inverting input of CSOS3 and provided as the output of the amplifier 501. CSOS4 provides an output voltage LP1n, which is coupled to the inverting input of CSOS4 and provided as the output voltage of the first amplifier 501.

[0066] The first amplifier 501 amplifies the differential input potential (eg, the difference between INp and INn) using a gain A1d, which can be calculated by Equation 11 as follows:

[0067]

[0068] Assume that resistors R21 and R22 have equal resistances to each other, which is equal to R2. The first amplifier has a common-mode amplification A1C (e.g., amplification of the voltage shared across INp and INn) (e.g., A1C=1). Because amplifiers CSOS1 and CSOS2 include chopper circuits, the input offset voltages on CSOS1 and CSOS2 are canceled. However, a rectangular wave having an amplitude equal to the input offset voltage multiplied by A1d (see equation 11) is superimposed on the outputs of CSOS1 and CSOS2. Low-pass filters LPF1 and LPF2 can be used to reduce or remove the rectangular wave from the outputs of CSOS1 and CSOS2. Amplifiers CSOS3 and CSOS4 are used as voltage followers to boost the current along the outputs LP1p and LP1n. Therefore, a rectangular wave using the input offset voltage of CSOS3 and CSOS4 as part of its amplitude remains superimposed on the outputs LP1n and LP1p, but the rectangular wave is not amplified by the first amplifier, and therefore, may have a negligible effect on the second amplifier 502.

[0069] The second amplifier 502 receives the outputs LP1p and LP1n provided by the first amplifier 501 as inputs. The second amplifier 502 also receives a bias voltage Vbiascom provided by a buffer circuit 508. The buffer circuit 508 may act as a voltage follower and may be an SOS amplifier SOS2. The non-inverting input of SOS2 is coupled to the voltage Vbiascom, and the output Vbiascom is coupled to the inverting input of SOS2. The input LP1p is coupled to Vbiascom through two resistors R31 and R41 coupled in series. The non-inverting input of the amplifier CSOS5 is coupled between R31 and R41. The input LP1n is coupled to the low pass filter LPF3 via two resistors R32 and R42 in series. The inverting input of CSOS5 is coupled between R32 and R42. The output of CSOS5 is coupled between R42 and LPF3. LPF3 provides a filtered output to the non-inverting input of the amplifier CSOS6, and the amplifier CSOS6 outputs a voltage LP2out coupled back to the inverting input of CSOS6. The second amplifier 502 provides a voltage Vbiascom as a first output voltage and provides LP2out as a second output voltage.

[0070] The second amplifier 502 amplifies the difference between the inputs LP1p and LP1n by a gain A2d given by the following equation 12:

[0071]

[0072] Resistors R41 and R42 have equal values ​​of R4, and resistors R31 and R32 have equal values ​​of R3. If there is no differential voltage between the inputs (e.g., LP1p-LP1n=0), the output of the chopper amplifier CSOS5 is the bias voltage Vbiascom. In the scenario, the input offset voltage of CSOS5 is amplified by a gain of A2os, which is given by the following equation 13:

[0073]

[0074] The amplified input offset voltage is superimposed on the output of CSOS5 as a rectangular wave. Low pass filter LP3 can remove the amplified input offset voltage. Amplifier CSOS6 can be used as a voltage follower to drive the current on the output. The rectangular wave applied by the chopper circuit of CSOS6 is superimposed on the output voltage LP2out. However, since this wave is not amplified, its effect on the third amplifier 503 can be negligible.

[0075] The third amplifier 503 receives the output Vbiascom and LP2out of the second amplifier 502 as inputs. The third amplifier 503 can couple Vbiascom to Lp2out with two resistors R61 and R51 coupled in series. The chopper amplifier CSOS7 can have a non-inverting input coupled between R61 and R51. The amplifier CSOS7 can provide an output, which is coupled to the low pass filter LPF4 and is also coupled to Vbiascom via two resistors R62 and R52 coupled in series. The inverting input of CSOS7 is coupled between R52 and R62. The filtered output of the low pass filter LPF4 is coupled to the non-inverting input of the chopper amplifier CSOS8, which provides an output voltage LP3out. The inverting input of CSOS8 is coupled to the output LP3out. The third amplifier 503 provides bias voltages Vbiascom and LP3out as outputs.

[0076] The third amplifier 503 can be substantially similar to the second amplifier 502, except that the third amplifier 503 has a chopper amplifier CSOS7, in which both the inverting input and the non-inverting input are coupled to the bias voltage Vbiascom (via resistors R52 and R61, respectively). The input of the chopper amplifier CSOS7 is the difference between Vbiascom and LP2out, and the output is expressed by a differential gain A3d given by the following equation 14:

[0077]

[0078] In the third amplifier 503, resistors R61 and R62 may have a value equal to R6, while resistors R51 and R52 may have a value equal to R5. The common mode voltage output by the third amplifier may be Vbiascom. The chopper amplifier CSOS7 provides an output with a superimposed rectangular wave having an amplitude determined by the input offset voltage of CSOS7 and amplified by a gain of A3os given by the following equation 15:

[0079]

[0080] In order to remove this amplified rectangular wave, the output of the chopper amplifier CSOS7 is provided to a low-pass filter LPF4, which separates the rectangular wave from the amplified signal. The low-pass filter LPF4 then provides the separated amplified signal to a second chopper amplifier CSOS8 that acts as a voltage follower. The chopper amplifier CSOS8 also applies a rectangular wave to the output signal, which is however not amplified and therefore can have a negligible effect on the fourth amplifier 504.

[0081] The fourth amplifier 504 receives the output Vbiascom and LP3out of the third amplifier as inputs. The fourth amplifier 504 can couple the input voltage LP3out to ground through resistors R72 and R82 coupled in series. The non-inverting input of the amplifier SOS1 is coupled between resistors R72 and R82. The amplifier SOS1 provides an output OUT, which is coupled to the input Vbiascom via two resistors R81 and R71 coupled in series. The inverting input of the amplifier is coupled between resistors R71 and R81. The output voltage OUT is provided as the output of the fourth amplifier 504.

[0082] The fourth amplifier 504 may have a differential gain of Ad4, which is applied to the potential difference between LP3out and Vbiascom and is given by the following Equation 16:

[0083]

[0084] In the fourth amplifier 504, resistors R71 and R72 may have a value equal to R7, and resistors R81 and R82 may have a value of R8. The fourth amplifier may provide a common mode voltage of 0V. Amplifier SOS1 may not include a chopper circuit and may increase the input offset by a gain of A4os given by the following equation 17:

[0085]

[0086] The amplified offset voltage provided by amplifier SOS1 may be maintained as an error in the output voltage OUT. The superimposed (unamplified) rectangular wave superimposed on LP3out by the voltage follower CSOS8 of the third amplifier 503 may be maintained on the output voltage OUT. However, the superimposed rectangular wave may be of small magnitude compared to the signal on the output voltage OUT and may be a 'ripple' on the signal.

[0087] Thus, in general, amplifier 500 receives differential inputs INp and INn and amplifies them by a total differential gain A to provide an output voltage OUT. The total differential gain A can be found by multiplying the differential gain of each of amplifiers 501 to 504 and is given by the following equations 18 and 19:

[0088] A=A1d*A2d*A3d*A4d Equation 18

[0089]

[0090] From Equation 19, it can be seen that the total amplification of the differential signal is determined by the selected resistor values ​​R1 to R8. These values ​​can be selected based on the desired application and desired operating characteristics of the amplifier. In some embodiments, the gain of each of the stages (amplifiers 501 to 504) can be kept low. By keeping the gain of each stage low, the amplitude of the rectangular wave caused by the input offset voltage is also kept relatively low. This prevents the waveform of the amplifier 500 from reaching the rail voltage (e.g., Vdd and Vss) and deforming the waveform. The low-pass filter (e.g., LPF1 to LPF4) and the voltage follower (e.g., CSOS3, CSOS4, CSOS6, and CSOS8) can reduce the output ripple imposed by the first three stages 501 to 503 to an amount equivalent to the input offset of each voltage follower. This can reduce the risk of the waveform being deformed by the subsequent stages of the chopper instrumentation amplifier 500.

[0091] The allowable common-mode voltage (e.g., the range of common-mode voltages that do not cause any deformation of the waveform due to chopping on the rail voltage) of the chopper instrumentation amplifier 500 can span nearly the full range of the rail voltage (e.g., from approximately Vdd to approximately ground). The low gain of the first stage 501 can be dispersed by the low gain of the subsequent stages 502-503.

[0092] In one example, the total gain A may be approximately 125. In other examples, higher or lower total gains are possible. In an example where the total gain A is 125, the resistor values ​​R1 to R8 may be set so that A1d=5, A2d=5, A3d=5, and A4d=1. In other examples, other gains and other gain distributions between amplifiers 501 to 504 may be used. The gain of the final stage may be set to 1 (e.g., A4d=1), which allows the error voltage to be close to 0V, since the output waveform and its deformation are not increased by the fourth amplifier 504. In this example, the input common mode voltage may be between Vdd*(1 / 50) and Vdd*(1-1 / 50). Therefore, in this configuration, the range of common mode voltages may be allowed to be between 98% of Vdd and 2% of Vdd. In other examples, the gain of the final stage (e.g., the fourth amplifier 504) may be greater than 1.

[0093] As an example application of the chopper instrumentation amplifier 500, the chopper instrumentation amplifier 500 can be used to amplify the voltage Vm from the TSV test. The chopper instrumentation amplifier 500 can be configured as previously described, so that the gain of amplifiers 501 to 503 is 5, and the gain of amplifier 504 is 1. If the maximum input offset of the CIA 500 is assumed to be 10mV, then the input offset appearing at the output is 20mV (10mV*A4os=10mV*2). The 20mV offset is the result of the input offset of the amplifier SOS1 of the fourth amplifier 504. When the offset is converted to the input, the offset error equivalent value can be found to be 160μV (20mV / 125). Only a rectangular wave with an amplitude of a maximum of 10mV is superimposed, so that the output ripple containing the error caused by the superposition is an offset of 240μV (30mV / 125) converted to the input. In the TSV test scenario, a current of 200μA can be driven through the TSV. If the TSV has a resistance of 10Ω, then the voltage Vm is 2 mV. Therefore, the error caused by the 240 μV offset is 1.2Ω. Therefore, the CIA 500 may be sensitive enough to measure small (eg, about 10Ω) resistances in TSVs.

[0094] Although in Figure 5 Specific implementations of the chopper instrumentation amplifier 500 are described in , but it should be understood that the configuration of the amplifier 500 may be changed in other implementations. For example, the third amplifier 503 may be omitted from the chopper instrumentation amplifier 500. In the example, the second amplifier 502 may provide the voltages Vbiascom and Lp2out (respectively) to the resistors R71 and R72 of the fourth amplifier 504.

[0095] Figure 6 A non-chopper amplifier (SOS amplifier) ​​600 is shown according to an embodiment of the present invention. In some embodiments, the SOS amplifier 600 can be used as Figure 4 The SOS amplifier 600 can act as a differential amplifier and amplify the potential difference across the two inputs INp and INn. The SOS amplifier 600 can provide an output voltage OUT based on the inputs INp and INn. The SOS amplifier 600 includes a main amplifier 610, a sub-amplifier 612, and an output stage 614. The main amplifier 610 is coupled to the input voltages INp and INn and provides an output to the output stage 614, which provides the output voltage OUT. The main amplifier 610 can be coupled to the sub-amplifier 612, which can provide feedback to adjust the voltage on the main amplifier 610. Although Figure 6 A specific implementation of the SOS amplifier 600 may be shown, but it is understood that variations may be made to the layout and components of the SOS amplifier 600 without departing from the invention.

[0096] The main amplifier 610 includes transistors MN1, MN2, MP1, MP2, and MP5 and a capacitor C1. The gate of transistor MP1 is coupled to INp, and the gate of transistor MP2 is coupled to INn. The sources of transistors MP1 and MP2 can be coupled together through a tail voltage Tail. Tail is coupled to a source voltage Vdd and a drain of transistor MP5 through capacitor C1. The drain of transistor MP1 is coupled to a voltage ODn, and the drain of transistor MP2 is coupled to a voltage ODp. The gates of transistors MN2 and MN1 are coupled together and coupled to a voltage ODp. The drain of transistor MN2 is coupled to a voltage ODp, and the drain of transistor MN1 is coupled to a voltage ODn. The sources of both transistors MN1 and MN2 are coupled to ground. The voltages ODn and ODp are provided as outputs of the main amplifier 610 and as inputs of a sub-amplifier 612. The voltage ODn is additionally provided as an input to an output stage 614.

[0097] Sub-amplifier 612 can maintain the relationship of voltages ODp and Odn within main amplifier 610. Sub-amplifier includes transistors MN3, MN4, MP3 and MP4 and capacitor C2. Gates of transistors MN3 and MN4 are coupled to input voltages ODp and ODn. Sources of transistors MN3 and MN4 are both coupled to ground, and their drains are coupled to voltages CPp and CPn, respectively. Voltages CPp and CPn are coupled to drains of transistors MP3 and MP4, respectively. Sources of transistors MP3 and MP4 are coupled to source voltage Vdd. Gates of transistors MP3 and MP4 are coupled together, coupled to source voltage Vdd through capacitor C2, and coupled to voltage CPn. Voltage CPp is also coupled to the gate of transistor MP5 of main amplifier 610.

[0098] Sub-amplifier 612 may control the gate bias of transistor MP5 so as to keep voltages ODp and ODn equal to each other. Keeping voltages ODp and ODn equal also causes voltages CPp and CPn to be equal. Thus, transistor pairs MN1 and MN2 and MP1 and MP2 operate at the same operating point. In this way, the system offset voltage is minimized. In some examples, the system offset may be ±50 μV or less, even over a wide range of input voltages in a state where there is no device dispersion.

[0099] Output stage 614 is provided with voltage ODn as input and amplifies it to output voltage OUT. Output stage 614 may include transistors MN5, MP6, MP7 and MP8, resistors R1 and R2 and capacitors C3, C4 and C5. Input voltage ODn is coupled to the gate of transistor MN5, which has a source coupled to ground and a drain coupled to output voltage OUT. Input voltage ODn is also coupled to output voltage OUT via resistor R1 and capacitor C3 coupled in series. Output voltage OUT is also coupled to ground via capacitor C4 and to ground via resistor R2 and capacitor C5 coupled in series. A series of transistors MP8 to MP6 are coupled such that the drain of MP8 is coupled to the source of MP7 and the drain of MP7 is coupled to the source of MP6. The drain of MP6 is coupled to output voltage OUT. The source of MP8 is coupled to source voltage Vdd. The gates of MP8 and MP7 are coupled to ground. The gate of MP6 is coupled between resistor R1 and capacitor C3.

[0100] Figure 7 A chopper amplifier (CSOS amplifier) ​​700 is shown according to an embodiment of the present invention. In some embodiments, the chopper amplifier 700 may be used to implement Figure 5 The chopper amplifiers CSOS1 to CSOS8 of the chopper instrumentation amplifier 500 are shown in FIG. 700. The CSOS amplifier 700 includes a main amplifier 710, a sub-amplifier 712, and an output stage 714. In addition, the CSOS amplifier 700 also includes chopper circuits 716a to c. The chopper amplifier 700 may be substantially similar to Figure 6 The SOS amplifier 600 is similar to the SOS amplifier 600, except that chopper circuits 716a to c are added between the input and the main amplifier 710 and between the main amplifier 710 and the sub-amplifier 712. For the sake of brevity, the previous description of Figure 6 Describes the features and components.

[0101] The CSOS amplifier 700 includes a first chopper circuit 716a, which is positioned between input voltages INp and INn and a main amplifier 710. The first chopper circuit 716a receives inputs INp and INn, and provides outputs INpx and INnx to the respective gates of transistors MP1 and MP2 of the main amplifier 710. A second chopper circuit 716b is inserted into the main amplifier 710 and coupled to the voltages ODn and ODp as inputs. The second chopper circuit provides a voltage ODnx coupled to the gates of transistors MN1 and MN2, and also provides a voltage ODpx provided to the output stage 714 as an output of the main amplifier 710. A third chopper circuit 716c is coupled into the sub-amplifier 712 and receives voltages CPp and CPn as inputs. The third chopper circuit 716c provides an output voltage CPnx coupled to the gates of transistors MP3 and MP4 and also coupled to a source voltage Vdd via a capacitor C2. The third chopper circuit 716 c also provides a voltage CPpx that is coupled to the gate of transistor MP5 of the main amplifier 710 .

[0102] The chopper circuits 716a to c may receive a first input and a second input and provide a first output and a second output. The chopper circuits 716a to c may vary over time so that they alternately provide a first input voltage as a first input and a second input voltage as a second input and provide a first input voltage as a second input and a second input voltage as a first input. The coupling of the input to the output may vary over time based on the rate of the clock signals φ1 and φ2. The clock signals φ1 and φ2 may be provided from outside the CSOS amplifier 700. Because the CSOS amplifier 700 is a differential amplifier, the use of a chopper circuit to alternate the inputs may reduce or cancel the input voltage offset by causing the input voltage offset to appear at the two input terminals of the CSOS amplifier 700.

[0103] The first chopper circuit 716a can act as a modulation switch, while the second chopper circuit 716b and the third chopper circuit 716c can act as demodulation switches. The chopper circuits 716a to c can each receive clock signals φ1 and φ2. The clock signal can have a frequency that can be used by the chopper circuit to converge the input offset and input signal upward to the odd-order frequency of the clock signal. The demodulation switch can then remove these frequency components by converging the voltage that has been amplified by the CSOS amplifier 700 downward. The demodulation chopper circuits 716b and 716c are coupled to ODn and ODp, and CPp and CPn, respectively. As Figure 6The amplifier 600 of FIG. 6A maintains the voltages ODn and ODp equal to each other, and maintains the voltages CPp and CPn equal to each other. Thus, if the input offset is zero, the voltage does not change before and after the chopper circuit is activated by the clock signal. By maintaining the voltages equal at the chopper circuits 716 b and 716 c, the instantaneous output error from the switching of the chopper circuits is reduced.

[0104] Figure 8 A chopper circuit 800 according to an embodiment of the present invention is shown. In some embodiments, the chopper circuit 800 may be used to implement Figure 7 The chopper circuit 800 is a chopper circuit 716a to c. In some embodiments, the chopper circuit 800 may be a chopper switch. The chopper circuit 800 includes transistors MN21 to MN24 and MP21 to MP24 that act as analog switches. The chopper circuit 800 receives a first clock signal φ1 and a second clock signal φ2 that is complementary to the first clock signal φ1. The chopper circuit also receives a first input voltage IN1 and a second input voltage IN2, and outputs corresponding output voltages OUT1x and OUT2x.

[0105] The clock signal φ1 may be coupled to the gates of transistors MN21, MP22, MP23, and MN24 to operate them as switches. The clock signal φ2 may be coupled to the respective gates of transistors MN22, MP21, MP24, and MN23 to operate them as switches. The chopper circuit 700 may have two similar sides that may be generally symmetrical to each other. The first side may include MN21, MP21, MP22, and MN22 and may selectively couple the first input IN1 to the first output OUT1x and the second output OUT2x. The second side may include transistors MN23, MP23, MP24, and MN24 and may selectively couple the second input IN2 to the first output OUT1x and the second output OUT2x. Because the circuit may be generally symmetrical, only the coupling of the first side will be described in detail. However, it should be understood that analog connections may also exist on the second side.

[0106] The first input voltage IN1 is coupled to the first output OUT1x via two transistors MN21 and MP21 coupled in parallel, and is coupled to the second output OUT2x via two transistors MP22 and MPN22 coupled in parallel. The first input voltage IN1 is coupled to the source of transistor MP21 and the drain of transistor MN21. The drain of MP21 and the source of MN21 are coupled to the output OUT1x. The first input IN1 is also coupled to the drain of MP22 and the source of MN22. The source of MP22 and the drain of MN22 are coupled to the second output OUT2x. The gates of MN21 and MP22 are coupled to the clock signal φ1, and the gates of MP21 and MN22 are coupled to the clock signal φ2. Since the two clock signals are complementary to each other (e.g., when φ1 is at a 'high' level, φ2 is at a 'low' level and vice versa), when transistors MP22 and MN22 are inactive, transistors MN21 and MP21 are activated together, and when transistors MN21 and MP21 are inactive, transistors MP22 and MN22 are activated together. In a similar manner, transistors MN23 and MP23 are activated together and transistors MP24 and MN24 are activated together. Four pairs of transistors are activated so that when MP22, MN22, MN23, and MP23 are inactive, MN21, MP21, MP24, and MN24 are active, and vice versa. In this way, the chopper circuit 700 alternately provides IN1 on OUT1x and IN2 on OUT2x and provides IN1 on OUT2x and IN2 on OUT1x. The alternation may occur at the frequency f of the clock signals φ1 and φ2.

[0107] Fig. 9 A low pass filter 900 according to an embodiment of the present invention is shown. In some embodiments, the low pass filter 900 may be used to implement Figure 5 One or more of the low pass filters LPF1 to LPF4 of the chopper instrumentation amplifier 500. The low pass filter receives an input signal IN and provides an output signal OUT. The low pass filter may have a transmission function that allows low frequency signal components and blocks high frequency signal components. The low pass filter 900 may be synchronized with the chopper circuit and may remove the rectangular wave imposed by the chopper circuit.

[0108] The low pass filter 900 receives an input signal IN and two clock signals S1 and S2 as inputs and provides an output signal OUT. The clock signals S1 and S2 may have the same frequency as the clock signals φ1 and φ2. In some embodiments, the clock signals S1 and S2 may be provided by the same components (e.g., clock circuits) that provide the clock signals φ1 and φ2. The low pass filter 900 includes transistors MP11 to MP14 and MN11 to MN14, capacitors C11 to C13, and inverters INV11 and INV12 that may act as switches. The input signal IN may be coupled to the output OUT through two parallel circuit paths. The circuit paths may be substantially symmetrical to each other. One of the two circuit paths involves transistors MP11, MN11, MP13, and MN13 and INV11 and C11, while the other path involves MN12, MP12, MN14, MP14, INV12, and C12. For simplicity, only one circuit path will be described in detail.

[0109] The input signal IN is coupled to the source of MP11 and the drain of MN11. The gate of MN11 is coupled to the clock signal S1, and the gate of MP11 is coupled to the inverse of the clock signal S1 (via inverter INV11). The drain of MP11 is coupled to the source of MN11, which is coupled to ground via capacitor C11. The coupled drains and sources of MP11 and MN11 are coupled to the source of MP13 and the drain of MN13, respectively. The gate of MN13 is coupled to the clock signal S2, and the gate of MP13 is coupled to the inverse of the clock signal S2 (provided by inverter INV12). The gate of MP13 is coupled to the source of MN13 and both are coupled to the output voltage OUT. The output voltage OUT is also coupled to ground via capacitor C13. The two capacitors C11 and C12 may have equal capacitance. Capacitors C11 and C12 may have an equivalent resistance R given by the following equation 20:

[0110]

[0111] The frequency of the clock signals S1 and S2 may be f. The overall cutoff frequency of the low-pass filter 900 may be given by the following equation 21:

[0112]

[0113] Fig.10 1 is a timing diagram of signals for operating a chopper instrumentation amplifier according to an embodiment of the present invention. Timing diagram 1000 shows the signals provided to a chopper circuit (e.g., Figure 8 The chopper circuit 800) and the low pass filter (eg, Fig. 91 , 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 114, 115, 116, 117, 118, 119, 119, 120, 121, 122, 123, 124, 130, 131, 132, 133

[0114] The top two lines of the timing diagram 1000 show clock signals φ1 and φ2. The clock signals may be rectangular waves that periodically alternate between a 'high' level (e.g., a first voltage) and a 'low' level (e.g., a second voltage or a ground voltage) at a frequency f. The first clock signal φ1 starts at a low level and switches to a high level at time T1. At each time T2 to T6, the signal switches voltage levels. The second clock signal φ2 is the complement of the first clock signal φ1. Thus, the second clock signal φ2 starts at a high level and drops to a low level at T1 and then alternates at each time T2 to T6 thereafter.

[0115] The bottom two lines of the timing diagram 1000 show clock signals S1 and S2. S1 may be synchronized with φ1 and S2 may be synchronized with φ2. Clock signals S1 and S2 may transition from a low voltage to a high voltage at some time after the synchronized clock signals φ1, φ2, but may transition from a high voltage back to a low voltage at the same time as the synchronized clock signals φ1, φ2. The operation of S1 and φ1 will be described, however, it should be understood that the same description may apply to S2 and φ2, but offset in time.

[0116] From time T0 to T1, signal φ1 is at a low voltage, and therefore, signal S1 is also at a low voltage. At time T1, signal φ1 switches from a low voltage to a high voltage, but at T1, S1 remains at a low voltage. At some time after T1, clock signal S1 switches to a high voltage. At time T2, clock signal φ1 switches back to a low voltage, and therefore, clock signal S1 also transitions back to a low voltage. Signals S1 and S2 may be delayed relative to φ1 and φ2 in order to allow the transient voltage imposed by the chopper circuit to pass through a low-pass filter (e.g., Fig. 9 The low-pass filter 900) is stable before sampling.

[0117] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes or separated and / or performed in a separate device or device portion according to the present systems, devices, and methods.

[0118] Finally, the above discussion is intended to be merely illustrative of the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the inventive system has been described in particular detail with reference to exemplary embodiments, it should also be understood that many modifications and alternative embodiments may be envisioned by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the inventive system as set forth in the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An instrumentation amplifier, comprising: A pair of input terminals; A first intermediate node and a second intermediate node; Output terminals; a first amplifier stage coupled between the pair of input terminals and the first intermediate node, the first amplifier stage comprising a first chopper amplifier; a second amplifier stage coupled between the first intermediate node and the second intermediate node, the second amplifier stage comprising a second chopper amplifier; and a third amplifier stage coupled between the second intermediate node and the output terminal, the third amplifier stage comprising a non-chopper amplifier; wherein the gain of the first amplifier stage is greater than the gain of the third amplifier stage, and the gain of the second amplifier stage is greater than the gain of the third amplifier stage, wherein the pair of input terminals comprises a first input terminal and a second input terminal; and The first chopper amplifier includes a first sub-chopper amplifier and a second sub-chopper amplifier, the first sub-chopper amplifier is coupled to the first input terminal, and the second sub-chopper amplifier is coupled to the second input terminal.

2. The instrumentation amplifier of claim 1, wherein the gain of the third amplifier stage is approximately 1.

3. The instrumentation amplifier according to claim 1, wherein the first amplifier stage further comprises a first low pass filter LPF circuit coupled to the output of the first chopper amplifier; and Wherein the second amplifier stage further comprises a second LPF circuit coupled to the output of the second chopper amplifier. 4 . The instrumentation amplifier of claim 1 , wherein the first chopper amplifier and the second chopper amplifier each include at least one chopper circuit. 5 . The instrumentation amplifier of claim 1 , further comprising a buffer circuit configured to provide a bias voltage coupled to the second and third amplification stages.

6. An instrumentation amplifier, comprising: A pair of input terminals; A first intermediate node and a second intermediate node; Output terminals; a first amplifier stage coupled between the pair of input terminals and the first intermediate node, the first amplifier stage comprising a first chopper amplifier; a second amplifier stage coupled between the first intermediate node and the second intermediate node, the second amplifier stage comprising a second chopper amplifier; a third amplifier stage coupled between the second intermediate node and the output terminal, the third amplifier stage comprising a non-chopper amplifier, wherein a gain of the first amplifier stage is greater than a gain of the third amplifier stage, and a gain of the second amplifier stage is greater than the gain of the third amplifier stage; and at least one additional amplifier stage inserted between the second amplifier stage and the third amplifier stage, the at least one additional amplifier stage comprising a third chopper amplifier, Wherein a gain of the at least one additional amplifier stage is greater than the gain of the third amplifier stage. 7 . The instrumentation amplifier of claim 6 , wherein the gain of the third amplifier stage is approximately 1 and the gains of the first amplifier stage, the second amplifier stage, and the at least one additional amplifier stage are approximately equal to one another.

8. An apparatus for measuring a semiconductor device, comprising: A first input and a second input; a first chopper circuit coupled to the first input and the second input and providing a first chopper input and a second chopper input; a main amplifier comprising a first main input coupled to the first chopped input, a second main input coupled to the second chopped input, first and second main intermediate nodes, a main amplifier output, and a second chopper circuit coupled between the output and the first and second main intermediate nodes, wherein a voltage at the first main intermediate node is substantially equal to a voltage at the second main intermediate node; a sub-amplifier coupled to the first main intermediate node and the second main intermediate node, the sub-amplifier comprising first and second sub-intermediate nodes and a third chopper circuit coupled to the first and second sub-intermediate nodes, wherein a voltage at the first sub-intermediate node is substantially equal to a voltage at the second sub-intermediate node, and wherein an output of the third chopper circuit is coupled to the main amplifier; and An output stage is coupled to the main amplifier output and is configured to provide an output voltage.

9. The apparatus of claim 8, wherein the first chopper circuit, the second chopper circuit, and the third chopper circuit each comprise a chopper switch.

10. The apparatus of claim 8, wherein the first chopper circuit, the second chopper circuit, and the third chopper circuit are configured to switch a pair of input signals between a pair of output terminals.

11. The apparatus of claim 10, wherein the first chopper circuit, the second chopper circuit, and the third chopper circuit each switch at a frequency determined by a clock signal coupled to the chopper circuit.

12. The apparatus of claim 8, wherein the first chopper circuit is configured to modulate a respective input signal and wherein the second chopper circuit and the third chopper circuit are configured to demodulate the respective input signal.

13. The apparatus of claim 8, wherein the sub-amplifier is configured to keep the voltage on the first main intermediate node substantially equal to the voltage on the second main intermediate node.

14. A method for measuring a semiconductor device, comprising: modulating the signal using a first chopper circuit; amplifying the modulated signal; demodulating the signal using a second chopper circuit; filtering the demodulated signal using a low pass filter; synchronizing the first chopper circuit and the second chopper circuit with a clock signal; and The low pass filter is synchronized with a second clock signal based on the clock signal, wherein the second clock signal has a delayed activation compared to the clock signal.

15. The method of claim 14, wherein after filtering the demodulated signal, the method further comprises amplifying the filtered signal. The method of claim 14 , wherein said demodulating said signal comprises canceling an offset of said signal.

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