Processor core, processor, device and instruction processing method

Abstract

Disclosed are a processor core, a processor, a device, and an instruction processing method. The processor core includes: an instruction fetch unit, the instruction fetch unit includes a speculative execution predictor, the speculative execution predictor compares the program pointer of the memory access instruction with the table entry stored therein, and marks the memory access instruction; a scheduling unit, which is used to adjust the sending order of the marked memory access instructions and send them accordingly; and an execution unit, which is used to execute the memory access instructions in the sending order. In the instruction fetch unit, the memory access instructions are marked according to the speculative execution prediction result, in the scheduling unit, the sending order of the memory access instructions is determined and sent according to the marked memory access instructions, and in the execution unit, the memory access instructions are executed in the sending order, so as to avoid the need to re-execute the memory access instructions due to the address correlation of the memory access instructions, thereby avoiding the problem of adding empty beats to the instruction pipeline and having to clear the speculative error memory access instructions through the pipeline flushing operation.

Description

Technical Field

[0001] The present invention relates to the field of chip manufacturing, and more specifically, to a processor core, a processor, a device and an instruction processing method. Background Art

[0002] Improving processor architecture is a very difficult task. Researchers put a lot of effort into this, hoping to make progress in even the smallest aspects. In the design of high-performance processors, for performance considerations, the concept of speculative execution is usually introduced, that is, when the current instruction cannot be sent in sequence due to correlation, the subsequent unrelated instructions are sent in advance for execution.

[0003] In the related art, the relevance of instructions usually refers only to register relevance, that is, the source register of the subsequent instruction is the destination register of the previous instruction. However, for memory access instructions, the relevance also includes address relevance, that is, the memory read and write addresses are relevance. Since the memory access instruction can only detect the relevance of the register during the instruction sending stage, and cannot detect the address relevance, the address relevance will only be found by calculating the address during the memory access instruction execution stage. Therefore, speculative execution may cause the load instruction (load instruction) with address relevance to be executed ahead of the store instruction (store instruction), which will cause the data loaded by the load instruction (load instruction) to be wrong. When encountering this situation, it is necessary to re-execute the load instruction (load instruction) after the execution of the store instruction (store instruction). This increases the number of empty beats on the instruction pipeline, reduces the execution efficiency of the program and the execution efficiency of the processor. In addition, although the memory access instruction with speculative errors can be cleared by flushing the pipeline operation after the speculation fails, since the execution of the memory access instruction has ended when the speculation fails, the flushing pipeline operation will cause a certain performance loss, and the deeper the pipeline, the greater the performance loss. Summary of the invention

[0004] In view of this, the present invention proposes a processor core, a processor, a device and an instruction processing method to solve the above problems.

[0005] To achieve this object, according to a first aspect of the present invention, the present invention provides a processor core, comprising:

[0006] an instruction fetch unit, the instruction fetch unit comprising a speculative execution predictor, the speculative execution predictor comparing a program pointer of a memory access instruction with a table entry stored therein, and marking the memory access instruction accordingly, the memory access instruction being a load instruction or a store instruction, and the table entry being a program pointer of a load instruction and a store instruction having address correlation;

[0007] A scheduling unit, used to adjust the sending order of the marked memory access instructions and send them to the execution unit;

[0008] An execution unit is used to execute the marked memory access instructions in the sending order.

[0009] In some embodiments, the instruction fetch unit includes a register group for storing the table entry.

[0010] In some embodiments, the speculative execution predictor further comprises:

[0011] The table entry in the speculative predictor is updated according to the speculative execution prediction result of the memory access instruction.

[0012] In some embodiments, the register set further includes: multiple groups of registers, each group of registers including a saturation counter and one or two PC registers for storing one table entry.

[0013] In some embodiments, the speculative execution predictor starts executing speculative prediction when the value of the saturation counter is greater than a first set value, and stops executing speculative prediction when the value of the saturation counter is less than a second set value, and the first set value is greater than the second set value.

[0014] In some embodiments, the speculative execution predictor, for the same pair of store instruction and load instruction, increases the value of the saturation counter according to the speculative prediction error before the speculative prediction is started, and decreases the value of the saturation counter according to the speculative prediction error after the speculative prediction is started.

[0015] In some embodiments, the instruction fetch unit further includes: a pre-decoding unit for distinguishing normal instructions from memory access instructions, and sending the normal instructions to the scheduling unit and sending the memory access instructions to the speculative execution predictor.

[0016] In some embodiments, the speculative execution predictor only marks load instructions for which speculative execution is expected to fail.

[0017] In some embodiments, the speculative execution predictor only flags store instructions for which speculative execution is expected to fail.

[0018] In some embodiments, the scheduling unit sends the tagged load instruction after the tagged store instruction is sent.

[0019] In some embodiments, the scheduling unit includes: an instruction sending queue and a blocking sending execution module,

[0020] The instruction sending queue is used to cache all received instructions;

[0021] The blocking sending execution module is used to block the marked load instruction and send the marked load instruction after the marked storage instruction is sent.

[0022] In some embodiments, it further includes: a retirement unit, the retirement unit includes: a prediction result summary module, the prediction result summary module is used to summarize the speculative prediction results and provide the speculative execution prediction results of the memory access instruction to the speculative execution predictor.

[0023] According to a second aspect of the present invention, a processor is provided, comprising a processor core as described in any one of the above items.

[0024] According to a third aspect of the present invention, there is provided a system on chip, comprising any one of the processor cores described above.

[0025] According to a fourth aspect of the present invention, there is provided a device comprising a memory and the above-mentioned processor coupled via a bus.

[0026] According to a fifth aspect of the present invention, there is provided an instruction processing method, comprising:

[0027] Get the instruction packet;

[0028] Pre-decoding the instruction packet to distinguish between a memory access instruction and a general instruction in the instruction packet, wherein the memory access instruction is a load instruction or a store instruction, and the general instruction is an instruction other than the memory access instruction in the instruction set;

[0029] Performing speculative prediction on memory access instruction pairs in the instruction packet, and marking the memory access instructions accordingly;

[0030] Adjust the sending order of the marked memory access instructions and send them accordingly;

[0031] The memory access instructions are executed in the order in which they are sent.

[0032] In some embodiments, the sending order of the memory access instruction after the adjustment mark and the normal instruction, and sending accordingly includes:

[0033] The tagged load instruction is issued after the tagged store instruction is issued.

[0034] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0035] The instruction fetch unit makes a speculative prediction on the memory access instructions and marks the memory access instructions according to the prediction results. The scheduling unit adjusts the sending order of the memory access instructions according to the marked memory access instructions. The execution unit executes the memory access instructions according to the sending order, thereby avoiding the need to re-execute the memory access instructions due to the address correlation of the memory access instructions, thereby avoiding the need to add empty beats to the instruction pipeline and the need to clear speculative erroneous memory access instructions through a pipeline flush operation, so that the performance of the processor will not be affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present invention will become more apparent through the description of the embodiments of the present invention with reference to the following drawings, in which:

[0037] Figure 1 is a schematic diagram of the structure of a system according to an embodiment of the present invention;

[0038] Figure 2 is a schematic diagram of the structure of a processor according to an embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of the structure of a processor core according to an embodiment of the present invention;

[0040] Figure 4 Yes and Figure 3 The structural schematic diagram shown corresponds to the flowchart. DETAILED DESCRIPTION

[0041] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0042] The following terms are used in this article.

[0043] Program PC, program pointer.

[0044] Instruction pipeline, the instruction pipeline is to improve the efficiency of the processor in executing instructions by dividing the operation of an instruction into multiple small steps, each step is completed by a special circuit. The current mainstream instruction pipeline technologies include three-level, four-level, five-level, seven-level and super instruction pipelines, etc. For example, the five-level instruction pipeline in the textbook example includes the instruction fetch level, decoding level, execution level, memory access level and write-back level. In this article, the instruction fetch level, decoding level, execution level, memory access level and write-back level are also called instruction fetch unit, decoding unit, execution unit, memory access unit and retirement unit. The combination of software and hardware that implements the instruction pipeline is called the instruction pipeline structure.

[0045] An instruction packet is a fixed-length binary segment that the processor obtains from the instruction cache or external bus.

[0046] In addition, it should be noted that "updating the table entry of the speculative execution predictor" described in this article may include the following: changing one or some fields of an existing table entry in the speculative execution predictor; and adding a new table entry in the speculative execution predictor. Table entries in this article refer to a group of related data items.

[0047] Figure 1 1 is a schematic diagram of the structure of a system according to an embodiment of the present invention. The system is, for example, a computer system. System 100 is an example of a "center" system architecture. The system 100 can be constructed based on various types of processors currently on the market and driven by operating systems such as WINDOWS™ operating system versions, UNIX operating system, Linux operating system, etc. In addition, the system 100 is generally implemented in a PC, a desktop, a notebook, or a server. Therefore, the system 100 in the embodiment of the present invention is not limited to any specific combination of hardware circuits and software.

[0048] refer to Figure 1 As shown, system 100 includes processor 101. Processor 101 has data processing capabilities known in the art. It can be a processor of complex instruction set (CISC) architecture, reduced instruction set (RISC) architecture, very long instruction set (VLIW) architecture, or a processor that implements a combination of the above instruction sets, or any processor device built for a special purpose.

[0049] The processor 101 is coupled to the system bus 102, which may be an interconnection circuit for connecting the processor 101 and various other components, and the interconnection circuit support may include various interconnection protocols and interface circuits required for different needs. Thus, the communication relationship between the processor 101 and various components is realized. The processor 101 also includes a processor core 1021 improved according to the technical solution provided in the embodiment of the present invention, and its specific details will be provided below.

[0050] The system 100 further includes a memory 104 and a graphics card 107. The memory 104 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory or other memory. The memory 104 includes an instruction memory 105 and a data memory 106. By storing the instruction information and the data information represented by the data signal separately, when the processor 101 executes the instruction pipeline, it can fetch instructions from the instruction memory 105 and fetch data from the data memory 106 at the same time. The graphics card 107 includes a display driver for controlling the correct display of the display signal on the display screen.

[0051] The system 100 also includes a memory controller hub (MCH) 103, which can be coupled to the system bus 102, the memory 104, the graphics card 107, and the I / O controller hub (ICH) 108. The processor 101 can communicate with the memory controller hub (MCH) 103 via the system bus 102. The memory controller hub (MCH) 103 provides a high-bandwidth memory access path to the memory 104 for storing and reading instruction information and data information. At the same time, the memory controller hub (MCH) 103 and the graphics card 107 transmit display signals based on the graphics card signal input and output interface. The graphics card signal input and output interface is, for example, an interface type such as DVI, HDMI, etc.

[0052] The memory controller hub (MCH) 103 not only transmits digital signals between the processor 101 , the memory 104 and the graphics card 107 , but also bridges digital signals between the system bus 102 and the memory 104 and the I / O controller hub (ICH) 108 .

[0053] The system 100 further includes an I / O controller hub (ICH) 108, which is coupled to the memory controller hub (MCH) 103 via a dedicated hub interface bus, and some I / O devices are connected to the input / output control hub (ICH) 108 via a local I / 0 bus. The local I / 0 bus is used to couple peripheral devices to the input / output control hub (ICH) 108, and then to the memory controller hub (MCH) 103 and the system bus 102. The peripheral devices include, but are not limited to, the following devices: a hard disk 109, an optical drive 110, a sound card 111, a serial expansion port 112, an audio controller 113, a keyboard 114, a mouse 115, a GPIO interface 116, a flash memory 117, and a network card 118.

[0054] Of course, different computer systems have different structure diagrams according to different motherboards, operating systems and instruction set architectures. For example, many computer systems currently integrate the memory controller hub (MCH) 103 into the processor 101, so that the input / output control hub (ICH) 108 becomes the control hub coupled to the processor 101.

[0055] Figure 2 2 is a schematic diagram of a system on chip 200 for implementing the present invention. As a system on chip, the system 200 can be produced and sold as an independent device, or combined with other components to form a new device for production and sale.

[0056] System 200 can be manufactured using various types of processors currently on the market, and can be driven by operating systems such as WINDOWS™, UNIX, Linux, Android, RTOS, etc. System 200 can be implemented in computer devices, handheld devices, and embedded products. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded products can include network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can execute one or more instructions.

[0057] refer to Figure 2 As shown, the system 200 includes a processor 202 , a static random access memory 205 , an LCD controller 204 , a flash memory 206 , and an AHB / APB bridge 207 coupled via an AHB (Advanced High performance Bus, system bus) bus 201 .

[0058] The processor 202 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction set computer (VLIW) microprocessor, a microprocessor implementing a combination of the above instruction sets, or any other processor device. The processor 202 also includes a processor core 221 improved according to the technical solution provided in an embodiment of the present invention, and its specific details will be provided below.

[0059] The static random access memory 205 and the flash memory 206 are used to store instruction information and / or data information represented by digital signals. For example, the static random access memory 205 can be used as a running space for various applications, creating heaps, stacks, storing intermediate data, etc. for various applications, and the flash memory 206 can store executable codes of various applications and executable codes of the operating system.

[0060] The AHB bus 201 is used to transmit digital signals between high-performance modules of the system 200 , such as transmitting digital signals between the processor 202 and the static random access memory 205 , the processor 202 and the LCD controller 204 , the processor 202 and the flash memory 206 , and the processor 202 and the AHB / APB bridge 207 .

[0061] The AHB / APB bridge 207 is used to bridge data transmission between the AHB bus and the APB bus, and realizes the conversion from the AHB protocol to the APB protocol by latching the address, data and control signals from the AHB bus and providing secondary decoding to generate the selection signal of the APB peripheral device.

[0062] The system 200 may also include various interfaces coupled to the APB bus. The various interfaces include, but are not limited to, the following interface types: Secure Digital High Capacity (SDHC), I2C bus, Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Universal Serial Bus (USB), General-purpose input / output (GPIO), and Bluetooth UART. Peripheral devices coupled to the interface are, for example, USB devices, memory cards, message transceivers, Bluetooth devices, etc.

[0063] It is worth pointing out that with the increasing complexity of SoC design and the continuous improvement of processor processing power, the performance limitations of the bus structure have led to the replacement of the bus structure. For example, ARM has launched a higher-performance AXI (Advanced eXtensible Interface) bus based on the above-mentioned AHB bus. Therefore, the AXI bus can be used to replace the AHB bus 201 in the figure. Moreover, researchers in this field can also improve the existing bus structure or build a new bus structure based on their actual needs. Therefore, although the AHB bus is shown in the figure, in fact, the choice of bus for SoC can be diverse.

[0064] In addition, for Figure 1 and Figure 2 It should also be noted that these systems are only used to illustrate some application scenarios of the embodiments of the present invention, but are not intended to limit the embodiments of the present invention. The present invention improves the existing processor or processor core, so it can theoretically be applied to systems with any processor architecture and instruction set architecture.

[0065] Figure 3 1 is a schematic diagram of the structure of a processor core according to an embodiment of the present invention. In the figure, arrows represent the coupling relationship between two or more units and the data transmission direction between the two.

[0066] The processor core 300 includes a pipeline structure, which is used to fetch, decode, and execute program codes according to the instruction set encapsulated in the processor core. Figure 3 As shown, the processor core 300 includes an instruction fetch unit 301 , a decoding unit 302 , a scheduling unit 303 , an execution unit 304 and a retirement unit 305 .

[0067] In the pipeline structure of the processor core, the instruction fetch unit 301 may be coupled to an instruction cache (not shown) inside the processor core 300 to obtain a physical address from the translation detection buffer according to a program pointer (program PC) and obtain an instruction packet from the instruction cache accordingly.

[0068] In some embodiments, the instruction fetch unit 301 may further include: a pre-decoding module 3011 and a speculative execution predictor 3012. For the instruction packet fetched by the instruction fetch unit 301, the pre-decoding module 3011 pre-decodes the instruction meta field in the instruction packet to determine the instruction type of each instruction. The instruction type may include a normal instruction and a memory access instruction, where the memory access instruction includes a store instruction (store instruction) and a load instruction (load instruction), and the normal instruction may be other instructions except the memory access instruction, including a branch instruction, a data transfer instruction, etc.

[0069] When the pre-decoding module 3011 determines that the current instruction is a normal instruction, the current instruction is sent to the decoding unit 302. When the pre-decoding module 3011 determines that the instruction is a memory access instruction, the memory access instruction is sent to the speculative execution predictor 3012 to perform speculative prediction. The speculative execution predictor 3012 is used to compare the program pointer of the current memory access instruction with the program pointer of the load instruction and / or store instruction stored therein to obtain the search result of the current memory access instruction, mark at least one of the load instruction and the store instruction according to the search result, and send the marked instruction to the decoding unit 302.

[0070] In some embodiments, the speculative execution predictor 3012 may further include: a register set 30121 and a speculative execution unit 30124. The register set 30121 is coupled to the prediction result summary module 3051 of the retirement unit 305, and receives the speculative execution prediction result (including the prediction result error and / or the prediction result correctness) returned from the prediction result summary module 3051.

[0071] The register group 30121 stores table entries of program pointers of load instructions and store instructions with address correlation. The register group 30121 may further include multiple register groups, each register group includes a saturation counter 30122 and one or two PC registers 30123. Among them, one or two PC registers 30123 are used to store a table entry of program pointers of load instructions and store instructions with address correlation. The speculative execution predictor 3012 starts or stops speculative prediction according to the value of the saturation counter 30122. Specifically, in the initial stage, the register does not store a table entry of a load instruction and a store instruction with address correlation. Therefore, when the load instruction and the store instruction are executed, a prediction result error will be returned to the speculative execution predictor 3012. The speculative execution predictor 3012 adds a table entry of the load instruction and the store instruction in one or two PC registers 30123, and sets the value of the saturation counter 30122 to 1. When the speculation fails again for the load instruction and the store instruction, the value of the saturation counter is increased by 1. For the third time, since the value of the counter is ≥2, the speculative prediction is enabled, and the load / store instruction is marked. When the speculative prediction is wrong, the count value is reduced by 1. That is, only when the count value of the saturation counter 30122 is greater than or equal to 2, the prediction of the memory access instruction is started. When the count value is less than 1, the prediction of the memory access instruction is stopped. When the value of the saturation counter 30122 is 0, the corresponding entry is released, so that a new entry can be added to the register corresponding to the entry, so that the space in the register group 30121 can be recycled. The register group 30121 stores the latest entries of the program pointers of the load instructions and / or store instructions with address correlation, which helps to improve the accuracy of speculative prediction.

[0072] In some embodiments, the speculative execution unit 30124 only marks load instructions that are predicted to fail speculative execution in the execution unit 304. In other embodiments, the speculative execution unit 30124 only marks store instructions that are predicted to fail speculative execution in the execution unit 304.

[0073] The decoding unit 302 extracts the opcode, source register, destination register and immediate value of the current instruction according to the instruction set architecture. The instruction set architecture is determined by the manufacturer of the processor. When the program is compiled into an executable form, the compiler only uses the instructions defined in the instruction set architecture to organize the executable code. If the compiler uses an undefined instruction, the decoding unit 302 cannot understand the meaning that the instruction is trying to express, causing the instruction decoding to fail.

[0074] The scheduling unit 303 is used to adjust the sending order of the received multiple instructions and send them to the execution unit 304 according to the sending order. The multiple instructions of the scheduling unit 303 can come from the instruction package fetched once by the instruction fetch unit 301, or from the instruction package fetched multiple times. The scheduling unit 303 can adjust the sending order in a variety of ways. For example, for a storage instruction and a load instruction marked as a pair, the storage instruction is sent before the load instruction. For another example, all marked storage instructions are sent before the load instruction.

[0075] In some embodiments, the scheduling unit 303 may further include: an instruction sending queue 3031 and a blocking sending execution module 3032. The scheduling unit 303 receives the decoded current instruction and stores it in the instruction sending queue 3031 in sequence, but sends the current instruction whose source operand is ready in the instruction sending queue 3031 out of order. For example. Instruction I3 and instruction I4 are register-related instructions. In the instruction sending queue 3031, instruction I3 is the instruction sent after instruction I4, and the source register of instruction I3 is the destination register of instruction I4. The instruction sending queue 3031 sends instruction I4 first and then sends instruction I3 to avoid the performance loss of the processor core caused by the speculative execution failure caused by the occurrence of register correlation. If the instruction I6 to be sent is a marked load instruction (load instruction), instructions I2 and I5 in the instruction sending queue 3031 are marked storage instructions (store instructions), and instruction I1 is an unmarked storage instruction (store instruction). The blocking sending execution module 3032 blocks the sending of instruction I6, and sends instruction I6 after both instruction I2 and instruction I5 are sent.

[0076] In other embodiments, the scheduling unit 303 may selectively perform speculative execution on the marked storage instruction. For example, in some cases, the scheduling unit 303 receives the decoded current instruction (including the marked storage instruction) and stores it sequentially in the instruction sending queue 3031, and then sends the current instruction with the source operand ready in the instruction sending queue 3031, that is, the scheduling unit 303 abandons the speculative execution of the storage instruction. Whether to perform speculative execution may depend on, for example, the judgment of whether the scheduling unit 303 is blocked. Optionally, the number of instructions in the instruction sending queue 3031 is used as a judgment condition for whether there is a blockage in the scheduling unit 303, and when the number of instructions is greater than or equal to a set value, the speculative execution of the marked storage instruction is stopped. Of course, the present invention is not limited to this. The instruction pipeline structure can choose to start or abandon speculative execution under any condition.

[0077] The execution unit 304 may include: multiple execution modules 3041 (for executing normal instructions) and a memory access instruction execution module 3042. For the instruction I6 in the above example, the memory access instruction execution module 3042 performs a corresponding load operation according to the instruction I6 and determines whether the speculative execution prediction result of the instruction fetch unit 301 on the instruction I6 is correct according to the execution result information of the instruction I6. In the retirement unit 305, the execution unit 304 receives the instruction I5, and the memory access instruction execution module 3042 performs a corresponding storage operation according to the instruction I5 and determines whether the speculative execution prediction result of the instruction fetch unit 301 on the instruction I5 is correct according to the execution result information of the instruction I5. The execution unit 304 receives the instruction I4, which may be a normal instruction, and the multiple execution modules 3041 perform various arithmetic operations according to the instruction I4.

[0078] The retirement unit 305 writes the relevant content to the memory. In some embodiments, the retirement unit 305 may include a prediction result summary module 3051, which returns a speculative prediction error to the speculative execution predictor 3012 based on the judgment result information of the memory access instruction execution module 3042 on the memory access instruction when the memory access instruction execution module 3042 determines that the speculative prediction of the memory access instruction by the instruction fetch unit 301 fails.

[0079] It should be understood that although the instruction fetch unit, decoding unit, scheduling unit, execution unit and retirement unit are used to represent the instruction pipeline structure in the figure, the present invention is not limited to this. Those skilled in the art may use other instruction pipelines to implement this embodiment, such as using the standard five-stage pipeline structure shown in the textbook to implement this embodiment.

[0080] Table 1 is an exemplary instruction stream. In order to more intuitively illustrate the process of the processor core of this solution processing the instruction stream, the instruction stream shown in Table 1 is used as an example:

[0081] Table 1 Instruction flow

[0082] 1 mov r2,0x120000 2 mov r1,0x1 3 div r3,r2,r1 4 st r2,0x0(r3) 5 ld r4,0x(r2)

[0083] As shown in the instruction flow in Table 1, since the registers of the store instruction (store instruction) and the load instruction (load instruction) are different, there is no register correlation, but the addresses used for reading and writing memory are the same. Therefore, there is address correlation between the store instruction (st instruction in the figure) and the load instruction (ld instruction in the figure).

[0084] Table 2 is the execution timing of the instruction stream shown in Table 1 without speculative execution prediction. For the store instruction (store instruction), it needs to wait for the execution of the preceding division instruction (div instruction) to be completed before it can be executed, and the division execution may require multiple beats to complete, so it will be blocked in the instruction sending queue. The subsequent load instruction (load instruction) will be sent to the memory access instruction execution module 3042 in advance because there is no register correlation problem. The subsequent load instruction speculative execution causes a writing error in reading and writing. Its instruction behavior is shown in Table 2. After the store instruction (store instruction) retires in the 10th cycle, the load instruction (load instruction) will be re-executed, resulting in the empty flush pipeline behavior of the processor core execution instruction, reducing the execution efficiency of the processor core.

[0085] Table 2 Execution timing of instruction stream without speculative execution prediction

[0086] cycle IF (Instruction Fetch) ID (decoding) IS (Send) EX (Execute) RT (retired) 0 mov1 1 mov2 mov1 2 Div mov2 mov1 3 St Div mov2 mov1 4 Ld St div mov2 mov1 5 Ld st div mov2 6 stld div 7 st Divld 8 St div 9 st 10 Ld

[0087] Table 3 shows the execution timing of the instruction stream shown in Table 1 when speculative execution prediction is included. If a speculative execution predictor is added, the execution of the instruction stream is shown in Table 3. The store instruction and the load instruction are marked by the speculative execution predictor. In the instruction dispatch queue, when the store instruction is not dispatched, the load instruction cannot be dispatched ahead of the store instruction, so that at the 10th cycle, all instruction sequences have been executed and retired.

[0088] Table 3. Execution timing of instruction stream with speculative execution prediction

[0089] cycle IF (Instruction Fetch) ID (decoding) IS (Send) EX (Execute) RT (retired) 0 mov1 1 mov2 mov1 2 Div mov2 mov1 3 St Div mov2 mov1 4 Ld St div mov2 mov1 5 Ld St div mov2 6 stld div 7 S L div 8 Ld st div 9 ld st 10 ld

[0090] Figure 4 Yes and Figure 3 The structural schematic diagram shown corresponds to the flowchart. As shown in the flowchart, the process of the operation is described as follows.

[0091] In step S400, the instruction fetch unit obtains an instruction, and the pre-decoding module pre-decodes the instruction to determine the instruction type.

[0092] In step S401, it is determined whether the current instruction is a memory access instruction. If yes, step S402 is executed, and if no, step S406 is executed.

[0093] In steps S400-S401, the instruction fetch unit obtains an instruction packet from the instruction cache and pre-decodes the instruction packet to distinguish between memory access instructions and normal instructions. If the current instruction is a memory access instruction, step S402 is executed; if the instruction is a normal instruction, step S406 is executed.

[0094] In step S402, a plurality of table entries are accessed by program PC using a memory access instruction.

[0095] In some embodiments, the plurality of table entries may be composed of a PC register, in which the program PCs of the plurality of memory access instructions having address correlation are stored. The saturation counter may be a 2-bit saturation counter. The saturation counter counts the program PC of each memory access instruction in the plurality of table entries, increases by 1 when a new table entry is added, and decreases by 1 when a speculative prediction error is received.

[0096] In step S403, the program PC of the memory access instruction is compared with the stored table entry to determine whether there is address correlation.

[0097] In step S404, it is determined whether there is address correlation, if yes, step S405 is executed, otherwise step S406 is executed.

[0098] In step S405, the memory access instruction is marked and the marked memory access instruction is sent to the decoding unit.

[0099] In step S406 , the decoding unit performs decoding, ie, extracts the operation code, source register, destination register and immediate value of the instruction according to the instruction set architecture.

[0100] In step S407, the decoded instructions are received and sequentially stored in the instruction sending queue. For each instruction to be sent in the instruction sending queue, it is determined whether it is a marked load instruction. If yes, step S408 is executed, and if not, step S409 is executed.

[0101] In step S408 , it is determined whether all the marked storage instructions (store instructions) in the instruction sending queue have been sent. If yes, step S409 is executed; if not, step S410 is executed.

[0102] In step S409, the instruction is sent to the execution unit.

[0103] In step S410 , the sending of the marked load instruction is blocked, and the marked load instruction is sent after all the marked store instructions in the instruction sending queue are sent.

[0104] In step S411, various execution modules are used to execute the current instruction, wherein the memory access instruction execution module executes the corresponding storage or loading operation according to the memory access instruction, and determines whether the speculative execution prediction result of the memory access instruction is correct according to the execution result information.

[0105] In step S412, when the currently executed information is written back to the register from the instruction pipeline, the prediction result summary module provides feedback information to the saturation counter based on the judgment result information when the speculative prediction of the memory access instruction is wrong.

[0106] In step S413, the table entry stored in the speculative execution predictor is updated. The saturation counter reduces the count value of the saturation counter corresponding to the memory access instruction by 1. When the count value of the saturation counter corresponding to the memory access instruction is less than 2, the speculative execution predictor stops predicting the speculative execution result of the memory access instruction.

[0107] In an embodiment of the present invention, an instruction fetch unit performs speculative prediction on memory access instructions and marks the memory access instructions according to the prediction results. The scheduling unit adjusts the sending order of the memory access instructions according to the marked memory access instructions. The execution unit executes the memory access instructions in the sending order, thereby avoiding the need to re-execute the memory access instructions due to the address correlation of the memory access instructions, thereby avoiding the need to add empty beats to the instruction pipeline and the need to clear speculative erroneous memory access instructions through a pipeline flush operation, so that the performance of the processor will not be affected.

[0108] Furthermore, the table entries in the speculative execution predictor are updated according to the speculative prediction results, so that the table entries stored therein are the latest table entries of address correlation, which can further improve the accuracy of speculative prediction.

[0109] Furthermore, the confidence of the speculative execution predictor is reflected by a saturation counter. When the saturation counter is less than a set value, the speculative execution predictor is no longer used for speculative prediction, and invalid work of the speculative execution predictor is avoided.

[0110] For the present invention, the above-described processing units, processing systems, and electronic devices may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present invention is not limited thereto. Although various aspects of the present invention may be illustrated and described as block diagrams, flow charts, or using some other graphical representations to illustrate and describe various aspects of the present invention, it is well understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, software, dedicated circuits or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof. If involved, the circuit design of the present invention may be implemented in various components such as integrated circuit modules.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A processor core, comprising: an instruction fetch unit, the instruction fetch unit comprising a speculative execution predictor, the speculative execution predictor comparing a program pointer of a memory access instruction with a table entry stored therein, and marking the memory access instruction accordingly, the memory access instruction being a load instruction or a store instruction, and the table entry being a program pointer of a load instruction and a store instruction having address correlation; A scheduling unit, used to adjust the sending order of the marked memory access instructions and send them to the execution unit; An execution unit, configured to execute the marked memory access instructions in the sending order; a retirement unit, the retirement unit comprising: a prediction result aggregation module, the prediction result aggregation module being used to aggregate speculative prediction results and provide the speculative execution prediction results of the memory access instruction to the speculative execution predictor, The speculative execution predictor includes a saturation counter, and the speculative execution predictor starts to execute speculative prediction when the value of the saturation counter is greater than a first set value, and stops to execute speculative prediction when the value of the saturation counter is less than a second set value, and the first set value is greater than the second set value; and for the same pair of storage instructions and load instructions, before the execution of speculative prediction is started, the value of the saturation counter is increased according to the speculative prediction error fed back by the prediction result summary module according to the speculative execution predictor, and after the execution of speculative prediction is started, the value of the saturation counter is reduced according to the speculative prediction error fed back by the prediction result summary module. 2 . The processor core according to claim 1 , wherein the instruction fetch unit comprises a register group for storing the table entry.

3. The processor core of claim 1 , wherein the speculative execution predictor further comprises: The table entry in the speculative execution predictor is updated according to the speculative execution prediction result of the memory access instruction.

4. The processor core according to claim 2, wherein the register set further comprises: A plurality of register groups, each register group includes the saturation counter and one or two PC registers for storing one table entry.

5. The processor core according to claim 1, wherein the instruction fetch unit further comprises: The pre-decoding unit is used to distinguish between normal instructions and memory access instructions, and send the normal instructions to the scheduling unit and send the memory access instructions to the speculative execution predictor. 6 . The processor core of claim 1 , the speculative execution predictor only marking load instructions that are expected to fail speculative execution.

7. The processor core of claim 1, the speculative execution predictor to flag only store instructions that are expected to fail speculative execution.

8. The processor core of claim 1, wherein the scheduling unit sends the tagged load instruction after the tagged store instruction is sent.

9. The processor core according to claim 8, wherein the scheduling unit comprises: Instruction sending queue and blocking sending execution module, The instruction sending queue is used to cache all received instructions; The blocking sending execution module is used to block the marked load instruction and send the marked load instruction after the marked storage instruction is sent.

10. A processor, comprising the processor core according to any one of claims 1 to 9.

11. A system on chip, comprising the processor core according to any one of claims 1 to 9.

12. An apparatus comprising a memory and the processor as claimed in claim 10 coupled via a bus.

13. A method for processing an instruction, comprising: Get the instruction packet; Pre-decoding the instruction packet to distinguish between a memory access instruction and a general instruction in the instruction packet, wherein the memory access instruction is a load instruction or a store instruction, and the general instruction is an instruction other than the memory access instruction in the instruction set; A speculative execution predictor is used to perform speculative prediction on the memory access instruction pairs in the instruction packet, and the memory access instructions are marked accordingly, wherein the speculative execution predictor starts to execute speculative prediction when the value of the saturation counter is greater than a first set value, and stops to execute speculative prediction when the value of the saturation counter is less than a second set value, before the speculative predictor is started, the value of the saturation counter is increased according to the feedback speculative prediction error, and after the speculative prediction is started, the value of the saturation counter is reduced according to the feedback speculative prediction error; Adjust the sending order of the marked memory access instructions and send them accordingly; The memory access instructions are executed in the order in which they are sent.

14. The instruction processing method according to claim 13, wherein the sending order of the memory access instruction after the mark and the normal instruction is adjusted, and the sending order accordingly comprises: The tagged load instruction is issued after the tagged store instruction is issued.

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