Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a layer to be etched; forming an initial mask layer on the layer to be etched; forming a patterned structure on the initial mask layer, exposing a part of the initial mask layer; forming a barrier layer on the sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask to perform ion doping treatment on the initial mask layer to form a doped region and an undoped region in the initial mask layer. Removing the patterned structure and the barrier layer; after removing the patterned structure and the barrier layer, removing the undoped region, forming a mask layer on the surface of the layer to be etched, the mask layer having a first opening exposing the top surface of the layer to be etched. By forming a barrier layer on the sidewall surface of the patterned structure, doping ions can be effectively blocked from entering the patterned structure and then diffusing to the undoped region, reducing the undoped region. The barrier layer is used to effectively improve the consistency between the undoped region and the patterned structure, thereby improving the accuracy of pattern transfer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, a semiconductor structure is formed on a semiconductor substrate through a series of processes, such as deposition, lithography, etching, etc. Among them, the lithography process is to form a required pattern in a photoresist to obtain a patterned photoresist, defining an area to be etched. The etching process is used to transfer the pattern in the patterned photoresist to a layer to be etched.

[0003] However, in the process of forming a semiconductor structure in the prior art, the accuracy of pattern transfer still needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the accuracy of pattern transfer.

[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, which is characterized by including: providing a layer to be etched; forming an initial mask layer on the layer to be etched; forming a patterned structure on the initial mask layer, exposing a part of the initial mask layer; forming a blocking layer on the sidewall surface of the patterned structure; using the patterned structure and the blocking layer as masks to perform ion doping treatment on the initial mask layer, forming doped regions and undoped regions between the doped regions in the initial mask layer. Removing the patterned structure and the blocking layer; after removing the patterned structure and the blocking layer, removing the undoped regions, forming a mask layer on the surface of the layer to be etched, and the mask layer has a first opening exposing the top surface of the layer to be etched.

[0006] Optionally, the layer to be etched includes a single-layer structure or a multi-layer structure.

[0007] Optionally, when the layer to be etched is a multi-layer structure, the layer to be etched includes a substrate and a dielectric layer on the substrate.

[0008] Optionally, the substrate includes a base and a device layer on the base; the dielectric layer is on the device layer.

[0009] Optionally, the method for forming the patterned structure includes: forming a patterned layer on the surface of the initial mask layer; forming a photoresist layer on the surface of the patterned layer; etching the patterned layer using the photoresist layer as a mask until the top surface of the initial mask layer is exposed, forming the patterned structure; after forming the patterned structure, removing the photoresist layer.

[0010] Optionally, the material of the initial mask layer is different from that of the patterned layer.

[0011] Optionally, the material of the initial mask layer includes amorphous silicon, polysilicon, or doped silicon.

[0012] Optionally, the height of the patterned structure is 10 nm to 30 nm, and the direction of the height is perpendicular to the top surface of the initial mask layer.

[0013] Optionally, the method for forming the barrier layer includes: forming an initial barrier layer on the surface of the patterned structure and the top surface of the exposed initial mask layer; removing the initial barrier layer on the top surface of the patterned structure and the top surface of the initial mask layer to form the barrier layer.

[0014] Optionally, the material of the barrier layer includes silicon oxide, silicon nitride, or silicon oxynitride.

[0015] Optionally, the process for forming the initial barrier layer uses atomic layer deposition process.

[0016] Optionally, the process for removing the initial barrier layer on the top surface of the patterned structure and the top surface of the initial mask layer uses a first wet etching process; the etching solution used in the first wet etching process includes hydrofluoric acid solution and hydrogen peroxide solution.

[0017] Optionally, the thickness of the barrier layer is 1 nm to 10 nm, and the direction of the thickness is perpendicular to the sidewall of the patterned structure.

[0018] Optionally, the doping ions used in the ion doping treatment include boron ions, phosphorus ions, or nitrogen ions.

[0019] Optionally, the parameters of the ion doping treatment include: doping energy is 10 KeV to 30 KeV, doping dose is 1E7 atoms / cm 2 ~3E7 atoms / cm 2 , and doping time is 30 s to 120 s.

[0020] Optionally, the process for removing the patterned structure and the barrier layer uses a second wet etching process; the etching solution used in the second wet etching process includes hydrofluoric acid solution and hydrogen peroxide solution.

[0021] Optionally, the process for removing the undoped region uses a third wet etching process; the etching solution used in the third wet etching process includes hydrofluoric acid solution, hydrogen peroxide solution, and ammonia water.

[0022] Optionally, after forming the first opening, the method further includes: etching the layer to be etched using the mask layer as a mask to form a second opening in the layer to be etched; and removing the mask layer after forming the second opening.

[0023] Correspondingly, the present invention further provides a semiconductor structure formed by the above method, including: a layer to be etched; and a mask layer located on the layer to be etched, the mask layer having a first opening exposing the top surface of the layer to be etched.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the technical solution of the present invention, by forming a blocking layer on the sidewall surface of the patterned structure, the blocking layer has strong isolation properties, can effectively block dopant ions from entering the sidewalls of the patterned structure and then diffusing into the undoped region, reducing the undoped region. The use of the blocking layer effectively improves the consistency between the undoped region and the patterned structure, and further improves the accuracy of pattern transfer.

[0026] Further, in the technical solution of the present invention, the height of the patterned structure is 10 nm to 30 nm. For a patterned structure within this height range, it can avoid the dopant ions diffusing from the top surface of the patterned structure into the undoped region when the height of the patterned structure is relatively low; and it can also avoid the collapse of the patterned structure when the height of the patterned structure is relatively high.

[0027] Further, in the technical solution of the present invention, the thickness of the blocking layer is 1 nm to 10 nm. For a blocking layer within this thickness range, it can avoid dopant ions breaking through the blocking layer and entering the patterned structure when the thickness of the blocking layer is relatively small; and it can also avoid resource waste and reduction of production efficiency caused by a relatively large thickness of the blocking layer.

[0028] Further, in the technical solution of the present invention, the doping energy of the ion doping process is 10 KeV to 30 KeV, the doping dose is 1E7 atoms / cm 2 ~3E7 atoms / cm 2 , and the doping time is 30 s to 120 s. Through the ion doping process with parameters within this range, it can ensure that the doping region is fully doped with ions, and avoid affecting the morphology of the first opening due to insufficient doping in the doping region. Description of the Drawings

[0029] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure;

[0030] Figures 5 to 20It is a schematic structural diagram of each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed implementation manners

[0031] As described in the background art, in the process of forming a semiconductor structure in the prior art, the accuracy of pattern transfer still needs to be improved. The following will be combined with Figures 1 to 4 for illustration. Figures 1 to 4 It is a schematic structural diagram of each step in the process of forming a semiconductor structure.

[0032] Please refer to Figure 1 and Figure 2 , Figure 2 which is Figure 1 a schematic cross-sectional view along line A-A, providing an etch layer 100 to be etched; forming an initial mask layer 101 on the etch layer 100 to be etched; forming a patterned structure 102 on the initial mask layer 101, exposing a part of the initial mask layer 101.

[0033] Please refer to Figure 3 and Figure 4 , Figure 4 which is Figure 3 a schematic cross-sectional view along line A-A. Using the patterned structure 102 as a mask, the initial mask layer 101 is subjected to ion doping treatment to form a mask layer (not labeled), and the mask layer includes a doped region A and an undoped region B.

[0034] In the above embodiment, a mask layer is formed by ion doping treatment of the initial mask layer 101. The mask layer includes a doped region A and an undoped region B. Ideally, the region of the mask layer covered by the patterned structure 102 is the undoped region B. Subsequently, by wet etching the mask layer, using the characteristics of different etching selectivity ratios of the doped region A and the undoped region B to the etching solution, the undoped region B is etched and removed, thereby realizing pattern transfer.

[0035] However, in the actual operation process, a part of the implanted doping ions will be implanted into the sidewall of the patterned structure 102. Since the sidewall of the patterned structure 102 is relatively close to the undoped region B, some of the doping ions will diffuse into the undoped region B through diffusion, making the undoped region B smaller and the doped region A larger. Subsequently, when the mask layer is etched, the formed opening pattern will be smaller compared to the patterned structure 102, and the accuracy of pattern transfer will be reduced.

[0036] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By forming a barrier layer on the sidewall surface of the patterned structure, the barrier layer can effectively prevent doped ions from entering the sidewall of the patterned structure and further diffusing into the undoped region, thereby improving the consistency between the undoped region and the patterned structure, and further improving the accuracy of pattern transfer.

[0037] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0038] Figures 5 to 20 , is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 5 and Figure 6 , Figure 6 is Figure 5 a cross-sectional schematic view along line A-A, providing a layer to be etched.

[0040] In this embodiment, the layer to be etched includes a multi-layer structure, and the layer to be etched includes a substrate and a dielectric layer 202 located on the substrate; in other embodiments, the layer to be etched may also be a single-layer structure.

[0041] The substrate includes a base 200 and a device layer 201 located on the base 200.

[0042] In this embodiment, the material of the base 200 is silicon; in other embodiments, the material of the base may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the base may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0043] The device layer 201 includes a device structure, an electrical interconnect structure electrically connected to the device structure, and a device dielectric layer (not shown) surrounding the device structure and the electrical interconnect structure.

[0044] The device structure includes one or more of a PMOS transistor, an NMOS transistor, a CMOS transistor, a resistor, a capacitor, and an inductor.

[0045] The electrical interconnect structure includes a conductive plug formed on the surface of the base 200 or the device structure, and a conductive layer formed on the top of the conductive plug, and the conductive layer is used to electrically connect the conductive plugs.

[0046] The material of the electrical interconnect structure includes a metal or a metal compound, such as one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride.

[0047] The material of the device dielectric layer is silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

[0048] In this embodiment, the dielectric layer 202 is located on the device layer 201, and the dielectric layer 202 is a multi-layer structure; in other embodiments, the dielectric layer may also adopt a single-layer structure.

[0049] Please refer to Figure 7 and Figure 8 , Figure 8 is Figure 7 a schematic cross-sectional view along line A-A. An initial mask layer 203 is formed on the layer to be etched.

[0050] The function of the initial mask layer 203 is to serve as a mask for the layer to be etched in the subsequent formation of the second opening.

[0051] In this embodiment, the material of the initial mask layer 203 is amorphous silicon; in other embodiments, the material of the initial mask layer may also be polycrystalline silicon or doped silicon.

[0052] Please refer to Figure 9 and Figure 10 , Figure 10 Figure 9 a schematic cross-sectional view along line A-A. A patterned structure 204 that exposes part of the initial mask layer 203 is formed on the initial mask layer 203.

[0053] In this embodiment, the method for forming the patterned structure 204 includes: forming a patterned layer on the surface of the initial mask layer 203; forming a photoresist layer on the surface of the patterned layer; etching the patterned layer using the photoresist layer as a mask until the top surface of the initial mask layer is exposed, thereby forming the patterned structure; after forming the patterned structure, removing the photoresist layer (not shown).

[0054] In this embodiment, the material of the initial mask layer 203 is different from that of the patterned layer, so that when etching the patterned layer, a large etching selectivity ratio can be generated between the initial mask layer and the patterned layer, avoiding damage to the initial mask layer 203.

[0055] The formation process of the photoresist layer includes a photolithography patterning process; the process for removing the patterned layer includes a wet stripping process or an ashing process, and the gas for the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0056] In this embodiment, the height of the formed patterned structure 204 is 10 nm to 30 nm, and the direction of the height is perpendicular to the top surface of the initial mask layer 203.

[0057] The patterned structure 204 within this height range can not only avoid the situation where, when the height of the patterned structure 204 is relatively low, during the subsequent ion doping process, the doped ions diffuse from the top surface of the patterned structure 204 into the undoped region, thereby affecting the accuracy during pattern transfer; but also avoid the collapse of the patterned structure 204 caused by the excessive height of the patterned structure 204.

[0058] Please refer to Figure 11 and Figure 12 , Figure 12 Figure 11 A schematic cross-sectional view along line A-A, where a barrier layer 205 is formed on the sidewall surface of the patterned structure 204.

[0059] In this embodiment, the method for forming the barrier layer 205 includes: forming an initial barrier layer (not shown) on the surface of the patterned structure 204 and the top surface of the exposed initial mask layer 203; removing the initial barrier layer on the top surface of the patterned structure 204 and the top surface of the initial mask layer 203 to form the barrier layer 205.

[0060] By forming the barrier layer 205 on the sidewall surface of the patterned structure 204, and utilizing the strong isolation property of the barrier layer 205, it can effectively prevent doped ions from entering the sidewall of the patterned structure 204 during the subsequent ion doping process, and then diffusing into the undoped region, reducing the undoped region. The barrier layer 205 effectively improves the consistency between the undoped region and the patterned structure 204, thereby improving the accuracy of pattern transfer.

[0061] The properties that the barrier layer 205 needs to possess include: having strong hardness, aiming to prevent doped ions from penetrating, so that the doped ions enter the sidewall of the patterned structure 204; being able to be cleaned and removed. After ion doping, the barrier layer 205 and the patterned structure 204 need to be removed to achieve subsequent pattern transfer.

[0062] In this embodiment, the material of the barrier layer 205 is silicon oxide; in other embodiments, the material of the barrier layer can also be silicon nitride or silicon oxynitride.

[0063] In this embodiment, the formation process of the initial barrier layer uses atomic layer deposition process. The initial barrier layer formed by the atomic layer deposition process has good uniformity, step coverage, and thickness control ability.

[0064] Since subsequent ion doping treatment needs to be carried out into the initial mask layer 203, it is necessary to remove the initial barrier layer on the top surface of the initial mask layer 203.

[0065] In this embodiment, the process of removing the initial barrier layer on the top surface of the patterned structure 204 and the top surface of the initial mask layer 203 uses a first wet etching process; the etching solution used in the first wet etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

[0066] In this embodiment, the thickness of the barrier layer 205 is 1 nm to 10 nm, and the direction of the thickness is perpendicular to the sidewall of the patterned structure 204.

[0067] For the barrier layer 205 within this thickness range, it can avoid the doping ions breaking through the barrier layer 205 and entering the patterned structure 204 during subsequent ion doping treatment when the thickness of the barrier layer 205 is small; and it can also avoid the waste of resources and the reduction of production efficiency caused by a large thickness of the barrier layer 205.

[0068] Please refer to Figure 13 and Figure 14 , Figure 14 Figure 13 A cross-sectional schematic view along line A-A. Using the patterned structure 204 and the barrier layer 205 as masks, ion doping treatment is performed on the initial mask layer 203 to form a doped region A and an undoped region B located between the doped regions A in the initial mask layer 203.

[0069] Through ion doping treatment, the doped region A and the undoped region B are formed in the initial mask layer 203. When etching the undoped region B subsequently, the purpose is to form a large etching selectivity between the undoped region B and the doped region A, and to avoid damaging the doped region A when etching and removing the undoped region B subsequently, ensuring the accuracy of pattern transfer.

[0070] In this embodiment, the doping ions used in the ion doping treatment are boron ions; in other embodiments, the doping ions can also be phosphorus ions or nitrogen ions.

[0071] In this embodiment, the parameters of the ion doping treatment include: doping energy is 10 KeV to 30 KeV, doping dose is 1E7 atoms / cm 2 ~3E7 atoms / cm 2 , and doping time is 30 s to 120 s.

[0072] Through the ion doping treatment with parameters within this range, it can ensure that the doped region A is sufficiently ion-doped, and avoid affecting the morphology of the first opening due to insufficient doping of the doped region A.

[0073] Please refer to Figure 15 andFigure 16 , Figure 16 Figure 15 Schematic cross-sectional view along line A-A, removing the patterned structure 204 and the barrier layer 205.

[0074] By removing the patterned structure 204 and the barrier layer 205, the top surface of the undoped region B is exposed, and then by etching and removing the undoped region B, the pattern transfer from the patterned structure 204 to the initial mask layer 203 is achieved.

[0075] In this embodiment, the process for removing the patterned structure 204 and the barrier layer 205 includes a second wet etching process; the etching solution used in the second wet etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

[0076] Please refer to Figure 17 and Figure 18 , Figure 18 Figure 17 Schematic cross-sectional view along line A-A, after removing the patterned structure 204 and the barrier layer 205, removing the undoped region B, a mask layer 206 is formed on the surface of the layer to be etched, and a first opening 207 exposing the top surface of the layer to be etched is formed in the mask layer 206.

[0077] The morphology of the first opening 207 is obtained by pattern transfer based on the patterned structure 204 and the barrier layer 205.

[0078] In this embodiment, the process for removing the undoped region B includes a third wet etching process; the etching solution used in the third wet etching process includes a hydrofluoric acid solution, a hydrogen peroxide solution, and ammonia water.

[0079] Please refer to Figure 19 and Figure 20 , Figure 20 Figure 19 Schematic cross-sectional view along line A-A, after forming the first opening 207, etching the layer to be etched with the mask layer 206 as a mask to form a second opening 208 in the layer to be etched; after forming the second opening 208, removing the mask layer 206.

[0080] In this embodiment, the second opening 208 exposes the top surface of the device layer 201, the second opening 208 is located in the dielectric layer 202, and its function is to form a conductive plug structure for electrical connection between the device structure in the device layer 201 and the outside.

[0081] Please continue to refer to Figure 17 and Figure 18 ,Figure 18 Figure 17 Schematic cross-sectional view along line A-A. Correspondingly, in an embodiment of the present invention, a semiconductor structure formed by the above method is also provided, including: an etching layer to be etched; a mask layer 206 located on the etching layer to be etched, and a first opening 207 exposing the top surface of the etching layer to be etched is formed in the mask layer 206.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing an etch layer to be etched; Forming an initial mask layer on the etch layer to be etched; Forming a patterned structure on the initial mask layer, exposing a part of the initial mask layer; Forming a barrier layer on the sidewall surface of the patterned structure; Using the patterned structure and the barrier layer as a mask to perform ion doping treatment on the initial mask layer, forming a doped region and an undoped region between the doped regions in the initial mask layer; Removing the patterned structure and the barrier layer; After removing the patterned structure and the barrier layer, removing the undoped region, and forming a mask layer on the surface of the etch layer to be etched, the mask layer having a first opening exposing the top surface of the etch layer to be etched; wherein, The barrier layer is used to block doping ions from entering the sidewall of the patterned structure and then diffusing to the undoped region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The etch layer to be etched includes a single-layer structure or a multi-layer structure.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, When the etch layer to be etched is a multi-layer structure, the etch layer to be etched includes a substrate and a dielectric layer on the substrate.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The substrate includes a base and a device layer on the base; the dielectric layer is on the device layer.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the patterned structure includes: forming a patterned layer on the surface of the initial mask layer; forming a photoresist layer on the surface of the patterned layer; using the photoresist layer as a mask to etch the patterned layer until the top surface of the initial mask layer is exposed, forming the patterned structure; after forming the patterned structure, removing the photoresist layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The materials of the initial mask layer and the patterned layer are different.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The material of the initial mask layer includes amorphous silicon, polycrystalline silicon or doped silicon.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The height of the patterned structure is 10 nm to 30 nm, and the direction of the height is perpendicular to the top surface of the initial mask layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the barrier layer includes: forming an initial barrier layer on the surface of the patterned structure and the exposed top surface of the initial mask layer; removing the initial barrier layer on the top surface of the patterned structure and the top surface of the initial mask layer to form the barrier layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The material of the barrier layer includes silicon oxide, silicon nitride or silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The formation process of the initial barrier layer adopts an atomic layer deposition process.

12. The method for forming a semiconductor structure according to claim 9, characterized in that, The process of removing the initial barrier layer on the top surface of the patterned structure and the top surface of the initial mask layer adopts a first wet etching process; the etching solution used in the first wet etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the barrier layer is 1 nm to 10 nm, and the direction of the thickness is perpendicular to the sidewall of the patterned structure.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, The doping ions used in the ion doping treatment include boron ions, phosphorus ions or nitrogen ions.

15. The method for forming a semiconductor structure according to claim 1, characterized in that, The parameters of the ion doping treatment include: doping energy is 10 KeV to 30 KeV, doping dose is 1E7 atoms / cm 2 ~3E7 atoms / cm 2 , and doping time is 30 s to 120 s.

16. The method for forming a semiconductor structure as described in claim 1, wherein, The process of removing the patterned structure and the barrier layer adopts a second wet etching process; the etching solution used in the second wet etching process includes a hydrofluoric acid solution and a hydrogen peroxide solution.

17. The method for forming a semiconductor structure as described in claim 1, wherein, The process of removing the undoped region adopts a third wet etching process; the etching solution used in the third wet etching process includes a hydrofluoric acid solution, a hydrogen peroxide solution and ammonia water.

18. The method for forming a semiconductor structure as described in claim 1, wherein, After forming the first opening, the method further includes: using the mask layer as a mask to etch the layer to be etched, so as to form a second opening in the layer to be etched; and removing the mask layer after forming the second opening.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18.

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