Semiconductor devices

Abstract

A semiconductor device is expected to have high tolerance. A semiconductor device is provided, comprising: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region provided on the semiconductor substrate and arranged to sandwich the active portion when viewed from above; a peripheral well region provided on the semiconductor substrate and arranged to surround the active portion when viewed from above; an intermediate well region provided on the semiconductor substrate and arranged between the first well region and the second well region when viewed from above; a first pad provided above the first well region; a second pad provided above the second well region; and a temperature sensing diode provided above the intermediate well region.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there is known a semiconductor device in which an element such as an IGBT (Insulated Gate Bipolar Transistor) is formed (for example, refer to Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-59672

[0006] Patent Document 2: Japanese Patent Application Publication No. 2004-55812 Summary of the invention

[0007] Technical issues

[0008] Semiconductor devices are expected to have high durability.

[0009] Technical Solution

[0010] In order to solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an active portion provided on the semiconductor substrate. The semiconductor device may have a first well region and a second well region, which are provided on the semiconductor substrate and are configured to sandwich the active portion when viewed from above. The semiconductor device may have a peripheral well region, which is provided on the semiconductor substrate and is configured to surround the active portion when viewed from above. The semiconductor device may have an intermediate well region, which is provided on the semiconductor substrate and is configured between the first well region and the second well region when viewed from above. The semiconductor device may have a first solder pad provided above the first well region and a second solder pad provided above the second well region. The semiconductor device may have a temperature sensing diode provided above the intermediate well region.

[0011] The first well region and the second well region may protrude further toward the center side of the active portion than the peripheral well region.

[0012] The semiconductor substrate may have a first end side and a second end side that are opposite to each other in a plan view. The first well region may be disposed between the active portion and the first end side. The second well region may be disposed between the active portion and the second end side.

[0013] The semiconductor device may include a gate channel connected to the first pad. The first pad may be arranged at the center of the first end side.

[0014] The gate flow channel may have an active peripheral portion surrounding the active portion in a plan view. The gate flow channel may have a first well peripheral portion surrounding the first well region in a plan view. The gate flow channel may have a second well peripheral portion surrounding the second well region in a plan view.

[0015] The first well peripheral portion may be disposed at the center of the first end side. The second well peripheral portion may be disposed at the center of the second end side.

[0016] The middle well region may be provided from the first well region to the second well region in a plan view.

[0017] The middle well region may include a wide portion having a width in a direction perpendicular to a direction connecting the first well region and the second well region in a plan view that is wider than other portions. A temperature sensing diode may be disposed above the wide portion.

[0018] The gate flow channel may include an annular portion surrounding the temperature sensing diode in a plan view. The gate flow channel may include a first extension portion extending from the first well region to the annular portion. The gate flow channel may include a second extension portion extending from the second well region to the annular portion.

[0019] In a second aspect of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an active portion provided on the semiconductor substrate. The semiconductor device may have a gate flow channel provided on the semiconductor substrate and arranged to cross the active portion when viewed from above. The semiconductor device may have a temperature sensing diode arranged above the semiconductor substrate. The gate flow channel may have an annular portion surrounding the temperature sensing diode when viewed from above. The gate flow channel may have a first extension portion extending from one end of the annular portion to one end of the active portion. The gate flow channel may have a second extension portion extending from the other end of the annular portion to the other end of the active portion.

[0020] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0022] Figure 2 1 is a diagram showing the temperature sensing diode 178 , the emitter electrode 52 , and each pad disposed above the semiconductor substrate 10 .

[0023] Figure 3 1 is a diagram showing an example of arrangement of the gate flow channel 48 on the upper surface of the semiconductor device 100 .

[0024] Figure 4 yes Figure 3Magnified view of area A in FIG.

[0025] Figure 5 It is shown Figure 4 A diagram showing an example of the bb cross section in FIG.

[0026] Figure 6 Yes Figure 4 A top view of a transistor portion 70 and a diode portion 80 in FIG.

[0027] Figure 7 It is shown Figure 6 A diagram showing an example of the cc cross section in FIG.

[0028] Figure 8 1 is a plan view showing another arrangement example of the gate flow channel 48 .

[0029] Fig. 9 1 is a diagram showing an example of an XZ cross section of the current detection unit 110 .

[0030] Explanation of symbols

[0031] 10: semiconductor substrate, 12: emitter region, 14: base region, 15: contact region, 16: accumulation region, 18: drift region, 20: buffer region, 21: upper surface, 22: collector region, 23: lower surface, 24: collector electrode, 25: connection portion, 29: extension portion, 30: dummy groove portion, 31: front end portion, 32: dummy insulating film, 34: dummy conductive portion, 38: interlayer insulating film, 39: extension portion, 40: gate groove portion, 41: front end portion, 42: gate insulating film, 44: gate conductive portion, 48: gate flow channel, 48-1: first well peripheral portion, 48-2: second well peripheral portion, 48-3: active peripheral portion, 48-4a: first extension portion, 48-4b: second extension portion, 48-5: ring portion , 48-6: Current sensor peripheral portion, 50: Gate pad, 52: Emitter electrode, 54: Contact hole, 56: Contact hole, 60: Mesa portion, 70: Transistor portion, 80: Diode portion, 82: Cathode region, 90: Intermediate region, 100: Semiconductor device, 102: End edge, 110: Current detection portion, 111: First well region, 112: Second well region, 113: Peripheral well region, 114: Intermediate well region, 115: Wide portion, 120: Active portion, 172: Current detection pad, 174: Anode pad, 176: Cathode pad, 178: Temperature sensing diode, 180: Anode wiring, 181: Wiring, 182: Cathode wiring, 184: Anode region, 186: Cathode region, 190: Protective layer, 192: Straight line DETAILED DESCRIPTION

[0032] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0033] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other side is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0034] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis does not limit the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the positive and negative are not recorded but the Z-axis direction is recorded, it means a direction parallel to the +Z-axis and the -Z-axis. In addition, in this specification, the situation of observing from the +Z-axis direction is sometimes referred to as a top view.

[0035] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0036] In this specification, the conductivity type of the doping region doped with impurities is set to P type or N type for description. However, the conductivity type of each doping region can also be opposite in polarity. In addition, in this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0037] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes set to the concentration of the donor or acceptor, whichever is greater. The concentration difference can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by diffusion resistance measurement (SR) can be used as the concentration of the donor or acceptor. In addition, in the case where the concentration distribution of the donor or acceptor has a peak, the peak value can be used as the concentration of the donor or acceptor in the region. In the case where the concentration of the donor or acceptor in the region where the donor or acceptor is present is roughly uniform, the average value of the donor or acceptor concentration in the region can be used as the donor or acceptor concentration.

[0038] Figure 11 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has an edge 102 when viewed from above. The semiconductor substrate 10 of this example has two sets of edge 102 that are opposite to each other when viewed from above. Figure 1 In FIG. 1 , a set of first end edges 102-1 and second end edges 102-2 that are opposite to each other are shown. Figure 1 In the diagram, a direction parallel to the first end side 102-1 and the second end side 102-2 is set as a Y-axis direction, and a direction perpendicular to the first end side 102-1 and the second end side 102-2 is set as an X-axis direction.

[0039] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. Figure 1 The area inside the well region indicated by the oblique lines is the active portion 120. The active portion 120 may include a transistor portion 70 including a transistor element such as an IGBT (insulated gate bipolar transistor). The active portion 120 may also include a diode portion 80 including a diode element such as a FWD (freewheeling diode). The active portion 120 may be an area where at least one of the transistor portion 70 and the diode portion 80 is provided.

[0040] exist Figure 1 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". The transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction. When the active portion 120 is divided in a plan view, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each region of the active portion 120.

[0041] A P-type well region is provided in the semiconductor substrate 10. The well region is a region having a higher doping concentration than the base region described later, and is formed in contact with the upper surface of the semiconductor substrate 10 and is formed to a position deeper than the bottom of the base region. The depth is the depth with the upper surface of the semiconductor substrate 10 as the reference position. Figure 1 FIG. 2 shows an example of the arrangement of the well region on the upper surface of the semiconductor substrate 10. Figure 1 In FIG. 1 , the well region is marked with a hatching line with an oblique line.

[0042] The well region is a P-type region with a high concentration, so it is difficult for the electron current to flow. Therefore, if the well region is unevenly configured, the area where the electron current is difficult to flow will be uneven. The semiconductor device 100 of this example configures the well region with good balance when viewed from above, thereby configuring the area where the electron current is difficult to flow with good balance. As a result, the imbalance of the electron current can be suppressed and the tolerance of the semiconductor device 100 can be improved.

[0043] The semiconductor device 100 includes a first well region 111 and a second well region 112. The first well region 111 and the second well region 112 are arranged in a predetermined direction (in Figure 1 The two well regions sandwich the active portion 120, which means that any straight line connecting the two well regions passes through the active portion 120 in a plan view.

[0044] The first well region 111 may be disposed near the first end edge 102-1. That is, the distance between the first well region 111 and the first end edge 102-1 is smaller than the distance between the first well region 111 and the second end edge 102-2. The second well region 112 may be disposed near the second end edge 102-2. That is, the distance between the second well region 112 and the second end edge 102-2 is smaller than the distance between the second well region 112 and the first end edge 102-1.

[0045] The first well region 111 of this example is arranged between the active portion 120 and the first end side 102-1 in the X-axis direction. The active portion 120 is not arranged between the first well region 111 and the first end side 102-1. That is, the first well region 111 is arranged between one end of the active portion 120 in the X-axis direction and the first end side 102-1. The active portion 120 may have a side parallel to the first end side 102-1. The first well region 111 may be arranged to protrude from the side of the active portion 120 toward the inner side of the active portion 120.

[0046] The second well region 112 of this example is arranged between the active portion 120 and the second end side 102-2 in the X-axis direction. The active portion 120 is not arranged between the second well region 112 and the second end side 102-2. That is, the second well region 112 is arranged between the end of the active portion 120 in the X-axis direction and the second end side 102-2. The active portion 120 may have a side parallel to the second end side 102-2. The second well region 112 may be arranged to protrude from the side of the active portion 120 toward the inner side of the active portion 120.

[0047] The first well region 111 may be disposed in a range including a central position Yc of the first end side 102-1 in the Y-axis direction. The second well region 112 may be disposed in a range including a central position Yc of the second end side 102-2 in the Y-axis direction. The first well region 111 may be sandwiched by the active portion 120 in the Y-axis direction. The second well region 112 may be sandwiched by the active portion 120 in the Y-axis direction. The second well region 112 may be disposed in a range wider than the first well region 111 in the Y-axis direction.

[0048] The second well region 112 may also surround a predetermined area when viewed from above. The second well region 112 of this example surrounds the current detection section 110 provided in the semiconductor substrate 10. The current detection section 110 has the same structure as the transistor section 70, but has a smaller area than the transistor section 70 when viewed from above. A current proportional to the main current in the transistor section 70 flows through the current detection section 110.

[0049] The semiconductor device 100 has a peripheral well region 113 configured to surround the active portion 120 when viewed from above. The peripheral well region 113 can be provided in parallel with each end side of the semiconductor substrate 10. The peripheral well region 113 of this example is an annular region surrounding the active portion 120 when viewed from above. The width of the peripheral well region 113 in a direction perpendicular to each end side of the semiconductor substrate 10 can be constant.

[0050] In this example, the first well region 111 and the second well region 112 protrude further toward the center Ac side of the active portion 120 than the peripheral well region 113. The center Ac of the active portion 120 refers to the geometric center of gravity of the active portion 120 when viewed from above. In another example, at least one of the first well region 111 and the second well region 112 may be disposed between the peripheral well region 113 and the edge 102 of the semiconductor substrate 10. In this case, at least one of the first well region 111 and the second well region 112 protrudes from the peripheral well region 113 toward the edge 102 side.

[0051] The semiconductor device 100 has an intermediate well region 114 that divides the active portion 120 when viewed from above. The active portion 120 can be divided into two or more regions by the well region including the intermediate well region 114. The intermediate well region 114 has a long side in a predetermined well long side direction. The intermediate well region 114 of this example extends along the well long side direction and crosses the active portion 120. Figure 1 The long side direction of the well is the X-axis direction.

[0052] The middle well region 114 is disposed between the first well region 111 and the second well region 112. One end of the middle well region 114 in the longitudinal direction may be connected to the first well region 111, and the other end may be connected to the second well region 112. The middle well region 114 may be disposed in a region overlapping with the center Ac of the active portion 120.

[0053] As described later, a temperature sensing diode is arranged above the middle well region 114. In the semiconductor device having the temperature sensing diode, the first well region 111 and the second well region 112 are arranged with the active portion 120 sandwiched therebetween, and the middle well region 114 is arranged between the first well region 111 and the second well region 112, so that these well regions can be arranged dispersedly in a plan view. Therefore, the well regions can be arranged with good balance without bias. Thus, local concentration of current can be suppressed.

[0054] As described above, the first well region 111 and the second well region 112 are preferably provided in a range including the center position Yc of the edge 102. This allows the well regions to be arranged in a more balanced manner.

[0055] The middle well region 114 may have a wide portion 115 whose width in a direction perpendicular to the long side direction of the well (in this example, the Y-axis direction) is wider than other portions when viewed from above. The wide portion 115 is also provided between the first well region 111 and the second well region 112. The wide portion 115 may be arranged in the center between the first well region 111 and the second well region 112. The wide portion 115 may be provided in an area overlapping with the center Ac of the active portion 120. The wide portion 115 may be arranged in an area in the center of the long side direction of the well including the middle well region 114. The temperature sensing diode is arranged above the wide portion 115. Thus, in a semiconductor device having a temperature sensing diode, the well regions can be arranged in a balanced manner.

[0056] exist Figure 1 , a line connecting the center position Yc of the first end side 102-1 and the center position Yc of the second end side 102-2 is set as a straight line 192. The straight line 192 of this example is a straight line that divides the semiconductor substrate 10 into two equal parts in the Y-axis direction. The first well region 111, the second well region 112, and the middle well region 114 can be arranged above the straight line 192. That is, each region of the first well region 111, the second well region 112, and the middle well region 114 has a portion overlapping with the straight line 192. Thus, in a semiconductor device having a temperature sensing diode, the well regions can be evenly arranged.

[0057] The semiconductor device 100 may include an edge termination structure between the peripheral well region 113 and the edge 102 of the semiconductor substrate 10. The edge termination structure alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure includes, for example, a guard ring that surrounds the active portion 120 and is provided in an annular shape, a field plate, a surface electric field reduction, and a combination thereof.

[0058] Figure 21 is a diagram showing a temperature sensing diode 178, an emitter electrode 52, and pads disposed above a semiconductor substrate 10. The semiconductor device 100 of this example includes a gate pad 50, a current detection pad 172, an anode pad 174, and a cathode pad 176. The gate pad 50 is an example of a first pad disposed above the first well region 111. The current detection pad 172, the anode pad 174, and the cathode pad 176 are examples of second pads disposed above the second well region 112.

[0059] exist Figure 2 In the figure, the dashed line shows Figure 1 The temperature sensing diode 178, the emitter electrode 52 and the pads are indicated by solid lines. The temperature sensing diode 178 of this example is a PN junction diode formed of a semiconductor material such as polysilicon.

[0060] The temperature sensing diode 178 is disposed above the wide portion 115. That is, at least a portion of the temperature sensing diode 178 overlaps with at least a portion of the wide portion 115. In this example, more than half of the temperature sensing diode 178 in a plan view overlaps with the wide portion 115. The temperature sensing diode 178 may overlap with the wide portion 115 in its entirety.

[0061] An anode wiring 180 and a cathode wiring 182 are connected to the anode region and the cathode region of the temperature sensing diode 178. The anode wiring 180 and the cathode wiring 182 are wirings containing metal such as aluminum. The anode wiring 180 and the cathode wiring 182 are arranged above the middle well region 114. An insulating film is provided between the temperature sensing diode 178, the anode wiring 180 and the cathode wiring 182, and the semiconductor substrate 10.

[0062] The emitter electrode 52 and each pad are electrodes made of metal such as aluminum. An insulating film is provided between the emitter electrode 52 and each pad and the semiconductor substrate 10. The emitter electrode 52 and each pad are connected to the semiconductor substrate 10 via contact holes provided in the insulating film. Figure 2 In the figure, the insulating film and the contact holes are omitted.

[0063] The emitter electrode 52 is arranged above the active portion 120. The emitter electrode 52 is connected to the active portion 120 via the above-mentioned contact hole. A wire or a lead frame is connected to the upper surface of the emitter electrode 52, and a predetermined emitter voltage is applied. The emitter electrode 52 and each pad are arranged separately from each other in a plan view. A wire is connected to the upper surface of each pad. The emitter electrode 52 can be provided for the active portion 120-1 and the active portion 120-2, respectively. The emitter electrode 52 can also be provided to connect the active portion 120-1 and the active portion 120-2. It should be noted that the emitter electrode 52 can also be locally arranged above each well region.

[0064] A predetermined gate voltage is applied to the gate pad 50. The gate voltage applied to the gate pad 50 is supplied to the transistor portion of the active portion 120 through a gate flow channel described later, etc. The gate pad 50 is arranged above the first well region 111. That is, at least a portion of the gate pad 50 overlaps with at least a portion of the first well region 111. In this example, more than half of the gate pad 50 overlaps with the first well region 111 when viewed from above. The gate pad 50 may also overlap with the first well region 111 as a whole.

[0065] The current detection pad 172 is connected to the current detection unit 110 to detect the current flowing in the current detection unit 110. The anode pad 174 is connected to the temperature sensing diode 178 via the anode wiring 180. The cathode pad 176 is connected to the temperature sensing diode 178 via the cathode wiring 182. The current detection pad 172, the anode pad 174 and the cathode pad 176 are arranged above the second well region 112. For each pad of the current detection pad 172, the anode pad 174 and the cathode pad 176, at least a portion of the pad overlaps with at least a portion of the second well region 112. In this example, more than half of the area of ​​the current detection pad 172, the anode pad 174 and the cathode pad 176 when viewed from above overlaps with the second well region 112. The current detection pad 172, the anode pad 174 and the cathode pad 176 may also overlap with the second well region 112 as a whole.

[0066] Figure 3 1 is a diagram showing an example of the arrangement of the gate channel 48 on the upper surface of the semiconductor device 100. Figure 3 In FIG. 5 , the emitter electrode 52, the temperature sensing diode 178, and each pad are shown by solid lines, and the gate runner 48 is shown by dotted lines. Figure 3 In the figure, each well region is omitted.

[0067] The gate flow channel 48 is a wiring formed of a conductive material such as polysilicon or metal to which impurities are added. The gate flow channel 48 is arranged above the semiconductor substrate 10. An insulating film is provided between the gate flow channel 48 and the semiconductor substrate 10. The gate flow channel 48 is connected to the gate pad 50, and the gate voltage applied to the gate pad 50 is supplied to each transistor unit 70. The gate flow channel 48 can be arranged above the well region.

[0068] The gate pad 50 is arranged at the center position Yc of the first end side 102-1 in the Y-axis direction. That is, the gate pad 50 is arranged to overlap with the straight line 192. The straight line 192 may pass through the center of the gate pad 50 in the Y-axis direction. That is, the gate pad 50 may be arranged between each active portion 120 divided by the straight line 192. Figure 3, two active portions 120-1 and 120-2 are shown divided by a straight line 192. According to this example, the length of the gate flow path 48 between the gate pad 50 and the transistor portion 70 can be made uniform between the two active portions 120-1 and 120-2.

[0069] The gate flow channel 48 of this example includes an active peripheral portion 48-3 arranged to surround the active portion 120 in a plan view. The active peripheral portion 48-3 can be arranged between the active portion 120 and each edge 102 of the semiconductor substrate 10 in a plan view. The active peripheral portion 48-3 of this example is arranged at Figure 1 The active peripheral portion 48-3 may have a portion parallel to each edge 102 of the semiconductor substrate 10. The first well region 111, the second well region 112 and the middle well region 114 may be arranged in the area surrounded by the active peripheral portion 48-3.

[0070] The active peripheral portion 48-3 disposed along the first end side 102-1 is connected to the gate pad 50. The gate pad 50 is disposed at the center of the end side 102, so that the length of the active peripheral portion 48-3 connecting the active portion 120-1 and the gate pad 50 and the length of the active peripheral portion 48-3 connecting the active portion 120-2 and the gate pad 50 can be made consistent. As a result, the amplitude attenuation and the transmission delay of the gate voltage can be made consistent between the active portion 120-1 and the active portion 120-2. Therefore, in the active portion 120, local concentration of current can be suppressed, and the tolerance of the semiconductor device 100 can be improved.

[0071] The gate flow channel 48 of this example includes a first well peripheral portion 48-1 arranged to surround the first well region 111 in a plan view. The first well peripheral portion 48-1 may surround a portion of the first well region 111. The first well peripheral portion 48-1 of this example is arranged at Figure 1 The first well region 111 is shown above the first well region 111. The first well peripheral portion 48-1 may have a portion parallel to each end side of the first well region 111. The first well peripheral portion 48-1 may be configured to surround at least a portion of the gate pad 50 when viewed from above. At least a portion of the first well peripheral portion 48-1 may be configured between the gate pad 50 and the emitter electrode 52 (or the active portion 120) when viewed from above.

[0072] The first well peripheral portion 48-1 can be arranged at the central position Yc of the first end side 102-1. That is, the straight line 192 passes through the area surrounded by the first well peripheral portion 48-1. According to this example, the shape of the first well peripheral portion 48-1 in a plan view can be made substantially line-symmetrical with respect to the straight line 192. Therefore, the amplitude attenuation and transmission delay of the gate voltage can be made consistent between the active portions 120-1 and 120-2 divided into two parts by the straight line 192.

[0073] The gate runner 48 of this example includes a second well peripheral portion 48-2 arranged to surround the second well region 112 in a plan view. The second well peripheral portion 48-2 may surround a portion of the second well region 112. The second well peripheral portion 48-2 of this example is arranged at Figure 1 The second well region 112 is shown in FIG. The second well peripheral portion 48-2 may have a portion parallel to each end side of the second well region 112. The second well peripheral portion 48-2 may be configured to surround at least a portion of the current detection pad 172, the anode pad 174, and the cathode pad 176 when viewed from above. At least a portion of the second well peripheral portion 48-2 may be configured between the current detection pad 172 and the emitter electrode 52 (or the active portion 120) when viewed from above. At least a portion of the second well peripheral portion 48-2 may be configured between the anode pad 174 and the emitter electrode 52 (or the active portion 120) when viewed from above. At least a portion of the second well peripheral portion 48-2 may be configured between the cathode pad 176 and the emitter electrode 52 (or the active portion 120) when viewed from above.

[0074] The second well peripheral portion 48-2 can be arranged at the central position Yc of the second end side 102-2. That is, the straight line 192 passes through the area surrounded by the second well peripheral portion 48-2. According to this example, the shape of the second well peripheral portion 48-2 in a plan view can be made substantially line-symmetrical with respect to the straight line 192. Therefore, the amplitude attenuation and transmission delay of the gate voltage can be made consistent between the active portions 120-1 and 120-2 divided into two parts by the straight line 192.

[0075] The gate flow channel 48 of this example includes an annular portion 48-5 surrounding the temperature sensing diode 178 in a plan view. The annular portion 48-5 may surround a portion of the temperature sensing diode 178. The annular portion 48-5 of this example is disposed at Figure 1 The ring portion 48-5 may have a portion parallel to each end side of the wide portion 115. At least a portion of the ring portion 48-5 may be disposed between the temperature sensing diode 178 and the emitter electrode 52 (or the active portion 120) in a plan view.

[0076] The annular portion 48-5 may be arranged so as to surround the center Ac of the active portion 120. The straight line 192 may pass through the region surrounded by the annular portion 48-5. According to this example, the shape of the annular portion 48-5 in a plan view can be made approximately line-symmetrical with respect to the straight line 192. Therefore, the amplitude attenuation and the transmission delay of the gate voltage can be made uniform between the active portions 120-1 and 120-2 divided into two parts by the straight line 192.

[0077] The gate channel 48 of this example has a first extension portion 48-4a extending from the first well region 111 to the annular portion 48-5 in a plan view. The first extension portion 48-4a is provided to extend from the end of the annular portion 48-5 to the end of the active portion 120, and connects the annular portion 48-5 to the first well peripheral portion 48-1. The first extension portion 48-4a of this example is arranged at Figure 1 The first extension portion 48 - 4 a may have a portion parallel to the straight line 192 . The first extension portion 48 - 4 a may be disposed overlapping the straight line 192 .

[0078] The gate channel 48 of this example has a second extension portion 48-4b extending from the second well region 112 to the annular portion 48-5 when viewed from above. The second extension portion 48-4b is provided to extend from the end of the annular portion 48-5 to the end of the active portion 120, connecting the annular portion 48-5 to the second well peripheral portion 48-2. The first extension portion 48-4a and the second extension portion 48-4b are connected to different parts of the annular portion 48-5. The first extension portion 48-4a and the second extension portion 48-4b of this example are connected to both ends of the annular portion 48-5 in the X-axis direction. The second extension portion 48-4b of this example is arranged at Figure 1 The second extension portion 48 - 4 b may have a portion parallel to the straight line 192 . The second extension portion 48 - 4 b may be disposed overlapping the straight line 192 .

[0079] The first extension portion 48-4a, the second extension portion 48-4b, and the annular portion 48-5 are arranged to cross between the active portion 120-1 and the active portion 120-2 along the X-axis direction. Thus, in the configuration provided with the temperature sensing diode 178, the active portion 120-1 and the active portion 120-2 can be respectively surrounded by the gate runner 48. Therefore, for each region of the active portion 120, it is possible to suppress the wiring distance from the gate pad 50 from becoming longer. Therefore, for each region of the active portion 120, it is possible to reduce the variation of the wiring distance, and make the amplitude attenuation and transmission delay of the gate voltage uniform.

[0080] Figure 4 yes Figure 3 1 is an enlarged view of region A in FIG. Region A is a region including the ring portion 48-5 of the gate flow channel 48, the temperature sensing diode 178, the transistor portion 70, and the diode portion 80. It should be noted that the gate flow channel 48 other than the ring portion 48-5 is also arranged in the same manner with respect to the transistor portion 70 and the diode portion 80. Figure 4 Same as the example.

[0081] As described above, the temperature sensing diode 178 of this example is surrounded by the annular portion 48-5 when viewed from above. The annular portion 48-5 is provided between the temperature sensing diode 178 and the transistor portion 70 and between the temperature sensing diode 178 and the diode portion 80. The wide portion 115 of the intermediate well region 114 is provided below the temperature sensing diode 178 and below the annular portion 48-5. The wide portion 115 may be provided closer to the active portion 120 than the annular portion 48-5. It should be noted that the well region other than the wide portion 115 also has the same Figure 4 The wide portion 115 described in the above description has the same structure.

[0082] The temperature sensing diode 178 of this example has a plurality of PN junctions formed by an N-type cathode region 186 and a P-type anode region 184. Each PN junction is connected in series by wiring 181. Wiring 181 is, for example, a metal wiring. Through wiring 181, the anode region 184 of a certain PN junction is connected to the cathode region 186 of another PN junction. A plurality of PN junctions can be arranged along the X-axis direction. At least one PN junction can be arranged at a position opposite to the diode portion 80 in the Y-axis direction. At least one PN junction can be arranged at a position opposite to the transistor portion 70 in the Y-axis direction.

[0083] The semiconductor device 100 of this example includes a gate trench portion 40 and a dummy trench portion 30 provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 is electrically connected to the gate flow channel 48, and the dummy trench portion 30 is electrically connected to the emitter electrode 52. The gate trench portion 40 is provided in the transistor portion 70, and the dummy trench portion 30 is provided in the diode portion 80. The dummy trench portion 30 may also be provided in the transistor portion 70. The gate trench portion 40 and the dummy trench portion 30 are provided on the upper surface of the semiconductor substrate 10 in a predetermined long side direction (in Figure 4 It has a long side in the Y-axis direction.

[0084] The gate groove portion 40 of this example is extended to a position overlapping with the annular portion 48-5 of the gate flow channel 48 and connected to the annular portion 48-5. In addition, the dummy groove portion 30 may terminate at a position that does not overlap with the wide portion 115 in the Y-axis direction. The dummy groove portion 30 may be extended to a position overlapping with the wide portion 115. The dummy groove portion 30 may be connected to the emitter electrode 52 in the region overlapping with the wide portion 115.

[0085] Figure 5 It is shown Figure 4bb section is a YZ plane including the diode portion 80. In this example, a temperature sensing diode 178, an annular portion 48-5 of the gate flow channel 48, and an emitter electrode 52 are provided above the upper surface 21 of the semiconductor substrate 10. An interlayer insulating film 38 is provided between the upper surface 21 of the semiconductor substrate 10 and the temperature sensing diode 178, the annular portion 48-5, and the emitter electrode 52. The interlayer insulating film 38 may be a thermal oxide film, a glass such as BPSG, or other insulating films. In addition, the interlayer insulating film 38 may be a film in which a plurality of insulating films are stacked.

[0086] The annular portion 48-5 may be arranged to sandwich the temperature sensing diode 178 in the Y-axis direction. The emitter electrode 52 is provided in a range that does not overlap with the temperature sensing diode 178. The wide portion 115 of the well region is provided below the annular portion 48-5 and the temperature sensing diode 178. A protective film 190 such as polyimide is provided above the temperature sensing diode 178 and the annular portion 48-5. The protective film 190 may cover a portion of the emitter electrode 52. A wiring such as a wire is connected to the surface of the emitter electrode 52 that is not covered by the protective film 190.

[0087] In the diode portion 80, a P-type base region 14 is provided in a region in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 functions as an anode region of the diode. The base region 14 is provided from the diode portion 80 to a position in contact with the wide portion 115. The well region such as the wide portion 115 is a P-type region formed from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the base region 14, and is a region with a higher doping concentration than the base region 14.

[0088] An N-type drift region 18 is provided below the wide portion 115 and the base region 14. The drift region 18 is a region through which carriers pass in the depth direction in the transistor portion 70 and the diode portion 80. In the diode portion 80, an N+ type cathode region is provided in a region in contact with the lower surface 23 of the semiconductor substrate 10. The cathode region can be configured separately from the well region such as the wide portion 115 when viewed from above. In this example, in addition to the diode portion 80, the region in contact with the lower surface 23 of the semiconductor substrate 10 can be a P+ type collector region 22. In addition, an N-type buffer region 20 can be provided between the drift region 18 and the cathode region and the collector region 22. A collector electrode 24 can be provided below the cathode region and the collector region 22.

[0089] Figure 6 Yes Figure 4 A top view of a transistor portion 70 and a diode portion 80 in FIG. Figure 6The vicinity of the annular portion 48-5 of the gate flow channel 48 is enlarged. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region such as a wide portion 115, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. Figure 6 The vicinity of the wide portion 115 is magnified in the figure, but the transistor portion 70 and the diode portion 80 also have the same structure in the vicinity of the first well region 111 , the second well region 112 , the peripheral well region 113 , and the intermediate well region 114 .

[0090] exist Figure 6 , the range where the emitter electrode 52 is provided is shown. The emitter electrode 52 of this example is provided in the range overlapping with the annular portion 48-5, but it may not overlap with the annular portion 48-5. An interlayer insulating film is provided between the emitter electrode 52 and the upper surface 21 of the semiconductor substrate 10, but Figure 6 In the interlayer insulating film of this example, the contact hole 56 and the contact hole 54 are provided so as to penetrate the interlayer insulating film.

[0091] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface 21 of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. A connecting portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connecting portion 25 is provided on the upper surface of the semiconductor substrate. An insulating film such as a thermal oxide film is provided between the connecting portion 25 and the semiconductor substrate.

[0092] An insulating film such as a thermal oxide film is provided between the annular portion 48-5 and the semiconductor substrate 10. The annular portion 48-5 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface 21 of the semiconductor substrate 10. The annular portion 48-5 is not connected to the dummy conductive portion in the dummy groove portion 30. The annular portion 48-5 of this example is provided to overlap with the front end portion 41 of the gate groove portion 40. The front end portion 41 is the end closest to the annular portion 48-5 in the gate groove portion 40. At the front end portion 41 of the gate groove portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate and contacts the annular portion 48-5.

[0093] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium and / or a titanium compound, etc., in a lower layer of a region formed of aluminum, etc. Furthermore, a plug formed by embedding tungsten, etc., in a manner that contacts the barrier metal and aluminum, etc., may also be provided in the contact hole.

[0094] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction in the region of the transistor portion 70 . Figure 6 The arrangement direction in the embodiment is the X-axis direction. In the transistor portion 70 , one or more gate trench portions 40 and one or more dummy trench portions 30 may be alternately provided along the arrangement direction.

[0095] The gate trench portion 40 of this example may include two extending portions 39 extending in an extending direction perpendicular to the arrangement direction (portions forming a linear trench along the extending direction) and a front end portion 41 connecting the two extending portions 39 . Figure 6 The extension direction is the Y-axis direction. At least a portion of the front end portion 41 is preferably set to a curved shape. In the two extension portions 39 of the gate groove portion 40, the ends of the ends that are straight lines along the extension direction are connected to each other by the front end portion 41, so that the electric field concentration at the ends of the extension portion 39 can be alleviated.

[0096] The dummy trench portions 30 of this example are provided between the extension portions 39 of the gate trench portions 40. These dummy trench portions 30 may have a linear shape extending along the extension direction.

[0097] In the transistor portion 70, an intermediate region 90 in which no emitter region is provided on the surface may be provided at the boundary adjacent to the diode portion 80. In addition, in the transistor portion 70, a plurality of dummy groove portions 30 may be continuously arranged in a portion adjacent to the intermediate region 90. The dummy groove portion 30 provided in the portion adjacent to the intermediate region 90 may also have an extension portion 29 and a front end portion 31. The front end portion 31 and the extension portion 29 have the same shape as the front end portion 41 and the extension portion 39. The length in the extension direction of the dummy groove portion 30 having the front end portion 31 and the dummy groove portion 30 having a straight line shape may be the same.

[0098] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the wide portion 115, the emitter region 12, the base region 14, and the contact region 15. The wide portion 115 is disposed in a predetermined range away from the contact hole 54. In addition, in this example, the wide portion 115 is disposed in a predetermined range away from the contact hole 56. The diffusion depth of the wide portion 115 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The end of the gate trench portion 40 in the extension direction may be disposed at the wide portion 115.

[0099] The mesa portion 60 sandwiched between the grooves is provided with a base region 14. The mesa portion refers to a region on the upper surface side of the deepest bottom of the groove in the portion of the semiconductor substrate 10 sandwiched between the grooves. The base region 14 is of the second conductivity type with a doping concentration lower than that of the wide portion 115.

[0100] A contact region 15 of the second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 of this example is of P+ type. The wide portion 115 may be provided in a manner away from the contact region 15 disposed at the endmost portion in the extending direction of the groove portion in the contact region 15 in the direction of the annular portion 48-5. In addition, in the transistor portion 70, an emitter region 12 of the first conductivity type having a higher doping concentration than the semiconductor substrate 10 is selectively provided on a portion of the upper surface of the contact region 15. The emitter region 12 of this example is of N+ type.

[0101] The contact region 15 and the emitter region 12 are provided from one adjacent trench portion to the other. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are provided to be exposed alternately on the upper surface of the mesa portion 60 along the extending direction of the trench portion.

[0102] In other examples, the contact region 15 and the emitter region 12 may be arranged in stripes along the extending direction in the mesa portion 60 in the transistor portion 70. For example, the emitter region 12 may be arranged in a region adjacent to the trench portion, and the contact region 15 may be arranged in a region sandwiched by the emitter region 12.

[0103] The emitter region 12 may not be provided in the mesa portion 60 of the diode portion 80 . In addition, the contact region 15 is provided in the mesa portion 60 of the intermediate region 90 over a larger area than that of the mesa portion 60 of the transistor portion 70 .

[0104] In transistor section 70, contact hole 54 is provided above each region of contact region 15 and emitter region 12. Contact hole 54 is not provided in the region corresponding to base region 14 and wide portion 115. In diode section 80, contact hole 54 is provided above contact region 15 and base region 14.

[0105] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10. Figure 6 In FIG. 1 , the region where the cathode region 82 is provided is indicated by a dotted line. In the region adjacent to the lower surface 23 of the semiconductor substrate 10, a P+ type collector region may be provided in the region where the cathode region 82 is not provided. Figure 6 Although one mesa portion 60 of the diode portion 80 is shown in FIG. 8 , the diode portion 80 may have a plurality of mesa portions 60 in the X-axis direction.

[0106] An N+ type accumulation region 16 is provided in at least a portion of the transistor portion 70. Figure 6 In FIG. 1 , a region where accumulation region 16 is provided is indicated by a dotted line. Accumulation region 16 may be provided at a position below emitter region 12 or contact region 15 in each mesa portion 60 .

[0107] Figure 7 It is shown Figure 6 FIG. 1 is a diagram showing an example of a cc cross section in FIG. The cc cross section is an XZ plane passing through the emitter region 12. The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section. The emitter electrode 52 is provided on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.

[0108] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are provided by a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0109] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in this cross section.

[0110] In this cross section, on the upper surface 21 side of the semiconductor substrate 10 in the transistor portion 70 , an N+ type emitter region 12 , a P− type base region 14 , and an N+ type accumulation region 16 are provided in order from the upper surface 21 side of the semiconductor substrate 10 .

[0111] In this cross section, a P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode portion 80. In the diode portion 80 of this example, the accumulation region 16 is not provided. In other examples, the accumulation region 16 may also be provided in the diode portion 80. In addition, a contact region 15 is provided on the upper surface 21 of the semiconductor substrate 10 in the intermediate region 90.

[0112] In transistor section 70, N-type drift region 18 is provided below accumulation region 16. Providing accumulation region 16 having a higher concentration than drift region 18 between drift region 18 and base region 14 can enhance carrier injection enhancement effect (IE effect) and reduce on-voltage.

[0113] The accumulation region 16 of this example is provided in each mesa portion 60 of the transistor portion 70. The accumulation region 16 can be provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60. In the diode portion 80, the drift region 18 is provided on the lower surface of the base region 14. In both the transistor portion 70 and the diode portion 80, the N+ type buffer region 20 is provided under the drift region 18.

[0114] The buffer region 20 is provided at the lower side of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer that starts to diffuse from the lower surface of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0115] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. In addition, in the active portion 120, a region where a projected region when the collector region 22 is projected relative to the upper surface 21 of the semiconductor substrate 10 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10 and a predetermined unit structure including an emitter region 12 and a contact region 15 is regularly arranged is set as the transistor portion 70.

[0116] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion is provided in a manner that penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least any one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the order of forming the groove portion after the doped region is formed. The case where the doped region is formed between the groove portions after the groove portion is formed is also included in the case where the groove portion penetrates the doped region.

[0117] The gate groove portion 40 includes a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided in a manner covering the inner wall of the gate groove portion 40. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove portion 40. The gate conductive portion 44 is provided inside the gate groove portion 40 at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0118] The gate conductive portion 44 includes a region opposed to the base region 14 via a gate insulating film 42. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in contact with the gate groove in the base region 14.

[0119] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0120] Figure 8 FIG. 4 is a top view showing another configuration example of the gate flow channel 48. Figures 1 to 7 In the example described in the figure, the gate channel 48 of this example further includes a current sensor peripheral portion 48-6. The current sensor peripheral portion 48-6 is configured to surround the current detection portion 110 when viewed from above. The current sensor peripheral portion 48-6 can be arranged in the area surrounded by the second well peripheral portion 48-2. The second well peripheral portion 48-2 of this example has two straight portions extending in the Y-axis direction. The current sensor peripheral portion 48-6 can be set from one straight portion to another straight portion. The width of the current sensor peripheral portion 48-6 in the Y-axis direction can be greater than the width of the current detection portion 110 in the Y-axis direction.

[0121] Fig. 9 1 is a diagram showing an example of an XZ cross section of the current detection portion 110. The current detection portion 110 is surrounded by the second well region 112. The current detection portion 110 of this example has one or more gate trench portions 40 and one or more mesa portions 60.

[0122] The structure of the gate trench portion 40 of the current detection portion 110 may be the same as the structure of the gate trench portion 40 of the transistor portion 70. The gate trench portion 40 of the current detection portion 110 is connected to the current sensor peripheral portion 48-6. The density per unit area of ​​the gate trench portion 40 in the current detection portion 110 may be higher than the density per unit area of ​​the gate trench portion 40 in the transistor portion 70. A plurality of gate trench portions 40 may be provided in the current detection portion 110, and no dummy trench portion 30 may be provided.

[0123] The mesa portion 60 of the current detection section 110 may have the same structure as the mesa portion 60 of the transistor section 70. The emitter region 12 and the base region 14 are provided in the mesa portion 60 of the current detection section 110. Thus, the current detection section 110 performs the same operation as the transistor section 70. The accumulation region 16 may or may not be provided in the mesa portion 60 of the current detection section 110.

[0124] The mesa portion 60 of the current detection portion 110 is connected to the current detection pad 172. The current detection pad 172 may be connected to the mesa portion 60 via a through hole provided in the current sensor peripheral portion 48-6. The upper surface of the mesa portion 60 of the current detection portion 110 may have the same structure as the upper surface of the mesa portion 60 of the transistor portion 70. For example, on the upper surface of the mesa portion 60 of the current detection portion 110, the emitter region 12 and the contact region 15 may be alternately arranged along the Y-axis direction.

[0125] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, It is characterized in that have: Semiconductor substrates; An active portion, disposed on the semiconductor substrate; A first well region and a second well region are provided in the semiconductor substrate and are configured to sandwich the active portion when viewed from above; a peripheral well region disposed in the semiconductor substrate and configured to surround the active portion in a plan view; An intermediate well region, disposed in the semiconductor substrate and arranged between the first well region and the second well region when viewed from above; A first pad is disposed above the first well region; A second pad is disposed above the second well region; as well as A temperature sensing diode is arranged above the middle well region, The intermediate well region is provided from the first well region to the second well region in a plan view.

2. The semiconductor device according to claim 1, It is characterized in that The semiconductor substrate has a first end side and a second end side which are opposite to each other in a plan view. The first well region is arranged between the active portion and the first end side, The second well region is disposed between the active portion and the second end side.

3. The semiconductor device according to claim 2, It is characterized in that The semiconductor device further includes a gate channel connected to the first pad. The first pad is arranged at the center of the first end side.

4. The semiconductor device according to claim 3, It is characterized in that The gate flow channel has: an active peripheral portion surrounding the active portion in a plan view; A first well peripheral portion surrounding the first well region in a plan view; and The second well peripheral portion surrounds the second well region in a plan view.

5. The semiconductor device according to claim 4, It is characterized in that The first well peripheral portion is arranged at the center of the first end side, The second well peripheral portion is arranged at the center of the second end side.

6. The semiconductor device according to claim 1, It is characterized in that The first well region and the second well region protrude further toward the center of the active portion than the peripheral well region.

7. The semiconductor device according to claim 6, It is characterized in that The semiconductor substrate has a first end side and a second end side which are opposite to each other in a plan view. The first well region is arranged between the active portion and the first end side, The second well region is disposed between the active portion and the second end side.

8. The semiconductor device according to claim 7, It is characterized in that The semiconductor device further includes a gate channel connected to the first pad. The first pad is arranged at the center of the first end side.

9. The semiconductor device according to claim 8, It is characterized in that The gate flow channel has: an active peripheral portion surrounding the active portion in a plan view; A first well peripheral portion surrounding the first well region in a plan view; and The second well peripheral portion surrounds the second well region in a plan view.

10. The semiconductor device according to claim 9, It is characterized in that The first well peripheral portion is arranged at the center of the first end side, The second well peripheral portion is arranged at the center of the second end side.

11. The semiconductor device according to any one of claims 1 to 10, It is characterized in that The intermediate well region has a wide portion having a width in a direction orthogonal to a direction connecting the first well region and the second well region as viewed from above, which is wider than a width of other portions. The temperature sensing diode is arranged above the wide portion.

12. The semiconductor device according to any one of claims 3 to 5 or claims 8 to 10, It is characterized in that The gate flow channel has: an annular portion surrounding the temperature sensing diode in a plan view; A first extension portion, arranged from the first well region to the annular portion; as well as The second extension portion is provided from the second well region to the annular portion.

13. A semiconductor device, It is characterized in that have: Semiconductor substrates; An active portion, disposed on the semiconductor substrate; a gate channel disposed on the semiconductor substrate and arranged to cross the active portion when viewed from above; and A temperature sensing diode is disposed above the semiconductor substrate; The gate flow channel has: an annular portion surrounding the temperature sensing diode in a plan view; a first extending portion extending from one end of the annular portion to one end of the active portion; and a second extending portion extending from the other end of the annular portion to the other end of the active portion, The annular portion is arranged to surround the center of the active portion.

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