Series circuit, power-on timing control circuit and computing device

Abstract

Embodiments of the present disclosure relate to a series circuit, a power-on sequence control circuit, and a computing device. The series circuit described in the embodiment of the present disclosure includes at least one group of N levels of chips to be powered, connected in series, each of which has a main operating voltage input terminal. The power-on sequence control circuit provided by the embodiment of the present disclosure includes N levels of clamping circuits corresponding to the N levels of chips to be powered, connected in series. By adding a feedback output terminal to each level of the clamping circuit, feedback control of the power-on speed of the clamping circuit at a lower level is achieved based on the output voltage of the clamping circuit at the current level, ensuring consistent power-on speeds for each level of the clamping circuit. This allows for simultaneous power-on of each level of chips in each group of series chips in the series circuit, as well as simultaneous power-on of each level of chips and the clamping circuit. During the power-on process, negative voltage on the chip and voltage imbalance between the chips are avoided, thereby improving chip performance and the stability of the series circuit.

Description

Technical Field

[0001] The present application relates to the field of chip power supply technology, for example, to a series circuit, a power-on timing control circuit and a computing device. Background Art

[0002] Some computing devices include a series chipset, or a circuit consisting of multiple series chipsets connected in parallel. Each series chipset requires a series power supply. This type of circuit is called a series circuit. The multiple chips in each series chipset are connected in series, with the output voltage of the previous chip serving as the input voltage for the next chip. Because each chip level is connected in series, if the equivalent internal resistance of a particular chip is large or small, the voltage across that chip may not be the set voltage. This can cause the chip to malfunction or become inoperable, impacting the performance of the entire series circuit. In some data-intensive applications, DDR memory chips are required around each chip. The power consumption of these chips varies significantly at different times, leading to high initial currents and unbalanced loads on each chip level, resulting in unstable operating voltages. Therefore, a clamping circuit is required to clamp the voltage across each chip to the required voltage. During the power-up process of a series circuit, if the series chip serving as the main circuit is powered on first and the clamping circuit is powered on later, voltage imbalance may occur among the chips, and the clamping circuit may be unable to be turned on and used due to overvoltage protection. If the clamping circuit is powered on first and the series chip serving as the main circuit is powered on later, negative voltage will appear on the chip, affecting its performance. Summary of the Invention

[0003] The embodiment of the present disclosure provides a power-on timing control circuit for a series circuit, wherein the series circuit includes at least one group of chips to be powered that are sequentially connected in series, each of the chips to be powered has a main working voltage input terminal, and the power-on timing control circuit includes N levels of clamping circuits corresponding to the N levels of chips to be powered that are sequentially connected in series, each level of the clamping circuit has a voltage output terminal and a voltage input terminal, the voltage input terminal of each level of the clamping circuit is respectively connected to a first power supply, and the voltage output terminal of each level of the clamping circuit is connected to the main working voltage input terminal of the chip to be powered at the same level, so as to stabilize the main working voltage of each level of the chip to be powered; wherein N is an integer greater than 1, and the 1st to N-1th level clamping circuits are connected to the main working voltage input terminal of the chip to be powered. The clamping voltage of the circuit increases step by step; each clamping circuit also has an enable control terminal, and the power-on speed of each clamping circuit is controlled by the enable voltage of the enable control terminal; the clamping circuits of the second to Nth stages also have feedback output terminals, the voltage of which increases as the output voltage of the clamping circuit increases; the feedback output terminal of the i-th stage clamping circuit is connected to the enable control terminal of the i-1-th stage clamping circuit; when the output voltage of the i-th stage clamping circuit is the clamping voltage of the i-1-th stage clamping circuit, the feedback voltage of the feedback output terminal of the i-th stage clamping circuit is the clamping limit threshold voltage of the i-1-th stage clamping circuit, so as to control the power-on speed of each clamping circuit to be consistent; wherein i=2, ..., N.

[0004] Furthermore, based on the above-mentioned power-on timing control circuit, each level of the clamping circuit includes: a clamping main circuit unit, the clamping main circuit unit having an input end, an output end, an enable end and a clamping control end, the input end, output end and enable end of the clamping main circuit unit being respectively connected to the voltage input end, voltage output end and enable control end of the clamping circuit in which it is located; the clamping circuits of the second to Nth levels also include a first voltage dividing unit, the first voltage dividing unit having an input end and an output end, the input end of the first voltage dividing unit being connected to the voltage output end of the clamping circuit in which it is located, and the output end of the first voltage dividing unit being connected to the feedback output end of the clamping circuit in which it is located; the first voltage dividing unit of the i-th level clamping circuit is used to control the enable voltage of the enable control end of the i-1th level clamping circuit according to the output voltage of the clamping circuit in which it is located, so as to control the power-on speed of the clamping circuits of each level; wherein i=2,…,N.

[0005] Furthermore, based on the above-mentioned power-on timing control circuit, each level of the clamping circuit also includes: a second voltage divider unit, the second voltage divider unit having an input end and an output end, the input end of the second voltage divider unit is connected to the voltage output end of the clamping circuit, the output end of the second voltage divider unit is connected to the clamping control end of the clamping main circuit unit, and the second voltage divider unit is used to control the clamping limit voltage of the clamping circuit according to the voltage output end of the clamping circuit; when the output voltage of the clamping circuit is the clamping voltage, the voltage at the output end of the second voltage divider unit is the clamping limit threshold voltage of the clamping circuit.

[0006] Furthermore, based on the above power-on timing control circuit, the first voltage divider unit of the i-th clamping circuit and the second voltage divider unit of the (i-1)-th clamping circuit have the same voltage dividing ratio to control the power-on speed of each clamping circuit to be consistent.

[0007] Furthermore, based on the above power-on timing control circuit, for each clamp circuit, during the power-on process of the clamp circuit, as the output voltage of the clamp circuit increases, the clamp limit voltage output by the second voltage divider unit of the clamp circuit to the clamp control terminal of the clamp circuit increases.

[0008] Furthermore, based on the above-mentioned power-on timing control circuit, the voltage of the clamp control terminal is the clamp limit voltage of the clamp circuit in which it is located, and the maximum voltage of the clamp control terminal is the clamp limit threshold voltage of the clamp circuit in which it is located; for each level of the clamp circuit, during the power-on process of the clamp circuit, when the clamp limit voltage of the clamp circuit is less than the clamp limit threshold voltage, the output voltage of the clamp circuit continues to increase; when the clamp limit voltage of the clamp circuit reaches the clamp limit threshold voltage, the output voltage of the clamp circuit reaches the clamp voltage, and the power-on of this level of the clamp circuit is completed.

[0009] Furthermore, based on the above power-on timing control circuit, the clamping limit threshold voltage of each stage of the clamping circuit is the same.

[0010] Furthermore, the first voltage divider unit includes a first resistor and a second resistor connected in series, the first end of the first resistor is connected to the voltage output end of the clamping circuit where the first voltage divider unit is located, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is grounded, and the feedback output end of the clamping circuit where the first voltage divider unit is located is connected to the second end of the first resistor.

[0011] Furthermore, the second voltage-dividing unit includes a third resistor and a fourth resistor connected in series, the first end of the third resistor is connected to the voltage output end of the clamping circuit where the second voltage-dividing unit is located, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, and the clamping control end of the clamping circuit where the second voltage-dividing unit is located is connected to the second end of the third resistor.

[0012] Furthermore, based on the above power-on timing control circuit, the enable terminal of the N-th stage clamping circuit is grounded through the packaging component.

[0013] Furthermore, the packaging component is a capacitor.

[0014] An embodiment of the present disclosure also provides a series circuit, comprising: at least one group of chips to be powered connected in series in sequence, each of the chips to be powered having a main working voltage input terminal and a ground terminal, and a power-on timing control circuit as described above.

[0015] An embodiment of the present disclosure further provides a computing device comprising any of the power-on timing control circuits described above.

[0016] An embodiment of the present disclosure further provides a computing device, characterized in that it comprises the series circuit described above.

[0017] The series circuit, power-on timing control circuit, and computing device provided by the embodiments of the present disclosure add feedback output terminals to each level of clamping circuits. Based on the output voltage of the clamping circuit at the current level, feedback control of the power-on speed of the clamping circuit at the next lower level is implemented, thereby making the power-on speed of each level of clamping circuits consistent. This enables simultaneous power-on of each level of chips in each group of series chips in the series circuit, as well as simultaneous power-on of each level of chips and the clamping circuit. During the power-on process, negative voltage will not appear on the chip, and voltage imbalance will not occur between the chips. This can improve chip performance and the stability of the series circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0019] Figure 1 A schematic diagram of a series circuit provided in an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram of a power-on timing control circuit for a series circuit provided by an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of a first-level clamping circuit of a power-on timing control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0023] An embodiment of the present disclosure provides a power-on timing control circuit for a series circuit. Figure 1 A schematic diagram of a series circuit provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of a power-on timing control circuit for a series circuit provided by an embodiment of the present disclosure. Figure 1 and Figure 2 As shown in , the series circuit includes at least one group of chips to be powered that are sequentially connected in series, and each chip to be powered has a main working voltage input terminal. Wherein N is an integer greater than 1. For example, Figure 1 Taking the series circuit shown in FIG. 1 as an example, the structure of the series circuit is explained exemplarily. Figure 1 The series circuit shown includes two parallel series chip groups (that is, two groups of series chips in the series circuit), each series chip group (that is, each group of series chips) includes 6 levels of chips connected in series in sequence. The power supply for the series chips group of the main line can be 9V, and the power supply for the clamping circuit can be 12V.

[0024] Figure 2 A group of series chips of a series circuit is shown in FIG. 1 , and each group of series chips includes 6 levels of chips connected in series in sequence.

[0025] In the embodiment of the present disclosure, the series circuit may include multiple groups of series chips, each group of series chips is connected in parallel to each other, and the number of chips connected in series in each group is multiple. There is no specific limitation on the number of series chip groups and the number of chips connected in series in each group of series chips.

[0026] like Figure 2 As shown, the power-on timing control circuit of the series circuit includes: N-stage clamping circuits corresponding to the N-stage chips to be powered that are sequentially connected in series.

[0027] like Figure 3 As shown, each clamping circuit has a voltage output terminal and a voltage input terminal. The voltage input terminal of each clamping circuit is respectively connected to a first power supply (not shown in the figure). The voltage output terminal of each clamping circuit is connected to the main working voltage input terminal of the chip to be powered at the same level, so as to stabilize the main working voltage of each chip to be powered. Wherein, N is an integer greater than 1, and the clamping voltage of the clamping circuits of the 1st to the N-1th levels increases step by step. Wherein, the first power supply is the power supply for the clamping circuit, for example Figure 1 A 12V power supply connected to the clamp circuit is shown in FIG.

[0028] Each stage of the clamping circuit further has an enable control terminal (also called an enable pin or EN pin), and the power-on speed of each stage of the clamping circuit is controlled by the enable voltage of the enable control terminal.

[0029] The second through Nth clamping circuits further have feedback output terminals, the voltage of which increases as the output voltage of the corresponding clamping circuit increases. The feedback output terminal of the i-th clamping circuit is connected to the enable control terminal of the i-1st clamping circuit. When the output voltage of the i-th clamping circuit reaches the clamping voltage of the i-1st clamping circuit, the feedback voltage at the feedback output terminal of the i-th clamping circuit reaches the clamping limit threshold voltage of the i-1st clamping circuit, thereby controlling the power-on speed of each clamping circuit to be consistent. Where i = 2, ..., N.

[0030] In the embodiment of the present disclosure, each level of the clamping circuit includes a clamping main circuit unit, which has an input end, an output end, an enable end and a clamping control end. The clamping main circuit unit can be implemented using any chip in the prior art that implements the clamping function (referred to as a clamping circuit chip in this embodiment), wherein the input end and the output end of the clamping main circuit unit correspond to the voltage input pin and the voltage output pin of the clamping circuit chip respectively, the enable end of the clamping main circuit unit corresponds to the enable pin (also called the SS pin) of the clamping circuit chip, and the clamping control end of the clamping main circuit unit corresponds to the control pin (also called the FB pin) of the clamping circuit chip.

[0031] In addition, the clamping main circuit unit of each stage of the clamping circuit may be implemented using the same clamping circuit chip, or may be implemented using different clamping circuit chips, which is not specifically limited in this embodiment.

[0032] The input terminal, output terminal and enable terminal of the clamping main circuit unit are respectively connected to the voltage input terminal, voltage output terminal and enable control terminal of the clamping circuit.

[0033] The clamping limit threshold voltage refers to the maximum limit voltage of the clamping control terminal (i.e., the FB pin) in the clamping circuit. The clamping limit threshold voltage can generally be a preset fixed voltage value, for example, the clamping limit threshold voltage can be 0.6V.

[0034] During the power-on process of the clamp circuit, the voltage of the FB pin increases as the output voltage of the clamp circuit increases. When the FB pin voltage of the clamp circuit reaches the clamp limit threshold voltage, the output terminal voltage of the clamp circuit reaches a maximum value and no longer increases. That is, when the FB pin voltage of the clamp circuit reaches the clamp limit threshold voltage, the output terminal voltage of the clamp circuit reaches the clamp voltage of the clamp circuit.

[0035] The power-on timing control circuit based on the aforementioned series circuit, during the power-on process, uses a first power supply to input voltages to the voltage input terminals of the clamping circuits. The voltage output terminals of each clamping circuit stage are connected to the main operating voltage input terminals of the same stage of the power supply chip, thereby stabilizing the main operating voltage of each stage of the power supply chip. In the first phase after power-on begins, the voltages at the output terminals of each clamping circuit gradually increase, and the voltages at the feedback output terminals of the second through Nth stage clamping circuits also increase as the output voltages of their respective clamping circuits increase. The feedback output terminal of the i-th stage clamping circuit is connected to the enable control terminal of the i-1-th stage clamping circuit. In other words, the feedback output voltage of each clamping circuit serves as the enable control voltage for the clamping circuit in the next lower stage, controlling the power-on speed of the clamping circuit in the next lower stage, thereby ensuring consistent power-on speeds for all clamping circuits. When the output voltage of the i-th clamping circuit is the clamping voltage of the i-1-th clamping circuit, the feedback voltage at the feedback output end of the i-th clamping circuit is the clamping limit threshold voltage of the i-1-th clamping circuit; and at this time, the output voltage of the i-1-th clamping circuit also reaches its clamping voltage, and the FB pin voltage of the i-1-th clamping circuit reaches the clamping limit threshold voltage; at this time, the voltages of the SS pin and the FB pin of the i-1-th clamping circuit simultaneously reach the clamping limit threshold voltage.

[0036] In summary, for each level of clamping circuit, when the output voltage of the clamping circuit reaches the clamping voltage, the voltages at the SS pin and FB pin of the clamping circuit simultaneously reach the clamping limit threshold voltage. In this way, during the power-on process, the voltages at the SS pin and FB pin of each level of clamping circuit increase at the same rate, thereby ensuring consistent power-on speed for each level of clamping circuit.

[0037] In the embodiment of the present disclosure, by adding a feedback output terminal to each level of the clamping circuit, feedback control of the power-on speed of the lower-level clamping circuit is implemented according to the output voltage of the current-level clamping circuit, so that the power-on speed of each level of the clamping circuit is consistent. In this way, when the output voltage of the first-level clamping circuit reaches the corresponding clamping voltage, the output voltages of the second to N-level clamping circuits all reach the clamping voltage of the first-level clamping circuit. Thereafter, the output voltage of the first-level clamping circuit no longer increases. At this time, the voltage of the main working voltage input terminal of the first-level chip is the clamping voltage of the first-level clamping circuit, and the power-on of the first-level clamping circuit and the chip is completed; in the subsequent power-on process, the output voltages of the second to N-level clamping circuits continue to increase to the clamping voltage of the second-level clamping circuit, and thereafter the output voltage of the second-level clamping circuit does not increase. Increase again, at this time, the voltage of the main working voltage input terminal of the second-level chip is the clamping voltage of the second-level clamping circuit, and the second-level clamping circuit and chip are powered on; in the subsequent power-on process, the output voltage of the clamping circuits of the 3rd to Nth levels continues to increase to the clamping voltage of the third-level clamping circuit, and thereafter the output voltage of the third-level clamping circuit no longer increases. At this time, the voltage of the main working voltage input terminal of the third-level chip is the clamping voltage of the third-level clamping circuit, and the third-level clamping circuit and chip are powered on; and so on, until the output voltage of the N-th level clamping circuit reaches the corresponding clamping voltage, at this time the voltage of the main working voltage input terminal of the N-th level chip is the clamping voltage of the N-th level clamping circuit, and the N-th level clamping circuit and chip are powered on, and at this time, all levels of the clamping circuits and chips are powered on.

[0038] The disclosed embodiments add feedback output terminals to each level of clamping circuits, thereby implementing feedback control of the power-on speed of the clamping circuit at a lower level based on the output voltage of the clamping circuit at the current level. This ensures that the power-on speeds of the clamping circuits at each level are consistent, thereby enabling simultaneous power-on of each level of chips in each group of series-connected chips in the series circuit, as well as simultaneous power-on of each level of chips and the clamping circuit. During the power-on process, negative voltage will not appear on the chip, and voltage imbalance will not occur among the chips. This can improve chip performance and the stability of the series circuit.

[0039] Based on the above power-on timing control circuit, in the embodiment of the present disclosure, by adding feedback output terminals to each level of clamping circuit, feedback control of the power-on speed of the lower level clamping circuit is achieved according to the output voltage of the current level clamping circuit. Specifically, this can be achieved by adding a voltage divider unit. Figure 2 and Figure 3 As shown, in the power-on timing control circuit, the clamping circuits of the 2nd to Nth stages further include a first voltage divider unit, which has an input end and an output end. The input end of the first voltage divider unit is connected to the voltage output end of the clamping circuit, and the output end of the first voltage divider unit is connected to the feedback output end of the clamping circuit.

[0040] The first voltage divider unit of the i-th clamp circuit is used to control the enable voltage of the enable control terminal of the i-1-th clamp circuit according to the output voltage of the clamp circuit, so as to control the power-on speed of each clamp circuit so that the power-on speed of each clamp circuit is consistent.

[0041] For example, Figure 3 As shown, the first voltage divider unit of each stage of the clamping circuit can be composed of a first resistor R1 and a second resistor R2 connected in series, the first end of the first resistor R1 is connected to the voltage output end of the clamping circuit, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded, and the feedback output end of the clamping circuit is connected to the second end of the first resistor R1.

[0042] In addition, the first voltage dividing unit can be replaced by any circuit in the prior art that can realize the voltage dividing function. This embodiment does not specifically limit the specific implementation method of the first voltage dividing unit.

[0043] For example, Figure 3 As shown, the Nth level clamp circuit (that is, the highest level clamp circuit, such as Figure 3 The enable terminal of the 6th-stage clamp circuit shown in FIG) can be grounded through a capacitor, and the power-on speed of the Nth-stage clamp circuit can be adjusted through the capacitor.

[0044] In addition, a packaging location can be reserved for the enable terminal of the N-stage clamp circuit, and a packaging component can be placed in this packaging location. This packaging component can be a capacitor, through which the enable terminal of the N-stage clamp circuit is grounded; this packaging component can also be a voltage divider resistor to achieve fine-tuning of the enable terminal voltage of the N-stage clamp circuit, etc. In addition, the packaging component can also be configured by technicians as other devices according to actual application scenarios and needs, and this embodiment does not specifically limit this.

[0045] Based on the above power-on timing control circuit, in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, each level of the clamping circuit further includes: a second voltage dividing unit, the second voltage dividing unit having an input end and an output end, the input end of the second voltage dividing unit being connected to the voltage output end of the clamping circuit, and the output end of the second voltage dividing unit being connected to the clamping control end of the clamping main circuit unit.

[0046] The second voltage divider is used to control the clamping limit voltage of the clamping circuit according to the voltage output terminal of the clamping circuit. When the output voltage of the clamping circuit is the clamping voltage, the voltage at the output terminal of the second voltage divider is the clamping limit threshold voltage of the clamping circuit.

[0047] For example, Figure 3As shown, the second voltage divider unit of each stage of the clamping circuit can be composed of a third resistor R3 and a fourth resistor R4 connected in series, the first end of the third resistor R3 is connected to the voltage output end of the clamping circuit, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is grounded, and the clamping control end of the clamping main circuit unit in the clamping circuit is connected to the second end of the third resistor R3.

[0048] In addition, the second voltage dividing unit can be replaced by any circuit in the prior art that can realize the voltage dividing function. This embodiment does not specifically limit the specific implementation method of the second voltage dividing unit.

[0049] Based on the power-on timing control circuit of the series circuit, the voltage of the clamp control terminal is the clamp limit voltage of the clamp circuit, and the maximum voltage of the clamp control terminal is the clamp limit threshold voltage of the clamp circuit.

[0050] For each level of the clamping circuit, during the power-on process of the clamping circuit, when the clamping limit voltage of the clamping circuit is less than the clamping limit threshold voltage, the output voltage of the clamping circuit continues to increase; when the clamping limit voltage of the clamping circuit reaches the clamping limit threshold voltage, the output voltage of the clamping circuit reaches the clamping voltage, and the power-on of this level of the clamping circuit is completed.

[0051] In the disclosed embodiment, for each clamping circuit stage, as the clamping circuit's output voltage increases during power-up, the clamping voltage output by the clamping circuit's second voltage divider to the clamping control terminal (FB pin) of the clamping circuit increases. When the clamping voltage at the clamping control terminal of the clamping circuit reaches the clamping threshold voltage, the voltage at the output of the clamping circuit reaches its maximum value and stops increasing, reaching the clamping voltage of the clamping circuit.

[0052] Furthermore, in the embodiment of the present disclosure, the first voltage divider unit of the i-th clamping circuit and the second voltage divider unit of the i-1-th clamping circuit have the same voltage divider ratio, thereby ensuring that when the output voltage of the i-th clamping circuit is the clamping voltage of the i-1-th clamping circuit, the feedback voltage at the feedback output terminal of the i-th clamping circuit is the clamping limit threshold voltage of the i-1-th clamping circuit. Where i = 2, ..., N.

[0053] For example, when selecting the clamping main circuit unit of each clamping circuit, the clamping limit threshold voltage of each clamping circuit can be made the same, which makes it easier to configure the first voltage divider unit and the second voltage divider unit of each clamping circuit.

[0054] For example, the embodiment of the present disclosure provides a specific implementation of the first voltage dividing unit and the second voltage dividing unit in each level of the clamping circuit. Figure 2As shown in the figure, taking the clamping voltages of the 1st to 6th level clamping circuits as 1.5V, 3V, 4.5V, 6V, 7.5V and 9V respectively; and the clamping limit threshold voltage of each level clamping circuit as 0.6V as an example, the possible settings of the various resistance values ​​in the first voltage divider unit and the second voltage divider unit in each level clamping circuit are exemplarily described.

[0055] For example, Figure 2 As shown, the values ​​of the third resistor R3 and the fourth resistor R4 of the second voltage divider unit in the first-stage clamping circuit can be 15K ohms and 10K ohms, respectively. When the voltage output terminal voltage of each stage of the clamping circuit is 1.5V, the clamping control terminal voltage of the clamping main circuit unit obtained by the voltage division of the first voltage divider unit in the first-stage clamping circuit is 0.6V, reaching the clamping limit threshold voltage. After that, the output voltage of the first-stage clamping circuit will no longer increase.

[0056] The first voltage divider of the second-stage clamp circuit can be the same as the second voltage divider of the first-stage clamp circuit. Specifically, the first resistor R1 and the second resistor R2 of the first voltage divider are 15k ohms and 10k ohms, respectively. When the output voltage of the second-stage clamp circuit is equal to the clamp voltage of the first-stage clamp circuit, 1.5V, the feedback voltage at the feedback output terminal of the second-stage clamp circuit is 0.6V, which is the clamping threshold voltage of the first-stage clamp circuit. The third resistor R3 and the fourth resistor R4 of the second voltage divider of the second-stage clamp circuit can be 40k ohms and 10k ohms, respectively. When the voltage output terminal of the second- to sixth-stage clamp circuit reaches 3V, the voltage at the clamp control terminal of the clamp main circuit unit, obtained by dividing the voltage by the first voltage divider in the second-stage clamp circuit, is 0.6V, reaching the clamping threshold voltage. Thereafter, the output voltage of the second-stage clamp circuit will no longer increase.

[0057] The first voltage divider of the third-stage clamp circuit can be the same as the second voltage divider of the second-stage clamp circuit. Specifically, the first resistor R1 and the second resistor R2 of the first voltage divider of the third-stage clamp circuit are 40k ohms and 10k ohms, respectively. When the output voltage of the third-stage clamp circuit reaches the clamping voltage of the second-stage clamp circuit, 3V, the feedback voltage at the feedback output terminal of the third-stage clamp circuit is 0.6V, which is the clamping threshold voltage of the second-stage clamp circuit. The third resistor R3 and the fourth resistor R4 of the second voltage divider of the third-stage clamp circuit can be 65k ohms and 10k ohms, respectively. When the voltage output terminal of the third- to sixth-stage clamp circuit reaches 4.5V, the voltage at the clamping control terminal of the clamping main circuit unit, obtained by dividing the voltage by the first voltage divider of the third-stage clamp circuit, reaches 0.6V, reaching the clamping threshold voltage. Thereafter, the output voltage of the third-stage clamp circuit will no longer increase.

[0058] The first voltage divider of the fourth-stage clamp circuit can be the same as the second voltage divider of the third-stage clamp circuit. Specifically, the first resistor R1 and the second resistor R2 of the first voltage divider of the fourth-stage clamp circuit are 65k ohms and 10k ohms, respectively. When the output voltage of the fourth-stage clamp circuit reaches the clamping voltage of the third-stage clamp circuit, 4.5V, the feedback voltage at the feedback output terminal of the fourth-stage clamp circuit is 0.6V, which is the clamping limit threshold voltage of the third-stage clamp circuit. The third resistor R3 and the fourth resistor R4 of the second voltage divider of the fourth-stage clamp circuit can be 90k ohms and 10k ohms, respectively. When the voltage output terminal of the fourth- to sixth-stage clamp circuit reaches 6V, the voltage at the clamping control terminal of the clamping main circuit unit, obtained by dividing the voltage by the first voltage divider in the fourth-stage clamp circuit, reaches 0.6V, reaching the clamping limit threshold voltage. Thereafter, the output voltage of the fourth-stage clamp circuit will no longer increase.

[0059] The first voltage divider of the fifth-stage clamp circuit can be the same as the second voltage divider of the fourth-stage clamp circuit. Specifically, the first resistor R1 and the second resistor R2 of the first voltage divider of the fifth-stage clamp circuit are 90k ohms and 10k ohms, respectively. When the output voltage of the fifth-stage clamp circuit reaches the clamping voltage of the fourth-stage clamp circuit, which is 6V, the feedback voltage at the feedback output terminal of the fifth-stage clamp circuit is 0.6V, which is the clamping limit threshold voltage of the fourth-stage clamp circuit. The third resistor R3 and the fourth resistor R4 of the second voltage divider of the fifth-stage clamp circuit can be 115k ohms and 10k ohms, respectively. When the voltage output terminal of the fifth-stage clamp circuit reaches 7.5V, the voltage at the clamping control terminal of the clamping main circuit unit, obtained by dividing the voltage by the first voltage divider of the fifth-stage clamp circuit, reaches 0.6V, reaching the clamping limit threshold voltage. Thereafter, the output voltage of the fifth-stage clamp circuit will no longer increase.

[0060] The first voltage divider of the sixth-stage clamp circuit can be the same as the second voltage divider of the fifth-stage clamp circuit. Specifically, the first resistor R1 and the second resistor R2 of the first voltage divider of the sixth-stage clamp circuit are 115k ohms and 10k ohms, respectively. When the output voltage of the sixth-stage clamp circuit reaches the clamping voltage of the fifth-stage clamp circuit, 7.5V, the feedback voltage at the feedback output terminal of the sixth-stage clamp circuit is 0.6V, which is the clamping threshold voltage of the fifth-stage clamp circuit. The third resistor R3 and the fourth resistor R4 of the second voltage divider of the sixth-stage clamp circuit can be 140k ohms and 10k ohms, respectively. When the voltage at the output terminal of the sixth-stage clamp circuit reaches 9V, the voltage at the clamping control terminal of the clamping main circuit unit, obtained by dividing the voltage by the first voltage divider of the sixth-stage clamp circuit, reaches 0.6V, reaching the clamping threshold voltage. Thereafter, the output voltage of the sixth-stage clamp circuit will no longer increase.

[0061] like Figure 2As shown, the first through sixth clamping circuits all include a second voltage divider unit, and the second through sixth clamping circuits also include a first voltage divider unit. The first voltage divider unit of each clamping circuit in the second through sixth clamping circuits is consistent with the second voltage divider unit of the clamping circuit in the next lower level. This ensures that the voltages at the SS and FB pins of each clamping circuit increase at the same rate before reaching the clamping voltage, thereby ensuring consistent power-up speeds for each clamping circuit and, consequently, for each chip.

[0062] In addition, the sixth-level clamp circuit is the highest-level clamp circuit. The voltage of the SS pin can be adjusted through the capacitor or voltage-dividing resistor connected to the SS pin to control the power-on speed of the sixth-level clamp circuit.

[0063] The disclosed embodiment adds a first voltage divider unit to the second to Nth clamping circuits and a second voltage divider unit to each clamping circuit. The first voltage divider unit of the i-th clamping circuit controls the enable voltage of the enable control terminal of the i-1st clamping circuit according to the output voltage of the clamping circuit. The second voltage divider unit of each clamping circuit controls the clamping limit voltage of the clamping circuit according to the voltage output terminal of the clamping circuit. By setting the clamping limit threshold voltage of each clamping circuit to be the same, and the voltage dividing ratio of the first voltage divider unit of the i-th clamping circuit to be the same as the second voltage divider unit of the i-1st clamping circuit, the power-on speed of each clamping circuit is controlled to be consistent, thereby controlling the power-on speed of each chip to be consistent, and powering on each chip in a step-by-step manner. The embodiment can achieve simultaneous power-on of each chip in each group of series-connected chips in the series circuit at a consistent power-on speed, as well as simultaneous power-on of each chip and the clamping circuit. During the power-on process, negative voltage on the chip and voltage imbalance between the chips are avoided, thereby improving chip performance and the stability of the series circuit.

[0064] An embodiment of the present disclosure also provides a series circuit, comprising: at least one group of chips to be powered connected in series in sequence, each of the chips to be powered having a main working voltage input terminal and a ground terminal, and a power-on timing control circuit provided by any of the above embodiments.

[0065] This embodiment uses a power-on timing control circuit to achieve simultaneous power-on of chips at all levels in each group of series-connected chips in a series circuit with consistent power-on speeds, as well as simultaneous power-on of chips at all levels and clamping circuits. During the power-on process, there will be no negative voltage on the chip and no voltage imbalance between the chips, thereby improving chip performance and the stability of the series circuit.

[0066] An embodiment of the present disclosure also provides a computing device, comprising the above-mentioned series circuit, which includes: at least one group of chips to be powered that are connected in series in sequence, each of the chips to be powered having a main working voltage input terminal and a ground terminal, and a power-on timing control circuit provided by any of the above-mentioned embodiments.

[0067] An embodiment of the present disclosure further provides a computing device comprising the power-on timing control circuit provided by any of the above embodiments.

[0068] When used in this application, although the terms "first," "second," etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be called a second element, and similarly, a second element can be called a first element, without changing the meaning of the description, as long as all occurrences of "first element" are consistently renamed and all occurrences of "second element" are consistently renamed. A first element and a second element are both elements, but they do not have to be the same element.

[0069] The terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates, the singular forms "a", "an" and "the" are intended to also include the plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups of these.

[0070] The various aspects, implementations, implementations, or features of the described embodiments can be used individually or in any combination. The various aspects of the described embodiments can be implemented by software, hardware, or a combination of software and hardware. The described embodiments can also be embodied by a computer-readable medium storing computer-readable code, the computer-readable code comprising instructions executable by at least one computing device. The computer-readable medium can be associated with any data storage device capable of storing data that can be read by a computer system. Examples of computer-readable media include read-only memory, random access memory, CD-ROM, HDD, DVD, magnetic tape, and optical data storage devices. The computer-readable medium can also be distributed among computer systems connected via a network so that the computer-readable code can be stored and executed in a distributed manner.

[0071] The above technical description may refer to the accompanying drawings, which form a part of this application and illustrate implementation methods in accordance with the described embodiments in the drawings. Although these embodiments are described in sufficient detail to enable those skilled in the art to implement these embodiments, these embodiments are non-limiting; other embodiments can be used and changes can be made without departing from the scope of the described embodiments. For example, the order of operations described in the flowchart is non-limiting, so the order of two or more operations illustrated in the flowchart and described according to the flowchart can be changed according to several embodiments. As another example, in several embodiments, one or more operations illustrated in the flowchart and described according to the flowchart are optional or deletable. In addition, certain steps or functions can be added to the disclosed embodiments, or the order of two or more steps can be replaced. All these changes are considered to be included in the disclosed embodiments and the claims.

[0072] In addition, terms are used in the above technical description to provide a thorough understanding of the described embodiments. However, overly detailed details are not required to implement the described embodiments. Therefore, the above description of the embodiments is presented for the purpose of illustration and description. The embodiments presented in the above description and the examples disclosed based on these embodiments are provided separately to add context and help understand the described embodiments. The above description is not intended to be exhaustive or to limit the described embodiments to the precise form of the present disclosure. Based on the above teachings, several modifications, selective applications and variations are feasible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

1. A power-on timing control circuit for a series circuit, the series circuit comprising at least one group of N chips to be powered connected in series, each chip to be powered having a main working voltage input terminal, characterized in that: The power-on timing control circuit includes N levels of clamping circuits corresponding to the N levels of chips to be powered, which are sequentially connected in series. Each level of the clamping circuit has a voltage output end and a voltage input end. The voltage input end of each level of the clamping circuit is respectively connected to the first power supply. The voltage output end of each level of the clamping circuit is connected to the main working voltage input end of the chip to be powered at the same level, so as to stabilize the main working voltage of each level of the chip to be powered. Wherein, N is an integer greater than 1, and the clamping voltage of the clamping circuits from the 1st level to the N-1st level increases step by step. Each level of the clamping circuit also has an enable control terminal, and the power-on speed of each level of the clamping circuit is controlled by the enable voltage of the enable control terminal; The clamping circuits of the second to Nth stages further have feedback output terminals, the voltage of which increases as the output voltage of the clamping circuit increases. The feedback output terminal of the i-th stage clamping circuit is connected to the enable control terminal of the i-1-th stage clamping circuit. When the output voltage of the i-th stage clamping circuit is the clamping voltage of the i-1-th stage clamping circuit, the feedback voltage of the feedback output terminal of the i-th stage clamping circuit is the clamping limit threshold voltage of the i-1-th stage clamping circuit, thereby controlling the power-on speed of each stage clamping circuit to be consistent; wherein i=2, ..., N.

2. The power-on timing control circuit according to claim 1, wherein: Each level of the clamping circuit includes: a clamping main circuit unit, the clamping main circuit unit having an input terminal, an output terminal, an enable terminal and a clamping control terminal, the input terminal, the output terminal and the enable terminal of the clamping main circuit unit being respectively connected to the voltage input terminal, the voltage output terminal and the enable control terminal of the clamping circuit; The clamping circuits of the second to Nth stages further include a first voltage dividing unit, wherein the first voltage dividing unit has an input end and an output end, wherein the input end of the first voltage dividing unit is connected to the voltage output end of the clamping circuit, and the output end of the first voltage dividing unit is connected to the feedback output end of the clamping circuit; The first voltage divider unit of the i-th clamp circuit is used to control the enable voltage of the enable control terminal of the i-1-th clamp circuit according to the output voltage of the clamp circuit, so as to control the power-on speed of each level of the clamp circuit; wherein i=2, ..., N.

3. The power-on timing control circuit according to claim 2, wherein: Each stage of the clamping circuit further includes: a second voltage dividing unit, the second voltage dividing unit having an input end and an output end, the input end of the second voltage dividing unit being connected to the voltage output end of the clamping circuit, the output end of the second voltage dividing unit being connected to the clamping control end of the clamping main circuit unit, and the second voltage dividing unit being used to control the clamping limit voltage of the clamping circuit according to the voltage output end of the clamping circuit; When the output voltage of the clamping circuit is the clamping voltage, the voltage at the output end of the second voltage dividing unit is the clamping limit threshold voltage of the clamping circuit.

4. The power-on timing control circuit according to claim 3, wherein: The voltage dividing ratio of the first voltage dividing unit of the i-th clamping circuit is the same as that of the second voltage dividing unit of the (i-1)-th clamping circuit, so as to control the power-on speed of each clamping circuit to be consistent.

5. The power-on timing control circuit according to claim 3, wherein: For each stage of the clamping circuit, during the power-on process of the clamping circuit, as the output voltage of the clamping circuit increases, the clamping limit voltage output by the second voltage divider unit of the clamping circuit to the clamping control terminal of the clamping circuit increases.

6. The power-on timing control circuit according to any one of claims 3 to 5, characterized in that: The voltage of the clamp control terminal is the clamp limit voltage of the clamp circuit, and the maximum voltage of the clamp control terminal is the clamp limit threshold voltage of the clamp circuit; For each level of the clamping circuit, during the power-on process of the clamping circuit, when the clamping limit voltage of the clamping circuit is less than the clamping limit threshold voltage, the output voltage of the clamping circuit continues to increase; when the clamping limit voltage of the clamping circuit reaches the clamping limit threshold voltage, the output voltage of the clamping circuit reaches the clamping voltage, and the power-on of this level of the clamping circuit is completed.

7. The power-on timing control circuit according to claim 6, wherein: The clamping limit threshold voltage of each stage of the clamping circuit is the same.

8. The power-on timing control circuit according to any one of claims 2 to 5, wherein: The first voltage divider unit includes a first resistor and a second resistor connected in series, the first end of the first resistor is connected to the voltage output end of the clamping circuit where the first voltage divider unit is located, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is grounded, and the feedback output end of the clamping circuit where the first voltage divider unit is located is connected to the second end of the first resistor.

9. The power-on timing control circuit according to any one of claims 3 to 5, characterized in that: The second voltage dividing unit includes a third resistor and a fourth resistor connected in series, the first end of the third resistor is connected to the voltage output end of the clamping circuit where the second voltage dividing unit is located, the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is grounded, and the clamping control end of the clamping circuit where the second voltage dividing unit is located is connected to the second end of the third resistor.

10. The power-on timing control circuit according to claim 1, wherein: The enable terminal of the N-th stage clamping circuit is grounded through the package component.

11. The power-on timing control circuit according to claim 10, wherein: The package component is a capacitor.

12. A series circuit, characterized in that: include: At least one group of N levels of chips to be powered that are sequentially connected in series, each of the chips to be powered having a main operating voltage input terminal and a ground terminal, and a power-on timing control circuit according to any one of claims 1 to 11.

13. A computing device, characterized in that The invention comprises the power-on timing control circuit according to any one of claims 1 to 11.

14. A computing device, characterized in that The device comprises the series circuit according to claim 12.

Images