Storage control device, processing device, computer system and storage control method

Abstract

Disclosed are a storage control device, a storage control method, a processing device, and a computer system. The storage control device includes: an address detection unit, adapted to detect whether a physical address mapped by a write access request that arrives in sequence jumps; and a logic control unit, adapted to adopt a non-write allocation strategy when a cache memory misses and the physical addresses mapped by multiple write access requests that arrive in sequence do not jump, wherein under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by multiple write access requests that arrive in sequence is less than a preset number, the logic control unit maintains the non-write allocation strategy, and the preset number is greater than 1. The embodiment of the present disclosure can maintain the non-write allocation strategy when the number of consecutive jumps of the physical addresses mapped by the write access requests that arrive in sequence is less than a preset number, thereby avoiding the selection of a write allocation strategy when processing information with a low access probability, and enhancing the robustness and stability of the computer system.

Description

Technical Field

[0001] The present invention relates to the field of processors, and more specifically, to a storage control device, a processing device, a computer system and a storage control method. Background Art

[0002] In order to alleviate the speed difference between the processor and the memory, a cache memory is usually set between the processor and the memory. The access speed of the cache memory is higher than that of the memory. The cache memory is used to cache some data information and / or instruction information such as program data or message data in the memory that may be repeatedly called. The memory here usually refers to the main memory (or simply main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data provided by the processor and / or realizing information exchange between the processor and an external storage device.

[0003] The processor can access the main memory by initiating a write access request, which specifies the physical address of the data to be written and the data to be written. After the processor initiates the write access request, if the data block to be accessed has been cached by the cache memory, that is, the cache memory hits, the processor can directly access the cache memory without accessing the memory, thereby avoiding the long delay caused by accessing the memory; if the data block to be accessed is not cached by the cache memory, that is, the cache memory misses, the processor can use a write allocation strategy or a non-write allocation strategy to process the write access request.

[0004] The Write Allocate strategy means that when a cache memory misses, a read request is first initiated to the next-level memory of the cache memory to call the data block in the memory that matches the write access request into the cache memory; then, the corresponding data block in the cache memory is updated according to the data specified by the write access request.

[0005] The Not Write Allocate or Write Non-allocate strategy means that when a cache memory misses, a write request is directly initiated to the memory to update the corresponding data block in the memory according to the data specified in the write access request without modifying the cache memory.

[0006] Compared with the write allocation strategy, the non-write allocation strategy takes less time and is more suitable for processing data that will not be accessed again in a short period of time; the write allocation strategy can store the data specified by the write access request in the cache memory, so compared with the non-write allocation strategy, the write allocation strategy is more suitable for processing data that may be accessed repeatedly.

[0007] In the traditional scheme, if it is detected that continuous write access requests are mapped to continuous physical addresses (i.e., no jump occurs), a non-write allocation strategy is used to respond to the write access requests; once it is detected that the physical addresses mapped by continuous write access requests jump, the non-write allocation operation is directly exited and switched to the write allocation operation.

[0008] However, for continuous write access requests, some data that may not be accessed repeatedly may not correspond to continuous physical addresses. For example, during operations such as memory copying, the processor may need to jump to other addresses every once in a while to perform operations such as memory transfer; in some processes, data blocks that need to be accessed continuously may have continuous virtual addresses and discontinuous physical addresses. Traditional solutions will use write allocation operations in these cases where physical address jumps occur, which will reduce processor efficiency and performance. Summary of the invention

[0009] In view of this, embodiments of the present invention provide a more robust storage control device, processing device, computer system and storage control method to solve the above problems.

[0010] In order to achieve this object, in a first aspect, the present invention provides a storage control device, comprising: an address detection unit, suitable for detecting whether the physical address mapped by the write access request arriving in sequence has jumped; and a logic control unit, coupled to the address detection unit, suitable for adopting a non-write allocation strategy to process the write access request when the cache memory misses and the physical addresses mapped by the multiple write access request arriving in sequence have not jumped, wherein, under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access request arriving in sequence is less than a preset number, the logic control unit maintains the non-write allocation strategy, and the preset number is greater than 1.

[0011] In some embodiments, the write access request includes: a physical address mapped by a storage instruction; and write data specified by the storage instruction, and under the no-write allocation policy, the write data is written to the memory and is not written to the cache memory.

[0012] In some embodiments, the logical control unit is suitable for: under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to the preset number of times, the logical control unit adopts a write allocation strategy, and under the write allocation strategy, the write data is written to the cache memory.

[0013] In some embodiments, the logic control unit is suitable for: in the initial state, selecting to adopt the write allocation strategy, if the physical address mapped by the write access request that arrives in sequence does not jump, the logic control unit exits the initial state and enters the primary shielding state; in the primary shielding state, adopting a non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by multiple write access request that arrive in sequence is equal to the preset number, then returning to the initial state.

[0014] In some embodiments, the logic control unit is also suitable for: in the primary shielding state, if the physical address mapped by the write access request that arrives in sequence does not jump, then entering the first level buffer state; in the first level buffer state, if the physical address mapped by the write access request that arrives in sequence jumps, then returning to the primary shielding state.

[0015] In some embodiments, the logic control unit is also suitable for: in the first-level buffer state to the K-1-level buffer state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, then transfer to the next-level buffer state; in the second-level buffer state to the K-th-level buffer state, if the physical addresses mapped by the write access requests that arrive in sequence jump, then transfer to the previous-level buffer state, where K is a natural number greater than / equal to 2.

[0016] In some embodiments, the storage control device also includes a register for storing a buffer depth value, and the logic control unit is also suitable for: adopting the write allocation strategy in the initial stage and resetting the buffer depth value to the initial value; if the write access requests that arrive in sequence are mapped to continuous physical addresses in sequence, the buffer depth value is increased according to a first preset gradient; if the physical address mapped by the write access requests that arrive in sequence jumps, the buffer depth value is reduced according to a second preset gradient; when the buffer depth value is less than a set threshold, the write allocation strategy is selected to be adopted, and when the buffer depth value is greater than / equal to the set threshold, the non-write allocation strategy is selected to be adopted.

[0017] In some embodiments, the set threshold is greater than / equal to the sum of the initial value and the first preset gradient.

[0018] In some embodiments, the write access request also includes write policy information, the write policy information indicates one of the write allocation policy and the non-write allocation policy, and the logic control unit is configured to perform: masking the write policy information of the write access request to select the non-write allocation policy; or adopting the write allocation policy according to the write policy information of the write access request.

[0019] In some embodiments, the storage control device further includes: a read buffer unit adapted to initiate a read request to the memory under the write allocation strategy, and store the data block returned by the memory into the cache memory so as to modify the data block according to the write data.

[0020] In some embodiments, the storage control device further includes: a write buffer unit adapted to initiate a write request to the memory under the non-write allocation strategy so as to modify a corresponding data block in the memory according to the write data.

[0021] In some embodiments, the preset number of times is set to a fixed value, or is determined according to the number of times a memory access function is called, and the memory access function is implemented by at least one of the write access requests.

[0022] In a second aspect, an embodiment of the present disclosure provides a processing device, which is a processor, a processor core, or a system on a chip, and includes any one of the storage control devices described above.

[0023] In some embodiments, the processing device further comprises: an instruction execution unit adapted to provide the write access request according to the storage instruction; and a hardware register adapted to provide the write strategy information.

[0024] In some embodiments, the processing device also includes: a memory management unit, coupled to the register, suitable for providing a table entry matching the virtual address specified by the storage instruction, so as to translate the virtual address into a physical address mapped by the storage instruction according to the table entry, and provide the write strategy information to the instruction execution unit.

[0025] In some embodiments, the hardware register is a global register.

[0026] In the third aspect, the embodiment of the present disclosure also provides a storage control method, including: detecting whether the physical address mapped by the write access request arriving in sequence jumps; and if the cache memory does not hit and the physical addresses mapped by the multiple write access request arriving in sequence do not jump, then using a non-write allocation strategy to process the write access request, wherein, under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access request arriving in sequence is less than a preset number, then maintaining the non-write allocation strategy, and the preset number is greater than 1.

[0027] In some embodiments, the write access request includes: a physical address mapped by a storage instruction; and write data specified by the storage instruction, and under the no-write allocation policy, the write data is written to the memory and is not written to the cache memory.

[0028] In some embodiments, the storage control method also includes: under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to the preset number of times, the logical control unit adopts a write allocation strategy, and under the write allocation strategy, the write data is written to the cache memory.

[0029] In some embodiments, the storage control logic includes: in the initial state, selecting to adopt the write allocation strategy, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, the logic control unit exits the initial state and enters the primary shielding state; in the primary shielding state, adopting a non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is equal to the preset number, then returning to the initial state.

[0030] In some embodiments, the storage control logic also includes: in the primary shielding state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, entering the first level buffer state; in the first level buffer state, if the physical addresses mapped by the write access requests that arrive in sequence jump, returning to the primary shielding state.

[0031] In some embodiments, the storage control logic also includes: in the first-level buffer state to the K-1-level buffer state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, then transfer to the next-level buffer state; in the second-level buffer state to the K-th-level buffer state, if the physical addresses mapped by the write access requests that arrive in sequence jump, then transfer to the previous-level buffer state, where K is a natural number greater than / equal to 2.

[0032] In some embodiments, the storage control logic includes: adopting the write allocation strategy in the initial stage and resetting the buffer depth value to the initial value; if the physical address mapped by the write access request that arrives in sequence does not jump, increasing the buffer depth value according to a first preset gradient; if the physical address mapped by the write access request that arrives in sequence jumps, reducing the buffer depth value according to a second preset gradient; when the buffer depth value is less than a set threshold, selecting to adopt the write allocation strategy, and when the buffer depth value is greater than / equal to the set threshold, selecting to adopt the non-write allocation strategy.

[0033] In some embodiments, the set threshold is greater than / equal to the sum of the initial value and the first preset gradient.

[0034] In some embodiments, the write access request also includes write policy information, and the write policy information indicates one of the write allocation policy and the non-write allocation policy. The storage control logic selects to adopt the non-write allocation policy by masking the write policy information of the write access request, or adopts the write allocation policy according to the write policy information of the write access request.

[0035] In some embodiments, the storage control method also includes: obtaining a table entry that matches the virtual address specified by the storage instruction; translating the virtual address specified by the storage instruction into a physical address mapped by the storage instruction based on the identifier and data of the table entry; and providing the write strategy information based on the attribute flag of the table entry.

[0036] In some embodiments, the write strategy information is provided by a global register.

[0037] In some embodiments, the storage control logic further comprises: initiating a read request to the memory under the write allocation strategy, and storing the data block returned by the memory into the cache memory, so as to modify the data block according to the write data.

[0038] In some embodiments, the storage control logic further includes: initiating a read request to the memory under the non-write allocation strategy, so as to modify a corresponding data block in the memory according to the write data.

[0039] In some embodiments, the preset number of times is set to a fixed value, or is determined according to the number of times a memory access function is called, and the memory access function is implemented by at least one of the write access requests.

[0040] In a fourth aspect, an embodiment of the present disclosure further provides a computer system, comprising: any one of the processing devices described above; a cache memory coupled to the storage control device; and a memory coupled to the storage control device.

[0041] In some embodiments, the computer system is implemented as a system on a chip.

[0042] Compared with traditional solutions, the storage control method, storage control device, processing device and computer system provided by the embodiments of the present disclosure can detect whether the physical address mapped by the write access requests that arrive in sequence has multiple jumps. If the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is less than the preset number, the non-write allocation strategy is maintained instead of storing the write data specified by the write access request in the cache memory and / or the memory, so as to avoid, as far as possible, choosing to complete the storage of the write data through the write allocation strategy when processing information with a low access probability, avoid the write data with a low access probability from being stored in the cache memory, improve the performance and efficiency of the computer system, and enhance the robustness and stability of the processor and the computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present invention will become more apparent through the description of the embodiments of the present invention with reference to the following drawings, in which:

[0044] Figure 1 A schematic block diagram showing a computer system in an embodiment of the present invention;

[0045] Figure 2 is a schematic block diagram of a processor in an embodiment of the present invention;

[0046] Figure 3 A partial schematic diagram of a process of executing a storage instruction according to an embodiment of the present invention is shown;

[0047] Figure 4 A schematic diagram of a storage control unit according to an embodiment of the present invention is shown;

[0048] Figures 5a to 5c A schematic diagram of state transition of storage control logic according to an embodiment of the present invention is shown respectively;

[0049] Figure 6 A schematic flow chart of a storage control method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0050] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0051] The following terms are used in this article.

[0052] Computer systems: general purpose embedded systems, desktops, servers, system-on-chips, or other systems with information processing capabilities.

[0053] Memory: A physical structure located within a computer system and used to store information. Depending on the purpose, memory can be divided into main memory (also called internal memory, or simply internal memory / main memory) and auxiliary memory (also called external memory, or simply auxiliary memory / external memory). Main memory is used to store instruction information and / or data information represented by data signals, such as data provided by the processor, and can also be used to implement information exchange between the processor and external memory. The information provided by the external memory needs to be transferred to the main memory before it can be accessed by the processor. Therefore, the memory mentioned in this article generally refers to the main memory, and the storage device mentioned in this article generally refers to the external memory.

[0054] Physical Address (PA): an address on the address bus. The processor or other hardware can provide a physical address to the address bus to access the main memory. The physical address may also be referred to as an actual address, a real address, or an absolute address. The "continuous physical addresses" described herein may correspond to binary codes that are numerically continuous, but the embodiments of the present disclosure are not limited thereto. In some specific designs, "continuous physical addresses" may also correspond to binary codes that differ by only 1 bit.

[0055] Virtual address: An abstract address used by software or programs. The virtual address space can be larger than the physical address space, and the virtual address can be mapped to the corresponding physical address.

[0056] Paging management mechanism: divide the virtual address space into multiple parts, each part is a virtual page, and divide the physical address space into multiple parts, each part is a physical page (page frame). Physical page is also called physical block or physical page frame.

[0057] Page table: used to specify the correspondence between virtual pages and physical pages, usually stored in main memory. The page table includes multiple entries, each of which is used to specify the mapping relationship between virtual pages and physical pages and some management flags, so that the virtual address in the virtual page can be translated into the physical address in the corresponding physical page. Some of the entries contained in the page table can be cached in registers outside the main memory to facilitate being called during the address translation process.

[0058] Write allocation strategy: When the cache memory misses, first initiate a read request to the next level memory of the cache memory to load the data block in the memory that matches the write access request into the cache memory; then, update the corresponding data block in the cache memory according to the data specified by the write access request. The write allocation operation can also be called the Fetch On Write operation.

[0059] Non-write allocation strategy: When the cache memory misses, a write request is directly initiated to the memory to update the corresponding data block in the memory according to the data specified by the write access request without modifying the cache memory.

[0060] Cache hits and misses: When the processor needs to access information in the main memory, it can first search for the required information in the cache memory. If the required information is already stored in the cache memory, it is called a cache hit or hit, and there is no need to search the main memory again; if the required information is not stored in the cache memory, it is called a cache miss, which can also be called a miss, failure or miss.

[0061] Memory access function: a function that needs to access memory, such as a memory copy function or a memory initialization function.

[0062] Memory copy operation: an operation implemented by the memory copy function memcpy in C and C++ languages, used to copy a number of data (each data is, for example, one byte long) from a source main memory address to a target main memory address. Each memory copy operation can be implemented by calling the memory copy function at least once.

[0063] Memory initialization operation: An operation implemented by the memory initialization function memset in C and C++ languages, which is used to set all specified contents of the main memory to specified values. Each memory initialization operation can be implemented by calling the memory initialization function at least once.

[0064] Operations such as memory copying or memory initialization usually require a series of information (instruction information and / or data information) to be written into the main memory. This information is accessed less frequently and has a large amount of information. Therefore, it is not desired that this information be written into the cache memory to save time and avoid the cache memory being occupied by information with a lower access frequency.

[0065] When performing operations such as memory copy or memory initialization that require updating the main memory, the processor will initiate multiple write access requests in sequence to modify the corresponding information in the main memory. Each write access request specifies the physical address to be accessed, the data to be written, and some auxiliary information. The auxiliary information may include write allocation information indicating whether the write allocation policy is valid. The "continuous write access requests" or "write access requests that arrive in sequence" mentioned in this article refer to write access requests that are continuous in the order of initiation, and this series of write access requests will be processed in order.

[0066] However, write access requests that come in sequence are mapped to discontinuous physical addresses in some cases. For example, when performing a memory copy operation, the physical address that the processor needs to access may jump at intervals, that is, the physical address specified by a series of write access requests initiated by the processor will jump; for another example, the program-oriented virtual pages are continuous, but these continuous virtual pages may be mapped to discontinuous physical pages, resulting in continuous virtual addresses being mapped to discontinuous physical addresses.

[0067] In the traditional scheme, if it is detected that continuous write access requests are mapped to continuous physical addresses (i.e., no jump occurs), the non-write allocation strategy is used to respond to the write access request; once it is detected that the physical address mapped by the continuous write access request jumps, the non-write allocation strategy is directly exited and switched to the write allocation strategy. Based on the above analysis, during operations such as memory copy, it is possible that continuous incoming write access requests are mapped to discontinuous physical addresses (i.e., the physical address jumps). Therefore, the traditional scheme will cause unnecessary switching between the write allocation strategy and the non-write allocation strategy multiple times in similar operations such as memory copy, which will reduce the performance and efficiency of the processor.

[0068] Based on this, an embodiment of the present application provides a storage control scheme for dynamically selecting and switching between a write allocation strategy and a non-write allocation strategy according to the physical addresses mapped by the write access requests that arrive in sequence. When the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is less than a preset number, the non-write allocation strategy can still be maintained without storing the write data specified by the write access request in the cache memory and / or the memory, so that the non-write allocation strategy can be restored to the write allocation strategy only when the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to a preset number, so as to optimize the processing process of the write access requests and improve the robustness and efficiency of the processor.

[0069] The following will exemplify the embodiment of the present invention by taking the application scenario of memory copy operation as an example. However, the embodiment of the present invention is not limited thereto. The present application can also be applied to other operations based on the inspiration of the embodiment of the present invention, such as memory initialization operation implemented by functions or instructions such as memory initialization, or other related operations that may be oriented to discontinuous physical addresses and oriented to information with a low access probability.

[0070] System Overview

[0071] Figure 1 A schematic block diagram of a computer system in an embodiment of the present invention is shown. The computer system 10 is an example of a "center" system architecture. The computer system 10 can be constructed based on various types of processors currently on the market and driven by operating systems such as WINDOWSTM operating system versions, UNIX operating system, and Linux operating system. In addition, the computer system 10 can be implemented in hardware and / or software such as a PC, a desktop, a notebook, a server, and a mobile communication device.

[0072] like Figure 1 As shown, the computer system 10 according to the embodiment of the present invention may include one or more processors 12 and a memory 14 .

[0073] The memory 14 in the computer system 10 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0074] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 10 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0075] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and a storage control unit 123. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory. The write access request specifies the write data and the corresponding physical address that need to be written into the memory; the memory management unit 122 is used to translate the virtual address specified by these instructions into the physical address mapped by the virtual address, and the physical address specified by the write access request can be consistent with the physical address specified by the corresponding instruction; the storage control unit 123 is used to store the write data into the storage location pointed to by the physical address mapped by the write access request through a write allocation operation or a non-write allocation operation.

[0076] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0077] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 10.

[0078] In addition, the computer system 10 may also include input / output devices such as a storage device 16, a display device 13, an audio device 14, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0079] The computer system 10 also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication that complies with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication that complies with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module that uses other protocols, such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0080] Of course, the structure of different computer systems may vary according to the motherboard, operating system and instruction set architecture. For example, many computer systems are currently provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated into the processor 12 or independent of the processor 12.

[0081] As described below, the storage control unit 23 of the computer system 10 of the embodiment of the present disclosure detects whether the physical address mapped by the write access requests that arrive in sequence has multiple jumps, and selects one of the write allocation operation and the non-write allocation operation to store the write data specified by the write access request into the cache memory 18 and / or the memory 14, so as to avoid choosing to complete the storage of write data through the write allocation operation when processing information with a low access probability, avoid the write data with a low access probability from being stored in the cache memory, and improve the performance and efficiency of the computer system.

[0082] processor

[0083] Figure 2 is a schematic block diagram of the processor 12 in an embodiment of the present invention.

[0084] In some embodiments, each processor 12 may include one or more processor cores 120 for processing instructions, and the processing and execution of instructions may be controlled by a user (e.g., through an application) and / or a system platform. In some embodiments, each processor core 120 may be used to process a specific instruction set. In some embodiments, the instruction set may support complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW)-based computing. Different processor cores 120 may each process different or the same instruction sets. In some embodiments, the processor core 120 may also include other processing modules, such as a digital signal processor (DSP), etc. As an example, Figure 2 , processor cores 1 to m are shown, where m is a non-zero natural number.

[0085] In some embodiments, Figure 1 The cache memory 18 shown may be fully or partially integrated into the processor 12. And according to different architectures, the cache memory 18 may be a single or multiple levels of internal high-speed cache memory located inside and / or outside each processor core 101 (e.g., Figure 2 The three-level high-speed cache memory L1 to L3 shown, Figure 2 The processor 12 may include an instruction cache and a data cache. In some embodiments, the various components in the processor 12 may share at least a portion of the cache memory, such as Figure 2As shown, the processor cores 1 to m, for example, share a third-level high-speed cache memory L3. The processor 12 may also include an external high-speed cache (not shown), and other high-speed cache structures may also serve as the external high-speed cache of the processor 12.

[0086] In some embodiments, Figure 2 As shown, the processor 12 may include a register file 126 (Register File), and the register file 126 may include multiple registers for storing different types of data and / or instructions, and these registers may be of different types. For example, the register file 126 may include: integer registers, floating point registers, status registers, instruction registers, and pointer registers. The registers in the register file 126 may be implemented by selecting general registers, or may adopt a specific design according to the actual needs of the processor 12.

[0087] The processor 12 may include a memory management unit (MMU) 122 for implementing the translation of virtual addresses to physical addresses. The memory management unit 122 caches some entries in the page table, and the memory management unit 122 may also obtain uncached entries from the memory. One or more memory management units 122 may be set in each processor core 120, and the memory management units 120 in different processor cores 120 may also be synchronized with the memory management units 120 in other processors or processor cores, so that each processor or processor core can share a unified virtual storage system.

[0088] The processor 12 is used to execute the instruction sequence (i.e., program). The process of the processor 12 executing each instruction includes: fetching the instruction from the memory storing the instruction, decoding the fetched instruction, executing the decoded instruction, saving the instruction execution result, etc., and the cycle continues until all the instructions in the instruction sequence are executed or a shutdown instruction is encountered.

[0089] To implement the above process, the processor 12 may include an instruction fetch unit 124 , an instruction decoding unit 125 , an instruction issuing unit (not shown), an instruction execution unit 121 , an instruction retirement unit (not shown), and the like.

[0090] The instruction fetch unit 124 acts as the startup engine of the processor 12 and is used to transfer instructions from the memory 14 to the instruction register (which may be Figure 2 A register in the register file 26 shown is used to store instructions) and receives the next instruction fetch address or calculates the next instruction fetch address according to an instruction fetch algorithm. The instruction fetch algorithm includes, for example, increasing or decreasing the address according to the instruction length.

[0091] After fetching the instruction, the processor 12 enters the instruction decoding stage, and the instruction decoding unit 125 decodes the fetched instruction according to the predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. The operand acquisition information, for example, points to an immediate number, a register, or other software / hardware that can provide a source operand.

[0092] The instruction issuing unit is usually present in a high-performance processor 12, located between the instruction decoding unit 125 and the instruction execution unit, and is used for scheduling and controlling instructions to efficiently allocate each instruction to different instruction execution units 121, so that the parallel operation of multiple instructions becomes possible. After the instruction is fetched, decoded and scheduled to the corresponding instruction execution unit 121, the corresponding instruction execution unit 121 starts to execute the instruction, that is, to execute the operation indicated by the instruction and realize the corresponding function.

[0093] The instruction retirement unit (or instruction write back unit) is mainly responsible for writing the execution results generated by the instruction execution unit 121 back to the corresponding storage location (for example, the register inside the processor 12), so that subsequent instructions can quickly obtain the corresponding execution results from the storage location.

[0094] For different types of instructions, different instruction execution units 121 may be provided in the processor 12 accordingly. The instruction execution unit 121 may be an operation unit (for example, including an arithmetic logic unit, a vector operation unit, etc., for performing operations according to operands and outputting operation results), a memory execution unit (for example, for accessing a memory according to an instruction to read data in the memory or write specified data to the memory, etc.), a coprocessor, etc. In the processor 12, each instruction execution unit 121 may run in parallel and output corresponding execution results.

[0095] When executing a certain type of instruction (eg, memory access instruction), the instruction execution unit 121 needs to access the memory 14 to obtain information stored in the memory 14 or provide data that needs to be written into the memory 14 .

[0096] It should be noted that the instruction execution unit 121 for executing memory access instructions may also be referred to as a memory execution unit, which may be, for example, a load store unit (LSU) and / or other units for memory access.

[0097] After the memory access instruction is fetched by the instruction fetch unit 124, the instruction decoding unit 125 can decode the memory access instruction so that the source operand of the memory access instruction can be obtained. The decoded memory access instruction is provided to the corresponding instruction execution unit 121, and the instruction execution unit 121 can perform corresponding operations on the source operand of the memory access instruction (for example, the arithmetic logic unit performs operations on the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests according to the address information, such as address translation requests, write access requests, etc.

[0098] The source operand of the memory access instruction usually includes an address operand, and the instruction execution unit 121 operates on the address operand to obtain the virtual address or physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 121 is enabled, the corresponding instruction execution unit 121 initiates an address translation request according to the virtual address corresponding to the memory access instruction, and the address translation request includes the virtual address corresponding to the address operand of the memory access instruction; the memory management unit 122 responds to the address translation request, and converts the virtual address in the address translation request into a physical address according to the table entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and / or the memory 14 according to the translated physical address.

[0099] Depending on the function, the memory access instruction may include a load instruction and a store instruction. The execution process of the load instruction usually does not require modification of the information in the memory 14 or the cache memory 18. The instruction execution unit 121 only needs to read the data stored in the memory 14, the cache memory 18 or the external storage device according to the address operand of the load instruction.

[0100] Different from the load instruction, the source operand of the store instruction includes not only the address operand but also the data information, and the execution process of the store instruction usually requires modification of the memory 14 and / or the cache memory 18. The data information of the store instruction can point to the write data, and the source of the write data can be the execution result of the operation instruction, the load instruction and other instructions, or the data provided by the register or other storage unit in the processor 12, or the immediate value.

[0101] The memory copy operation is usually used to copy a number of bytes stored in a source storage area of ​​the memory 14 to a target storage area of ​​the memory 14. The function format of the memory copy function memcpy is, for example:

[0102] memcpy(destin,source,n)

[0103] Among them, destin points to the target storage area (a storage area of ​​memory 14) where the copied content needs to be stored, source points to the source storage area (a storage area of ​​memory 14) where the copied content is located, and n indicates the number of bytes contained in the copied content.

[0104] The memory copy function can be implemented by a series of memory access instructions. The processor 12 can obtain the n bytes of copy content stored in the source storage area and execute the storage instruction stream to write the copy content into the target storage area. The copy content can be divided into multiple write data according to bytes, words or other units, and each storage instruction is used to write a corresponding write data into a corresponding storage location in the target storage area.

[0105] Figure 3 A partial flow chart of executing a storage instruction according to an embodiment of the present invention is shown. Figure 2 and Figure 3 An exemplary description is given of the execution process of the storage instruction.

[0106] exist Figure 3 In operation 310 shown, the instruction execution unit 121 initiates a write access request. The write access request includes the write data specified by the storage instruction and the physical address mapped by the storage instruction.

[0107] In operation 310, the instruction execution unit 121 may first initiate an address translation request based on the address operand of the storage instruction, and the address translation request includes a virtual address corresponding to the address operand of the storage instruction; then, the memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address that can be used to access the memory, i.e., the physical address mapped by the storage instruction, according to the corresponding table entry in the page table.

[0108] The write access request may also specify some auxiliary information, which may include write allocation information for indicating whether the write allocation policy is effective. The write allocation information may be derived from the global configuration information provided by the register stack 126, or may be provided by the attribute flag bit of the table entry in the page table that matches the virtual address of the storage instruction, or may be derived from other configuration information.

[0109] exist Figure 3 In operation 320 shown, in response to the write access request, the storage control unit 123 compares the physical address mapped by the storage instruction with the addresses of each cache block in the cache memory to determine whether the cache memory hits.

[0110] The method for determining whether the cache memory 18 hits may include: determining whether each cache block address of the cache memory 18 matches the physical address mapped by the write access request. If the cache block address of a cache block matches the physical page number of the physical address mapped by the write access request, then it may be further determined whether there is a corresponding cache entry (each cache block includes multiple cache entries that can be indexed by several bits of the physical address) in the matching cache block according to the physical address mapped by the write access request. If so, the cache memory 18 hits. If there is no cache block and cache entry mapped to the write access request in the cache memory 18, it means that the cache memory 18 does not hit the write access request.

[0111] If the cache memory hits, operation 330 is performed: the instruction execution unit 121 updates the corresponding cache entry according to the write data specified by the write access request.

[0112] If there is a cache miss, operation 340 described below is performed.

[0113] exist Figure 3 In operation 340 shown, the storage control unit 123 selects to adopt a write allocation strategy or a non-write allocation strategy to process a write access request, so as to update a corresponding cache block and / or memory block according to the write data specified by the storage instruction.

[0114] It should be noted that the write allocation strategy itself does not affect the function of the computer system, but only affects the performance of the computer system and the processor, such as reducing the speed at which the computer system and the processor execute certain storage instructions.

[0115] In some embodiments, the storage control unit 123 may be implemented by software and / or hardware. For example, the storage control unit 123 implemented by hardware may be integrated into the processor 12 or the cache memory 18, or integrated into the same system on chip with the processor 12 and / or the cache memory 18, or coupled with the processor and the cache memory in other forms.

[0116] Storage Management Unit

[0117] Figure 4A schematic diagram of a storage control unit 123 according to an embodiment of the present invention is shown. The storage control unit may be a storage management device implemented by hardware and / or software. The storage control device may be integrated in the processor 12 or the cache memory 18, or may be integrated in the same system on chip with the processor 12 and / or the cache memory 18, or may be a packaged chip independent of the processor 12 and the cache memory 18. Since the storage management unit may be used to select one of the write allocation strategy and the split write allocation strategy, it may also be referred to as an allocation mode regulator (Allocate Mode Regulator, AMR).

[0118] The storage control unit 123 is used to receive write access requests, determine whether the physical address mapped by the write access requests that arrive in sequence jumps, and select one of the write allocation strategy and the non-write allocation strategy based on the judgment result information and the storage control logic, so that when the cache memory misses, the selected write allocation strategy or non-write allocation strategy is used to process the corresponding write access request to update the memory 14 and / or the cache memory 18.

[0119] The storage control unit 123 may include an address detection unit 33, a logic control unit 34, a search unit 35, a write buffer unit 32, and a read buffer unit 31. However, the embodiments of the present application are not limited thereto.

[0120] During the execution of the memory copy operation, the storage control unit 123 receives a series of write access requests corresponding to the storage instruction stream. The search unit 35 is used to compare the physical address mapped by the write access request with each cache block address in the cache memory 18 to determine whether the cache memory hits.

[0121] If the cache memory 18 hits, the write data specified by the write access request is directly written into the corresponding cache block. The cache block can be marked as a dirty block. In some subsequent steps, the cache block marked as a dirty block can be unified with the corresponding memory block in the memory 14, and then the mark indicating the dirty block is eliminated.

[0122] If the cache memory misses, the logic control unit 34 selects a write allocation strategy or a non-write allocation strategy according to the determination result information provided by the storage control logic and the address detection unit 33 .

[0123] Under the write allocation strategy, the logic control unit 34 controls the read buffer unit 31 to initiate a read request, so that the memory 14 responds to the read request to return the required data block to the read buffer unit 31, and the read buffer unit 31 then writes the data block into the corresponding cache block address of the cache memory 18. Subsequently, the search unit 35 can search each cache block in the cache memory again. Since there is a cache block matching the physical address mapped by the write access request in the cache memory at this time, the cache memory hits, and the specified write data can be directly stored in the corresponding cache block to modify the data cached in the cache memory.

[0124] Under the non-write allocation strategy, the logic control unit 34 controls the write buffer unit 32 to initiate a write request to the memory 14. The write buffer unit 32 caches the write data specified by the write access request and updates the corresponding memory block in the memory 14 according to the cached write data, without writing the corresponding memory block in the memory 14 into the cache memory or modifying the data stored in the cache memory.

[0125] The address detection unit 33 is used to detect the physical address mapped by the write access request to determine whether the physical addresses mapped by the write access request that arrives successively have jumped, and provide judgment result information. For example, when the physical addresses mapped by two consecutive write access requests correspond to discontinuous physical pages, the physical addresses mapped by the two write access requests are discontinuous. At this time, the judgment result information indicates that the physical addresses mapped by the write access request that arrives successively have jumped. The judgment result information can be stored in a corresponding register, for example, including: whether the physical address mapped by the current write access request is continuous with the physical address mapped by the previous write access request; the number of consecutive jumps of the physical addresses mapped by the write access request that arrives successively; whether the physical addresses mapped by the write access request that arrives successively have not jumped for multiple consecutive times. However, the judgment result information of the embodiment of the present disclosure is not limited to this.

[0126] In some embodiments, when the judgment result information indicates that the physical addresses mapped by the multiple write access requests that arrive in sequence have not jumped, the logic control unit 34 may choose to use a non-write allocation strategy to process the current write access request; under the non-write allocation strategy, if the judgment result information indicates that the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to the preset number y, the logic control unit 34 reverts from the non-write allocation strategy to the write allocation strategy. The preset number y may be set to a fixed value greater than 1, or may be determined based on the number of times the memory copy function described above is called in the current memory copy operation, or may be set or dynamically adjusted based on other factors.

[0127] In some embodiments, the address detection unit 33 can cache the physical address mapped by the previously received write access request (for example, using a corresponding register for caching), and compare the cached physical address with the physical address mapped by the currently received write access request bit by bit to determine whether the physical addresses of the two successively received write access request mappings jump.

[0128] In some embodiments, the write access request may include the above-mentioned write allocation information. When the write allocation information indicates a write allocation strategy, the logic control unit 34 may shield the write strategy information of the write access request when selecting a non-write allocation strategy; if the logic control unit 34 selects a write allocation strategy, the write allocation information is not shielded, so that the write access request is processed using the write allocation strategy. The write allocation information is, for example, a flag bit stored in a corresponding register.

[0129] The storage control logic may be implemented by hardware and / or software, for example, by components such as a counter, some registers in a register file, and a logic circuit.

[0130] Next, a storage control method implemented by the storage control logic will be described exemplarily based on the above analysis.

[0131] Example 1

[0132] According to one embodiment, the storage control logic is implemented by a state machine, and the state machine may include an initial state and a primary shielding state, but the present application is not limited thereto.

[0133] Figure 5a A schematic diagram showing state transition of storage control logic according to an embodiment of the present invention is shown.

[0134] Initial state: the storage control logic adopts a write allocation strategy. In this state, if the judgment result information indicates that the physical addresses mapped by the i write access requests that arrive in sequence have not jumped, the logic control logic exits the initial state and enters the primary shielding state; otherwise, the storage control logic remains in the initial state. The i write access requests here point to i consecutive physical addresses, which correspond to several or dozens of bytes of data, for example. Where i is a natural number greater than / equal to 1.

[0135] Primary shielding state: The storage control logic adopts a non-write allocation strategy, for example, by shielding the write allocation information in the write access request. In this state, if the physical addresses mapped by the multiple write access requests that arrive in sequence jump Y1 times in a row, the initial state is returned; if the number of consecutive jumps of the physical addresses mapped by the write access requests that arrive in sequence is less than Y1 or no jump occurs, the storage control logic will remain in the primary shielding state to process the current write access request using a non-write allocation strategy. In this embodiment, Y1 is equal to the preset number y.

[0136] It can be seen that in this embodiment, the condition for transferring from the initial state to the primary shielding state is that "the physical addresses mapped by the i write access requests that arrive in sequence do not jump", and the condition for transferring from the primary shielding state to the initial state is that "the physical addresses mapped by the write access requests that arrive in sequence jump Y1 times in a row".

[0137] It can be seen from the above examples that this embodiment avoids unnecessary switching between write allocation strategy and non-write allocation due to jumps in the physical address mapped by write access requests in operations such as memory copy for processing data with low access frequency, thereby improving the performance and efficiency of the processor.

[0138] After the memory copy operation is completed, the storage control logic will restore the write allocation policy based on subsequent write access requests.

[0139] Example 2

[0140] According to one embodiment, the storage control logic is implemented by a state machine, and the state machine may include an initial state, a primary shielding state, and a first-level buffer state, but the present application is not limited thereto.

[0141] Figure 5b A schematic diagram showing state transition of storage control logic according to an embodiment of the present invention is shown.

[0142] Initial state: the storage control logic adopts a write allocation strategy. In this state, if the judgment result information indicates that the physical addresses mapped by the i write access requests that arrive in sequence have not jumped, the logic control logic exits the initial state and enters the primary shielding state; otherwise, the storage control logic remains in the initial state. Here, i is the same as the definition in Example 1 and will not be repeated here.

[0143] Primary shielding state: The storage control logic adopts a non-write allocation strategy, for example, by shielding the write allocation information in the write access request. In this state, if the judgment result information indicates that the physical address mapped by the write access requests that arrive in sequence jumps Y2 times in a row, then the primary shielding state is exited and the initial state is returned; if the consecutive write access requests are mapped to consecutive physical addresses, then the primary shielding state is exited and the first-level buffer state is entered; in other cases, no state transfer occurs. Among them, Y2 can be set to a fixed value greater than 1, or it can be determined according to the number of times the memory copy function described above is called in the current memory copy operation, and it can also be set or dynamically adjusted according to other factors.

[0144] Level 1 buffer state: The storage control logic adopts a non-write allocation strategy. In this state, if the judgment result information indicates that multiple consecutive write access requests are mapped to consecutive physical addresses in sequence, the storage control logic maintains the level 1 buffer state; if the judgment result information indicates that the physical addresses mapped by the sequentially arriving write access requests jump, the level 1 buffer state is exited and the primary shielding state is returned.

[0145] In this embodiment, the storage control logic of the initial state is mainly used to process some operations other than the memory copy operation, so that the write data specified by the write access request initiated by these operations can be written into the cache memory through the write allocation strategy to facilitate access; the primary shielding state and the first-level buffer state are both states that adopt the non-write allocation strategy, but the shielding strength of the primary shielding state and the first-level buffer state is different. The shielding strength described here means: in order to return from the current state to the initial state, the physical addresses mapped by the write access requests that come in sequence need to jump continuously for a number of times, that is, the preset number of times y.

[0146] The condition for the primary shielding state to transfer to the initial state is "the physical address mapped by the write access requests that arrive in sequence jumps Y2 times in a row", so the shielding strength of the primary shielding state is equal to Y2, that is: in the primary shielding state, the preset number y=Y2.

[0147] Returning from the first-level buffer state to the initial state requires going through the primary shielding state, and after the first-level buffer state returns to the primary shielding state, once the write access request is mapped to multiple consecutive physical addresses again, the storage control logic may transfer from the primary shielding state to the first-level buffer state again. Therefore, the shielding strength of the first-level buffer state is greater than Y2 (that is, in the first-level buffer state, the preset number of times y>Y2), thereby further avoiding unnecessary switching between the write allocation strategy and the non-write allocation strategy caused by a single jump or a few jumps of the physical address.

[0148] Based on this embodiment, preferably, the condition for transferring from the initial state to the primary shielding state is "the physical addresses mapped by the i write access requests that arrive in sequence have not jumped", the condition for transferring from the primary shielding state to the first-level buffer state is "the physical addresses mapped by the multiple write access requests that arrive in sequence have not jumped", the condition for transferring from the first-level buffer state to the primary shielding state is "the physical addresses mapped by the currently received write access request and the previous write access request that arrive are not continuous", and the condition for transferring from the primary shielding state to the initial state is "the physical addresses mapped by the multiple write access requests that arrive in sequence have jumped Y2 times in a row". However, this embodiment is not limited to this, for example: the condition for transferring from the primary shielding state to the first-level buffer state can also be "the currently received write access request and the previous write access request that arrive are mapped to continuous physical addresses".

[0149] It can be seen from the above examples that this embodiment avoids unnecessary switching between write allocation strategy and non-write allocation due to jumps in the physical address mapped by write access requests in operations such as memory copy for processing data with low access frequency, thereby improving the performance and efficiency of the processor.

[0150] After the memory copy operation is completed, the storage control logic will gradually restore the write allocation policy based on subsequent write access requests.

[0151] Example 3

[0152] According to one embodiment, the storage control logic is implemented by a state machine, which may include an initial state, a primary shielding state, and 1st to Kth level buffer states, but the present application is not limited thereto. K is a natural number greater than or equal to 2. Different states in the state machine may correspond to different state numbers, and the state numbers are stored in registers, for example.

[0153] Figure 5c A schematic diagram showing state transition of storage control logic according to an embodiment of the present invention is shown.

[0154] Initial state: the storage control logic adopts a write allocation strategy. In this state, if the judgment result information indicates that the physical addresses mapped by the i write access requests that arrive in sequence have not jumped, the logic control logic exits the initial state and enters the primary shielding state; otherwise, the storage control logic remains in the initial state. Here, i is the same as the definition in Example 1 and will not be repeated here.

[0155] Primary shielding state: The storage control logic adopts a non-write allocation strategy, for example, by shielding the write allocation information in the write access request. In this state, if the judgment result information indicates that the physical address mapped by the write access requests that arrive in sequence jumps Y3 times in a row, then the primary shielding state is exited and the initial state is returned; if the consecutive write access requests are mapped to consecutive physical addresses, then the primary shielding state is exited and the first-level buffer state is entered; in other cases, no state transfer occurs. Among them, Y3 can be set to a fixed value greater than 1, or it can be determined according to the number of times the memory copy function described above is called in the current memory copy operation, and it can also be set or dynamically adjusted according to other factors.

[0156] 1st to Kth level buffer states: the storage control logic adopts a non-write allocation strategy.

[0157] In the first-level buffer state, if the judgment result information indicates that the physical address mapped by the write access request arriving in sequence has jumped, the primary shielding state is returned; in the first to K-1th level buffer states, if the judgment result information indicates that the physical address mapped by the multiple write access request arriving in sequence has not jumped, the storage control logic is transferred to the next-level buffer state; in the second-level buffer state to the Kth-level buffer state, if the judgment result information indicates that the physical address mapped by the write access request arriving in sequence has jumped, it is transferred to the previous-level buffer state.

[0158] Similar to the above-mentioned second embodiment, in this embodiment, the primary shielding state and the 1st to Kth level buffer states are all states that adopt the non-write allocation strategy, but the shielding strength of the primary shielding state and the 1st to Kth level buffer states increases successively, and the value of K can be determined according to the preset number of times y.

[0159] For example, returning to the initial state from the first-level buffer state requires going through the primary shielding state. Only when the physical address mapped by the write access requests that arrive in sequence jumps continuously for a number of times reaching Y3+1, the storage control logic can restore the write allocation strategy. For the second-level buffer state, returning to the initial state from the second-level buffer state requires going through the primary shielding state and the first-level buffer state. After the second-level buffer state returns to the first-level buffer state, if the write access request is mapped to multiple consecutive physical addresses again, the storage control logic may transfer from the first-level buffer state to the second-level buffer state again.

[0160] Therefore, the shielding strength of each level of buffer state increases successively (that is, the preset number y corresponding to each level of buffer state increases), and it can avoid unnecessary switching between the write allocation strategy and the non-write allocation strategy caused by a single jump or a few jumps of the physical address, and can also avoid unnecessary switching between the write allocation strategy and the non-write allocation strategy caused by discontinuous single jumps or a few jumps of the physical address.

[0161] Based on this embodiment, preferably, the condition for transferring from the initial state to the primary shielding state is "the physical addresses mapped by the i write access requests that arrive in sequence have not jumped", the condition for transferring from the primary shielding state to the first-level buffer state and from each level of buffer state to the next-level buffer state is "the physical addresses mapped by the multiple write access requests that arrive in sequence have not jumped", the condition for returning from the first-level buffer state to the primary shielding state is "the physical addresses mapped by the two write access requests that arrive in sequence have jumped", the condition for returning from each level of buffer state to the previous level of buffer state is "the physical addresses mapped by the two write access requests that arrive in sequence have jumped", and the condition for transferring from the primary shielding state to the initial state is "the physical addresses mapped by the multiple write access requests that arrive in sequence have jumped Y3 times in a row". However, this embodiment is not limited to this, for example: the condition for transferring from the primary shielding state to the first-level buffer state / the condition for transferring from each level of buffer state to the next-level buffer state can also be "the currently received write access request and the previous write access request are mapped to consecutive physical addresses".

[0162] After the memory copy operation is completed, the storage control logic will restore the write allocation policy based on subsequent write access requests.

[0163] Similar to the above-mentioned Embodiments 1 and 2, this embodiment reduces unnecessary switching between write allocation strategy and non-write allocation in operations such as memory copy for processing data with low access frequency, thereby improving the performance and efficiency of the processor.

[0164] Example 4

[0165] According to another embodiment, the storage control unit 123 may further include a register for storing a buffer depth value, and the storage control logic may implement a corresponding storage control method according to the buffer value.

[0166] Figure 6 A schematic flow chart of a storage control method according to an embodiment of the present invention is shown.

[0167] like Figure 6 In operation 601 , a write allocation strategy is adopted in the initial stage, and the buffer depth value is an initial value.

[0168] In operation 602, if the judgment result information indicates that the physical addresses mapped by at least two write access requests that arrive in sequence do not jump, the buffer depth value is increased according to a first preset gradient, for example, the buffer depth value is added by 1.

[0169] In operation 603, if the judgment result information indicates that the physical addresses mapped by at least two write access requests that arrive in sequence are not continuous, the buffer depth value is reduced according to a second preset gradient, for example, the buffer depth value is subtracted by 1. The second preset gradient is, for example, equal to the first preset gradient.

[0170] In operation 604 , it is determined whether the buffer depth value is less than a set threshold value. If so, operation 605 is executed to adopt a write allocation strategy. If not, operation 606 is executed to adopt a non-write allocation strategy.

[0171] In some embodiments, the threshold is set to be greater than / equal to the sum of the initial value and the first preset gradient (or the second preset), so that when the physical address mapped by the write access requests that arrive in sequence has a single jump or fewer jumps, the non-write allocation strategy will not be restored to the write allocation strategy.

[0172] This embodiment can also avoid unnecessary switching between write allocation strategy and non-write allocation due to jumps in the physical address mapped by write access requests in operations such as memory copy for processing data with low access frequency, thereby improving the performance and efficiency of the processor.

[0173] So far, a storage control method, a storage control device, and related processing devices and computer systems are described by way of example, which select one of a write allocation strategy and a non-write allocation strategy according to whether a physical address mapped by write access requests that arrive in sequence jumps.

[0174] In the traditional scheme, if it is detected that continuous write access requests are mapped to continuous physical addresses (i.e., no jump occurs), a non-write allocation strategy is used to respond to the write access requests; once it is detected that the physical addresses mapped by continuous write access requests jump, the non-write allocation operation is directly exited and switched to the write allocation operation.

[0175] However, for continuous write access requests, some data that may not be accessed repeatedly does not necessarily correspond to continuous physical addresses. For example, during operations such as memory copying, the processor may need to jump to other addresses every once in a while to perform operations such as memory transfer; in some processes, data that needs to be accessed continuously may have continuous virtual addresses, but these continuous virtual addresses may be mapped to discontinuous physical addresses. Traditional solutions will use write allocation operations in these cases where physical address jumps occur, which will reduce processor efficiency and performance.

[0176] Compared with traditional solutions, the storage control method, storage control device, processing device and computer system provided by the embodiments of the present disclosure can detect whether the physical address mapped by the write access requests that arrive in sequence has multiple jumps. If the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is less than the preset number, the non-write allocation strategy is maintained instead of storing the write data specified by the write access request in the cache memory and / or the memory, so as to avoid, as far as possible, choosing to complete the storage of the write data through the write allocation strategy when processing information with a low access probability, avoid the write data with a low access probability from being stored in the cache memory, improve the performance and efficiency of the computer system, and enhance the robustness and stability of the processor and the computer system.

[0177] The present application also discloses a computer-readable storage medium including computer-executable instructions stored thereon, and when the computer-executable instructions are executed by a processor, the processor is caused to perform the methods of the embodiments described herein.

[0178] In addition, the present application also discloses a system, which includes a device for implementing the methods of the embodiments described herein.

[0179] The present application also discloses a processing device, which includes the above-mentioned processor, processor core, or a system on a chip integrating the above-mentioned processor or processor core.

[0180] It should be understood that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, there are many variations of the embodiments of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0181] For example, in some embodiments, the storage control unit may include an enable register, and the storage control unit may be turned on and off by configuring at least one value in the enable register.

[0182] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the device and system implementation

[0183] The method described in the example is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0184] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0185] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0186] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. A storage control device, characterized in that: include: An address detection unit, adapted to detect whether the physical addresses mapped by the multiple write access requests that arrive in sequence have jumped; as well as A logic control unit is coupled to the address detection unit and is adapted to select a write allocation strategy and a non-write allocation strategy to process a plurality of write access requests that arrive in sequence, wherein the logic control unit is adapted to: Initially selecting a write allocation strategy when the cache memory misses and the number of consecutive jumps of the physical addresses mapped by the plurality of write access requests that arrive in sequence is greater than or equal to a preset number; When the cache memory misses and the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, switch to the non-write allocation strategy to process the multiple write access requests that arrive in sequence, wherein, under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is less than a preset number, the logic control unit maintains the non-write allocation strategy, and the preset number is greater than 1.

2. The storage control device according to claim 1, characterized in that: The write access request includes: storing the physical address of the instruction mapping; and The storage instruction specifies the write data, Under the no-write allocation policy, the write data is written to the memory and is not written to the cache memory.

3. The storage control device according to claim 2, characterized in that: The logic control unit is suitable for: Under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to the preset number of times, the logic control unit adopts the write allocation strategy, Under the write allocate policy, the write data is written to a cache memory.

4. The storage control device according to claim 3, characterized in that: The logic control unit is suitable for: In the initial state, the write allocation strategy is selected, and if the physical address mapped by the write access request that arrives in sequence does not jump, the logic control unit exits the initial state and enters the primary shielding state; In the primary shielding state, a non-write allocation strategy is adopted, and if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is equal to the preset number, the initial state is returned.

5. The storage control device according to claim 4, characterized in that: The logic control unit is also suitable for: In the primary shielding state, if the physical address mapped by the write access request that arrives in sequence does not jump, then the first level buffering state is entered; In the first-level buffer state, if the physical address mapped by the write access request that arrives in sequence jumps, the primary shielding state is returned.

6. The storage control device according to claim 5, characterized in that: The logic control unit is also suitable for: In the first level buffer state to the K-1th level buffer state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, then transfer to the next level buffer state; In the second-level buffer state to the K-th-level buffer state, if the physical address mapped by the write access request that arrives in sequence jumps, it is transferred to the buffer state of the previous level. K is a natural number greater than or equal to 2.

7. The storage control device according to claim 3, characterized in that: Also comprising a register for storing a buffer depth value, the logic control unit is further adapted to: In the initial stage, the write allocation strategy is adopted, and the buffer depth value is reset to an initial value; If the write access requests that arrive in sequence are mapped to consecutive physical addresses in sequence, increasing the buffer depth value according to a first preset gradient; If the physical address mapped by the write access request that arrives in sequence jumps, reducing the buffer depth value according to a second preset gradient; When the buffer depth value is less than a set threshold, the write allocation strategy is selected; when the buffer depth value is greater than / equal to the set threshold, the non-write allocation strategy is selected.

8. The storage control device according to claim 7, characterized in that: The set threshold is greater than / equal to the sum of the initial value and the first preset gradient.

9. The storage control device according to claim 3, characterized in that: The write access request further includes write policy information, wherein the write policy information indicates one of the write allocation policy and the non-write allocation policy, The logic control unit is configured to perform: shielding the write policy information of the write access request to select the non-write allocation policy; or The write allocation strategy is adopted according to the write strategy information of the write access request.

10. The storage control device according to claim 3, characterized in that: Also includes: The read buffer unit is adapted to initiate a read request to the memory under the write allocation strategy, and store the data block returned by the memory into the cache memory, so as to modify the data block according to the write data.

11. The storage control device according to claim 3, characterized in that: Also includes: A write buffer unit is adapted to initiate a write request to the memory under the non-write allocation strategy so as to modify a corresponding data block in the memory according to the write data.

12. The storage control device according to claim 1, characterized in that: The preset number of times is set to a fixed value, or is determined according to the number of times the memory access function is called, The memory access function is implemented by at least one of the write access requests.

13. A processing device, characterized in that: The processing device is a processor, a processor core or a system on a chip, and includes the storage control device according to any one of claims 1 to 12.

14. A processing device, characterized in that: The processing device is a processor, a processor core or a system on a chip, and includes: The storage control device according to claim 9; an instruction execution unit, adapted to provide the write access request according to the storage instruction; A hardware register is adapted to provide the write strategy information.

15. The processing device according to claim 14, characterized in that Also includes: A memory management unit is coupled to the hardware register and is suitable for providing a table entry matching the virtual address specified by the storage instruction so as to translate the virtual address into a physical address mapped by the storage instruction according to the table entry and provide the write strategy information to the instruction execution unit.

16. The processing device according to claim 14, characterized in that The hardware register is a global register.

17. A storage control method, characterized in that: include: Detect whether the physical addresses mapped by multiple write access requests that arrive in sequence jump; as well as Selecting a write allocation strategy and a non-write allocation strategy to process the multiple write access requests that arrive in sequence; wherein the method further includes: Initially selecting a write allocation strategy when the cache memory misses and the number of consecutive jumps of the physical addresses mapped by the plurality of write access requests that arrive in sequence is greater than or equal to a preset number; When the cache memory misses and the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, switch to the non-write allocation strategy to process the multiple write access requests that arrive in sequence, wherein, under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is less than a preset number, maintain the non-write allocation strategy, and the preset number is greater than 1.

18. The storage control method according to claim 17, characterized in that: The write access request includes: storing the physical address of the instruction mapping; and The storage instruction specifies the write data, Under the no-write allocation policy, the write data is written to the memory and is not written to the cache memory.

19. The storage control method according to claim 18, characterized in that: The storage control logic includes: Under the non-write allocation strategy, if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is greater than / equal to the preset number, the write allocation strategy is adopted. Under the write allocate policy, the write data is written to the cache memory.

20. The storage control method according to claim 19, characterized in that: The storage control logic includes: In the initial state, the write allocation strategy is selected, and if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, the initial state is exited and the primary shielding state is entered; In the primary shielding state, a non-write allocation strategy is adopted, and if the number of consecutive jumps of the physical addresses mapped by the multiple write access requests that arrive in sequence is equal to the preset number, the initial state is returned.

21. The storage control method according to claim 20, characterized in that: The storage control logic also includes: In the primary shielding state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, the first level buffering state is entered; In the first-level buffer state, if the physical address mapped by the write access request that arrives in sequence jumps, the primary shielding state is returned.

22. The storage control method according to claim 21, characterized in that: The storage control logic also includes: In the first level buffer state to the K-1th level buffer state, if the physical addresses mapped by the multiple write access requests that arrive in sequence do not jump, then transfer to the next level buffer state; In the second-level buffer state to the K-th-level buffer state, if the physical address mapped by the write access request that arrives in sequence jumps, it is transferred to the buffer state of the previous level. K is a natural number greater than or equal to 2.

23. The storage control method according to claim 19, characterized in that: The storage control logic includes: In the initial stage, the write allocation strategy is adopted and the buffer depth value is reset to the initial value; If the physical addresses mapped by the write access requests that arrive in sequence do not jump, increasing the buffer depth value according to a first preset gradient; If the physical address mapped by the write access request that arrives in sequence jumps, reducing the buffer depth value according to a second preset gradient; When the buffer depth value is less than a set threshold, the write allocation strategy is selected; when the buffer depth value is greater than / equal to the set threshold, the non-write allocation strategy is selected.

24. The storage control method according to claim 23, characterized in that: The set threshold is greater than / equal to the sum of the initial value and the first preset gradient.

25. The storage control method according to claim 19, characterized in that: The write access request further includes write policy information, wherein the write policy information indicates one of the write allocation policy and the non-write allocation policy, The storage control logic selects to adopt the non-write allocation strategy by shielding the write strategy information of the write access request, or The write allocation policy is adopted according to the write policy information of the write access request.

26. The storage control method according to claim 25, characterized in that: Also includes: Obtaining a table entry matching the virtual address specified by the storage instruction; translating the virtual address specified by the storage instruction into a physical address mapped by the storage instruction according to the identifier and data of the table entry; and The write strategy information is provided according to the attribute flag of the entry.

27. The storage control method according to claim 25, characterized in that: The write strategy information is provided by a global register.

28. The storage control method according to claim 19, characterized in that: The storage control logic further includes: A read request is initiated to the memory under the write allocation strategy, and a data block returned by the memory is stored in the cache memory so as to modify the data block according to the write data.

29. The storage control method according to claim 19, characterized in that: The storage control logic further includes: A read request is initiated to the memory under the non-write allocation strategy so as to modify a corresponding data block in the memory according to the write data.

30. The storage control method according to claim 17, characterized in that: The preset number of times is set to a fixed value, or is determined according to the number of times the memory access function is called, The memory access function is implemented by at least one of the write access requests.

31. A computer system, characterized in that: include: A processing device as claimed in any one of claims 13 to 16; a cache memory coupled to the storage control device; as well as A memory is coupled to the storage control device.

32. The computer system according to claim 31, characterized in that The computer system is implemented by a system on a chip.

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