High electron mobility transistor (HEMT) devices and methods

Abstract

Embodiments of this disclosure relate to high electron mobility transistor (HEMT) devices and methods. Several embodiments relate to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and a first heterostructure and a second heterostructure on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first and second heterostructures.

Description

Technical Field

[0001] This disclosure generally relates to high electron mobility transistor devices and methods, and more specifically to high electron mobility transistors having a vertically oriented heterostructure. Background Technology

[0002] A high electron mobility transistor (HEMT) is a type of field-effect transistor (FET) in which electron current flows freely within conductive channels in a semiconductor. Such essentially unobstructed conductive channels are formed in a two-dimensional electron gas (2DEG) layer adjacent to a heterojunction (i.e., the boundary between two different semiconductors).

[0003] In conventional HEMTs, heterostructures that facilitate the formation of 2DEG layers are formed as stacks of planar semiconductor materials, for example, having a first semiconductor layer on a substrate and a second semiconductor layer on the first semiconductor layer. Conventional HEMTs (especially conventional gallium nitride (GaN) HEMTs) are formed on different silicon substrates as other circuit devices (such as CMOS circuit devices), such as CMOS driver or logic circuit devices, electrically coupled to the HEMT. That is, conventional HEMTs generally cannot be monolithically integrated with CMOS circuit devices on the same semiconductor substrate or die. Thus, CMOS circuit devices are typically formed on a separator substrate or die serving as the HEMT, and the two separator substrates or dies are electrically connected to each other using wires, solder bumps, etc. Summary of the Invention

[0004] This disclosure generally relates to high-mobility electronic transistors (HEMTs), electronic devices including HEMTs, and methods for forming HEMTs, wherein a heterostructure is formed in a vertical orientation along the sidewalls of a trench formed in a semiconductor material, such as epitaxial silicon. The sidewalls of the trench may be sidewalls of epitaxial silicon and may be formed to have... <111> The crystal orientation facilitates the formation of HEMTs in the silicon substrate. This allows HEMT devices to be formed on the same die (e.g., a silicon die) that includes other circuitry (e.g., CMOS transistors). This provides a significant advantage over existing approaches because HEMT devices and driver circuitry, logic circuitry, or other circuitry that can be formed using CMOS processes can be integrated into the same silicon die, thus providing space savings compared to devices where two separate dies are used to form both the HEMT device and the CMOS device. Furthermore, embodiments of this disclosure offer improvements in speed and reduction of stray inductance because wiring or solder bumps between separate dies can be avoided.

[0005] In one or more embodiments, this disclosure provides a high electron mobility transistor (HEMT) including a substrate having a first surface. A first heterostructure and a second heterostructure are disposed on the substrate, and the first heterostructure and the second heterostructure face each other. Each of the first heterostructure and the second heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer. A doped semiconductor layer is disposed between the first heterostructure and the second heterostructure, and a source contact is disposed on the first heterostructure and the second heterostructure.

[0006] In one or more embodiments, this disclosure provides an electronic device including a silicon substrate having a first surface; a high electron mobility transistor (HEMT) on the silicon substrate; and a driving circuit on the silicon substrate and electrically coupled to the HEMT. The HEMT includes a first heterostructure and a second heterostructure, a doped semiconductor layer between the first heterostructure and the second heterostructure, source contacts on the first heterostructure and the second heterostructure, and a gate contact on the doped semiconductor layer. Each of the first heterostructure and the second heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer.

[0007] In one or more embodiments, this disclosure provides a method for forming a high electron mobility transistor (HEMT), comprising: forming a first heterostructure and a second heterostructure on a first surface of a substrate, each of the first heterostructure and the second heterostructure including a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer; forming a doped semiconductor layer between the first heterostructure and the second heterostructure; forming a source contact on the first heterostructure and the second heterostructure; forming a gate contact on the doped semiconductor layer; and forming a drain contact on a second surface of a silicon substrate opposite to the first surface. Attached Figure Description

[0008] In the accompanying drawings, unless the context otherwise indicates, the same reference numerals identify similar elements or actions. The dimensions and relative positions of the elements in the drawings need not be drawn to scale. For example, the shapes and angles of various elements need not be drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the readability of the drawings. Furthermore, the particular shapes of the elements drawn are not necessarily intended to convey any information about the actual shape of the particular element, and are chosen solely for ease of identification in the drawings.

[0009] Figure 1A This is a top view illustrating a two-dimensional electron gas (2DEG) confined device according to one or more embodiments of the present disclosure, which may be a high electron mobility transistor (HEMT) device.

[0010] Figure 1B It is based on one or more embodiments of this disclosure. Figure 1A The diagram shows a cross-sectional view of the HEMT device.

[0011] Figures 2 to 20B This is a view illustrating a method of manufacturing a HEMT device according to one or more embodiments of the present disclosure.

[0012] Figure 21 This is a schematic block diagram illustrating an electronic device according to one or more embodiments of the present disclosure. Detailed Implementation

[0013] In the following description, certain specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures associated with high electron mobility transistors (HEMTs) have not been shown and described in detail in order to avoid unnecessarily obscuring the description of the various embodiments provided herein.

[0014] Unless the context otherwise requires, throughout the specification and the following claims, the word "comprise" and its variations (such as "comprises" and "comprising") shall be interpreted in an open and inclusive sense, that is, "including but not limited to". Furthermore, unless the context explicitly indicates otherwise, the terms "first", "second", and similar sequence indicators shall be interpreted as interchangeable.

[0015] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in an embodiment" or "in one embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments of this disclosure, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0016] As used in this specification and the appended claims, unless otherwise expressly indicated, the singular forms “a,” “an,” and “the” include a plural of objects. It should also be noted that, unless otherwise expressly indicated, the term “or” is generally used in its broadest sense, that is, meaning “and / or.”

[0017] The headings and abstracts of this disclosure provided herein are for convenience only and do not define the scope or meaning of the embodiments.

[0018] Throughout this specification, references to conventional deposition techniques for depositing metal, semiconductor, dielectric, or similar materials include processes such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, etc. Specific embodiments are described herein with reference to such similar examples. However, this disclosure and references to certain deposition techniques should not be limited to those described. Furthermore, references to conventional techniques for forming various layers by deposition may include: in-situ growth of films or layers.

[0019] Throughout this specification, references are made to conventional photolithography techniques known in the semiconductor manufacturing industry for patterning various thin films, including a spin-coating-exposure-development sequence, typically followed by an etching process. Alternatively or additionally, photoresist can also be used to pattern hard masks, which in turn can be used to pattern substrate films.

[0020] Throughout this specification, references are made to conventional etching techniques known in the semiconductor manufacturing industry for the selective removal of metals, photoresists, dielectric materials, semiconductor layers, or similar materials, including wet chemical etching, reactive ion (plasma) etching (RIE), cleaning, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical planarization (CMP), etc. Specific embodiments are described herein with reference to examples of such techniques. However, this disclosure and reference to certain etching techniques should not be limited to those described. In some instances, two such techniques may be used interchangeably.

[0021] Figure 1A This is a perspective view illustrating a high electron mobility transistor (HEMT) device 10 according to one or more embodiments of the present invention, and Figure 1B This is a cross-sectional view of the HEMT device 10 taken along line 1B-1B.

[0022] HEMT device 10 includes a substrate 12 and a heterostructure 14 on the substrate 12. For example... Figure 1AAs shown, multiple heterostructures can be provided on the substrate 12, and corresponding pairs of heterostructures 14 can face each other, and each heterostructure 14 can have a length extending in a direction transverse to the surface of the substrate 12. For example, the substrate 12 can have a first direction (e.g., as in...) Figure 1A The heterostructure 14 may have a surface (e.g., an upper surface) extending in a horizontal direction (as shown in the figure), and each heterostructure in the heterostructure 14 may have a length or long axis extending in a second direction (e.g., a vertical direction as shown) transverse to the first direction. In some embodiments, the heterostructure 14 may be, for example, a vertical structure that extends in a vertical direction relative to the horizontal upper surface of the substrate 12.

[0023] In some embodiments, substrate 12 may be a silicon (Si) substrate, but the embodiments of this disclosure are not limited thereto, and in many embodiments, substrate 12 may be any suitable substrate.

[0024] Multiple heterostructures 14 may each comprise a stack of materials in which a uniform two-dimensional electron gas (2DEG) layer 16 can be formed. Figure 1A A two-layer heterostructure 14 comprising two different semiconductor materials (e.g., a first layer 14a and a second layer 14b) is shown and described herein; however, embodiments of this disclosure are not limited thereto. In various embodiments, the HEMT device 10 may include a heterostructure having more than two layers, including, for example, a structure in which each of the first layer 14a and the second layer 14b may comprise one or more semiconductors or other materials.

[0025] HEMT device 10 includes one or more source contacts 18, drain contacts 20, and gate contacts 22. Figure 1A The HEMT device 10 shown includes two HEMTs, namely, a first HEMT 60 and a second HEMT 62. Each of the first HEMT 60 and the second HEMT 62 is substantially identical in structure and operation, and the first HEMT 60 and the second HEMT 62 can share the same gate contact 22 (as shown). Therefore, the operation of the first HEMT 60 and the second HEMT 62 can be controlled by applying a suitable voltage to the shared gate contact 22.

[0026] The gate contact 22 modulates the electron mobility within the conductive channel of the HEMT device 10, for example by forming a 2DEG layer 16 and applying an appropriate voltage at the gate contact 22 to modulate the electron mobility within the heterostructure 14.

[0027] A 2DEG layer 16 and energy levels within the heterostructure 14 are formed at the heterojunction between the first layer 14a and the second layer 14b. In some embodiments, the semiconductor material in the second layer 14b of the heterostructure 14 is a doped semiconductor material with a wide bandgap. In some embodiments, the second layer 14b may be an aluminum gallium nitride (AlGaN) layer, or a layer comprising aluminum gallium nitride (AlGaN), which in some embodiments may be negatively doped (e.g., doped with an n-type dopant).

[0028] The semiconductor material in the first layer 14a of the heterostructure 14 can be an undoped semiconductor material or an intrinsic semiconductor material with a narrow band gap. In some embodiments, the first layer 14a can be an intrinsic semiconductor layer or include an intrinsic semiconductor layer (e.g., undoped gallium nitride (GaN)).

[0029] The term "band gap" refers to the difference between the energy of conduction band electrons (free electrons) and the energy of valence band electrons (atomic-bound electrons), i.e., the amount of energy required to release valence electrons from atoms in a semiconductor crystal. Because the band gaps between the first layer 14a and the second layer 14b of the heterostructure 14 are different, the conduction band energies of the materials are inconsistent. Therefore, when two such semiconductor material layers are placed in contact with each other, their energy levels are discontinuous at the boundary or heterojunction. This discontinuity creates a potential well at the heterojunction, which traps unbound donor electrons from the n-doped material (e.g., the second layer 14b) at the surface of the undoped material (e.g., the first layer 14a), resulting in a peak electron concentration at the heterojunction. This trapped donor electron is sometimes referred to as a two-dimensional electron gas (2DEG). Therefore, the location of the 2DEG layer 16 defines the conductive path of the HEMT device 10.

[0030] Because electrons in the conductive channels of the 2DEG layer 16 interact almost entirely with the lattice, their mobility is significantly higher than that in conventional transistor devices. This high electron mobility of the HEMT devices 10 (e.g., the first HEMT 60 and the second HEMT 62) allows large electron currents to flow within the conductive channels (i.e., the 2DEG layer 16), thereby increasing device speed. A voltage applied to the gate contact 22 alters the conductivity within the conductive channels, thus modulating the electron current between the source contact 18 and the drain contact 20. This ability to support such high electron currents makes HEMT devices suitable for high-power, high-frequency applications, such as chips used in RF communication devices (e.g., cellular phones, satellite TV receivers, radar equipment, etc.).

[0031] HEMT device 10 may further include an epitaxial semiconductor layer 24, which can be considered part of substrate 12. For example, the substrate of HEMT device 10 may include substrate 12 and epitaxial semiconductor layer 24. Epitaxial semiconductor layer 24 may be formed of the same semiconductor material as substrate 12. For example, in some embodiments, epitaxial semiconductor layer 24 may be an epitaxial silicon layer formed on substrate 12, and substrate 12 may be a silicon substrate. In some embodiments, substrate 12 may be a doped (e.g., n++ doped) substrate. In some embodiments, substrate 12 may have a different... <111> A silicon substrate with a oriented crystal orientation. For example, in some embodiments, substrate 12 may be a silicon substrate with a oriented crystal orientation. <100> A silicon substrate with crystal orientation. In some embodiments, the substrate 12 may be a silicon substrate with crystal orientation. <110> Crystal-oriented silicon substrate.

[0032] A feed layer 26 is formed between the side surface of the epitaxial semiconductor layer 24 and the first layer 14a of the heterostructure 14. In some embodiments, the feed layer 26 facilitates the formation of the first layer 14a of the heterostructure 14. In some embodiments, the feed layer 26 is an aluminum nitride (AlN) layer.

[0033] like Figure 1A As shown, an oxide layer 34 may be provided on the surface of the epitaxial semiconductor layer 24 (e.g., on its upper surface), and a feed layer 26 may be provided on the side surface of the oxide layer 34. In some embodiments, the oxide layer may be used as a mask during the process of forming the HEMT device 10, as described in more detail below.

[0034] A first dielectric layer 28 may be provided on the oxide layer 34. In some embodiments, such as Figure 1A As shown, a portion of the first dielectric layer 28 may also be provided between the two heterostructures 14. As shown, a portion of the first dielectric layer 28 may be provided on the substrate 12.

[0035] like Figure 1A As shown, a doped semiconductor layer 30 is formed on the first dielectric layer 28 and extends between the two heterostructures 14. The doped semiconductor layer 30 can be, for example, a positively doped semiconductor layer with a p-type dopant. In some embodiments, the doped semiconductor layer 30 is a GaN layer doped with a p-type dopant such as magnesium (Mg). The doped semiconductor layer 30 contacts the gate contact 22 and can be used as the gate region of the HEMT device 10, for example, as the gate region of the first HEMT 60 and the second HEMT 62. That is, the voltage applied to the gate contact 22 can be transmitted to the doped semiconductor layer 30, which causes the formation of a 2DEG layer 16 at the heterojunction between the first layer 14a and the second layer 14b, thereby facilitating current conduction between the source contact 18 and the drain contact 20.

[0036] A second dielectric layer 32 may be provided on the first dielectric layer 28. In some embodiments, such as Figure 1A As shown, a portion of the second dielectric layer 32 may also be provided between the two heterostructures 14. For example, the second dielectric layer 32 may be provided on the doped semiconductor layer 30 between the two heterostructures 14.

[0037] The source contact 18, gate contact 22, and drain contact 20 can be formed of any suitable conductive material, and in several embodiments, the suitable conductive material can be a metallic material. In some embodiments, the source contact 18 and gate contact 22 can be formed of the same metallic material, which can be patterned to form a separator between the source contact 18 and the gate contact 22. Figure 1A As shown, the drain contact 20 may be formed on the back side of the substrate 12. In some embodiments, the drain contact 20 may cover the entire area on the back side of the substrate 12 corresponding to the area on which the HEMT device 10 is formed. In some embodiments, the drain contact 20 is formed of the same metal material as the metal material used to form the source contact 18 and the gate contact 22.

[0038] As discussed previously, HEMT device 10 in Figure 1A The diagram shows two HEMTs 60 and 62 sharing the same gate contact 22. Furthermore, in some embodiments, the two HEMTs 60 and 62 may share the same drain contact 20. However, each of the HEMTs 60 and 62 has its own source contact 18. Moreover, each of the HEMTs 60 and 62 has its own heterostructure 14, or its own pair of heterostructures 14. For example, Figure 1A The depicted heterostructure pair 14 is included as a portion of the first HEMT 60. Similarly, the second HEMT 62 may include a heterostructure pair relative to the first HEMT 60 and... Figure 1A The heterostructure pairs shown are identical or substantially identical. The heterostructures of the first HEMT 60 and the second HEMT 62, and the structures or layers between the heterostructure pairs of the first HEMT 60 and the second HEMT 62, can be electrically isolated from each other. Thus, for each of the first HEMT 60 and the second HEMT 62, a suitable voltage applied to the shared gate contact 22 can form a 2DEG layer 16; however, the signals transmitted from the source contacts 18 of the first HEMT 60 and the second HEMT 62 can be different from each other, and in some embodiments, can be electrically isolated from each other.

[0039] Figure 1B It is intercepted along line 1B-1B. Figure 1AThe diagram shows a cross-sectional view of the HEMT device 10. Figure 1B As shown, one or more HEMTs (e.g., HEMT 60) of HEMT device 10 may include a plurality of heterostructures 14 pairs formed in separation trenches 50 and connected to the same source contact 18. More specifically, a plurality of trenches 50 may be formed. The structure within each trench of trench 50 may be similar to that previously described herein. Figure 1A The structure shown and described is the same. For example, the structure within each trench in trench 50 may include a feed layer 26 of heterostructure 14, a first layer 14a and a second layer 14b, and portions of the following: a first dielectric layer 28, a doped semiconductor layer 30 and a second dielectric layer 32 between the heterostructure 14 pairs in each trench 50.

[0040] During operation of the HEMT device 10, a voltage can be applied to the gate contact 22, which modulates the electron mobility within the conductive channels of the HEMT device 10 by forming a 2DEG layer 16. For example, by applying a suitable voltage to the gate contact 22, the 2DEG layer 16 can be formed in each of the heterostructures in each pair of heterostructures 14 in each trench of the HEMT device 10. Thus, a signal or current can be transferred from the source contact 18 to the drain contact 20 through the 2DEG layer 16 of the heterostructure 14.

[0041] Figures 2 to 20B This is a cross-sectional view illustrating a method for manufacturing a HEMT device according to one or more embodiments. The illustrated method can, for example, be used to manufacture a HEMT device relative to... Figure 1A and Figure 1B The HEMT device 10 shown and described is not limited thereto.

[0042] like Figure 2 As shown, an epitaxial semiconductor layer 24 is formed on substrate 12. Substrate 12 can be any semiconductor substrate and can include, for example, silicon (Si), silicon carbide (SiC), aluminum oxide (Al2O3), or any other suitable substrate. In some embodiments, substrate 12 is doped (e.g., n++ doped) and has <100> A silicon (Si) substrate with crystal orientation. However, embodiments of this disclosure are not limited thereto, and in various embodiments, the substrate 12 may have different... <111> Any crystal orientation (e.g., crystal orientation) <110> orientation).

[0043] The epitaxial semiconductor layer 24 can be formed of the same semiconductor material as the substrate 12. For example, in some embodiments, the epitaxial semiconductor layer 24 can be an epitaxial silicon layer formed on the silicon substrate 12. In some embodiments, for example, the substrate at the upper surface of the epitaxial semiconductor layer 24 can have a different material than the substrate. <111> Crystal orientation (e.g., <100> Crystal orientation or <110> (Crystal orientation). For example, an epitaxial semiconductor layer 24 can be formed on a substrate 12 by epitaxial growth of the epitaxial semiconductor layer 24.

[0044] like Figure 3 As shown, an oxide layer 34 is formed on the surface (e.g., the upper surface) of the epitaxial semiconductor layer 24. The oxide layer 34 can be formed using any suitable technique, and in some embodiments, it can be formed by surface oxidation. The oxide layer 34 can be an oxide of the semiconductor material of the epitaxial semiconductor layer 24. For example, the epitaxial semiconductor layer can be a silicon layer, and the oxide layer 34 can be silicon oxide.

[0045] like Figure 4 As shown, a mask 154 is formed on the oxide layer 34. The mask 154 can be any mask suitable for patterning the oxide layer 34, and in some embodiments, the mask 154 can be a photomask or photoresist, for example, used for patterning the oxide layer 34 in a photolithography process. In some embodiments, the mask 154 can be any photoresist, such as a negative photoresist or a positive photoresist. In some embodiments, the mask 154 can be formed directly on the upper surface of the oxide layer 34. In some embodiments, the mask 154 can be an etch-resistant hard mask and is used to selectively remove multiple portions of the oxide layer 34.

[0046] like Figure 5 As shown, multiple portions of the oxide layer 34 are removed, leaving as... Figure 5 Multiple regions of the oxide layer 34 are shown. Multiple portions of the oxide layer 34 can be selectively removed, for example, by any suitable etching process. For example, Figure 4 The structure shown can withstand etchants (e.g., etching gases, plasmas, liquids, etc.), and the mask 154 is etchant resistant. Thus, the etchant selectively removes only portions of the oxide layer 34 that are exposed or uncovered by the mask 154.

[0047] like Figure 6 As shown, mask 154 can be removed, leaving a patterned oxide layer 34 on the surface of epitaxial semiconductor layer 24. Mask 154 can be removed by any suitable process, including, for example, by using photoresist stripping materials and processes such as organic stripping, inorganic stripping, dry stripping, etc.

[0048] like Figure 7As shown, trench 50 is formed by selectively removing multiple portions of epitaxial semiconductor layer 24. In some embodiments, oxide layer 34 serves as a mask during the removal of multiple portions of epitaxial semiconductor layer 24. Any suitable technique for removing multiple portions of epitaxial semiconductor layer 24 can be used to form trench 50. In some embodiments, trench 50 is formed by an etching process, wherein oxide layer 34 is used as a mask against an etchant, and an etchant selectively removes the unmasked portions of epitaxial semiconductor layer 24, thereby forming trench 50. The etchant can be any suitable etchant, including, for example, etching gases, plasmas, liquids, etc.

[0049] In some embodiments, trench 50 is formed to expose the side surface of the epitaxial semiconductor layer 24, and the side surface of the epitaxial semiconductor layer 24 has <111> Crystal orientation. The exposed sidewalls of the epitaxial semiconductor layer 24 can be formed to have crystal orientation by any suitable technique. <111> Crystal orientation (e.g., silicon) <111> Orientation). In some embodiments, the exposed sidewalls of the epitaxial semiconductor layer 24 can be formed to have an orientation by tilting the substrate (e.g., substrate 12 and epitaxial semiconductor layer 24) during the formation of trench 50. <111> Crystal orientation such that, during etching, trenches 50 are formed, wherein the exposed vertical sidewalls of the epitaxial semiconductor layer 24 have <111> Crystal orientation. In some embodiments, the vertical sidewalls of the trench 50 (i.e., exposed sidewalls of the epitaxial semiconductor layer 24) are formed at a non-zero angle relative to a direction orthogonal to the plane of the wafer on which the epitaxial semiconductor layer 24 is formed (e.g., a plane on the substrate 12). In some embodiments, this angle can be approximately 19.4°, which can result in exposure at the sidewalls of the epitaxial semiconductor layer 24. <111> Crystal orientation.

[0050] By along with <111> The sidewalls of the crystal-oriented epitaxial semiconductor layer 24 form a HEMT structure (e.g., feed layer 26 and heterostructure 14), relative to the assumption that it is along a path with a different orientation. <111> (such as, <100> Crystal orientation or <110> (Crystal Orientation) The formation of a HEMT structure on the surface of a crystal-oriented semiconductor minimizes or reduces the mechanical stress generated, and this minimized or reduced mechanical stress can be due to the difference in thermal coefficients between materials with different crystal orientations or mesh spacings. Therefore, having <111> The exposure of the sidewalls of the crystal-oriented epitaxial semiconductor layer 24 facilitates the formation of a HEMT device 10 with advantageously improved quality, including performance improvements that can be promoted by reducing or minimizing mechanical stress.

[0051] like Figure 8As shown, a feed layer 26 is formed on the oxide layer 34 and in the trench 50. The feed layer 26 can be formed by any suitable process, and in some embodiments, it is formed by depositing one or more materials constituting the feed layer 26. In some embodiments, the feed layer 26 can be formed by a conformal deposition process, wherein the feed layer 26 is deposited on all exposed surfaces. In some embodiments, the feed layer 26 is formed on the upper surface of the oxide layer 34 in the trench 50, the side surfaces of the oxide layer 34, and the exposed side surfaces of the epitaxial semiconductor layer 24, as well as on the upper surface of the substrate 12 exposed in the trench 50.

[0052] The feed layer 26 can be formed of any suitable material that promotes the growth or formation of one or more layers of the heterostructure 14. In some embodiments, the feed layer 26 is an aluminum nitride (AlN) layer.

[0053] like Figure 9 As shown, multiple portions of the feed layer 26 are selectively removed such that the feed layer 26 is formed or retained substantially only on or on the sidewalls of the epitaxial semiconductor layer 24, and in some embodiments, the feed layer 26 is formed or retained on the sidewalls of the oxide layer 34 in the trench 50. Portions of the feed layer 26 can be selectively removed from the upper surface of the oxide layer 34 and the surface of the substrate 12 forming the lower boundary of the trench 50.

[0054] A portion of the feed layer 26 can be removed by any suitable technique or process, including, for example, by etching to selectively remove multiple portions of the feed layer 26. In some embodiments, multiple portions of the feed layer 26 are removed by dry etching.

[0055] like Figure 10 As shown, a first layer 14a of the heterogeneous structure is formed on the side surface of the feed layer 26 in the trench 50. The first layer 14a may include a corresponding portion on the side surface of each of a plurality of portions of the feed layer 26 in the trench 50. For example, pairs of feed layers 26 may be positioned opposite each other in each trench of the trench 50, and corresponding pairs of first layers 14a may be formed on each feed layer of the feed layer 26 in each trench 50, and the first layers 14a may be opposite each other in the trench 50.

[0056] In some embodiments, the first layer 14a may be formed by growth of the first layer 14a (e.g., by epitaxial growth). In some embodiments, the first layer 14a may be an undoped semiconductor material or an intrinsic semiconductor material having a narrow bandgap. In some embodiments, the first layer 14a may be or include an intrinsic semiconductor layer, such as undoped gallium nitride (GaN).

[0057] In several embodiments, for example, such as Figure 10As shown, the first layer 14a may have an upper surface that is recessed relative to the upper surface of the adjacent oxide layer 34 or the upper surface of the adjacent feed layer 26. However, the various embodiments of this disclosure are not limited thereto, and in various embodiments, the upper surface of the first layer 14a may be substantially coplanar with or extend above the upper surface of the oxide layer 34 or the feed layer 26.

[0058] like Figure 11 As shown, a second layer 14b of the heterogeneous structure is formed on the side surface of the first layer 14a in the trench 50. The second layer 14b may include a corresponding portion on the side surface of each of a plurality of portions of the first layer 14a in the trench 50. For example, pairs of second layers 14b may be formed on each of the first layers in each pair of first layers 14a in each trench, and the second layers 14b may be opposite each other in the trench 50.

[0059] In some embodiments, the second layer 14b can be formed by growing the second layer 14b (e.g., by epitaxial growth). In some embodiments, the second layer 14b can be a doped semiconductor material having a wide bandgap. In some embodiments, the second layer 14b can be or includes an aluminum gallium nitride (AlGaN) layer, which in some embodiments can be negatively doped (e.g., doped with an n-type dopant).

[0060] In various embodiments, the second layer 14b may have an upper surface recessed relative to the upper surface of the adjacent oxide layer 34 or the upper surface of the adjacent feed layer 26 (e.g., as shown in the figure). Figure 10 (As shown). However, embodiments of this disclosure are not limited thereto, and in various embodiments, the upper surface of the second layer 14b may be substantially coplanar with or extend above the upper surface of the oxide layer 34 or the feed layer 26. As shown, the upper surface of the second layer 14b is substantially coplanar with the upper surface of the first layer 14a.

[0061] like Figure 12 As shown, a first dielectric layer 28 is formed in the trench 50 and may cover the oxide layer 34, the feed layer 26, and the upper surfaces of the first layer 14a and the second layer 14b of the heterostructure 14. The first dielectric layer 28 may fill or substantially fill the space in the trench 50 between the respective pairs of second layers 14b of the heterostructure 14. As shown, the first dielectric layer 28 may contact the side surfaces of the second layers 14b.

[0062] The first dielectric layer 28 can be formed by any suitable technique or process, including, for example, by depositing the first dielectric layer 28. The first dielectric layer 28 can be formed of any dielectric material, and in some embodiments, the first dielectric layer 28 can be formed of silicon oxide (SiO2).

[0063] like Figure 13As shown, a mask 156 is formed on the first dielectric layer 28. The mask 156 can be any mask suitable for patterning the first dielectric layer 28, and in some embodiments, the mask 156 can be a photomask or photoresist, for example, used for patterning the first dielectric layer 28 in a photolithography process. In some embodiments, the mask 156 can be any photoresist, such as a negative photoresist or a positive photoresist. In some embodiments, the mask 156 can be formed directly on the upper surface of the first dielectric layer 28, wherein openings in the mask are aligned with or cover regions of the first dielectric layer 28 that fill trench 50. In some embodiments, the mask 156 can be an etchant-resistant hard mask, where an etchant is used to selectively remove multiple portions of the first dielectric layer 28.

[0064] like Figure 14A and Figure 14B As shown, multiple portions of the first dielectric layer 28 are removed, leaving regions of the first dielectric layer 28 as illustrated. More specifically, multiple portions of the first dielectric layer 28 are removed from multiple regions of the first dielectric layer 28 filling the trench 50. By removing multiple portions of the first dielectric layer 28 from the trench 50, the height of multiple regions of the first dielectric layer 28 within the trench 50 is reduced, such that the upper surface of the first dielectric layer 28 in the trench 50 is lower than the level of the upper surface of the heterostructure 14.

[0065] For example, multiple portions of the first dielectric layer 28 can be selectively removed using any suitable etching process. For instance, multiple portions of the first dielectric layer 28 exposed by openings in the mask 156 can be selectively removed using an etchant (e.g., etch gas, plasma, liquid, etc.), and the mask 156 is etchant-resistant. Thus, the etchant selectively removes only multiple portions of the first dielectric layer 28 exposed or uncovered by the mask 156. Etching chemistry, etching time, or other etching parameters can be selected to control the height of the remaining portions of the first dielectric layer 28 within the trench 50 to achieve a desired level.

[0066] like Figure 15A and Figure 15B As shown, the mask 156 can be removed after etching of the first dielectric layer 28 is completed, leaving a patterned first dielectric layer 28 on the substrate 12 within the trench 50, and multiple portions of the first dielectric layer 28 on the upper surfaces of the oxide layer 34, the feed layer 26, and the heterostructure 14. The mask 156 can be removed by any suitable process, including, for example, using photoresist stripping materials and processes such as organic stripping, inorganic stripping, dry stripping, etc.

[0067] like Figure 16A and Figure 16BAs shown, a doped semiconductor layer 30 is formed on the surface of the first dielectric layer 28 in the trench 50 and extends between the two heterostructures 14 in each trench 50. The doped semiconductor layer 30 can be formed to fill the trench 50 on the first dielectric layer 28, and the doped semiconductor layer 30 can also cover the upper surface of the first dielectric layer 28 outside the trench 50. The doped semiconductor layer 30 can be formed by any suitable technique or process, including, for example, by depositing the doped semiconductor layer 30.

[0068] The doped semiconductor layer 30 may be, for example, a positively doped semiconductor layer having a p-type dopant. In some embodiments, the doped semiconductor layer 30 is a GaN layer doped with a p-type dopant such as magnesium (Mg). Doping of the doped semiconductor layer 30 may be performed (e.g., by implanting an ionized dopant) after the deposition of the semiconductor material, or in some embodiments, the doped semiconductor layer 30 may be formed, for example, by depositing a semiconductor material including a dopant.

[0069] like Figure 17A and Figure 17B As shown, for example, the doped semiconductor layer 30 is patterned by selectively removing multiple portions of the doped semiconductor layer 30. Multiple portions of the doped semiconductor layer 30 can be selectively removed by any suitable process, including, for example, selectively removing multiple portions of the doped semiconductor layer 30 by any suitable etching process. For example, a mask etching process can be performed, wherein a mask (not shown) is formed on the surface of the doped semiconductor layer 30, and an etchant can be applied to etch areas of the doped semiconductor layer 30 exposed through openings in the mask.

[0070] By removing multiple portions of the doped semiconductor layer 30, a recess 150 is formed in the region of the trench 50. After patterning the doped semiconductor layer 30, the doped semiconductor layer 30 may have an upper surface within the trench 50, the level of which is lower than the level of the upper surfaces of the heterostructure 14 and the feed layer 26 in the trench 50. Further, from Figure 17A It can be seen that a portion of the doped semiconductor layer 30 extends above the upper surface of the first dielectric layer 28, and this portion of the doped semiconductor layer 30 is connected and electrically coupled to multiple portions of the doped semiconductor layer 30 formed in the trench 50.

[0071] like Figure 18A and Figure 18B As shown, a second dielectric layer 32 is formed in the trench 150 and may cover the upper surfaces of the doped semiconductor layer 30 and the first dielectric layer 28. In some embodiments, the second dielectric layer 32 may contact the side surface of the heterostructure 14 (e.g., the second layer 14b of the heterostructure 14) within the trench 50.

[0072] The second dielectric layer 32 can be formed by any suitable technique or process, including, for example, by deposition. The second dielectric layer 32 can be formed of any dielectric material, and in some embodiments, it can be formed of silicon oxide (SiO2). In some embodiments, the second dielectric layer 32 is formed of the same material as the first dielectric layer 28.

[0073] like Figure 19A and Figure 19B As shown, source contact regions 160 and gate contact regions 170 are formed by selectively removing multiple portions of the second dielectric layer 32 and the first dielectric layer 28. More specifically, source contact regions 160 are formed by selectively removing multiple portions of the first dielectric layer 28 and the second dielectric layer 32 covering the heterostructure 14. For example, multiple portions of the first dielectric layer 28 and the second dielectric layer 32 can be removed by etching to expose the upper surface of the heterostructure 14 in the trench. As shown, the second dielectric layer 32 may have an upper surface substantially coplanar with the upper surface of the heterostructure 14 within the trench. Separated source contact regions 160 can be formed for each of the heterostructures in the pair of heterostructures 14, for example, each source contact region in the source contact regions 160 may expose the corresponding heterostructure 14 pair in a corresponding trench within the trench.

[0074] like Figure 19A As shown, gate contact regions 170 can be formed by selectively removing (e.g., by etching) multiple portions of the second dielectric layer 32 to expose multiple portions of the doped semiconductor layer 30. In some embodiments, multiple gate contact regions 170 are formed, for example, to increase the contact area between the exposed portions of the doped semiconductor layer 30 and the gate contacts formed by subsequent processes (see [link to documentation]). Figure 20A , Figure 20B ).

[0075] like Figure 20A and Figure 20B As shown, a gate contact 22, a source contact 18, and a drain contact 20 are formed. The gate contact 22, source contact 18, and drain contact 20 can be formed by any suitable technique or process, including, for example, by depositing and patterning a conductive material. The source contact 18, gate contact 22, and drain contact 20 can be formed of any suitable conductive material; in several embodiments, the suitable conductive material can be a metallic material.

[0076] In some embodiments, the source contact 18 and the gate contact 22 can be formed by depositing the same metal layer, which can be patterned to form a separation between the source contact 18 and the gate contact 22. For example, the drain contact 20 can be formed on the back side of the substrate 12 by depositing a metal material on the back side of the substrate 12. In some embodiments, the drain contact 20 can be formed to cover the entire area of ​​the back side of the substrate 12 corresponding to the region of the substrate 12 on which the HEMT device 10 is formed. In some embodiments, the drain contact 20 is formed of the same metal material as the metal material used to form the source contact 18 and the gate contact 22.

[0077] like Figure 20A and Figure 20B As shown, the HEMT device 10 is formed when the source contact 18, gate contact 22 and drain contact 20 are formed.

[0078] Although Figures 2 to 20B The method illustrated herein shows the formation of a HEMT device 10 having two HEMTs 60, 62, which share the same gate contact 22; however, the embodiments provided herein are not limited thereto. For example, in Figures 2 to 20B The method illustrated herein can be used to form a HEMT device, which includes any number of HEMTs, and can be designed, for example, according to desired specific characteristics, such as those of HEMT device 10. For example, in some embodiments, HEMT device 10 may include a plurality of gate contacts 22 and a plurality of source contacts 18, wherein the gate contacts 22 and source contacts 18 are arranged alternately in a comb-like pattern.

[0079] Furthermore, although each of the HEMTs 60, 62 of the HEMT device 10 is shown as having two trenches, each trench including a corresponding pair of heterostructures 14, embodiments of this disclosure are not limited thereto. In various embodiments, the HEMTs of the HEMT device 10 may include a single pair of heterostructures 14 (e.g., as provided in a single trench), or in some embodiments, may include any number of heterostructure pairs (e.g., as provided in any corresponding number of trenches). Therefore, the source contact 18 can be electrically coupled to any number of HEMTs.

[0080] Figure 21 This is a schematic block diagram of electronic device 200. Electronic device 200 may be a semiconductor die having multiple circuits, components, features, etc., formed on the same substrate 224. Substrate 224 may be, for example, a silicon substrate. In some embodiments, substrate 224 includes substrate 12 and an epitaxial semiconductor layer 24 as previously described herein.

[0081] Electronic device 200 includes at least one HEMT device 210, which may be the same as or substantially the same as the HEMT device 10 previously described herein. In some embodiments, a plurality of HEMT devices 210 are formed on substrate 224 of electronic device 200.

[0082] Electronic device 200 may further include driver circuitry 212 and logic circuitry 214. Driver circuitry 212 and logic circuitry 214 may each include multiple circuits, components, features, etc., formed on or in the same substrate 224 (e.g., a silicon substrate), on or in which the HEMT device 210 is formed. In some embodiments, driver circuitry 212 and logic circuitry 214 include multiple electronic devices, such as transistors, formed using conventional techniques in silicon, including, for example, complementary metal-oxide-semiconductor (CMOS) processes, double-diffused metal-oxide-semiconductor (DMOS) processes, bipolar CMOS-DMOS (BCD) processes, etc. For example, driver circuitry 212 and logic circuitry 214 may include multiple CMOS transistors. Since conventional HEMT devices (such as conventional GaN HEMT devices) are typically formed on or in a substrate with… <111> The electronic devices in the driver circuitry 212 and logic circuitry 214 are typically not formed on the same substrate as the HEMT device because of their crystal orientation. Furthermore, due to the lower carrier mobility, the driver circuitry 212, logic circuitry 214, or other circuitry electrically coupled to the HEMT device are typically formed on a substrate with a different crystal orientation. <111> Crystal orientation (such as, <100> Crystal orientation or <110> On a silicon substrate (with crystal orientation).

[0083] However, in the embodiments provided herein, due to the structure and process for forming HEMT devices as described herein, HEMT device 210 can be formed with a different configuration than described herein. <111> Crystal orientation (such as, <100> Crystal orientation or <110> (Crystal orientation) On a crystal-oriented silicon substrate. This facilitates the inclusion of driver circuitry 212, logic circuitry 214, and various other circuits or electronic components on the same silicon substrate or the same semiconductor die as the HEMT device 210. By including the driver circuitry 212 and logic circuitry on the same die as the HEMT device 210, the electronic device 200 offers significant advantages in terms of increased speed and reduced stray inductance compared to electronic devices where the driver circuitry and logic circuitry are formed on a die separated from the HEMT device. Due to the wires, solder bumps, etc., providing electrical connections between the die on which the HEMT device is formed and the separate die on which the driver circuitry and logic circuitry are formed, the electronic device where the driver circuitry and logic circuitry are formed on a die separated from the HEMT device experiences reduced speed and increased stray inductance. Therefore, since there is no need for such wires or solder bumps to electrically connect the separated dies, the embodiments provided herein have significant advantages in terms of increased speed and reduced stray inductance, as the HEMT device 210, driver circuitry 212 and logic circuitry 214 are formed on the same substrate 224 (e.g., on the same silicon die).

[0084] In some embodiments, the electronic device 200 may be a DC / DC converter. However, embodiments of this disclosure are not limited thereto, and in many embodiments, the electronic device 200 may be any electronic device, including one or more HEMT devices 210 and one or more electronic components, features, etc., formed in or on the same substrate 224.

[0085] The various embodiments described herein can be combined to provide other embodiments. These and other changes can be made to the embodiments based on the above detailed description. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and equivalents thereof within the full scope of the claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A high electron mobility transistor (HEMT), comprising: A substrate having a first surface, wherein the substrate is a silicon substrate; An epitaxial semiconductor layer is located on the first surface of the substrate, wherein the epitaxial semiconductor layer is an epitaxial silicon layer. A first heterostructure and a second heterostructure are on the substrate and face each other. Each of the first heterostructure and the second heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer of each of the first heterostructure and the second heterostructure is on the corresponding side surface of the epitaxial semiconductor layer; A doped semiconductor layer is located between the first heterostructure and the second heterostructure; as well as Source contacts are located on the first heterostructure and the second heterostructure.

2. The HEMT according to claim 1, wherein the source contact directly contacts the surface of the first semiconductor layer and the second semiconductor layer of each of the first heterostructure and the second heterostructure.

3. The HEMT according to claim 2, wherein the surface of the second semiconductor layer is substantially coplanar with the surfaces of the first heterostructure and the second heterostructure.

4. The HEMT according to claim 1, wherein the first semiconductor layer of the first heterostructure and the second heterostructure comprises gallium nitride (GaN), and the second semiconductor layer of the first heterostructure and the second heterostructure comprises aluminum gallium nitride (AlGaN).

5. The HEMT of claim 4, wherein the doped semiconductor layer comprises gallium nitride (GaN) doped with a p-type dopant.

6. The HEMT according to claim 5, further comprising: A first dielectric layer includes a portion on the first surface of the substrate between the first heterostructure and the second heterostructure, and the doped semiconductor layer is on the portion of the first dielectric layer; as well as The second dielectric layer is on the doped semiconductor layer.

7. The HEMT device according to claim 1, wherein the epitaxial semiconductor layer has a different surface area at its upper surface than... <111> The crystal orientation of the crystal, and the epitaxial semiconductor layer having at the side surface of the epitaxial semiconductor layer. <111> Crystal orientation.

8. The HEMT device of claim 1, further comprising a feed layer on the side surface of the epitaxial semiconductor layer, the feed layer being disposed between the side surface of the epitaxial semiconductor layer and the first semiconductor layer of the first heterostructure and the second heterostructure.

9. The HEMT device according to claim 8, wherein the feed layer comprises aluminum nitride.

10. The HEMT of claim 1, further comprising a gate contact on the doped semiconductor layer.

11. The HEMT of claim 10, further comprising a drain contact on a second surface of the substrate opposite to the first surface.

12. The HEMT device according to claim 1, further comprising: A third heterostructure and a fourth heterostructure are located on the substrate and face each other. Each of the third heterostructure and the fourth heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer. The third heterostructure and the fourth heterostructure are laterally spaced from the first heterostructure and the second heterostructure. The doped semiconductor layer extends between the third heterostructure and the fourth heterostructure, and the source contact is electrically coupled to the first heterostructure, the second heterostructure, the third heterostructure, and the fourth heterostructure.

13. An electronic device, comprising: A silicon substrate having a first surface; A high electron mobility transistor (HEMT) on the silicon substrate, the HEMT comprising: A first heterostructure and a second heterostructure are located on a first surface of the silicon substrate and face each other. Each heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer; a first dielectric layer included on the first surface of the substrate between the first heterostructure and the second heterostructure; and a doped semiconductor layer on the portion of the first dielectric layer between the first heterostructure and the second heterostructure. The second dielectric layer includes a portion on the first surface of the substrate between the first heterostructure and the second heterostructure, the second dielectric layer being on the doped semiconductor layer; Source contacts are located on the first heterostructure and the second heterostructure; A gate contact is located on the doped semiconductor layer; and Drain contact, on the second surface of the silicon substrate opposite to the first surface.

14. The electronic device according to claim 13, further comprising: A driver circuit device, on the silicon substrate, electrically coupled to the HEMT, wherein the driver circuit device includes a plurality of complementary metal-oxide-semiconductor CMOS transistors.

15. The electronic device of claim 13, wherein the first semiconductor layer of the first heterostructure and the second heterostructure comprises undoped gallium nitride (GaN), the second semiconductor layer of the first heterostructure and the second heterostructure comprises aluminum gallium nitride (AlGaN), and the doped semiconductor layer comprises gallium nitride (GaN) doped with a p-type dopant.

16. A method for forming a high electron mobility transistor (HEMT), the method comprising: An epitaxial semiconductor layer is formed on a substrate, wherein the substrate is a silicon substrate; Trenches are formed in the epitaxial semiconductor layer; A first heterostructure and a second heterostructure are formed on a first surface of the substrate and on corresponding side surfaces of the epitaxial semiconductor layer. Each of the first heterostructure and the second heterostructure includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer, comprising gallium nitride (GaN), is formed in the trench on the side surface of the epitaxial semiconductor layer. as well as A second semiconductor layer is formed on a side surface of the first semiconductor layer in the trench, the second semiconductor layer comprising aluminum gallium nitride (AlGaN); A first dielectric layer is formed in the trench on the first surface of the substrate; A doped semiconductor layer is formed on the portion of the first dielectric layer between the first heterostructure and the second heterostructure, wherein the doped semiconductor layer covers the upper surface of the first dielectric layer outside the trench; The first dielectric layer is between the first surface of the substrate and a portion of the doped semiconductor layer in the trench; A second dielectric layer is formed in the trench on the portion of the doped semiconductor layer; Source contacts are formed on the first heterostructure and the second heterostructure; A gate contact is formed on the doped semiconductor layer; as well as A drain contact is formed on a second surface of the silicon substrate opposite to the first surface.

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