Circuit and method for controlling a power converter based on a feedback current

Abstract

The invention is titled "Circuit and Method for Controlling a Power Converter Based on Feedback Current". The present disclosure relates to controlling a power converter based on feedback current. The controller includes: a feedback sensing circuit configured to generate a feedback current based on the output voltage of the power converter during a first time interval in a switching cycle of the power converter, and to generate a digital sensing signal indicative of the duration of the first time interval; and a feedback signal generator configured to determine the magnitude of the feedback current flowing during the first time interval based on the value of the digital sensing signal, and to generate a digital feedback signal based on the determined magnitude of the feedback current. The controller adjusts the output voltage of the power converter in response to the digital feedback signal.

Description

Technical Field

[0001] The present disclosure relates to a controller, a power converter including the controller, and a method for controlling the power converter. Background Art

[0002] A power converter converts an input voltage into an output voltage and supplies the output voltage to a load. The power converter may perform a feedback operation using a feedback current to maintain the output voltage at a predetermined level. For example, the power converter may include an optocoupler, a feedback capacitor, and a controller. The optocoupler may receive an electrical signal indicating the output voltage, convert the electrical signal into light, and cause the feedback current to flow therethrough in response to the converted light. The feedback capacitor is coupled in parallel to the optocoupler and adjusts the level of a feedback voltage at an end of the feedback capacitor in response to the feedback current. The controller adjusts a duty cycle of a power switch using the feedback voltage to maintain the output voltage at a predetermined level.

[0003] In such a conventional power converter, the feedback current continuously flows during the entire switching cycle of the power switch, thereby consuming a relatively large amount of power. In addition, the feedback capacitor is provided outside the controller and has a relatively large capacitance value, thereby occupying a relatively large circuit area. Summary of the Invention

[0004] Embodiments of the present application relate to a controller, a power converter including the controller, and a method for controlling the power converter.

[0005] In an embodiment, a controller includes: a feedback sensing circuit configured to generate a feedback current based on an output voltage of a power converter during a first time interval in a switching cycle of the power converter, and generate a digital sensing signal indicating a duration of the first time interval; and a feedback signal generator configured to determine an amplitude of the feedback current flowing during the first time interval based on a value of the digital sensing signal, and generate a digital feedback signal based on the determined amplitude of the feedback current. The controller adjusts the output voltage of the power converter in response to the digital feedback signal.

[0006] In the embodiment of the above controller, the first time interval is in a range of 5% to 45% of the switching cycle.

[0007] In the embodiment of the above controller, the first time interval varies with an amplitude of the feedback current.

[0008] In the above-described embodiment of the controller, the feedback sensing circuit includes: a first capacitor configured to regulate the level of a feedback sensing voltage using a feedback current during a first time interval; and a second capacitor configured to regulate the level of a first reference voltage using a reference current during the first time interval.

[0009] In the above-described embodiment of the controller, each of the first capacitor and the second capacitor has a capacitance value in the range from about 10 pF to about 20 pF.

[0010] In an embodiment, a power converter includes a first side having a controller and a second side having an output capacitor configured to provide an output voltage. The controller includes: a feedback sensing circuit configured to generate a feedback current based on the output voltage during a certain time interval in a switching cycle and generate a digital sensing signal indicating the duration of the time interval; and a feedback signal generator configured to determine the magnitude of the feedback current flowing during the time interval based on the value of the digital sensing signal and generate a digital feedback signal based on the determined magnitude of the feedback current. The controller regulates the output voltage of the power converter in response to the digital feedback signal.

[0011] In an embodiment, a method for controlling a power converter includes: generating a feedback current based on the output voltage of the power converter during a certain time interval in a switching cycle; generating a digital sensing signal indicating the duration of the time interval; determining the magnitude of the feedback current flowing during the time interval based on the value of the digital sensing signal; generating a digital feedback signal based on the determined magnitude of the feedback current; and regulating the output voltage of the power converter in response to the digital feedback signal.

[0012] In the above-described embodiment of the method, the time interval is in the range from 5% to 45% of the switching cycle.

[0013] In the above-described embodiment of the method, the method further includes changing the time interval as a function of the magnitude of the feedback current.

[0014] In the above-described embodiment of the method, generating the digital sensing signal includes: regulating the level of a feedback sensing voltage using a feedback current during the time interval; regulating the level of a reference voltage using a reference current during the time interval; comparing the level of the feedback sensing voltage with the level of the reference voltage to generate an output signal indicating the comparison result; and generating a digital sensing signal in response to the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A power converter is shown in accordance with an embodiment of the present disclosure.

[0016] Figure 2 Shows a flyback converter according to an embodiment of the present disclosure.

[0017] Figure 3 Shows a controller according to an embodiment of the present disclosure.

[0018] Figure 4 Shows a feedback sensing circuit according to an embodiment of the present disclosure.

[0019] Figure 5 Shows according to an embodiment of the present disclosure Figure 4 the operation of the feedback sensing circuit in

[0020] Figure 6 Shows a digital feedback signal generator according to an embodiment of the present disclosure.

[0021] Figure 7 Shows according to an embodiment of the present disclosure Figure 3 the operation of the controller in

[0022] Figure 8 Shows the process performed by the controller according to the embodiment in Figure 3 Detailed Description

[0023] Embodiments of the present application relate to a controller for controlling a power converter, a power converter including the controller, and a method for controlling the power converter.

[0024] In an embodiment, the controller controls the feedback current to flow during a certain time interval of the switching cycle rather than throughout the entire switching cycle. For example, the time interval is in the range of 5% to 45% of the switching cycle. As a result, compared with the power consumption of a conventional power converter in which the feedback current continuously flows throughout the entire switching cycle, the power converter including the controller according to the embodiment of the present disclosure reduces power consumption.

[0025] In an embodiment, the PWM controller includes one or more capacitors, each capacitor having a relatively small capacitance value and a relatively small size. As a result, compared with the circuit area of a conventional power converter including a feedback capacitor disposed outside the controller and having a relatively large capacitance value, the power converter including the PWM controller according to the embodiment of the present disclosure reduces the circuit area.

[0026] ​The following provides specific embodiments of the implementation in conjunction with the accompanying drawings. The scope of the present disclosure is limited only by the claims and encompasses many alternatives, modifications, and equivalents. Although the steps of various methods are presented in a given order, the embodiments need not be limited to being performed in the listed order. In some embodiments, certain operations may be performed simultaneously in an order other than the described order, or not at all.

[0027] Numerous specific details are set forth in the following description. These details are provided to promote a thorough understanding of the scope of the present disclosure through specific examples, and the embodiments may be practiced according to the claims without some of these specific details. Thus, the specific embodiments of the present disclosure are illustrative and not intended to be exclusive or restrictive. For clarity purposes, technical materials known in the technical field related to the present disclosure are not described in detail so as not to unnecessarily obscure the present disclosure.

[0028] Figure 1 A power converter 100 according to an embodiment of the present disclosure is shown. The power converter 100 receives an input signal (e.g., input voltage) V in , and provides an output signal (e.g., output voltage) V o to the load 160.

[0029] The power converter 100 can use feedback control based on information about the output voltage V o to regulate the level of the output voltage V o . For example, the power converter 100 can be any one of a forward converter, a power factor correction (PFC) converter, or a flyback converter.

[0030] The power converter 100 can be controlled by a controller 120. In an embodiment, the controller 120 controls the flow of feedback current during a certain time interval of the switching cycle of the power converter 100 rather than the entire switching cycle based on the output voltage V o . As a result, the power converter 100 including the controller 120 reduces power consumption compared to the power consumption of a conventional power converter in which the feedback current flows continuously throughout the switching cycle.

[0031] The PWM controller 120 can be integrated in one or more semiconductor chips. These semiconductor chips can be self - packaged or packaged together with one or more other semiconductor chips.

[0032] The load 160 can include one or more integrated chips (ICs). In an embodiment, the output voltage V oFor powering one or more of a central processing unit (CPU), a graphics processing unit (GPU), an integrated memory circuit, a battery charger, a light emitting diode (LED), or substantially any type of electrical load.

[0033] Figure 2 Shows a power converter (e.g., a flyback converter) 200 according to an embodiment of the present disclosure. Figure 2 The flyback converter 200 in receives an input signal (e.g., an input voltage) AC IN , and provides an output signal (e.g., an output voltage) V o to a load (e.g., Figure 1 the load 160 in).

[0034] The primary side of the flyback converter 200 includes a PWM controller 220, a rectifier 202, a first capacitor 204, a first resistor 206, and a primary coil 208, an auxiliary coil 232, a first diode 230, a second resistor 228, a second capacitor 226, and a first part of an optocoupler 222.

[0035] The PWM controller 220 includes a switching device (e.g., Figure 3 the switching device 342 in), and generates a drive signal (e.g., Figure 3 the drive signal DR in) to turn on or off the switching device. For example, during a first part of the cycle of the drive signal (e.g., the on-time duration), the PWM controller 220 turns on the switching device. This causes energy from the input voltage AC IN to be supplied to the primary coil 208, where the energy is stored as magnetic flux.

[0036] The PWM controller 220 also includes a feedback sensing circuit (FSC) 230 and a digital feedback signal generator (DFSG) 250. The FSC 230 generates a feedback current I that flows during a certain time interval in the switching cycle of the flyback converter 200 CSEN , and generates a digital sensing signal (e.g., Figure 3 the digital sensing signal D in) indicating the duration of the time interval. The DFSG 250 determines the magnitude of the feedback current I that flows during the time interval based on the value of the digital sensing signal, and generates a digital feedback signal (e.g., Δt ) based on the determined magnitude of the feedback current I CSEN . CSEN The DFSG 250 generates a digital feedback signal (e.g., Figure 3 the digital feedback signal D in) FB .

[0037] During the remainder of the cycle of the drive signal (e.g., the off-time duration), the PWM controller 220 turns off the switching device. In response, the energy stored in the primary coil 208 is transferred to the secondary coil 210, causing current to flow in the secondary coil 210 and generating a voltage across the end terminals of the secondary coil 210.

[0038] In Figure 2 the illustrated embodiment, the PWM controller 220 includes the switching device, but embodiments of the present disclosure are not limited thereto. For example, the switching device may be provided external to the PWM controller 220.

[0039] The second capacitor 226 has a first end coupled to the first node (or first pin) Vcc and a second end coupled to ground. When the flyback converter 200 performs normal switching operations, the auxiliary winding 232, the first diode 230, and the second resistor 228 provide power to charge the second capacitor 226.

[0040] The secondary side of the flyback converter 200 includes the secondary coil 210, the second diode 212, the output capacitor 214, the third resistor 216, the zener diode 218, and the second portion of the optocoupler 222.

[0041] The second portion of the optocoupler 222 receives an electrical signal (e.g., current) indicative of the output voltage V o of the flyback converter 200 and converts the received electrical signal into light. For example, the second portion of the optocoupler 222 includes a light-emitting diode (LED).

[0042] The first portion of the optocoupler 222, which is included on the primary side of the flyback converter 200, detects the converted light and modulates the feedback current I CSEN . The feedback current I CSEN can flow from the second node (e.g., the second pin) FB to ground during a given time interval within the switching cycle of the flyback converter 200 rather than throughout the switching cycle. For example, the switching cycle of the flyback converter 200 can be the period of a control signal (e.g., Figure 3 the drive signal DR in Figure 3 ) that turns on or off the switching device (e.g., Figure 3 the switching device 342 in Figure 5 ). In an embodiment, the period of the control signal is substantially equal to the period of a clock signal (e.g., Figure 3 the clock signal CLK in Figure 5 ) or the period of each of a plurality of switching signals (e.g., Figure 5 the second switching signal S2 and the fourth switching signal S4 in Figure 5 ) (e.g., s the switching cycle T s ) or both.

[0043] InFigure 2 In the illustrated embodiment, the flyback converter 200 uses an optocoupler 222 that modulates a feedback current I in response to an electrical signal indicative of an output voltage V generated from the secondary side. o However, embodiments of the present disclosure are not limited thereto, and embodiments of the present disclosure include various power converters (e.g., forward converters and PFC converters), each of which uses feedback control based on information about its output voltage. CSEN Shown is a controller (e.g., a PWM controller) 320 according to an embodiment of the present disclosure. In

[0044] Figure 3 In, the PWM controller 320 includes a feedback sensing circuit 330, a digital feedback signal generator 350, a digital-to-analog converter (DAC) 332, a comparator 334, an oscillator (OSC) 336, a flip-flop 338, a logic gate 340, a switching device 342, and a sense resistor 344. Figure 3 The feedback sensing circuit 330 is coupled to a first node (e.g., a feedback pin) 346 and generates a digital sensing signal D indicative of a specific time interval.

[0045] In an embodiment, the feedback sensing circuit 330 includes a first capacitor (e.g., the first capacitor 406 in Δt ) and a second capacitor (e.g., the second capacitor 408 in Figure 4 ), and the digital sensing signal D Figure 4 indicates a time interval during which the first capacitor is discharged by the feedback current I Δt and the second capacitor is charged by a reference current (e.g., the reference current I in CSEN ). During this time interval of the switching cycle, the feedback current I Figure 4 flows from the feedback sensing circuit 330 to ground through the feedback pin 346 and the optocoupler 322. During the remaining time interval of the switching cycle, the flow of the feedback current I REF from the feedback sensing circuit 330 is substantially prevented. CSEN The digital feedback signal generator 350 generates a digital feedback signal D CSEN in response to the digital sensing signal D

[0046] The digital feedback signal D is used to maintain the level of the output voltage of the power converter at a predetermined level. In an embodiment, the digital feedback signal generator 350 determines the magnitude of the feedback current I during a certain time interval in the switching cycle based on the digital sensing signal D indicative of the time interval, and based on the determined feedback current I Δt FB FB Δt CSEN CSEN ​​​​​to generate a feedback signal D based on the amplitude of FB . For example, the time interval is in the range of 5% to 45% of the switching period. The digital feedback signal D FB is converted into an analog feedback signal (e.g., feedback voltage) V DFB , and the analog feedback signal is used to maintain the level of the output voltage of the power converter (e.g., Figure 2 the output voltage V in o ) at a predetermined level. For example, when the output voltage of the power converter is greater than the predetermined level, the feedback current I CSEN during the interval of the switching period can become greater than a predetermined amplitude (e.g., about 100 μA), thereby reducing the digital sense signal D CSEN indicating the time interval during which the first capacitor is discharged by the feedback current I Δt . In response to the reduced value of the digital sense signal D Δt , the digital feedback signal generator 350 reduces the value of the digital feedback signal D FB . As a result, the value of the feedback voltage V DFB is reduced to reduce the on-time duration of the power switch, thereby reducing the output voltage.

[0047] The DAC 332 converts the digital feedback signal D FB into an analog feedback signal (e.g., feedback voltage) V DFB . The DAC 332 provides the feedback voltage V DFB to the comparator 334.

[0048] In an embodiment, the combination of the optocoupler 322, the feedback sensing circuit 330, the digital feedback signal generator 350, and the DAC 332 can be equivalent to an analog circuit (hereinafter referred to as a "virtual analog circuit") including an optocoupler 322, a current source, and a capacitor. For example, the current source generates a virtual feedback current (e.g., Figure 6 the digital feedback current I in DFB ), and a capacitor having a virtual capacitance value (e.g., Figure 6 the digital capacitance value C in DFB ) is coupled in parallel to the optocoupler 322, thereby generating a feedback voltage V CSEN at the end of the capacitor in response to the feedback current I DFB .

[0049] In an embodiment, the PWM controller 320 generates a digital feedback signal D CSEN based on the amplitude of the feedback current I FB flowing during the interval of the switching period, and generates a feedback voltage V FB in response to the digital feedback signal D DFBFor example, the DAC 332 reduces the feedback voltage V FB in response to a decreasing value of the digital feedback signal D DFB , such that the amount of decrease in the feedback voltage V DFB is due to the capacitor in the virtual analog circuit having a digital capacitance value C Figure 6 discharging current throughout the switching cycle. The current has an amplitude obtained by subtracting the amplitude of the digital feedback current I DFB in Figure 6 CSEN from the amplitude of the feedback current I Figure 6 in Figure 6 DFB (e.g., approximately 100 μA). Since the PWM controller 320 controls the feedback current I CSEN to flow during a time interval of the switching cycle rather than throughout the entire switching cycle in order to determine the digital feedback signal D FB , the power converter including the PWM controller 320 reduces power consumption compared to a conventional power converter in which the feedback current continuously flows throughout the entire switching cycle.

[0050] Comparator 334 has an inverting input that receives the feedback voltage V DFB and a non-inverting input that receives the sense voltage v cs . When the sense voltage v cs becomes equal to or greater than the feedback voltage V DFB , comparator 334 enables its output signal; otherwise, it disables the output signal.

[0051] A flip-flop (e.g., an RS flip-flop) 338 receives the clock signal CLK from the OSC 336 as a set signal and the output signal from the comparator 334 as a reset signal. When the reset signal has a logic high value, the RS flip-flop 338 generates an output signal QBS having a logic high value, and when the set signal has a logic high value, it generates an output signal QBS having a logic low value.

[0052] A logic gate (e.g., a NOR gate) 340 receives the clock signal CLK from the OSC 336 and the output signal QBS from the RS flip-flop 338. In an embodiment, the NOR gate 340 performs a logical NOR operation on the clock signal CLK and the output signal QBS and outputs a drive signal DR indicating the result of the logical operation to the switching device 342.

[0053] The switching device 342 is coupled between a second node (e.g., a drain pin) 348 and the sense resistor 344. In an embodiment, the switching device 342 includes an NMOS transistor having a drain coupled to the drain pin 348 and a source coupled to the first end of the sense resistor 334.

[0054] The sense resistor 334 also has a second end coupled to a third node (e.g., a ground pin) 342. The sense voltage v cs is the voltage between the first end and the second end of the sense resistor 334.

[0055] Figure 4 Illustrated is a feedback sense circuit 430 suitable for use as a Figure 3 feedback sense circuit 330 in accordance with an embodiment of the present disclosure. The feedback sense circuit 430 includes a first switch 402, a second switch 422, a third switch 418, a fourth switch 404, a first capacitor 406, a second capacitor 408, a current source 424, a switch control circuit 412, a comparator 410, a flip-flop 414, and a counter 416.

[0056] The first switch 402 couples a first reference voltage V REF to the first node N1 in response to a first switch signal S1. In an embodiment, when the first switch signal S1 has a first value (e.g., a logic high value), the first switch 402 is turned on to couple the first reference voltage V REF to the first node N1, and when the first switch signal S1 has a second value (e.g., a logic low value), the first switch is turned off to decouple the first reference voltage V REF from the first node N1.

[0057] The second switch 422 couples the first node N1 to the second node N2, and a feedback current I CSEN flows through the second node N2 in response to a second switch signal S2. In an embodiment, when the second switch signal S2 has a logic high value, the second switch 422 is turned on to couple the first node N1 to the second node N2, and when the second switch signal S2 has a logic low value, the second switch is turned off to decouple the first node N1 from the second node N2.

[0058] The third switch 418 couples the third node N3 to ground in response to a third switch signal S3. In an embodiment, when the third switch signal S3 has a logic high value, the third switch 418 is turned on to couple the third node N3 to ground, and when the third switch signal S3 has a logic low value, the third switch is turned off to decouple the third node N3 from ground.

[0059] The fourth switch 404 couples the current source 424 to the third node N3 in response to a fourth switch signal S4. In an embodiment, when the fourth switch signal S4 has a logic high value, the fourth switch 404 is turned on to couple the current source 424 to the third node N3, and when the fourth switch signal S4 has a logic low value, the fourth switch is turned off to decouple the current source 424 from the third node N3.

[0060] The first capacitor 406 is coupled between the first node N1 and ground and has a capacitance value C SEN The second capacitor 408 is coupled between the third node N3 and ground and has a capacitance value C REF In an embodiment, each of the first capacitor 406 and the second capacitor 408 has a relatively small capacitance value (e.g., in the range of about 10 pF to about 20 pF) compared to the capacitance value (e.g., several tens of nF) of an external capacitor disposed outside the PWM controller of a conventional power converter. Additionally, each of the first capacitor 406 and the second capacitor 408 is disposed within the PWM controller (e.g., Figure 3 the PWM controller 320 in), and thus has a relatively small size compared to the size of the external capacitor of a conventional power converter.

[0061] Comparator 410 compares the feedback sense signal (or feedback sense voltage) V CSEN and a second reference signal (e.g., second reference voltage) V CREF and provides an output signal indicative of the comparison result to the switch control circuit 412 and the flip-flop 414. Comparator 410 has an inverting input coupled to the first node N1 and a non-inverting input coupled to the third node N3.

[0062] The switch control circuit 412 receives the output signal, the clock signal CLK, and the internal clock ICLK from the comparator 410 and generates a first switch signal S1, a second switch signal S2, a third switch signal S3, and a fourth switch signal S4 in response to the output signal, the clock signal CLK, and the internal clock ICLK. In an embodiment, when the switch control circuit 412 detects a particular edge (e.g., rising edge) of the clock signal CLK, the switch control circuit 412 generates the second switch signal S2 and the fourth switch signal S4 each having a logic high value and the first switch signal S1 and the third switch signal S3 each having a logic low value. The switch control circuit 412 maintains generating the second switch signal S2 and the fourth switch signal S4 each having a logic high value and the first switch signal S1 and the third switch signal S3 each having a logic low value until the comparator 410 validates the output signal. When the switch control circuit 412 receives the validated output signal, the switch control circuit 412 generates the second switch signal S2 and the fourth switch signal S4 each having a logic low value and the first switch signal S1 and the third switch signal S3 each having a logic high value. The switch circuit 412 maintains generating the second switch signal S2 and the fourth switch signal S4 each having a logic low value and the first switch signal S1 and the third switch signal S3 each having a logic high value until the switch control circuit 412 detects the rising edge of the clock signal CLK again.

[0063] In an embodiment, the trigger 414 is an RS trigger that receives the second switch signal S2 as a set signal and the output signal from the comparator 410 as a reset signal. When the second switch signal S2 has a logic high value, the RS trigger 414 generates an output signal Q with a logic high value, and when the output signal from the comparator 410 has a logic high value, the trigger generates an output signal Q with a logic low value. In Figure 4 the illustrated embodiment, the RS trigger 414 receives the second switch signal S2 as a set signal, but the embodiments of the present disclosure are not limited thereto. For example, the RS trigger 414 may receive the fourth switch signal S4 as a set signal.

[0064] The counter 416 receives the output signal Q from the trigger 414 and generates a digital sensing signal D indicating the magnitude of the feedback current I CSEN in response to the output signal Q. Δt In an embodiment, when the output signal Q has a logic high value, the counter 416 counts at a predetermined rate, and when the output signal Q has a logic low value, the counter resets to zero, thereby generating a digital sensing signal D indicating the time interval (e.g., Figure 5 the first time interval Δt in Figure 5 ) from the first time (e.g., Figure 5 the first time t1 in Δt ) when the second switch signal S2 becomes effective to the second time (e.g.,

[0065] when the output signal becomes effective by the comparator 410 (e.g., Figure 5 the second time t2 in

[0066] The operation of the feedback sensing circuit 430 will be described in more detail below with reference to Figure 4 and Figure 5 . At the first time t1, the switch control circuit 412 makes the second switch signal S2 and the fourth switch signal S4 effective. In response to the second switch signal S2, the second switch 422 is turned on to discharge the first capacitor 406 through the feedback current I CSEN so that the level of the feedback sensing voltage V CSEN decreases from the level of the first given voltage (e.g., the first reference voltage V REF ). In response to the fourth switch signal S4, the fourth switch 404 is turned on to charge the second capacitor 408 through the reference current I REF so that the level of the second reference voltage V CREF increases from the level of the second given voltage (e.g., zero voltage).

[0067] During a first time interval Δt between a first time t1 and a second time t2, the flip-flop 414 generates an output signal Q with a logic high value in response to a second switch signal S2 with a logic high value, thereby incrementing the value of the counter 416 in response to an internal clock signal ICLK.

[0068] At the second time t2, the level of a second reference voltage V CREF becomes substantially equal to the level of a feedback sense voltage V CSEN . As a result, the comparator 410 enables the output signal and provides the enabled output signal to the RS flip-flop 414 as a reset signal. The flip-flop 414 generates an output signal Q with a logic low value in response to the output signal of the comparator 410 with a logic high value, thereby stopping the incrementing of the value of the counter 416 and outputting a digital sense signal D Δt .

[0069] In Figure 5 the illustrated embodiment, the magnitude of a feedback current I CSEN is represented by the following equation:

[0070]

[0071] In Equation 1, V n is the voltage of the feedback sense voltage V CSEN at the second time t2.

[0072] The magnitude of a reference current I REF is represented by the following equation:

[0073]

[0074] In Equation 2, V n is the voltage of the second reference voltage V CREF at the second time t2. In the embodiment, the magnitude of the reference current I REF can be determined based on the capacitance value C CSEN of the second capacitor 408, the maximum level of the feedback sense voltage V Figure 5 e.g., the first reference voltage V REF in Figure 7 , the period of a clock signal (e.g., the clock signal CLK in REF ) such that the second reference voltage V CREF can reach the first reference voltage V REF within the period of the clock signal. For example, when the capacitance value C REF is 10 pF, the first reference voltage V REF is 5 V, and the period of the clock signal is 10 μs, the reference current I REFhas an amplitude greater than 5 μA. Compared with the amplitude of the feedback current (e.g., 100 μA or greater) flowing through the optocoupler in a conventional power converter, the reference current I REF can have a relatively small amplitude.

[0075] In an embodiment, the capacitance value C of the first capacitor 406 SEN can be substantially the same as the capacitance value C of the second capacitor 408 REF . In such embodiments, Equation 1 can be rewritten for the amplitude of the feedback current I CSEN using Equation 2 as follows:

[0076]

[0077] In Equation 3, k is a given constant that can be represented by C SEN *C REF . As shown in Equation 3, the amplitude of the feedback current I CSEN can vary with the first time interval Δt. For example, when the amplitude of the feedback current I CSEN increases, the first time interval Δt decreases, and vice versa.

[0078] During a second time interval between a second time t2 and a third time t3, the switch control circuit 412 generates a second switch signal S2 and a fourth switch signal S4 each having a logic low value and a first switch signal S1 and a third switch signal S3 each having a logic high value. The first switch S1 is turned on in response to the first switch signal S1 to couple the first node N1 to the first reference voltage V REF , thereby maintaining the level of the feedback sense voltage V CSEN substantially equal to the level of the first reference voltage V REF . The third switch S3 is turned on in response to the third switch signal S3 to couple the third node N3 to ground, thereby maintaining the level of the second reference voltage V CREF substantially equal to the zero voltage.

[0079] During a third time interval between the third time t3 and the fourth time t4, the operation of the feedback sense circuit 430 is similar to the above-described operation during the first time interval Δt. Therefore, for the sake of brevity, a detailed description of the operation of the feedback sense circuit 430 during the third time interval is omitted herein.

[0080] Figure 6 Illustrates a digital feedback signal generator 650 according to an embodiment of the present disclosure. The digital feedback signal generator 650 includes a divider 652, a subtractor 654, a multiplier 698, and an adder 656.

[0081] The divider 652 divides the first constant k (e.g., the constant k in Equation 3) by the digital sense signal D Δt (e.g., Figure 4 the digital sense signal D in Δt ) and provides an output signal indicating the value after division to the subtractor 654. In an embodiment, the first constant k is the product result of the capacitance value of the first capacitor (e.g., Figure 4 the first capacitor 406 in Figure 4 ) and the capacitance value of the second capacitor (e.g., Δt the second capacitor 408 in Figure 5 ), and the digital sense signal D

[0082] indicates the time interval during which the first capacitor is discharged and the second capacitor is charged (e.g., DFB the first time interval Δt in REF ). Figure 4 the reference current I in REF ) and provides the value after subtraction to the multiplier 698. For example, the magnitude of the digital feedback current I DFB can be equal to the magnitude of the feedback current in a conventional power converter (e.g., about 100 μA) to keep the level of the feedback voltage constant when the conventional power converter generates an output voltage with a predetermined level.

[0083] The multiplier 698 multiplies the value after subtraction by the second constant h and provides the multiplied value to the adder 656. The second constant h can be obtained by dividing the switching period T Figure 5 (e.g., the first switching signal S1, the second switching signal S2, the third switching signal S3, and the fourth switching signal S4 in s ) of each of the plurality of switching signals by the digital capacitance value C Figure 5 (e.g., the switching period T in s ). For example, the digital capacitance value C DFB can be equal to the capacitance value of the feedback capacitor in a conventional power converter (e.g., several tens of nF), which has a first end coupled to an optocoupler and a current source generating a feedback current and a second end coupled to ground. DFB

[0084] The adder 656 adds the multiplied value to the previous value D Figure 3 (n - 1) of the digital feedback signal (e.g., the digital feedback signal D in FB ) and generates the current value D FB (n) of the digital feedback signal. In FB . Figure 6 ​In the illustrated embodiment, the current value D of the digital feedback signal FB (n) is represented by the following equation:

[0085]

[0086] Figure 7 Shows the operation of a PWM controller (e.g., Figure 2 the PWM controller 320 in) in a power converter according to an embodiment of the present disclosure (e.g., Figure 3 the flyback converter 200 in). The figure shows the clock signal CLK (e.g., Figure 3 the clock signal CLK in), the feedback sense signal V CSEN (e.g., Figure 4 the feedback sense voltage V CSEN in), the second reference voltage V CREF (e.g., Figure 4 the second reference voltage V CREF in), the virtual optocoupler current I opto , the feedback current I CSEN (e.g., Figure 4 the feedback current I CSEN in), the feedback signal V DFB (e.g., Figure 3 the feedback voltage V DFB in) and the sense voltage v cs (e.g., Figure 3 the sense voltage v cs in) example waveforms.

[0087] At the first time t1, Figure 4 the switch control circuit 412 in enables the second switch signal S2 and the fourth switch signal S4, and disables the first switch signal S1 and the third switch signal S3. Figure 4 The second switch 422 in is turned on to discharge the first capacitor 406 through the feedback current I CSEN , thereby reducing the level of the feedback sense voltage V CSEN from the level of the first reference voltage V REF . Figure 4 The fourth switch 404 in is turned on to charge the second capacitor 408 through the reference current I REF , thereby increasing the level of the second reference voltage V CREF from zero voltage.

[0088] During a first time interval Δt1 from the first time t1 to the second time t2, the feedback current I CSEN has an amplitude equal to the amplitude of the virtual optocoupler current I opto . For example, the virtual optocoupler current Iopto represents the assumed feedback current I CSEN that can flow continuously throughout the switching period T s is the feedback current I that flows. In an embodiment, the first time interval Δt1 is within the range of 5% to 45% of the switching period T CSEN . s

[0089] At the second time t2, the level of the second reference voltage V CREF becomes substantially equal to the level of the feedback sense voltage V CSEN . As a result, Figure 3 the feedback sense circuit 330 in Δt outputs a digital sense signal D indicating the first time interval Δt1, and Figure 3 the digital feedback signal generator 350 in FB outputs the digital feedback signal D to the DAC 332. The DAC 332 converts the digital feedback signal D FB into an analog feedback voltage V DFB . Additionally, Figure 4 the switch control circuit 412 in Figure 4 disables the second switch signal S2 and the fourth switch signal S4, and enables the first switch signal S1 and the third switch signal S3. As a result, CSEN the first switch 402 in REF is turned on to make the level of the feedback sense voltage V CREF substantially equal to the level of the first reference voltage V, and the third switch 418 is turned on to make the level of the second reference voltage V

[0090] At the third time t3, Figure 3 the oscillator 336 in cs disables the clock signal CLK to turn on the switching device 342. As a result, the current flowing through the switching device 342 starts to increase, thereby increasing the level of the sense voltage v

[0091] At the fourth time t4, when the sense voltage v cs reaches the feedback voltage V DFB to turn off the switching device 342, Figure 3 the comparator 334 in Figure 4 enables its output signal. The switch control circuit 412 in

[0092] At the fifth time t5, Figure 4 ​The switch control circuit 412 in the embodiment enables the second switch signal S2 and the fourth switch signal S4, and disables the first switch signal S1 and the third switch signal S3. As a result, the feedback sensing voltage V CSEN The level of the first reference voltage V REF The level of the second reference voltage V CREF The level increases from zero voltage.

[0093] During the second time interval Δt2 from the fifth time t5 to the sixth time t6, the feedback current I CSEN has a value substantially equal to the virtual optocoupler current I opto The feedback current I during the second time interval Δt2 is CSEN The amplitude of the feedback current I during the first time interval Δt1 is greater than CSEN The amplitude of , thereby making the second time interval Δt2 shorter than the first time interval Δt1.

[0094] At the sixth time t6, the second reference voltage V CREF The level becomes substantially equal to the feedback sensing voltage V CSEN Because the second time interval Δt2 is shorter than the first time interval Δt1, the digital feedback signal D FB Compared with the value at the second time t2, Figure 3 The digital feedback signal D FB The value of decreases at the sixth time t6. As a result, Figure 3 The DAC 332 in the circuit can generate a feedback voltage V DFB , the voltage decreases at the sixth time t6 by the same amount as the digital feedback signal D FB For example, the feedback voltage V DFB The reduction can be from Figure 6 The digital capacitance value C DFB The capacitor in the virtual simulation circuit is switched by a switching cycle T s The amount of current during discharge, which has a current from the feedback current I CSEN The magnitude minus Figure 6 Digital feedback current I DFB The feedback voltage V DFB The reduced value of makes the on-time duration (not shown) of the switching device 342 shorter than the on-time duration between the third time t3 and the fourth time t4 in the next switching cycle, thereby reducing the output voltage of the power converter (e.g., Figure 2 The output voltage V o ) and the feedback current I indicating the output voltage CSEN AlthoughFigure 7 The embodiments shown regulate the duty cycle of a power converter to adjust the output voltage, but embodiments of the present disclosure are not limited thereto. For example, the power converter may control the operating frequency to adjust the output voltage.

[0095] As described above, the PWM controller according to an embodiment of the present disclosure causes the feedback current to flow during a certain time interval of the switching cycle rather than during the entire switching cycle. As a result, the power consumption of the power converter including the PWM controller according to an embodiment of the present disclosure is reduced compared to that of a conventional power converter in which the feedback current continuously flows during the entire switching cycle.

[0096] In an embodiment, the PWM controller includes one or more capacitors, each having a relatively small capacitance value and a relatively small size. As a result, the circuit area of the power converter including the PWM controller according to an embodiment of the present disclosure is reduced compared to that of a conventional power converter including a feedback capacitor disposed outside the controller and having a relatively large capacitance value.

[0097] In an embodiment, the PWM controller generates a digital sensing signal having a value indicating the time interval during which the feedback current flows. The value of the digital sensing signal may indicate information about the duty cycle of the switching device in the power converter, and this duty cycle information can be used in various digital circuit components, each of which performs one or more specific functions (e.g., limiting the duty cycle to a given maximum value, performing line compensation, and performing slope compensation).

[0098] Figure 8 A process 800 performed by a controller (e.g., Figure 2 the PWM controller 320 in Figure 3 ) of a power converter (e.g., Figure 3 the flyback converter 200 in Figure 3 ) according to an embodiment is shown. In an embodiment, the PWM controller includes a feedback sensing circuit (e.g., Figure 3 the feedback sensing circuit 330 in Figure 3 ), a feedback signal generator (e.g., Figure 3 the feedback signal generator 350 in Figure 3 ), and a DAC (e.g., Figure 3 the DAC 332 in

[0099] At S810, the feedback sensing circuit generates a feedback current (e.g., Figure 2 during a certain time interval (e.g., o ) in the switching cycle (e.g., Figure 7 the switching cycle T s ) of the power converter based on the output voltage (e.g., Figure 7 the first time interval Δt1 inFigure 3 the feedback current I in CSEN ). For example, the time interval is in the range of 5% to 45% of the switching period, thereby reducing power consumption compared to a conventional power converter in which the feedback current flows continuously throughout the switching period. In an embodiment, the feedback sensing circuit discharges a first capacitor (e.g., Figure 4 the first capacitor 406 in

[0100] At S820, the feedback sensing circuit generates a digital sensing signal (e.g., Figure 4 the digital sensing signal D in Δt ) indicating the duration of the time interval. In an embodiment, the digital sensing signal indicates a time interval that varies with the magnitude of the feedback current.

[0101] At S830, the feedback signal generator determines the magnitude of the feedback current flowing during the time interval based on the value of the digital sensing signal. In an embodiment, when the magnitude of the feedback current I CSEN increases, the first time interval Δt decreases, and vice versa.

[0102] At S840, the feedback signal generator generates a digital feedback signal (e.g., Figure 3 the digital feedback signal D in FB ) based on the determined magnitude of the feedback current. In an embodiment, when the magnitude of the feedback current increases, the feedback signal generator decreases the value of the digital feedback signal.

[0103] At 850, the PWM controller regulates the output voltage of the power converter in response to the digital feedback signal. In an embodiment, the power converter controls the duty cycle, the operating frequency, or both, to regulate its output voltage. For example, the DAC of the PWM controller generates a feedback voltage that decreases by a specific amount corresponding to the decreased value of the digital feedback signal. When the output voltage of the power converter (e.g., Figure 2 the output voltage V in o ) becomes greater than a predetermined level, the value of the feedback voltage decreases. The decreased value of the feedback voltage causes the on-time duration of the switching device (e.g., Figure 3 the switching device 342 in Figure 7 ) to be shorter than the immediately preceding on-time duration (e.g.,

[0104] A1. Embodiments of the present disclosure include a controller comprising:

[0105] A feedback sensing circuit configured to generate a feedback current during a first time interval of a switching period of a power converter based on an output voltage of the power converter, and to generate a digital sensing signal indicative of a duration of the first time interval; and

[0106] A feedback signal generator configured to determine an amplitude of the feedback current flowing during the first time interval based on a value of the digital sensing signal, and to generate a digital feedback signal based on the determined amplitude of the feedback current,

[0107] wherein a controller regulates the output voltage of the power converter in response to the digital feedback signal.

[0108] A2. The controller according to A1, wherein the first time interval varies with the amplitude of the feedback current,

[0109] wherein the feedback sensing circuit includes:

[0110] A first capacitor configured to regulate a level of a feedback sensing voltage using the feedback current during the first time interval; and

[0111] A second capacitor configured to regulate a level of a first reference voltage using a reference current during the first time interval, and

[0112] wherein the controller further includes:

[0113] A current source configured to generate the reference current;

[0114] A node through which the feedback current flows during the first time interval;

[0115] A first switch configured to couple a first end of the first capacitor to the node in response to a first switch signal; and

[0116] A second switch configured to couple a first end of the second capacitor to the current source in response to a second switch signal.

[0117] A3. The controller according to A2, further including:

[0118] A third switch configured to couple a first end of the first capacitor to a second reference voltage in response to a third switch signal;

[0119] A fourth switch configured to couple a first end of the second capacitor to a second end of the second capacitor in response to a fourth switch signal; and

[0120] A switch control circuit, which is configured to generate a first switch signal, a second switch signal, a third switch signal, and a fourth switch signal in response to a comparison result between the level of a feedback sense voltage and the level of a first reference voltage.

[0121] A4. The controller according to A3, wherein the switch control circuit generates a first switch signal and a second switch signal each having a first logic value and a third switch signal and a fourth switch signal each having a second logic value during a first time interval of a switching period, and

[0122] wherein the switch control circuit generates a first switch signal and a second switch signal each having a second logic value and a third switch signal and a fourth switch signal each having a first logic value during a second time interval of the switching period.

[0123] A5. The controller according to A1, wherein the first time interval varies with the amplitude of the feedback current,

[0124] wherein the feedback sense circuit includes:

[0125] a first capacitor, which is configured to use the feedback current to regulate the level of the feedback sense voltage during the first time interval; and

[0126] a second capacitor, which is configured to use a reference current to regulate the level of the first reference voltage during the first time interval,

[0127] wherein the controller further includes:

[0128] a comparator, which is configured to compare the level of the feedback sense voltage and the level of the first reference voltage, and generate an output signal indicating the comparison result; and

[0129] a counter, which is configured to generate a digital sense signal in response to the output signal.

[0130] A6. The controller according to A1, wherein the first time interval varies with the amplitude of the feedback current, and

[0131] wherein when the value of the digital sense signal decreases, the feedback signal generator decreases the value of the digital feedback signal.

[0132] A7. The controller according to A6, wherein the feedback signal generator includes:

[0133] a divider, which divides a first constant by the value of the digital sense signal;

[0134] a subtractor, which subtracts the divided value and the amplitude of the reference current from the amplitude of the digital feedback current;

[0135] A multiplier that multiplies the value to be subtracted by a second constant; and

[0136] An adder that adds the multiplied value to a previous value of a digital feedback signal to generate a current value of the digital feedback signal.

[0137] A8. The controller according to A1, further comprising:

[0138] A digital-to-analog converter configured to convert the digital feedback signal into a feedback voltage;

[0139] and

[0140] A comparator configured to compare the feedback voltage and a sensed voltage and generate an output signal indicating the comparison result to control the operation of a switching device coupled to a sensing resistor, the sensed voltage being a voltage across the sensing resistor.

[0141] B1. Embodiments of the present disclosure include a power converter comprising:

[0142] A first side that includes a controller; and

[0143] A second side that includes an output capacitor configured to provide an output voltage,

[0144] wherein the controller comprises:

[0145] A feedback sensing circuit configured to generate a feedback current based on the output voltage during a certain time interval in a switching cycle and generate a digital sensing signal indicating the duration of the time interval; and

[0146] A feedback signal generator configured to determine the magnitude of the feedback current flowing during the time interval based on the value of the digital sensing signal and generate a digital feedback signal based on the determined magnitude of the feedback current, the controller adjusting the output voltage in response to the digital feedback signal.

[0147] B2. The power converter according to B1, further comprising an optocoupler configured to convert an electrical signal indicating the output voltage into light and adjust the magnitude of the feedback current in response to the light.

[0148] B3. The power converter according to B1, wherein the time interval is in the range of 5% to 45% of the switching cycle.

[0149] Aspects of the present disclosure have been described in connection with specific embodiments presented as examples. Various substitutions, modifications, and variations can be made to the embodiments described herein without departing from the scope of the claims set forth below. Accordingly, the embodiments described herein are intended to be illustrative and not restrictive.

Claims

1. A controller, comprising: A feedback sensing circuit configured to generate a feedback current based on an output voltage of a power converter during a first time interval in a switching cycle of the power converter and to generate a digital sensing signal indicative of a duration of the first time interval; and A feedback signal generator configured to determine an amplitude of the feedback current flowing during the first time interval based on a value of the digital sensing signal and to generate a digital feedback signal based on the determined amplitude of the feedback current, wherein the controller adjusts the output voltage of the power converter in response to the digital feedback signal, and wherein the first time interval varies with the amplitude of the feedback current.

2. The controller according to claim 1, wherein the first time interval is in the range of 5% to 45% of the switching period.

3. The controller according to claim 1, wherein the feedback sensing circuit comprises: A first capacitor configured to regulate a level of a feedback sensing voltage using the feedback current during the first time interval; and A second capacitor configured to regulate a level of a first reference voltage using a reference current during the first time interval.

4. The controller according to claim 3, wherein each of the first capacitor and the second capacitor has a capacitance value in the range from 10 pF to 20 pF.

5. A method for controlling a power converter, the method comprising: Generate a feedback current based on an output voltage of the power converter during a certain time interval in a switching cycle; Generate a digital sensing signal indicative of a duration of the time interval; Determine an amplitude of the feedback current flowing during the time interval based on a value of the digital sensing signal; Change the time interval with the amplitude of the feedback current; Generate a digital feedback signal based on the determined amplitude of the feedback current; and Adjust the output voltage of the power converter in response to the digital feedback signal.

6. The method according to claim 5, wherein the time interval is in the range of 5% to 45% of the switching period.

7. The method according to claim 5, wherein generating the digital sensing signal comprises: Regulate a level of a feedback sensing voltage using the feedback current during the time interval; Regulate a level of a reference voltage using a reference current during the time interval; Compare the level of the feedback sensing voltage with the level of the reference voltage to generate an output signal indicative of a result of the comparison; and Generate the digital sensing signal in response to the output signal.

8. A power converter, comprising: A first side including a controller; and A second side including an output capacitor configured to provide an output voltage, wherein the controller includes: A feedback sensing circuit configured to generate a feedback current based on the output voltage during a certain time interval in a switching cycle and to generate a digital sensing signal indicative of a duration of the time interval; and A feedback signal generator configured to determine an amplitude of the feedback current flowing during the time interval based on a value of the digital sensing signal and to generate a digital feedback signal based on the determined amplitude of the feedback current, the controller adjusting the output voltage in response to the digital feedback signal, wherein the time interval varies with the amplitude of the feedback current.

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