Error detection and correction

Abstract

Embodiments of the present disclosure relate to error detection and correction. A method tests at least three devices, each device including a test chain having multiple locations for storing test data. The test includes: comparing the test data in the last location of the test chain of each device in the device, and shifting the test data in the test chain of each device in the device, and storing the result of the comparison in the first location of the test chain of each device in the device. The comparison and the shifting and storing are repeated until all stored test data have been compared. At least three devices can have the same functionality and the same structure.

Description

Technical Field

[0001] The present disclosure generally relates to error detection and correction in electronic devices, and more particularly to a method for error detection and correction by comparing electronic devices. The present disclosure also relates to a device capable of implementing such an error detection and correction method in an electronic device. Background Art

[0002] In electronic devices, the use of electronic devices such as processors, microprocessors, integrated systems, memories, etc. is increasingly subject to performance and reliability constraints. In order to comply with certain standards and / or quality approvals, such devices are often coupled with error detection and / or correction devices. More specifically, operating errors may occur during the execution of one of these devices and interfere with the operation of these devices and / or the overall operation of the electronic system including these devices.

[0003] Several types of errors or faults can occur in electronic devices. As an example, certain errors (SPF (Single Point Failure)) directly lead to the violation of a safety goal. This safety goal is usually a safety goal based on a specification, such as the ISO26262 specification for safety systems. These errors are easy to identify by observation of the device and / or system. Other errors, so-called latent errors (LFM (Latent Fault Metric)), do not lead to a fault immediately, but may lead to a fault, for example later or when they merge with other errors. Such errors are more difficult to detect and therefore more difficult to correct, because simple observation of the operation of the device or system is usually not enough. Summary of the invention

[0004] Embodiments facilitate overcoming all or part of the disadvantages of known error detection and correction methods and devices implementing such methods.

[0005] In an embodiment, a method comprises: testing at least three devices, each device comprising a test chain, the test chain having a plurality of locations for storing test data, the testing comprising: comparing the test data in the last location of the test chain of each device in the device; shifting the test data in the test chain of each device in the device, and storing the result of the comparison in the first location of the test chain of each device in the device; and repeating the comparison and the shifting and storing until all the stored test data are compared. In an embodiment, each test data is stored in a test point. In an embodiment, the test point is a register or a flip-flop. In an embodiment, the test data is a binary word. In an embodiment, the test data is a binary word that is all of the same size. In an embodiment, the test data is a binary word of different sizes. In an embodiment, the devices each comprise a plurality of test chains. In an embodiment, the method comprises: testing more than three devices. In an embodiment, at least three devices have the same structure and the same function. In an embodiment, the result of the comparison is a value stored in the last location of the test chain of two or more devices of the at least three devices before the shift.

[0006] In an embodiment, the apparatus comprises: a comparator; and a control circuit arrangement coupled to the comparator, wherein the control circuit arrangement in operation controls testing of at least three electronic circuits, each electronic circuit comprising a test chain, the test chain having a plurality of locations for storing test data, the testing comprising: comparing the test data in the last location of the test chain of each of the electronic circuits; and shifting the test data in the test chain of each of the electronic circuits, and storing the result of the comparison in the first location of the test chain of each of the electronic circuits, wherein the comparison and the shifting and storing are repeated until all stored test data have been compared. In an embodiment, the control circuit arrangement comprises at least three feedback loops, each feedback loop coupling an output of the comparator and an input of the test chain of one of the three electronic circuits. In an embodiment, each feedback loop comprises a multiplexer.

[0007] In an embodiment, a system includes: at least three electronic devices, each of which includes a test chain, the test chain having multiple locations for storing test data, and a test circuit device, which tests at least three electronic devices in operation, the test including: comparing the test data in the last location of the test chain of each of the at least three electronic devices; and shifting the test data in the test chain of each of the at least three electronic devices, and storing the result of the comparison in the first location of the test chain of each of the devices, wherein the comparison and the shifting and storing are repeated until all the stored test data are compared. In an embodiment, each test data is stored in a test point of the test chain. In an embodiment, the test point is a register or a flip-flop. In an embodiment, the test data is a binary word. In an embodiment, the test data is a binary word of all the same size. In an embodiment, the test data is a binary word of different sizes. In an embodiment, the electronic devices each include multiple test chains. In an embodiment, at least three electronic devices have the same structure and the same functionality. In an embodiment, the test circuit device includes a comparator and multiple feedback loops, which couple one or more outputs of the comparator to the input of the test chain. In an embodiment, the result of the comparison is the value stored in the last position of the test chain of two or more devices of the at least three devices before the shift.

[0008] An embodiment provides an error detection and correction method, which includes comparing at least three functionally identical devices, each device including at least one test data chain, the method including the following steps: (a) comparing the test data in the last position in the chain of the at least three devices; (b) shifting other test data forward one position in their chain; (c) writing the result of the comparison step in the first position in the chain, repeating steps (a), (b) and (c) until all test data in the chain have been compared.

[0009] According to an embodiment, each test data is stored in a test point.

[0010] According to an embodiment, the test points are registers or flip-flops.

[0011] According to an embodiment, the test data are binary words.

[0012] According to an embodiment, the test data are binary words all of the same size.

[0013] According to an embodiment, the test data are binary words of different sizes.

[0014] According to an embodiment, the devices each comprise at least two test data chains.

[0015] According to an embodiment, the method is a method of comparing more than three identical electronic devices.

[0016] Another embodiment provides a comparison device suitable for executing the above method.

[0017] According to an embodiment, the device is a device for comparing at least three identical electronic devices, each electronic device includes at least one test data chain, the device includes a comparator circuit and at least three feedback loops, each feedback loop couples the output of the comparator circuit and the input of one of the test chains.

[0018] According to an embodiment, each feedback loop couples an output of a comparator circuit and an input of one of the chains via a multiplexer.

[0019] Another embodiment provides an electronic system, the electronic system comprising: at least three identical electronic devices, each electronic device comprising at least one test data chain, the electronic system comprising: the above-mentioned comparison device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 An electronic device is schematically shown in block form;

[0022] Figure 2 The diagram is very schematically shown in the form of a box. Figure 1 Embodiments of an error detection and correction device in an electronic device of the type of device; and

[0023] Figure 3 It's a picture. Figure 2 A flowchart of an example of the operation of an embodiment. DETAILED DESCRIPTION

[0024] In different figures, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, size and material properties.

[0025] For clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail.

[0026] Throughout this disclosure, the term “connected” is used to specify a direct electrical connection between circuit elements without intermediate elements other than conductors, while the term “coupled” is used to specify an electrical connection between circuit elements that may be direct or may be via one or more intermediate elements.

[0027] In the following description, when reference is made to terms that modify absolute positions (such as the terms "front", "back", "upper", "lower", "left", "right"), terms that modify relative positions (such as the terms "above", "below", "upper", "lower"), or terms that modify directions (such as the terms "horizontal", "vertical"), unless otherwise specified, it refers to the orientation of the figure.

[0028] The terms "about," "substantially," and "approximately" are used herein to designate a tolerance of plus or minus 10% or plus or minus 5% of the value under consideration.

[0029] Figure 1 The electronic device 100 is schematically shown in the form of a block. For example, the electronic device 100 is a processor, a microprocessor, an integrated system, a control unit, a memory, etc.

[0030] The electronic device 100 includes a plurality of test points 101. Each test point 101 stores functional data used during the execution of the device and call test data in the test phase. For example, the test points 101 are arranged in the device 100 according to their design, and are each associated with one or more circuits, units or components of the device 100. The test data stored in the test point 101 is data that provides an indication of the state of one or more components related to the test point 101 associated therewith. As an example, the test point 101 is a register or one or more flip-flops. For example, the test data is a binary word encoded by N bits. As an example, N is in the range of 1 bit to 64 bits, for example, equal to 1. As an example, the test points all include binary words of the same size. According to another example, some test points 101 include binary words of different sizes. In another example, the test point 101 may include a binary word or signature (MISR (multiple input signature register)) reflecting the state of the memory.

[0031] The test points 101 are organized into one or more test chains 103. Each test chain 103 includes an input node 103IN and an output node 103OUT.

[0032] The device 100 may include as many test points as possible, organized into as many test chains as possible. The test chains 103 may all have the same number of test points 101, but as a variant, may have a different number of test points 101. As an example, Figure 1 The device 100 shown comprises, for example, thirty-three test points 101 , which are organized into three test chains 103 , each of which comprises eleven test points 101 .

[0033] The error (or fault) detection or test phase of the device 100 generally includes reading and comparing all test data stored in the test points. Therefore, the number of test points 101 included in the test chain 103 can affect the duration of the test phase. More specifically, the more test points 101 the test chain 103 includes, the longer the test phase is. Organizing the test points 101 into test chains 103 can shorten this time period by enabling parallel reading of multiple test points 101.

[0034] The apparatus and method for error detection and correction in the apparatus 100 will be related to Figure 2 and Figure 3 Give a description.

[0035] Figure 2 A device 200 for error detection and correction by comparison is schematically shown in block form, or a comparison of Figure 1 Embodiments of devices of the type of device 100 are described as three devices 100A, 100B and 100C. The devices 100A, 100B and 100C may be identical, for example their structures are identical, but also have implemented the same operation and should be characterized by the same test data.

[0036] According to an embodiment, each device 100A (correspondingly 100B, 100C) includes a test chain 103A (correspondingly 103B, 103C), and each test chain includes a test point 101A (correspondingly 101B, 101C). Each test chain 103A (correspondingly 103B, 103C) includes an input 103INA (correspondingly 103INB, 103INC) and an output 103OUTA (correspondingly 103OUTB, 103OUTC). The devices 100A, 100B, and 100C have the same structure, and each includes the same test chain 103A, 103B, 103C.

[0037] exist Figure 2 In the case shown, each device 100A, 100B and 100C comprises two test chains 103A, 103B, 103C, each test chain comprising seven test points 101A, 101B, 101C. The devices 100A, 100B and 100C comprise two similar groups of test chains 103A, 103B, 103C.

[0038] The comparison device 200 comprises a comparator circuit 201 (COMP) comprising as many inputs 201N as the total number of test chains of the devices 100A, 100B and 100C and as many outputs 201OUT as there are test chains in the devices 100A, 100B and 100C. The comparator circuit 201 is capable of receiving as input the outputs 103OUTA, 103OUTB and 103OUTC of all the test chains 103A, 103B and 103C of the devices 100A, 100B and 100C and is capable of outputting as many signals as there are groups of similar test chains 103A, 103B, 103C. Figure 2 In the case shown, the comparator circuit 201 comprises six inputs 201N and two outputs 201OUT.

[0039] The comparison device 200 further comprises as many feedback loops 203 as there are test chains in the device 100A, 100B or 100C. Each feedback loop 203 couples the output 201OUT of the comparator circuit 201 to the input 103INA, 103INB, 103INC of the test chain 103A, 103B, 103C. Further, each feedback loop 203 couples the output 201OUT to the input 103INA (respectively 103INB, 103INC) via, for example, a multiplexer 210A (respectively 210B, 210C). Each multiplexer 210A, 210B, 210C comprises at least two inputs, one coupled to one of the feedback loops 203 and the other receiving the signal SCAN-IN, and comprises at least one output coupled to the input 103INA, 103INB, 103INC of the test chain 103A, 103B, 103C. Each feedback loop 203 is also coupled to all inputs 103INA, 103INB, 103INC of similar test chains 103A, 103B, 103C of the devices 100A, 100B, 100C via multiplexers 210A, 210B, 210C. These multiplexers 210A, 210B and 210C are used to distinguish data from the feedback loop 203 during the test phase and other data used during the test phase using a different test protocol than the present embodiment. As shown, the comparison device 200 includes a control circuit device 230, which in operation controls the multiplexers 210A, 210B and 210C, generates error and reset signals, etc. (such as those referred to herein). Figure 3 discussed).

[0040] About Figure 3 The operation of device 200 is described.

[0041] Figure 3 It's a picture. Figure 2Flowchart 300 of an example of operation of device 200.

[0042] At step 301 (PUSH), all test data contained on the test points 101A, 101B, 101C are shifted towards the next test point 101A, 101B, 101C in their respective test chains 103A, 103B, 103C. The test data stored in the last test point 101A, 101B, 101C of all test chains 103A, 103B, 103C are sent to the input 201IN of the comparator circuit 201.

[0043] At step 302 (COMPDATA3), the comparator circuit 201 compares the data it has received with other data. More specifically, the comparator circuit 201 compares the data from the devices 100A, 100B, 100C originating from similar test chains 103A, 103B, 103C with each other. In other words, the comparator circuit 201 compares three data that should be identical to each other.

[0044] At step 303 (ERR?), the comparator circuit 201 detects whether the data it compares is different from the other two data among three data in a set of similar test chains 103A, 103B, 103C.

[0045] If the three data are the same (output No), the next step is step 301. Then, the comparator circuit 201 compares the next test data of the test chains 103A, 103B, 103C.

[0046] If one of the three data (so-called data A) is different from the other two data (so-called data B and C) (output yes), the next step is step 304 (COMPDATA2). The device 100A is then considered to be faulty and is no longer used during the test phase.

[0047] At step 304 , data B and data C are compared by the comparator circuit 201 .

[0048] At step 305 (error?), the comparator circuit 201 detects whether the data B and C are the same or different.

[0049] If the data B and C are different from each other (output YES), this means that the three data A, B, and C of the devices 100A, 100B, 100C are different from each other. In this case, the next step is step 306 (system failure).

[0050] At step 306, device 200, for example, enters a default mode, and devices 100A, 100B, and 100C, for example, cease operation. As an example, an error report may be established based on data A, B, and C, and the error report may be communicated to a central processing unit or a user of devices 100A, 100B, and 100C.

[0051] If data B and C are identical (output No), the next step is optional step 307 (corrupted?) or step 309 (restore).

[0052] At optional step 307, for example, the comparator circuit 201 determines whether one of the devices 100A, 100B, 100C is defective or damaged based on the data A, B, and C. For example, if the test points of the devices 100A, 100B, and 100C are not formed by flip-flops, as an example, when the device is a DRAM (dynamic random access memory) or an SRAM (static random access memory), the optional step 307 is added.

[0053] If one or more devices 100A, 100B, 100C are considered defective or damaged (output is), the next step is step 310 (restart), in which, for example, the device(s) involved are reset. In fact, the test data can be a binary word (or signature) reporting that one of the devices 100A, 100B and 100C has failed.

[0054] If the device 100A, 100B, 100C is not considered defective (output No), the next step is step 309 .

[0055] At step 309, the comparator circuit 201 outputs output data S equal to the same data B and C. The output data S is considered to be correct data, and the data A of the last test point 101A will be replaced with the correct data. The data S is sent by the appropriate feedback loop 203 and is written into the first test points 101A, 101B, and 101C of the test chains 103A, 103B, and 103C from which the data A, B, and C originate. Then, the incorrect test data A is corrected. The step following step 309 is step 311, which is the same as the above-mentioned step 301. More precisely, in step 311, all the test data contained on the test points 101A, 101B, and 101C are shifted to the next test points 101A, 101B, and 101C in their corresponding test chains 103A, 103B, and 103C. Step 311 is followed by the above-mentioned step 304. In fact, device 100A is considered to be faulty and only the test data of devices 100B and 100C are compared. This comparison method is repeated until all test data of all test chains 103B and 103C are compared and until all test data of all test chains 103A are corrected.

[0056] about Figure 2 and Figure 3 The described method of error detection and correction and the device implementing the method have the advantage that, independently of their operation, they can be applied to Figure 1 Any device of the type described as device 100 .

[0057] Figure 2 and Figure 3 Another advantage of the method and apparatus is that they can facilitate detection of different types of errors. More specifically, they can facilitate detection of errors without observing the operation of the devices 100A, 100B, or 100C or the general operation of the system to which they belong. The detection device 200 can also facilitate detection of errors that have a direct impact on operation (SPF (Single Point Failure)) and errors that have no direct impact on the operation of the devices 100A, 100B, and 100C (LFM (Latent Fault Metric)).

[0058] Another advantage is that embodiments of the comparison device 200 do not require the implementation of a memory storing all test data of the test chains 103A, 103B, 103C of the devices 100A, 100B, 100C in order to compare them.

[0059] Another advantage of the embodiment of the comparison device 200 is that it is easy to use in a system including Figure 1 The type of device 100 described is implemented in a system of electronic devices because it includes a single comparison circuit, a feedback loop, and a multiplexer.

[0060] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the error detection and correction device 200 may be adapted to compare three or more Figure 1 A device of the type of device 100 is described.

[0061] Finally, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art based on the functional indications given above.

[0062] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided, the computer readable medium including one or more computer programs suitable for performing the methods of the functions described herein. The medium may be a physical storage medium such as, for example, a read-only memory (ROM) chip, or a disk such as a multi-use disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, or a portable media article to be read by an appropriate drive or an appropriate connection, including portable media articles encoded in one or more bar codes or other related encodings stored on one or more such computer readable media and readable by an appropriate reader device.

[0063] In some embodiments, some or all of the methods and / or functionality may be implemented or provided in other ways, such as at least partially in firmware and / or hardware, including but not limited to one or more application specific integrated circuits (ASICs), digital signal processors, discrete circuit systems, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology and various combinations thereof.

[0064] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0065] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited to the present disclosure.

Claims

1. A method for error detection and correction, comprising: Testing at least three devices, each device including a test chain having a plurality of locations for storing test data, the testing comprising: Use the following steps to detect the error: comparing test data in a last position of the test chain for each of the at least three devices; and shifting test data in the test chain of each of the at least three devices; Correcting errors by storing a result of the comparison in a first location of the test chain for each of the at least three devices; and The comparison and the shifting and storing are repeated until all the stored test data have been compared.

2. The method according to claim 1, comprising: Store multiple test data in test points. The method according to claim 2 , wherein the test point is a register or a flip-flop. The method of claim 2 , wherein the test data comprises binary words. The method of claim 1 , wherein the test data comprises binary words, each of the binary words having the same size. The method of claim 1 , wherein the test data comprises binary words of different sizes. The method of claim 1 , wherein the at least three devices each include a plurality of test chains.

8. The method according to claim 1, comprising: Test more than three devices.

9. The method according to claim 1, wherein the at least three devices have the same structure and the same function.

10. The method of claim 1, wherein the result of the comparison is obtained based on a value stored in a last position of a test chain of two or more devices of the at least three devices before shifting.

11. A device for error detection and correction, the device comprising: Comparator; as well as control circuitry coupled to the comparator, wherein the control circuitry is operable to control error detection and error correction of at least three electronic circuits, each electronic circuit comprising a test chain having a plurality of locations for storing test data, the error detection and error correction comprising: comparing test data in a last position of the test chain for each of the at least three electronic circuits; as well as The test data in the test chain of each of the at least three electronic circuits are shifted and a result of the comparison is stored in a first position of the test chain of each of the at least three electronic circuits, wherein the comparison and the shifting and storing are repeated until all the stored test data have been compared.

12. The apparatus of claim 11, wherein the control circuitry comprises at least three feedback loops, each feedback loop coupling an output of the comparator and an input of the test chain of one of the at least three electronic circuits.

13. The apparatus of claim 12, wherein each feedback loop comprises a multiplexer.

14. A system for error detection and correction, the system comprising: at least three electronic devices, each electronic device including a test chain having a plurality of locations for storing test data; as well as A test circuit arrangement coupled to the at least three electronic devices, wherein the test circuit arrangement is operable to detect and correct errors of the at least three electronic devices, the detection and correction comprising: comparing test data in a last position of the test chain for each of the at least three electronic devices; as well as Shifting the test data in the test chain of each of the at least three electronic devices, and storing the result of the comparison in a first position of the test chain of each of the at least three electronic devices, wherein the comparison and the shifting and storing are repeated until all the stored test data have been compared.

15. The system of claim 14, wherein the test chain includes a test point, the test point being operable to store test data. The system of claim 15 , wherein the test point is a register or a flip-flop.

17. The system of claim 14, wherein the test data comprises binary words.

18. The system of claim 14, wherein the test data comprises binary words, each binary word having the same size.

19. The system of claim 14, wherein the test data comprises binary words of different sizes.

20. The system of claim 14, wherein the at least three electronic devices each include a plurality of test chains.

21. The system of claim 14, wherein the at least three electronic devices have the same structure and the same functionality.

22. The system of claim 14, wherein the test circuitry comprises a comparator and a plurality of feedback loops coupling one or more outputs of the comparator to inputs of the test chain.

23. The system of claim 14, wherein the result of the comparison is obtained based on a value stored in a last position of a test chain of two or more of the at least three electronic devices before the shifting.

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