Write assist circuit

Abstract

The present disclosure relates to a write assist circuit, which describes an embodiment of the write assist circuit. The write assist circuit includes a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit may include a transistor and a second output terminal electrically connected to the first output terminal. The transistor may include a first source / drain terminal, a second source / drain terminal, and a gate terminal. The first source / drain terminal may be electrically coupled to the second output terminal. The second source / drain terminal may be electrically connected to a voltage source. The gate terminal may be electrically connected to a ground voltage source.

Description

Technical Field

[0001] The present disclosure relates to a write assist circuit, in particular to a write assist circuit having a voltage boost circuit and a regulating circuit. Background Art

[0002] Static random access memory (SRAM) is a type of semiconductor memory used in computing applications that require high-speed data access. For example, cache applications use SRAM to store frequently accessed data, such as data accessed by a central processing unit.

[0003] The cell structure and architecture of SRAM can achieve high-speed data access. The SRAM cell includes a bi-stable flip-flop structure, which includes four to six transistors. The SRAM architecture may include one or more memory cell arrays and support circuitry. Each SRAM array is arranged in rows and columns, respectively referred to as "word lines" and "bit lines". The support circuitry includes address and driver circuits to access each SRAM cell through word lines and bit lines for various SRAM operations. Summary of the invention

[0004] The present disclosure provides a write assist circuit. The write assist circuit includes a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit includes a transistor and a second output terminal electrically connected to the first output terminal. The transistor includes a first source / drain terminal, a second source / drain terminal, and a gate terminal. The first source / drain terminal is electrically coupled to the second output terminal. The second source / drain terminal is electrically connected to a voltage source. The gate terminal is electrically connected to a ground voltage source.

[0005] The present disclosure provides a memory device. The memory device includes a memory cell array, a write driver circuit configured to provide a reference voltage, and a write assist circuit configured to couple the reference voltage from the write driver circuit to a first negative voltage. The write assist circuit includes a boost circuit configured to provide a second negative voltage lower than the first negative voltage, and an adjustment circuit configured to couple the second negative voltage to the first negative voltage. The adjustment circuit includes a transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal is electrically connected to a first voltage source. The first source / drain terminal is electrically connected to a second voltage source. The second source / drain terminal is electrically connected to the boost circuit and couples the second negative voltage to the first negative voltage.

[0006] The present disclosure provides a memory write operation method. The memory write operation method includes receiving memory address information related to a memory write operation of one or more memory cells; providing a reference voltage to one or more bit lines coupled to the memory cells; using a boost circuit to couple the reference voltage to a first negative voltage; and using one or more pull-up transistors to couple the reference voltage to a second negative voltage higher than the first negative voltage based on the memory address information. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The concepts of the present disclosure can be better understood from the following examples and the accompanying drawings. It should be noted that the schematic diagrams are examples and that different features are not illustrated here. The sizes of different features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A static random access memory with write assist circuitry is shown in accordance with some embodiments.

[0009] Figure 2 A static random access memory topology is shown according to some embodiments.

[0010] Figure 3 A write assist circuit, a column multiplexer, and a write driver circuit for a static random access memory are shown according to some embodiments.

[0011] Figure 4 Signal waveforms for a write assist circuit according to some embodiments are shown.

[0012] Figure 5 A trim module for a write assist circuit is shown according to some embodiments.

[0013] Figure 6 A static random access memory with an auxiliary bitline topology is shown in accordance with some embodiments.

[0014] Fig. 7A A static random access memory with trimming circuitry is shown in accordance with some embodiments.

[0015] Figure 7B A trim circuit, a column multiplexer, and a static random access memory are shown according to some embodiments.

[0016] Figure 8 A method for a memory write operation according to some embodiments is shown.

[0017] Fig. 9 A method of performing a memory write operation through a static random access memory having an auxiliary bitline topology according to some embodiments is shown.

[0018] Description of reference numerals:

[0019] 100: Static random access memory

[0020] 110: Write auxiliary circuit

[0021] 135: Line decoder

[0022] 130: word line driver

[0023] 140: Column decoder

[0024] 150: Column Multiplexer

[0025] 160: Write drive circuit

[0026] 180: Static Random Access Memory Array

[0027] 1700-170 N :List

[0028] 190,190 00 -190 MN : Memory unit

[0029] 162,164: Level shift device

[0030] 118: Reference voltage

[0031] 122: Boost circuit

[0032] 123: Output

[0033] 120: Adjustment circuit

[0034] 121: Output

[0035] 116: Negative bit line enable signal

[0036] 220,230: N-channel metal oxide semiconductor transfer gate transistor

[0037] 240,250: N-channel metal oxide semiconductor pull-down transistor

[0038] 260,270: P-channel metal oxide semiconductor pull-up transistor

[0039] 210: Bit line parasitic mode

[0040] 212,2120-212 M :Resistor element

[0041] 214,2141-214 M :Capacitor element

[0042] 318: Boost circuit

[0043] 320: Adjustment circuit

[0044] 340: Control circuit

[0045] 360: Voltage generator

[0046] 380: Pull-down transistor

[0047] 312: Memory address signal

[0048] 322: Transfer Gate Transistor

[0049] 326: Voltage Components

[0050] 321,323,325: endpoints

[0051] N1, N2: nodes

[0052] 520: Adjustment circuit

[0053] 580: Transistor Library

[0054] 524: Multiplexer

[0055] 5700-570 S : Transistor column

[0056] 522,522 00 ~522 RS :transistor

[0057] 526,526 00 ~526 RS :Voltage element

[0058] 5111~511 S : Input terminal

[0059] 525: Select signal

[0060] 513: Input

[0061] 600: Static Random Access Memory

[0062] 640: Column Decoder

[0063] 650: Column Multiplexer

[0064] 680: Static Random Access Memory Array

[0065] 6700~670 N :List

[0066] 612: Auxiliary bit line enable signal

[0067] 700: Static Random Access Memory

[0068] 720: Adjustment circuit

[0069] 724: Multiplexer

[0070] 721: Output

[0071] 800: Methods

[0072] 810-840: Operation

[0073] 900: Methods

[0074] 910-940: Operation DETAILED DESCRIPTION

[0075] The present disclosure provides many different embodiments or examples to implement different features of the present disclosure. The following disclosure describes specific embodiments of various components and their arrangements to simplify the description. These specific examples are not intended to be limiting. In addition, the following different embodiments of the present disclosure may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity (unless otherwise indicated) and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0076] Spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, are used to facilitate describing the relationship of one element or feature to another element or feature in a diagram. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. In addition, the device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0077] In some embodiments, the terms "about" and "approximately" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value).

[0078] As used herein, the term "logic low" refers to a voltage level corresponding to a binary content of a logic zero (e.g., bit '0') in an integrated circuit or static random access memory (SRAM). In some embodiments, logic low may refer to a voltage level approximately at ground level (e.g., approximately 0V) or a negative power supply voltage (e.g., -0.4V, -0.6V, -0.7V, -1.0V, -1.2V, -1.8V, -2.4V, -3.3V, -5V, or a combination thereof).

[0079] As used herein, the term "logic high" refers to a voltage level corresponding to a binary content of a logic one (e.g., bit '1') in an integrated circuit or static random access memory (SRAM). In some embodiments, logic high may refer to a voltage level of approximately a positive power supply voltage or a negative power supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or a combination thereof).

[0080] Static random access memory (SRAM) can be used in integrated circuits (ICs) for high-speed communications, imaging processing, and system-on-chip (SOC) applications. The SRAM may include a plurality of SRAM cells, each of which may include a pair of cross-coupled inverters and a transmission gate transistor, through which binary content (e.g., a bit) may be read from or written to the SRAM cell. During a write operation for a selected SRAM cell, one of the output nodes of the cross-coupled inverters of the selected SRAM cell may be initially charged (e.g., to an ON state or a logic high value), while the corresponding transmission gate transistor attempts to discharge the output node through a bit line or a complementary bit line. In order to enhance the corresponding transfer gate transistor (e.g., increase the gate-to-source voltage (VGS) of the transfer gate transistor), a negative voltage may be applied to the bit line or complementary bit line to facilitate the discharge process (also referred to herein as a negative bitline (NBL) scheme). On the other hand, due to temperature fluctuations or process variations of the IC, the threshold voltage of the transfer gate transistor in the SRAM cell may be different from the threshold voltage of another transfer gate transistor in other SRAM cells of the same IC. Such a threshold voltage fluctuation of the transfer gate transistor may inadvertently cause the binary content of the unselected SRAM cells to change during the NBL scheme. This inadvertent change of the binary content of the unselected SRAM cells is referred to herein as a "dummy write issue" and may cause erroneous operation of the IC.

[0081] The present disclosure is directed to a method and circuit structure for adjusting a negative bit line voltage to resolve a virtual write problem. In some embodiments, an SRAM may include a plurality of SRAM cells and a write assist circuit (e.g., an NBL scheme) configured to provide a reference voltage to the SRAM cells. In some embodiments, the write assist circuit may include a boost circuit configured to provide a first negative voltage (e.g., -200 mV) to a bit line of the SRAM, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage (e.g., -100 mV). The adjustment circuit may be configured to adjust the NBL scheme by increasing the bit line voltage from a first negative voltage (e.g., -200 mV) to a second negative voltage (e.g., -100 mV). The second negative voltage may be higher than the first negative voltage and may be provided to the SRAM bit line as a reference voltage. In some embodiments, the adjustment circuit may include a bias compensation transistor, wherein the threshold voltage of the bias compensation transistor may be substantially equal to the threshold voltage of each transmission gate transistor of the SRAM cell. In some embodiments, the gate of the bias compensation transistor may be electrically connected to a ground level (e.g., approximately 0V), the source of the bias compensation transistor may be electrically connected to a ground level or a logic high voltage source, and the drain of the bias compensation transistor may be electrically coupled to a boost circuit and provide a second negative voltage. The advantage of the present disclosure is that the dummy write problem during a write operation is effectively resolved by reducing the voltage difference between the gate of the pass gate transistor of the unselected SRAM cell and the bit line / complementary bit line, thereby reducing the leakage current flowing through the pass gate transistor and preventing the binary content stored in the unselected SRAM cell from being changed.

[0082] The present disclosure describes various aspects of static random access memory (SRAM). Specifically, the present disclosure describes different embodiments related to SRAM memory write operations. For ease of explanation, certain SRAM circuit elements and control logic are disclosed to facilitate the description of different embodiments. SRAM may include other circuit elements and control logic. These other circuit elements and control logic are within the spirit and scope of the present disclosure.

[0083] Figure 11 is a schematic diagram of a static random access memory (SRAM) 100 having a write assist circuit 110 configured to provide a negative bit line (NBL) voltage (also referred to as an NBL scheme) according to some embodiments. The SRAM 100 may include a row decoder 135, a word line driver 130, a column decoder 140, a column multiplexer (MUX) 150, a write driver circuit 160, and an SRAM array 180. The SRAM array 180 may include columns 1700 to 1700 of SRAM cells. N In some embodiments, Figure 1 As shown, the write assist circuit 110, the column MUX 150, and the write driver circuit 160 can be located immediately below the SRAM array 180. For illustrative purposes, logic lows and logic highs associated with the SRAM 100 will be described individually in the context of a ground level (e.g., approximately 0 V) ​​and a positive voltage level (e.g., approximately 0.5 V). Other voltage levels for logic lows and logic highs are within the scope of the present disclosure.

[0084] Each SRAM cell in the SRAM array 180 may be accessed (for memory read operations and memory write operations) using a memory address. Based on the memory address, the row decoder 135 may select a row of memory cells to be accessed by the word line driver 130. Also, according to some embodiments, based on the memory address, the column decoder 140 may select columns 1700 to 1701 of SRAM cells (memory cells). N The write driver circuit 160 may generate columns 1700 to 1701 for SRAM cells. N The symbol “BL” refers to a bit line, and the symbol “BLB” refers to the complement of “BL” (also referred to herein as a complementary bit line). The intersection of an accessed row and an accessed column of memory cells can result in access to a single memory cell 190.

[0085] The columns 1700 to 170 of the SRAM cells N Each of the SRAM arrays 180 may include a plurality of memory cells 190. The memory cells 190 may be arranged in one or more arrays in the SRAM 100. In the present disclosure, a single SRAM array 180 is shown to simplify the description of the disclosed embodiments. The SRAM array 180 has "M" rows and "N" columns. The symbol "190 00 ” refers to the memory cell 190 located in row '0', column 1700. Similarly, the symbol “190 MN ” refers to the position at row 'M', column 170 N Memory cell 190 in.

[0086] In some embodiments, Figure 1 As shown, the write driver circuit 160 may include level shift devices 162 and 164, which may each receive a reference voltage 118. According to some embodiments, the reference voltage 118 may be a ground level (e.g., 0V), a negative voltage (e.g., -100mV, -200mV, or -300mV), or a combination thereof. In some embodiments, in the case of receiving a logic low input by the level shift device 162 or 164, the corresponding level shift device may output a logic high value. Conversely, in the case of receiving a logic high input by the level shift device 162 or 164, the corresponding level shift device may output the reference voltage 118.

[0087] In some embodiments, Figure 1 As shown, the write assist circuit 110 may be configured to provide a reference voltage 118. The write assist circuit 110 may include a boost circuit 122 configured to provide a first voltage at an output terminal 123, and an adjustment circuit 120 configured to couple the first voltage to a second voltage (higher than or equal to the first voltage) at an output terminal 121. Both the first voltage and the second voltage may be equal to or lower than a logic low. In some embodiments, the reference voltage 118 may be substantially equal to the first voltage at the output terminal 123. In some embodiments, the reference voltage 118 may be substantially equal to the second voltage at the output terminal 121. In some embodiments, the reference voltage 118 may be pulled up from the first voltage provided by the boost circuit 122 to the second voltage provided by the adjustment circuit 120. In some embodiments, the reference voltage 118 may be between the first voltage provided by the boost circuit 122 and the second voltage provided by the adjustment circuit 120. In some embodiments, as Figure 1 As shown, the output terminals 121 and 123 can be electrically connected to each other and provide the reference voltage 118. In some embodiments, the reference voltage 118 can be initialized to a ground level by the boost circuit 122.

[0088] The boost circuit 122 may receive a negative bit line (NBL) enable signal 116 to determine a first voltage at the output terminal 123. For example, in response to the NBL enable signal 116 being '1' or logic high, the first voltage provided by the boost circuit 122 at the output terminal 123 may be a negative voltage (e.g., -100 mV, -200 mV, or -300 mV) below the ground level. The adjustment circuit 120 may increase the first voltage from the boost circuit 122 to provide a second voltage ranging from the first voltage to the ground level at the output terminal 121. For example, the first voltage provided by the boost circuit 122 at the output terminal 123 may be -200 mV, and the adjustment circuit 120 may increase the first voltage (-200 mV) to provide a second voltage of -130 mV at the output terminal 121. Therefore, the adjustment circuit 120 may be a compensation circuit for adjusting the reference voltage 118. In some embodiments, the second voltage at the output terminal 121 may be in a range from the first voltage to about a logic low (e.g., from -200 mV to about 0 V). In some embodiments, the NBL enable signal 116 is '0' or logic low, and the first voltage at the output terminal 123 may be about a ground level. In some embodiments, in response to the first voltage at the output terminal 123 being about a ground level, the adjustment circuit 120 may provide a second voltage at about a ground level at the output terminal 121; therefore, the reference voltage 118 may be about a ground level.

[0089] Figure 2 Two memory cells 190 in column 1700 of SRAM 100 are shown in accordance with some embodiments. 00 and 190 M0 Unless otherwise stated, Figure 1 and Figure 2 The discussion of elements having the same symbols in FIG. 1 applies to each other. Figure 2 As shown, the memory unit 190 00 can represent an addressed (eg, selected) SRAM cell, and the memory cell 190 M0 190 may represent an unselected SRAM cell. The memory cell 190 may have different circuit topologies. For example, each memory cell 190 00 and 190 M0A "6T" circuit topology may be provided. The 6T circuit topology may include N-channel metal-oxide-semiconductor (NMOS) transfer gate transistors 220 and 230, NMOS pull-down transistors 240 and 250, and P-channel metal-oxide-semiconductor (PMOS) pull-up transistors 260 and 270. A voltage from the word line driver 130 may be coupled to the gate terminal of each of the NMOS transfer gate transistors 220 and 230. This may allow the NMOS transfer gate transistors 220 and 230 to transfer a voltage from the bit line pair BL / BLB to a bistable flip-flop structure formed by the NMOS pull-down transistors 240 and 250 and the PMOS pull-up transistors 260 and 270. The bit line pair BL / BLB voltage may be used during a memory write operation. For example, if bit line BL is at '1' or logic high, and complementary bit line BLB is at '0' or logic low, the voltage applied by word line driver 130 to the gates of NMOS pass-gate transistors 220 and 230 may be at sufficient voltage levels to transfer the logic high value of bit line BL and the logic low value of complementary bit line BLB to the flip-flop structure. As a result, these logic values ​​are written (or programmed) into the flip-flop structure.

[0090] In reference Figure 2 2 , for illustrative purposes, a bit line parasitic model 210 for bit line BL is described. Complementary bit line BLB may have a similar bit line parasitic model. M and capacitor elements 2141 to 214 M A network of resistors 212 (e.g., capacitors, capacitor circuits, or combinations thereof) may represent a bit line parasitic model 210. Each resistor element 212 may represent a bit line path resistance between two SRAM cells along a column of memory cells. Each capacitor element 214 may represent a parasitic capacitance associated with a pass gate in each SRAM cell along a column of memory cells (e.g., a parasitic capacitance associated with an NMOS pass gate transistor 220 in memory cell 190).

[0091] During a memory write operation, an addressed SRAM cell that is farther away from the write driver circuit (e.g. Figure 2 Memory cell 190 in 00 ) can receive a bit line voltage that is different from its expected voltage level. This can be due to in-place changes in the write driver circuitry (e.g. Figure 1The voltage difference is caused by the voltage at the output of the write driver circuit 160 and the voltage at the bit line location associated with the addressed SRAM cell. This voltage difference is attributable to the bit line path resistance between the write driver circuit and the addressed SRAM cell.

[0092] Reference Figure 2 , resistor element 2120 to 210 M The resistance of the bit line path can be modeled. If the write driver circuit 160 outputs 0V on the bit line BL, due to the resistance across the resistor elements 2120 to 212 M Due to the "IR" (current × resistance) voltage drop, the voltage at the addressed memory cell 190 can be greater than 0V. This voltage drop can cause an unexpected increase in voltage at the bit line location associated with the addressed SRAM cell. This unexpected increase in voltage (e.g., a voltage greater than 0V) may degrade the memory write operation of the SRAM cell because the bistable flip-flop structure of the SRAM cell may not be able to track its voltage level to the expected voltage (i.e., the write circuit output voltage). In other words, the unexpected voltage increase prevents the SRAM cell from changing state. Advanced process technology further exacerbates the impact of this IR voltage drop because as advanced process technology reduces the physical size of the bit line, the bit line parasitic resistance increases. As a result, having write assist circuits (e.g.: Figure 1 It would be beneficial to provide an intentional negative voltage on the bit line BL or the complementary bit line BLB to compensate for the accidental increase in voltage (NBL scheme).

[0093] On the other hand, due to process fluctuations or high temperatures of the SRAM 100, the threshold voltage associated with each of the NMOS pass gate transistors 220 and 230 in each memory cell 190 may deviate from its designed value. Based on the target setting of the threshold voltage or the temperature of the operating environment of the SRAM 100, such undesirable threshold voltage deviation may exceed the designed amplitude range of the NBL scheme. For example, during a write operation using the NBL scheme, the voltage boost circuit 122 (shown in FIG. 1 ) may be used to increase the threshold voltage of the NMOS pass gate transistor 220 and 230 in the memory cell 190. Figure 1 ) may be -200 mV or less. If the threshold voltage fluctuation of the gate terminals of the NMOS pass-gate transistors 220 and 230 is greater than about 130 mV, the unselected SRAM cells (e.g.: Figure 2 Memory cells (SRAM cells) in 190 M0) may accidentally open to transfer the logic state of BL and / or BLB to its flip-flop structure, thereby causing write operation errors (e.g., virtual write problems). In some embodiments, the threshold voltage fluctuation may be in the range of from about 130 mV to about 270 mV to cause virtual write operations. Therefore, having a write assist circuit (e.g., Figure 1 It would be beneficial to use a write assist circuit 110 as shown to track and adjust the negative voltage range provided by the NBL scheme to compensate for the phantom write problem.

[0094] Figure 3 The write assist circuit 110, the column MUX 150, the write driver circuit 160, and the unselected memory cell (SRAM cell) 190 are shown in accordance with some embodiments. M0 Unless otherwise stated, Figure 1 and Figure 3 The discussion of elements with the same symbols in FIG. 1 is applicable to each other. The write assist circuit 110 may include a boost circuit 318 and an adjustment circuit 320. Unless otherwise stated, the discussion of the boost circuit 122 and the adjustment circuit 120 may apply to the boost circuit 318 and the adjustment circuit 320, respectively. Although Figure 3 Display a memory cell 190 M0 1 is an unselected SRAM cell, but other SRAM cells in the SRAM 100 (including addressed (selected) SRAM cells and / or unselected SRAM cells) may also be included in Figure 3 scope and discussion.

[0095] The boost circuit 318 may include a voltage generator 360, a pull-down transistor 380, and a control circuit 340 configured to control the voltage generator 360 and the pull-down transistor 380. During a memory write operation, based on the memory address signal 312 and the NBL enable signal 116, the control circuit 340 may couple a reference voltage (e.g., the reference voltage 118 provided to the write driver circuit 160) to a first negative voltage through the voltage generator 360 and / or the pull-down transistor 380. For example, according to some embodiments, the memory address signal 312 may indicate a location of a memory cell 190 in the SRAM array 180 that is subject to a memory write operation. In response to the NBL enable signal 116 being '1' or logic high, the control circuit 340 may trigger the voltage generator 360 based on the memory address signal 312 to provide a first voltage (e.g., a negative voltage, such as -100mV, -200mV, and -300mV) at the output terminal 123. As previously described, Figure 1 and Figure 2 As described above, the first voltage provided by the voltage generator 360 may be an embodiment of the NBL scheme to compensate for the SRAM cell (eg: Figure 2 In some embodiments, in response to NBL enable signal 116 being '0' or logic low, control circuit 340 may deactivate voltage generator 360 and activate pull-down transistor 380 to provide a ground level at output terminal 123 (e.g., reference voltage 118 may be approximately 0V).

[0096] Adjustment circuit 320 may include a transfer gate transistor 322 and a voltage element 326, where transfer gate transistor 322 is configured to compensate (e.g., pull up) the negative voltage provided by boost circuit 318, and voltage element 326 is connected to transfer gate transistor 322. Transfer gate transistor 322 may have a threshold voltage substantially equal to the threshold voltage of NMOS transfer gate transistor 220 / 230 in any memory cell 190, and may have terminals 321, 323, and 325. Terminal 323 of transfer gate transistor 322 may be a gate terminal of transfer gate transistor 322 and may be electrically connected to (and electrically wired to) a ground level or a logic low. Terminals 321 and 325 of transfer gate transistor 322 may interchangeably be a drain terminal and a source terminal of transfer gate transistor 322. As shown in FIG. Figure 3 As shown, a terminal 321 (e.g., a drain terminal) of the transmission gate transistor 322 may be electrically coupled to the output terminal 121 of the adjustment circuit 320, and a terminal 325 (e.g., a source terminal) of the transmission gate transistor 322 may be electrically connected to (and electrically wired to) a voltage element 326. The voltage element 326 may be a ground in the SRAM 100. In some embodiments, the voltage element 326 may be a power supply voltage source that provides a logic low level, a logic high level, or a voltage level between the logic low level and the logic high level.

[0097] The pass-gate transistor 322 may have a voltage-passing capability similar to that of the pass-gate transistor of any unselected memory cell 190, where the voltage-passing capability is determined by the difference between the gate-to-source voltage and the threshold voltage (V GS -V t ). For example, refer to Figure 3 , the pass gate transistor 322 may have a M0 The NMOS pass gate transistor 220 is substantially the same (V GS -V t ). This is because the transfer gate transistor 322 and the unselected memory cell 190 M0The NMOS pass-gate transistors 220 of the unselected memory cell 190 may both have similar threshold voltages, have substantially the same bias voltage (e.g., ground level) at their gate terminals, and have substantially the same bias voltage (e.g., reference voltage 118 may be transferred from terminal 121 to bit line BL via level shift device 162) at their drain terminals. Therefore, the pass-gate transistor 322 and the unselected memory cell 190 M0 The NMOS pass-gate transistor 220 can both isolate or transmit the voltage between its source terminal and drain terminal. For example, in response to the reference voltage 118 being at a negative voltage level (eg, below -200 mV), the unselected memory cell 190 M0 The NMOS pass gate transistor 220 is associated with (V GS -V t ) can be partially activated to form undesirable electrical conduction between the bit line BL and the node N1. However, the approximately equal (V GS -V t ) value can be associated with the transmission gate transistor 322 to form substantially the same electrical conduction between the terminals 321 and 325. Since the voltage element 326 can at least provide a voltage level equal to or higher than the ground level, the reference voltage 118 can be positively pulled up by the voltage element 326 to have a smaller negative value (for example, the reference voltage 118 can be pulled up from -200mV to -100mV). This can therefore reduce the transmission gate transistor 322 and the unselected memory cell 190 M0 The NMOS pass gate transistor 220 has both (V GS -V t ), thus ensuring that the unselected memory cell 190 M0 The NMOS pass-gate transistor 220 is turned off, thereby maintaining the binary contents stored at the node N1.

[0098] Figure 4 is a schematic diagram of signal waveforms for write assist circuit 110 during a write operation using an NBL scheme according to some embodiments. By way of example and not limitation, Figure 4 The NBL enable signal 116 is shown, and the unselected memory cells 190 (eg: Figure 3 The unselected memory cell 190 is shown M0 ) of nodes N1 and N2 (both in Figure 3 ), and signal waveforms of reference voltage 118 at output terminals 121 and 123. These example waveforms assume that a '1' or logic high is associated with a positive voltage VDD, and a '0' or logic low is associated with a ground level (eg, approximately 0V) during a memory write operation.

[0099] From time 0 to time t1, NBL enable signal 116 is set to logic low '0', and nodes N1 and N2 may be at logic high and logic low, respectively. Also, with NBL enable signal 116 at logic low, reference voltage 118 provided by write assist circuit 110 may be at ground level.

[0100] At time t1, the NBL enable signal 116 changes from logic low to logic high, thereby activating the write assist circuit 110 to set the reference voltage 118 to a negative value (e.g., -100 mV, -200 mV, or -300 mV). Such a negative reference voltage 118 can be transferred to the bit line BL (e.g., Figure 3 as shown) and coupled to unselected memory cell 190.

[0101] In some embodiments, the write assist circuit 110 does not include the adjustment circuit 120, wherein the reference voltage 118 is provided by a boost circuit 122 (eg, Figure 1 In response to the reference voltage 118 being negative (eg, below -200 mV), the NMOS pass-gate transistor 220 (eg, Figure 3 ) may be partially turned on to form an electrical conduction path between its drain terminal and source terminal. This promotes the discharge process to change the binary content of node N1 from '1' to '0' before the end of the write operation (e.g., before time t2). As the binary content of node N1 is erroneously changed, node N2 is also individually erroneously changed from '0' to '1'.

[0102] In some embodiments, the write assist circuit 110 may include an adjustment circuit 120, wherein the reference voltage 118 may be provided by a boost circuit 122 and the adjustment circuit 120 (both of which are provided in Figure 1 As previously mentioned in Figure 1 and Figure 3 As described in (e.g., adjustment circuit 320, embodiments of adjustment circuit 120), adjustment circuit 120 can compensate for and adjust (e.g., pull up) the negative voltage provided by boost circuit 122. This can set reference voltage 118 to a smaller negative value (e.g., -100 mV). As a result, the gate-to-source voltage (V GS ) to reduce the electrical conduction between its drain terminal and source terminal. This can limit the discharge / charge process affecting the binary content stored in nodes N1 and N2, thereby avoiding write errors (phantom write problem) on unselected memory cells 190.

[0103] At time t2, NBL enable signal 116 transitions from logic high to logic low. This may disable write assist circuit 110 to set reference voltage 118 to ground level. In response, unselected memory cells 190 are not subject to phantom write issues; i.e., the binary content stored in unselected memory cells 190 after time t2 may be the same as the binary content before time t1.

[0104] Figure 5 5 shows an adjustment circuit 520 according to some embodiments. Unless otherwise stated, Figures 1 to 3 and Figure 5 5. Discussions of elements with the same symbols in FIG. 5 apply to each other. Unless otherwise noted, discussions of adjustment circuits 120 and 320 can all be applied to adjustment circuit 520. Adjustment circuit 520 may include a transistor bank 580 and a MUX 524 connected to transistor bank 580. Transistor bank 580 may include a plurality of transistor columns 5700 to 570 S , where "S" represents the number of transistor columns in transistor bank 580. In some embodiments, the number S can be 1, 2, 4, or any other number. Transistor columns 5700 to 570 S Each of the transistors 522 may include a plurality of transistors 522 and a voltage element 526 connected to the individual transistors 522. Unless otherwise noted, the discussion of transistors 322 and voltage element 326 may apply to transistors 522 and voltage element 526, respectively. The symbol "522 RS ” refers to the transistors in row “R” and column 570 S Similarly, the symbol "526 RS ” refers to the transistors in row “R” and column 570 S In some embodiments, transistor columns 5700 to 570 S Each of may have a different number (R) of transistors 522 / voltage elements 526 from each other. In some embodiments, the number R may be 64, 128, 256, or any other number.

[0105] Each transistor column 5700 to 570 S The transistors 522 in the embodiment may have threshold voltages substantially equal to each other, and each of the transistor columns 5700 to 570 S The transistors 522 between the transistor columns 5700 may have different threshold voltages from each other. For example, each transistor 522 in the transistor column 5700 00 To 522 R0 may have a threshold voltage of about 0.3 V, and each transistor 522 in transistor column 5701 01 To 522 R1The transistor arrays 5700 to 570 may have a threshold voltage of about 0.5 V. S At least one of the associated threshold voltages may be substantially equal to a threshold voltage of one or more NMOS pass-gate transistors 220 and 230 in memory cell 190 .

[0106] like Figure 5 As shown, each transistor column 5700 to 570 S Each transistor 522 in the transistor array 5700 to 5701 may have a gate terminal electrically connected to a ground level or a logic low. S Each transistor 522 in the embodiment may have input terminals 5111 to 5112 that are interchangeably connected to the voltage element 526 and the MUX 524. S Each transistor column 5700 to 570 S It can be considered as a plurality of adjustment circuits 320 connected in parallel. When the compensation is performed by the boost circuit 120 (such as Figure 1 and Figure 3 When a negative voltage is provided by the transistors 5700 to 5701 (as shown in FIG. 5 ), such parallel connection can enhance the driving capability to charge / discharge the bit line BL / complementary bit line BLB. MUX 524 can select transistor columns 5700 to 5701 based on the selection signal 525. S and connect the source terminal or the drain terminal of the respective transistor 522 to the output terminal 121 of the adjustment circuit 520 .

[0107] In some embodiments, the MUX 524 may further include an input terminal 513 that connects a high impedance (High Z) (e.g., open circuit) to the input terminal 513 based on a selection signal 525. In response to the high impedance on the input terminal 513 selected by the MUX 524, the adjustment circuit 520 may be disabled to stop compensating for the negative voltage provided by the boost circuit 120. In this way, the NBL voltage provided by the write assist circuit 110 is provided by the boost circuit 120.

[0108] Figure 6 FIG. 6 shows an SRAM 600 with an auxiliary bit line topology according to some embodiments. Unless otherwise stated, Figure 1 and Figure 6 The discussion of elements with the same symbols in FIG. 1 is applicable to each other. Unless otherwise stated, the discussion of SRAM 100 can be applied to SRAM 600. SRAM 600 may include row decoder 135, word line driver 130, column decoder 640, column multiplexer (MUX) 650, write driver circuit 160, write assist circuit 110, and SRAM array 680. In some embodiments, as shown in FIG. Figure 6As shown, the write assist circuit 110 , the column MUX 650 , and the write driver circuit 160 may be located immediately below the SRAM array 680 .

[0109] The SRAM array 680 may include columns 6700 to 6700 of memory cells. N . Columns 6700 to 670 N Each of the columns 6700 to 670 may include memory cell 190. In some embodiments, columns 6700 to 670 N Each of the SRAM arrays 680 may also include a bit line pair BL / BLB (also referred to herein as a “first group of bit lines”) and an auxiliary bit line pair FBL / FBLB (also referred to herein as a “second group of bit lines”). The bit line pair BL / BLB may be used to access the memory cells 190 at the lower portion of the SRAM array 680, and the auxiliary bit line pair FBL / FBLB may be used to access the memory cells 190 at the upper portion of the SRAM array 680. For example, for an SRAM array 680 having 1024 rows, in columns 6700 to 6701, the bit line pairs BL / BLB and FBL / FBLB may be used to access the memory cells 190 at the upper portion of the SRAM array 680. N In each of the SRAM array 680, the bit line pair BL / BLB can be coupled to the NMOS pass gate transistors for the memory cells 190 in the '0' row to the '511' row. The auxiliary bit line pair FBL / FBLB can be coupled to the NMOS pass gate transistors for the memory cells 190 in the '512' row to the '1024' row. By implementing an alternative bit line path to the memory cells 190 in the upper portion of the SRAM array 680 through the auxiliary bit line pair FBL / FBLB, the total parasitic resistance and capacitance associated with the non-accessed memory cells 190 can be reduced, thereby reducing the IR voltage drop and RC time delay to the accessed memory cells 190 in the upper portion of the SRAM array 680.

[0110] According to some embodiments, the column decoder 640 may be used to select a bit line pair BL / BLB or an auxiliary bit line pair FBL / FBLB based on the location of the memory cell 190 in the SRAM array 680 that is subject to a memory write operation. In some embodiments, the column decoder 640 may receive an auxiliary bit line (FBL) enable signal 612, which may indicate whether the memory cell 190 is in the upper portion of the SRAM array 680 (e.g., memory cells in rows '512' to '1024'). In some embodiments, if the FBL enable signal 612 is '1' or logic high, a corresponding YSEL '[N:0] signal may be selected to activate a corresponding y-select transistor in the column MUX 650 to access the corresponding auxiliary bit line pair FBL / FBLB. Conversely, if the FBL enable signal 612 is '0' or logic low, a corresponding YSEL [N:0] signal may be selected to activate a corresponding y-select transistor in the column MUX 650 to access the corresponding bit line pair BL / BLB.

[0111] In SRAM 600, write assist circuit 110 can compensate for the IR voltage drop in the bit line. For the addressed SRAM cells, especially those cells far from the write driver circuit (e.g. Figure 6 Memory cell 190 in 0N ), the write assist circuit 110 can "pull" the voltage level at the bit line location associated with the addressed SRAM cell to make it closer to the expected voltage level. For example, if there is a 200mV bit line IR voltage drop between the write driver circuit 160 and the output of the addressed SRAM cell, the reference voltage output from the write driver circuit 160 can be adjusted to: (i) -300mV, so the bit line voltage at the addressed SRAM cell can be close to or at -100mV; (ii) -400mV, so the bit line voltage at the addressed SRAM cell can be close to or at -200mV; (iii) -500mV, so the bit line voltage at the addressed SRAM cell can be close to or at -300mV; (iv) or any other negative voltage to obtain the desired voltage level on the addressed SRAM cell.

[0112] In addition to compensating for the IR voltage drop in the bit line, the write assist circuit 110 can also provide negative voltage adjustments for different parts of the SRAM array to reduce power consumption. For example, for the SRAM cells in the lower part of the SRAM array (e.g.: Figure 1In some embodiments, the SRAM array may be divided into more than two portions, each of which may receive a different negative voltage based on the row position of the memory cell undergoing the memory write operation. Further adjusting the negative voltage based on the memory row position may further optimize the power consumption.

[0113] In addition, the write assist circuit 110 can also compensate for process variations in SRAM cell transistors. Figure 2 Memory cell 190 in 00 , process variations can cause PMOS pull-up transistors 260 and 270 to be stronger than NMOS pass-gate transistors 220 and 230. This process variation can cause problems during memory write operations because the PMOS pull-up transistors prevent the NMOS pass-gate transistors from pulling internal nodes (e.g., any internal nodes between the PMOS pull-up transistors and the NMOS pull-down transistors) from the supply voltage V DD The write assist circuit 110 can provide a negative voltage to the write driver circuit 160 to facilitate pulling the internal node to ground (e.g., 0V) to compensate for the weaker NMOS pass gate transistor.

[0114] Fig. 7A An SRAM 700 having a trimming circuit 720 is shown in accordance with some embodiments. Unless otherwise noted, the discussion of the SRAM 100 may apply to the SRAM 700. Unless otherwise noted, the discussion of the trimming circuit 520 may apply to the trimming circuit 720. Furthermore, unless otherwise noted, Figure 1 , Figure 2 , Figure 5 as well as Fig. 7A The discussion of elements having the same symbols is applicable to each other.

[0115] The SRAM 700 may include an SRAM array 180, a row decoder 135, a word line driver 130, a column decoder 140, a column MUX 150, a write driver circuit 160, a boost circuit 120, and a plurality of pairs of adjustment circuits 720. The boost circuit 122 may be configured to provide a reference voltage 118 to the write driver circuit 160 to generate a bit voltage on the bit line pair BL / BLB. Fig. 7A As shown, the columns 1700 to 170 of SRAM cells N Each of the columns 1700 to 1704 of SRAM cells may include one adjustment circuit 720 connected to the bit line BL and another adjustment circuit 720 connected to the complementary bit line BLB. Thus, a pair of adjustment circuits 720 may be configured to individually compensate (e.g., pull up) the bit line voltages on the bit line BL and the complementary bit line BLB to avoid the previously discussed phantom write problem. In some embodiments, the columns 1700 to 1704 of SRAM cells may include one adjustment circuit 720 connected to the bit line BL and another adjustment circuit 720 connected to the complementary bit line BLB. N Each of the SRAM arrays 180 may include multiple pairs of adjustment circuits 720, wherein each pair of adjustment circuits 720 may be located in a different portion of each column of the SRAM cells. For example, for an SRAM array 180 having 1024 rows, in columns 1700 to 170 N In each of the first pair of adjustment circuits 720, the first pair of adjustment circuits 720 may be placed adjacent to row 511, and the second pair of adjustment circuits 720 may be placed adjacent to row 1023. The first pair of adjustment circuits 720 and the second pair of adjustment circuits 720 may be configured to prevent dummy write issues in SRAM cells 190 in rows '0' to '511' and rows '512' to '1024', respectively.

[0116] Figure 7B A pair of adjustment circuits 720 are shown in accordance with some embodiments, connected to the bit line pair BL / BLB associated with the column 1700 of SRAM cells. Figure 1 , Figure 2 , Figure 5 as well as Figure 7B The discussion of elements with the same symbols in FIG. 7 is applicable to each other. The adjustment circuit 720 may include one or more transistor columns 5700 to 570 S ( Figure 7B Only one transistor column 5700 is shown) and the transistors connected to the transistor columns 5700 to 570 S Unless otherwise noted, the discussion of MUX 524 can apply to MUX 724. MUX 724 can select transistor columns 5700 to 570 based on selection signal 525. S and connect the source terminal or drain terminal of the individual transistor 522 to the output terminal 721 of the adjustment circuit 720. Figure 7BAs shown, the MUX 724 of one adjustment circuit 720 can connect its output terminal 721 to the bit line BL, and the MUX 724 of another adjustment circuit 720 can connect its output terminal 721 to the complementary bit line BLB. Figure 7B The illustrated pair of trim circuits 720 may be configured to avoid phantom write problems in the column 1700 of SRAM cells.

[0117] Figure 8 A method 800 for performing memory write operations on SRAM 100 according to some embodiments is shown. The operations shown in method 800 may be performed by Figure 1 and Figure 3 The write assist circuit 110 of the method 800 may be executed. Other operations in the method 800 may be executed. In addition, the operations of the method 800 may be executed in a different order and / or variation.

[0118] In operation 810, memory address information associated with a memory write operation for one or more memory cells is received. In some embodiments, the memory address information may include a row location of an SRAM cell subject to the memory write operation. Figure 1 , the column decoder 140 can receive memory address information.

[0119] In operation 820, a reference voltage is provided to one or more bit lines coupled to one or more memory cells. In some embodiments, the reference voltage may be provided by Figure 3 A pull-down transistor 380 is provided which can initialize the reference voltage to a ground level before coupling the reference voltage to a negative voltage (as discussed below in operations 830 and 840).

[0120] In operation 830, based on the memory address information, a reference voltage is coupled to a first negative voltage through a voltage boosting circuit. Figure 3 and Figure 4 When the NBL enable signal 116 changes from '0' to '1' (eg, from logic low to logic high), the reference voltage 118 may be coupled to a first negative voltage (eg, the reference voltage 118 without using the adjustment circuit 120, such as Figure 4 In some embodiments, the reference voltage 118 can be coupled to the first negative voltage after the pull-down transistor 380 is disabled.

[0121] In operation 840, the reference voltage is coupled to a second negative voltage higher than the first negative voltage by the adjustment circuit. Figure 3, the reference voltage 118 can be pulled up from the first negative voltage to the second negative voltage by the adjustment circuit 320 by grounding the gate terminal of the transistor 322, biasing the source terminal of the transistor 322 with a ground level or a positive voltage source, and pulling up the first negative voltage through the drain terminal of the transistor 322 to form a second negative voltage to provide a reference voltage. In some embodiments, the reference voltage 118 can be pulled up by the second negative voltage based on the selection signal 525, and the selection signal 525 selects the transistor columns 5700 to 570 of the adjustment circuit 520 that can receive the first negative voltage and can adjust the first negative voltage to the second negative voltage. S In some embodiments, the reference voltage may be substantially equal to the second negative voltage. In some embodiments, the reference voltage may be between the first negative voltage and the second negative voltage. In some embodiments, the reference voltage may be determined based on the memory address information. In some embodiments, operations 830 and 840 may be performed simultaneously.

[0122] Fig. 9 A method 900 for performing memory write operations on SRAM 600 according to some embodiments is shown. The operations shown in method 900 may be performed by Figure 6 The write assist circuit 110 of the method 900 may be executed. Other operations in the method 900 may be executed. In addition, the operations of the method 900 may be executed in a different order and / or variation.

[0123] In operation 910, memory address information associated with a memory write operation for one or more memory cells in a memory cell array is received. In some embodiments, the memory address information may include a row location of an SRAM cell subject to the memory write operation. Figure 6 , the column decoder 640 may receive the memory address information and the FBL enable signal 612 .

[0124] In operation 920, a reference voltage is provided to a first set of bit lines coupled to a first set of memory cells in the SRAM array and a second set of bit lines coupled to a second memory cell in the SRAM array. In some embodiments, the reference voltage may be provided by a pull-down transistor 380 (e.g., Figure 3 As shown), the pull-down transistor 380 can initialize the reference voltage to a ground level before coupling the reference voltage to a negative voltage (as discussed below in operations 930 and 940).

[0125] In operation 930, based on the memory address information, a reference voltage is coupled to a first negative voltage provided to the first group of bit lines and the second group of bit lines through a boosting circuit. Figure 4 and Figure 6When the NBL enable signal 116 changes from '0' to '1' (eg, from logic low to logic high), the reference voltage 118 may be coupled to a first negative voltage (eg, the reference voltage 118 without using the adjustment circuit 120, such as Figure 4 In some embodiments, the reference voltage 118 can be coupled to the first negative voltage after the pull-down device is disabled.

[0126] In operation 940, the reference voltage is coupled to a second negative voltage higher than the first negative voltage by the adjustment circuit, wherein the second negative voltage can be provided to the second group of bit lines based on the memory address information and the FBL enable signal 612. Figure 5 , the reference voltage 118 can be pulled up to a second negative voltage by the adjustment circuit 320 by biasing the gate terminal of the transistor 522 with a ground level or a logic low, biasing the source terminal of the transistor 522 with a ground level or a positive voltage source, and pulling up the first negative voltage through the drain terminal of the transistor 522 based on the selection signal 525 to generate a second negative voltage to provide a reference voltage. Therefore, the reference voltage 118 can be pulled up from the first negative voltage to the second negative voltage based on the memory address information and the FBL enable signal 612, and further coupled to the bit line pair BL / BLB or the auxiliary bit line pair FBL / FBLB. In some embodiments, the reference voltage may be substantially equal to the second negative voltage. In some embodiments, the reference voltage may be between the first negative voltage and the second negative voltage. In some embodiments, the reference voltage may be determined based on the memory address information. In some embodiments, operations 930 and 940 may be performed simultaneously.

[0127] In some embodiments, operation 940 may further include coupling the reference voltage to a third negative voltage, wherein the third negative voltage may be provided to the first group of bit lines. The third negative voltage may be higher than the first negative voltage and may be different from the second negative voltage. For example, the reference voltage 118 may be coupled to the third negative voltage based on the selection signal 525 of the adjustment circuit 520. The third negative voltage may be coupled to the first group of bit lines based on the memory address information and the FBL enable signal 612.

[0128] Embodiments of the present disclosure include a write assist circuit having a boost circuit and an adjustment circuit. The boost circuit can provide a first negative voltage for the NBL scheme. The adjustment circuit can receive the first negative voltage from the boost circuit, adjust the first negative voltage to a second negative voltage higher than the first negative voltage, and output the second negative voltage to a bit line and / or a complementary bit line of the SRAM. The adjustment circuit may include one or more transistors, and the one or more transistors are configured to provide a second negative voltage at their drain terminals. In some embodiments, each of the one or more transistors may have a threshold voltage that is substantially equal to that of a transfer gate transistor of an SRAM cell in the SRAM. In some embodiments, each of the gate terminals of the one or more transistors may be biased with a ground level or a logic low. In this way, each of the one or more transistors may have a threshold voltage (V GS -V t ). In some embodiments, each of the source terminals of the one or more transistors can be biased with ground or a positive voltage source. Thus, when the first negative voltage provided by the boost circuit generates an undesirable (V GS -V t ), the first negative voltage can be increased to a second negative voltage by adjusting the circuit. The advantage of the disclosed embodiment is that the virtual write problem of SRAM is solved by using a transistor that can be cost-effectively and simultaneously manufactured with the transfer gate transistor of the SRAM cell, thereby avoiding operation errors of the IC.

[0129] In some embodiments, the write assist circuit may include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit may include a transistor and a second output terminal electrically connected to the first output terminal. The transistor may include a first source / drain terminal, a second source / drain terminal, and a gate terminal. The first source / drain terminal may be electrically coupled to the second output terminal. The second source / drain terminal may be electrically connected to a voltage source. The gate terminal may be electrically connected to a ground voltage source.

[0130] In some embodiments, the second source / drain terminal is electrically connected to a ground voltage source.

[0131] In some embodiments, the voltage source is configured to provide a positive voltage.

[0132] In some embodiments, the second output terminal is electrically connected to the first output terminal through a wire.

[0133] In some embodiments, the regulating circuit further includes a plurality of transistors, wherein a plurality of gate terminals of the transistors are electrically connected to a ground voltage source, and a plurality of source / drain terminals of the transistors are electrically connected to the second output terminal.

[0134] In some embodiments, the adjustment circuit further includes a multiplexer, wherein an input terminal of the multiplexer is electrically connected to the first source / drain terminal, and an output terminal of the multiplexer is electrically connected to the second output terminal.

[0135] In some embodiments, the regulating circuit further comprises another transistor, wherein: a gate terminal of the another transistor is electrically connected to a ground voltage source; and a source / drain terminal of the another transistor is electrically connected to the second output terminal.

[0136] In some embodiments, a memory device may include a memory cell array, a write driver circuit configured to provide a reference voltage, and a write assist circuit configured to couple the reference voltage from the write driver circuit to a first negative voltage. The write assist circuit may include a boost circuit configured to provide a second negative voltage lower than the first negative voltage, and an adjustment circuit configured to couple the second negative voltage to the first negative voltage. The adjustment circuit includes a transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal may be electrically connected to a first voltage source. The first source / drain terminal may be electrically connected to a second voltage source. The second source / drain terminal may be electrically connected to the boost circuit and couple the second negative voltage to the first negative voltage.

[0137] In some embodiments, each of the memory cells in the memory cell array includes a pass-gate transistor, wherein a threshold voltage of the pass-gate transistor is substantially equal to a threshold voltage of the transistor.

[0138] In some embodiments, the source / drain terminal is electrically connected to a first voltage source.

[0139] In some embodiments, the second voltage source is configured to output a logic high level.

[0140] In some embodiments, the regulating circuit further includes a multiplexer configured to electrically couple the second source / drain terminal to the boost circuit.

[0141] In some embodiments, the boost circuit is configured to output a second negative voltage at a first output terminal; the adjustment circuit is configured to output the first negative voltage at a second output terminal; and the first output terminal and the second output terminal are electrically connected to each other.

[0142] In some embodiments, the adjustment circuit also includes another transistor, wherein: the other transistor includes another gate terminal, another first source / drain terminal, and another second source / drain terminal; the other gate terminal is electrically connected to the first voltage source; the other first source / drain terminal is electrically connected to the second voltage source; and the other second source / drain terminal is electrically connected to the second source / drain terminal of the transistor.

[0143] In some embodiments, the adjustment circuit also includes another transistor, wherein: the other transistor includes another gate terminal, another first source / drain terminal, and another second source / drain terminal; the other gate terminal is electrically connected to the first voltage source; the other first source / drain terminal is electrically connected to the second voltage source; and the other second source / drain terminal is electrically connected to the boost circuit.

[0144] In some embodiments, the adjustment circuit further includes a multiplexer electrically connected to the second source / drain terminal of the transistor and another second source / drain terminal of another transistor.

[0145] In some embodiments, a memory write operation method may include receiving memory address information associated with a memory write operation for one or more memory cells, providing a reference voltage to one or more bit lines coupled to the memory cells, coupling the reference voltage to a first negative voltage using a boost circuit, and coupling the reference voltage to a second negative voltage higher than the first negative voltage using one or more pull-up transistors based on the memory address information.

[0146] In some embodiments, the step of providing a reference voltage includes initializing the reference voltage to a ground level using a pull-down transistor before coupling the reference voltage to the first negative voltage and the second negative voltage.

[0147] In some embodiments, coupling the reference voltage to the second negative voltage includes biasing a gate terminal of each of the pull-up transistors to a ground level.

[0148] In some embodiments, coupling the reference voltage to the second negative voltage includes biasing a source terminal of each of the pull-up transistors; and coupling a drain terminal of each of the pull-up transistors to a bit line having the second negative voltage using a multiplexer.

[0149] It should be understood that the "Detailed Description" section (and the Abstract of the Disclosure) is intended to be used to interpret the claims. The Abstract of the Disclosure may set forth one or more (but not all) possible embodiments contemplated by the inventor(s), and is therefore not intended to limit the claims in any way.

[0150] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A write assist circuit, comprising: A boost circuit configured to output a first negative voltage at a first output terminal; as well as an adjusting circuit configured to increase the first negative voltage at the first output terminal to a second negative voltage higher than the first negative voltage, wherein the adjusting circuit comprises: a transistor including a first source / drain terminal, a second source / drain terminal, and a gate terminal; and A second output terminal is electrically connected to the first output terminal, wherein: The first source / drain terminal is electrically coupled to the second output terminal; The second source / drain terminal is electrically connected to a voltage source; and The gate terminal is electrically connected to a ground voltage source.

2. The write assist circuit as claimed in claim 1, wherein the second source / drain terminal is electrically connected to the ground voltage source.

3. The write assist circuit of claim 1, wherein the voltage source is configured to provide a positive voltage.

4. The write assist circuit as claimed in claim 1, wherein the second output end is electrically connected to the first output end through a wire.

5. The write assist circuit as described in claim 1, wherein the adjustment circuit further includes a plurality of transistors, wherein a plurality of gate terminals of the plurality of transistors are electrically connected to the ground voltage source, and a source / drain terminal of each of the plurality of transistors is electrically connected to the second output terminal.

6. A write assist circuit as described in claim 1, wherein the adjustment circuit further includes a multiplexer, wherein an input terminal of the multiplexer is electrically connected to the first source / drain terminal, and an output terminal of the multiplexer is electrically connected to the second output terminal, so that the first source / drain terminal is electrically coupled to the second output terminal through the multiplexer.

7. The write assist circuit of claim 1, wherein the ground voltage source is configured to provide a fixed logic low level.

8. A memory device comprising: a memory cell array; a write driver circuit configured to provide a reference voltage, and A write assist circuit is configured to couple the reference voltage from the write driving circuit to a first negative voltage, wherein the write assist circuit comprises: a boost circuit configured to provide a second negative voltage lower than the first negative voltage; and an adjusting circuit configured to increase the second negative voltage to the first negative voltage, wherein: The adjustment circuit includes a transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal; The gate terminal is electrically connected to a first voltage source; The first source / drain terminal is electrically connected to a second voltage source; and The second source / drain terminal is electrically connected to the boost circuit.

9. The memory device of claim 8, wherein each of the memory cells in the memory cell array comprises a pass gate transistor, wherein a threshold voltage of the pass gate transistor is substantially equal to a threshold voltage of the transistor.

10. The memory device of claim 8, wherein the first voltage source is grounded.

11. The memory device of claim 8, wherein the second voltage source is configured to output a fixed logic high level.

12. The memory device of claim 8, wherein the regulating circuit further comprises a multiplexer configured to electrically couple the second source / drain terminal to the boosting circuit.

13. The memory device of claim 8, wherein: The write driver circuit is configured to output the reference voltage on a bit line of the memory cell array; The boost circuit is configured to couple the reference voltage to the second negative voltage at the bit line; and The adjustment circuit is configured to increase the second negative voltage to the first negative voltage at the bit line.

14. The memory device of claim 8, wherein the adjustment circuit further comprises another transistor, wherein: The another transistor comprises another gate terminal, another first source / drain terminal, and another second source / drain terminal; The other gate terminal is electrically connected to the first voltage source; The other first source / drain terminal is electrically connected to the second voltage source; and The other second source / drain terminal is electrically connected to the second source / drain terminal of the transistor.

15. The memory device as claimed in claim 8, wherein the adjustment circuit further comprises another transistor, wherein: The another transistor comprises another gate terminal, another first source / drain terminal, and another second source / drain terminal; The other gate terminal is electrically connected to the first voltage source; The other first source / drain terminal is electrically connected to the second voltage source; and The other second source / drain terminal is electrically connected to the boost circuit. 16 . The memory device of claim 15 , wherein the adjustment circuit further comprises a multiplexer electrically connected to the second source / drain terminal of the transistor and the other second source / drain terminal of the other transistor.

17. A memory write operation method, comprising: receiving a memory address information associated with a memory write operation for one or more memory cells; providing a reference voltage to one or more bit lines coupled to the memory cell; Using a boost circuit to couple the reference voltage to a first negative voltage at the one or more bit lines; as well as Using one or more pull-up transistors, the first negative voltage is increased to a second negative voltage higher than the first negative voltage at the one or more bit lines based on the memory address information.

18. The memory write operation method as claimed in claim 17, wherein the step of providing the reference voltage comprises initializing the reference voltage to a ground level using a pull-down transistor before coupling the reference voltage to the first negative voltage and increasing the first negative voltage to the second negative voltage.

19. The memory write operation method as claimed in claim 17, wherein the step of increasing the first negative voltage to the second negative voltage comprises biasing a gate terminal of each of the pull-up transistors to the static logic low level through a voltage source configured to output a static logic low level.

20. The memory writing operation method as claimed in claim 17, wherein the step of increasing the first negative voltage to the second negative voltage comprises: biasing a source terminal of each of the pull-up transistors; as well as A multiplexer is used to couple a drain terminal of each of the pull-up transistors to the bit line having the second negative voltage.

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