Gate structures in semiconductor devices

Abstract

The present disclosure relates to a gate structure in a semiconductor device. A method includes depositing a high-k gate dielectric layer above a semiconductor fin and along a sidewall of the semiconductor fin. The method also includes depositing an n-type work function metal layer above the high-k gate dielectric layer, and performing a passivation process on the high-k gate dielectric layer by the n-type work function metal layer. The passivation process includes a remote plasma process. The method includes depositing a fill metal above the n-type work function metal layer to form a metal gate stack above the high-k gate dielectric layer. The metal gate stack includes an n-type work function metal layer and a fill metal.

Description

Technical Field

[0001] The present disclosure generally relates to gate structures in semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: depositing a high-k gate dielectric layer above a semiconductor fin and along a sidewall of the semiconductor fin; depositing an n-type work function metal layer above the high-k gate dielectric layer; performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation treatment comprises a remote plasma process; and depositing a fill metal above the n-type work function metal layer to form a metal gate stack above the high-k gate dielectric layer, the metal gate stack comprising the n-type work function metal layer and the fill metal.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor fin extending above an isolation region in a semiconductor device; depositing a high-k gate dielectric layer above and along a sidewall of the semiconductor fin, the high-k gate dielectric layer comprising deposition defects; depositing a first work function metal layer above the high-k gate dielectric layer, wherein the first work function metal layer comprises an n-type metal; introducing a passivating substance into the high-k gate dielectric layer through the first work function metal layer, wherein introducing the passivating substance comprises: generating a plasma; filtering the plasma to provide free radicals from an afterglow of the plasma, wherein the semiconductor device is exposed to the free radicals; and depositing a fill metal above the first work function metal layer after introducing the passivating substance.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor fin extending above an isolation region; a high-k gate dielectric layer extending above the semiconductor fin and along a sidewall of the semiconductor fin, the high-k gate dielectric layer comprising fluorine; and a gate stack above the high-k gate dielectric layer and along a sidewall of the high-k gate dielectric layer, wherein the gate stack comprises: a first work function metal layer comprising an n-type metal and fluorine; and a first filling metal layer above the first work function metal layer, wherein the first filling metal layer does not contain fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig. 21C , Fig.21D , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig.18C A process chamber for performing a process on a wafer is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0013] Various embodiments provide a passivation process for one or more gate dielectric layers of a transistor (e.g., a fin field effect transistor (FinFET)). The passivation process includes introducing a passivating substance (e.g., fluorine, nitrogen, etc.) into (one or more) gate dielectric layers using a remote plasma process. The passivating substance can be introduced in the form of free radicals (e.g., fluorine free radicals, nitrogen free radicals, etc.). The passivating substance can help repair defects (e.g., dangling bonds, oxygen vacancies, etc.) in (one or more) gate dielectric layers, thereby improving device performance. In some embodiments, an n-type work function metal above (one or more) gate dielectric layers can promote the passivation process by attracting the passivating substance into (one or more) gate dielectric layers. By using a remote plasma process, improved consistency and desired doping concentration of the passivating substance can be achieved in (one or more) gate dielectric layers. In addition, the passivation process can be performed at a relatively low temperature (e.g., with a lower thermal budget), which reduces the risk of damaging the transistor due to the passivation process.

[0014] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 is above and protrudes from adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to a portion extending between adjacent isolation regions 56.

[0015] Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is located over gate dielectric layer 92. Source / drain regions 82 are disposed in opposite sides of fin 52 relative to gate dielectric layer 92 and gate electrode 94. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 94 and in a direction perpendicular to the direction of current flow, for example, between source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52 and in a direction of current flow, for example, between source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0017] Figures 2 to 23B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA shown in , except for multiple fins / FinFETs. Fig. 8A , 9A , 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A and 23A along Figure 1 The reference cross section AA shown in FIG. 1 shows, and Figure 8B , 9B , 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B and 23B along Figure 1 A similar cross section BB as shown in FIG. 1 is shown, except with multiple fins / FinFETs. Fig. 10C and Fig. 10D Along Figure 1 The reference cross section CC shown in FIG. 1 shows, in addition to multiple fins / FinFETs.

[0018] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a portion of the wafer 10, which may start from a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0019] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). Region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between region 50N and region 50P.

[0020] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0021] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-aligned process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0022] exist Figure 4 In the embodiment, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material (e.g., oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the above-described filling material may be formed over the liner.

[0023] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed.

[0024] exist Figure 6 Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI region 56 may have a flat surface, a raised surface, a recessed surface (e.g., recessed) or a combination thereof as shown. The top surface of STI region 56 may be formed to be flat, raised and / or recessed by appropriate etching. STI region 56 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52)). For example, a chemical oxide that can be removed by an appropriate etching process using, for example, dilute hydrofluoric acid (dHF) acid may be used.

[0025] about Figures 2 to 6 The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material, and the epitaxially grown material arranged over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments in which a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and subsequent implants, but in-situ doping and implant doping may be used together.

[0026] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0027] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, a P-well or an N-well is formed in both the region 50N and the region 50P.

[0028] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an NMOS region). The n-type impurities implanted in this region may be at a concentration equal to or less than 10 18 cm -3 (For example, at about 10 17 cm -3 With about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0029] After the implantation of region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, e.g., an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P (e.g., a PMOS region). The p-type impurity implanted in this region may be a concentration equal to or less than 10 18 cm -3 (For example, at about 10 17 cm -3 and about 10 18 cm -3 Boron, BF2, etc. between the electrodes. After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0030] After implantation of regions 50N and 50P, annealing may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fins may be doped in-situ during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0031] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 may be deposited above the dummy dielectric layer 60, and then planarized (e.g., by CMP). The mask layer 64 may be deposited above the dummy gate layer 62. The dummy gate layer 62 may be a conductive material, and may be selected from a group including polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to produce polycrystalline silicon. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer 62 may be made of other materials that have high etch selectivity in the etching of the isolation region. For example, the mask layer 64 may include SiN, SiON, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. In some embodiments, separate dummy gate layers may be formed in the region 50N and the region 50P, and separate mask layers may be formed in the region 50N and the region 50P. Note that the dummy dielectric layer 60 is shown as covering only the fin 52 for purposes of illustration only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, extending between the dummy gate layer 62 and the STI region 56.

[0032] FIG. 8A to FIG. 16B Various additional steps in the fabrication of example devices are shown. FIG. 8A to FIG. 16B Features in either region 50N or region 50P are shown. For example, FIG. 8A to FIG. 16B The structure shown in is applicable to both region 50N and region 50P. The differences, if any, in the structure of region 50N and region 50P are described in the text of each figure.

[0033] exist Fig. 8A and Figure 8BIn the embodiment of the present invention, the mask layer 64 can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0034] In addition, Fig. 8A and Figure 8B In the embodiment of the present invention, a gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 may be formed by thermal oxidation or deposition followed by anisotropic etching.

[0035] After forming the gate sealing spacer 80, an implant for a lightly doped source / drain (LDD) region (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 50P, and an appropriate type of impurity (e.g., n-type or p-type) can be implanted into the exposed fins 52 in the regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the regions 50P, while exposing the regions 50N, and an appropriate type of impurity can be implanted into the exposed fins 52 in the regions 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have a doping range from about 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0036] exist Fig. 9A and Fig. 9B In the embodiment, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon nitride, SiCN, a combination thereof, etc.

[0037] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52 to apply strain in the corresponding channel regions 58 to improve performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between a corresponding pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit a subsequently formed gate of the resulting FinFET.

[0038] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any acceptable material (e.g., suitable for n-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, SiC, SiCP, SiP, etc. The epitaxial source / drain regions 82 in the region 50N may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0039] The epitaxial source / drain regions 82 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include any acceptable material (e.g., suitable for p-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 82 in the region 50P can also have surfaces that protrude from the corresponding surfaces of the fin 52 and can have small facets.

[0040] The epitaxial source / drain regions 82 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a dopant density of about 10 19 cm -3 to about 10 21 cm-3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 may be doped in situ during growth.

[0041] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets allow adjacent source / drain regions 82 of the same FinFET to merge, such as Fig. 10C In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, such as Fig. 10D shown.

[0042] exist Fig.11A and Fig. 11B in Fig. 10A and Fig. 10B A first ILD 88 is deposited over the structure shown. The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method (e.g., CVD, plasma enhanced CVD (PECVD), or FCVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. The semiconductor material may include amorphous silicon, silicon germanium (Si x Ge 1-x , where x can be between about 0 and 1), pure germanium, etc. Other insulating or semiconductor materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the hard mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material having a different etch rate than the material of the first ILD 88 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0043] exist Fig. 12A and Fig. 12B In the process, a planarization process (e.g., CMP) may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72. The planarization process may also remove the mask 74 on the dummy gate 72, and portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88.

[0044] FIG. 13A to FIG. 21D A replacement gate process is shown in which the dummy gate 72 is removed and replaced by a metal gate. As part of the replacement gate process, one or more gate dielectric layers are formed between the metal gate and the fin 52. In various embodiments, a passivation process is performed to introduce a passivating substance (e.g., fluorine, nitrogen, combinations thereof, etc.) into one or more gate dielectric layers and reduce defects found therein. The passivation process can be a remote plasma process, which advantageously provides a desired concentration of the passivating substance in the gate dielectric layer with a high degree of consistency. Another advantage of remote plasma processing is that it can be performed at relatively low process temperatures, thereby reducing the risk of damaging the device.

[0045] exist Fig.13A and Fig. 13B In the embodiment of the present invention, the dummy gate 72 is removed in the etching step(s) to form the recess 90. The portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region of the die (e.g., the core logic region) and remains in the recess 90 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between a pair of adjacent epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then optionally be removed after removing the dummy gate 72 .

[0046] exist Fig.14A and Fig. 14BIn the embodiment of the present invention, one or more gate dielectric layers 92 are deposited over the channel region 58 and along the sidewalls of the channel region 58. The gate dielectric layer 92 is conformally deposited in the recess 90, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the STI 56 and the first ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 92 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. In some embodiments, the gate dielectric layer 92 may include a high-k dielectric material layer and an underlying silicon oxide layer, both of which are formed after removing the dummy gate 72. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In an embodiment in which a portion of the dummy gate dielectric 60 remains in the recess 90, the gate dielectric layer 92 includes the material (e.g., SiO) of the dummy gate dielectric 60. Due to manufacturing limitations of the deposition process, the gate dielectric layer 92 may include defects, such as dangling bonds, oxygen vacancies, combinations thereof, etc.

[0047] Next, in Fig.15A and Fig. 15B In the embodiment of the present invention, an optional adhesion layer 94 is deposited over the gate dielectric layer 92. The adhesion layer 94 may be a metal-containing material, such as titanium silicon nitride (TSN), titanium nitride, a combination thereof, multiple layers, etc. The formation of the adhesion layer 94 may include one or more steps of MBD, ALD, PECVD, PVD, a combination thereof, etc. After the adhesion layer 94 is deposited, an optional post-metal anneal 96 may be performed to improve the adhesion characteristics of the adhesion layer 94 and / or the gate dielectric layer 92. In some embodiments, the post-metal anneal 96 may be in the range of about 100° C. to about 1200° C.

[0048] exist Fig.16A and Fig. 16B In the embodiment of the present invention, an optional capping layer 98 may be deposited on the adhesion layer 94. The capping layer 98 may be a semiconductor material such as silicon or the like. The formation of the capping layer 98 may include CVD, ALD, PVD, or the like. After depositing the capping layer 98, an optional post-capping anneal 100 may be performed to further improve the adhesion characteristics of the adhesion layer 94 and / or the gate dielectric layer 92. In some embodiments, the post-capping anneal 96 may be in the range of about 100°C to about 1200°C. After the post-capping anneal 100, the capping layer 98 may be removed using an appropriate etching process (e.g., a dry or wet etching process). Removing the capping layer 98 may further remove a portion of the adhesion layer 94 below. Fig.15A , Fig. 15B , Fig.16A and Fig. 16B The steps described in are optional, and one or both of the steps may be omitted in various embodiments.

[0049] exist Fig.17A and Fig. 17B In the embodiment, a work function metal (WFM) layer 102 is deposited over the gate dielectric layer 92. The WFM layer 102 may be a metal-containing material, such as Ti, TiN, TiO, Ta, TaN, TaC, Co, Ru, Al, W, combinations thereof, multiple layers thereof, etc. In the embodiment where the adhesion layer 94 is formed, the WFM layer 102 includes the adhesion layer 94.

[0050] For example, Fig. 17C It shows that according to the embodiment Fig.17A Detailed view of area 200 in FIG. Fig. 17C As shown, the gate dielectric layer 92 includes a first layer 92A (eg, silicon oxide, an interfacial layer) and a second layer 92B (eg, a high-k gate oxide). The first layer 92A may include the remaining portion of the dummy gate dielectric 60 (see Fig. 12A and Fig. 12B ), a silicon oxide layer formed after removing the dummy gate 72, a combination thereof, and the like.

[0051] The WFM layer 102 may include an optional adhesion layer 94, an n-type WFM layer 102A, and an optional cap layer 102B. The n-type WFM layer 102A may include a combination of an n-type metal (e.g., Al, Ti, Ta, etc.) and another metal (e.g., Ti, TiN, Ta, TaN, TaC, TiC, TiCSi, etc.). The formation of the n-type WFM layer 102A may include one or more deposition steps using CVD, ALD, PVD, etc. In some embodiments, the deposition process(es) may be performed at a temperature that promotes diffusion of the n-type metal throughout the n-type WFM layer 102A. In some embodiments, one or more annealing steps may be performed to promote diffusion of the n-type metal throughout the n-type WFM layer 102A. As explained in more detail below, the concentration of the n-type metal (e.g., Al) in the n-type WFM layer 102A may be selected to achieve a desired concentration of passivating species in the underlying gate dielectric layer 92 in subsequent process steps.

[0052] The cap layer 102B may be a metal-containing material, such as Ti, TiN, TiO, Ta, TaN, TaC, TiC, TiCSi, etc. The cap layer 102B may include the same elements as the n-type WFM layer 102A. For example, in some embodiments, the cap layer 102B includes Ti, and the n-type WFM layer 102A includes TiAl or TiAlN. In the cap layer 102B, the concentration of the n-type metal may gradually decrease along the direction of arrow 202. In some embodiments, the top surface of the cap layer 102B may be substantially free of the n-type metal. The cap layer 102B is optional and may be omitted in some embodiments.

[0053] Fig. 17C The illustrated embodiment WFM layer 102 is merely an example, and layers may be omitted or added in other embodiments. For example, although a single n-type WFM layer 102A is shown, multiple n-type WFM layers 102A (e.g., with varying n-type metal concentrations) may be used depending on the desired electrical characteristics of the resulting transistor. Fig. 17C to form an n-type device, for example, an NMOS transistor, such as an n-type FinFET.

[0054] Fig.17D An alternative embodiment is shown. Fig.17A Detailed view of area 200 in FIG. Fig.17D The configuration can be similar to Fig. 17C Configuration of the present invention, wherein the same reference numerals indicate the same elements formed using the same process.

[0055] Fig.17D The configuration also includes a p-type WFM layer 102C located between the n-type WFM layer 102A and the gate dielectric layer 92. The p-type WFM layer 102C may include a metal (e.g., Ti, TiN, Ta, TaN, TaC, WC, WCN, MoN, etc.), and the p-type WFM layer 102C may be substantially free of the n-type metal in the n-type WFM layer 102A. The formation of the p-type WFM layer 102C may include one or more deposition steps using CVD, ALD, PVD, etc. Although a single p-type WFM layer 102C is shown, multiple p-type WFM layers may be used depending on the desired electrical characteristics of the resulting transistor. Fig.17D The configuration may be used in region 50P to form a p-type device, for example, a PMOS transistor such as a p-type FinFET.

[0056] exist Fig.18A and Fig.18BIn the embodiment of the present invention, a passivation process is applied to the WFM layer 102. The passivation process may include introducing a passivation substance 104 to the exposed surface of the WFM layer 102. In some embodiments, the passivation substance 104 includes free radicals, such as fluorine free radicals, nitrogen free radicals, combinations thereof, etc. The passivation substance 104 may be combined with the WFM layer 102 (e.g., the n-type WFM layer 102A, see Fig. 17C and Fig.17D ) is highly reactive with n-type metals (e.g., Al) in WFM layer 102. As a result, n-type metals in WFM layer 102 can attract passivating substances 104 and attract them to the underlying gate dielectric layer 92. Passivating substances 104 passivate defects (e.g., fill oxygen vacancies, terminate dangling bonds, etc.). As a result, the film quality of gate dielectric layer 92 can be improved, and device reliability and performance can be improved. In some embodiments, passivating substances 104 can diffuse into only a subset of gate dielectric layer 92. For example, passivating substances 104 can passivate second layer 92B (e.g., high-k gate oxide, see Fig. 17C and Fig.17D ), without passivating the first layer 92A of the gate dielectric layer 92 (eg, silicon oxide, interface layer, see Fig. 17C and Fig.17D In other embodiments, the passivation material 104 may be present in the entire gate dielectric layer 92 .

[0057] Fig.18C A process tool according to various embodiments is shown during a passivation process of a wafer 10. The wafer 10 is placed on a support chuck 220 in an area 212 of the process tool.

[0058] The process tool includes an inlet 202 that allows a process gas to flow into the tool as indicated by arrow 203. The process gas may include a precursor. In embodiments where the passivation substance 104 includes fluorine or nitrogen, the precursor may be any fluorine and / or nitrogen containing precursor, such as NF3, NH3, combinations thereof, and the like. The process gas may further include a carrier gas, such as H2, N2, He, combinations thereof, and the like. In the process gas, the precursor may be diluted by a carrier gas, and the concentration of the precursor gas may be in a range of about 1.0 atomic percent (at%) to about 40.0 at%. The concentration, flow rate, and amount of time that the process gas flows may be selected based on the desired concentration of the passivation substance 104 in the gate dielectric layer 92 (see Fig.18A and 18B ).

[0059] The process gas flows into region 204, and plasma ions are generated from the process gas. Any method of generating plasma ions from the process gas may be used. For example, Fig.18CIn the embodiment of the present invention, plasma ions 208 are generated between two electrodes 206 and 210. The top electrode 206 can be an inductively coupled plasma (ICP) coil. Other plasma generation methods can be used in other embodiments. Depending on the plasma generation technology, the plasma ions 208 can be generated at a power in the range of about 5W to about 5000W and a pressure in the range of about 10mTorr to 5000mTorr. In addition, the passivation process can be performed at a relatively low temperature, for example, less than about 100°C, for example, in the range of about 15°C to about 87°C. The relatively low thermal budget of the passivation process advantageously reduces the risk of damaging the wafer 10.

[0060] The bottom electrode 210 can provide a filter that spatially separates region 204 (e.g., where plasma ions are generated) from region 212 (e.g., where wafer 10 is located). Thus, in some embodiments, the passivation process can be a remote plasma process. The bottom electrode 210 can include a plurality of openings through which a plasma afterglow (providing free radicals) is generated from the plasma ions 208. Other plasma ion filter methods (e.g., ion filter plasma tools) can be used in other embodiments. The wafer 10 is exposed to the passivating substance 104 (e.g., free radicals from the plasma afterglow). As shown by arrows 213, excess gas can be drawn out of the process chamber through one or more exhaust ports 214.

[0061] In various embodiments, the use of free radicals instead of plasma ions to perform the passivation process provides advantages. For example, free radicals have relatively low energy compared to plasma ions, and therefore, the risk of damaging the wafer 10 can be reduced. In addition, compared to anisotropic plasma ion implantation (e.g., directional and depending on the implantation angle), the use of plasma afterglow is isotropic. In this way, an isotropic process can be used to achieve improved conformality of free radicals in the gate dielectric layer 92. In addition, the remote plasma process does not rely on the consistency of the gap filling and deposition processes to diffuse the passivating material into the gate dielectric layer 92. Therefore, the remote plasma process may be useful for passivating the gate dielectric layer formed on the fins with high aspect ratios and / or closely spaced fins. In addition, the concentration of the passivating material can be controlled by adjusting the concentration of the n-type metal (e.g., Al) in the WFM layer 102 and / or the process parameters of the passivation process (e.g., precursor concentration, precursor flow rate, time, plasma power, plasma process, combinations thereof, etc.). Embodiment remote plasma, passivation processes allow the concentration of the passivating species to be easily adjusted to a desired range (eg, a range that efficiently passivates the gate dielectric layer 92 without significantly damaging the WFM layer 102).

[0062] Fig.19A and Fig.19B The WFM layer 102 and the gate dielectric layer 92 are shown after passivation processing. Fig.19C and Fig.19D Shows Fig.19A Detailed view of area 200 in FIG. Fig.19C Shows the corresponding Fig. 17C An embodiment of the invention, and Fig.19D Shows the corresponding Fig.17D As a result of the passivation process, passivating substances (e.g., F, N, etc.) may be found in the WFM layer 102 and the gate dielectric layer 92. Fig.19C and Fig.19D As shown, the passivating material may be present only in the second layer 92B (eg, high-k gate oxide) and not in the underlying first layer 92A (eg, interface layer). In other embodiments, the passivating material may be found throughout the gate dielectric layer 92.

[0063] Alternatively, when the WFM layer 102 includes the common element as the passivating species prior to the passivation process, a greater than stoichiometric concentration of the passivating species may be found in the WFM layer 102. For example, in embodiments where the WFM layer 102 includes nitrogen prior to the passivation process and the passivating species is nitrogen, the WFM layer 102 may include a greater than stoichiometric concentration of nitrogen as a result of the passivation process.

[0064] In some embodiments, the concentration of the passivation species in the WFM layer 102 on the top surface of the channel region 58 is in the range of 1.0 at% to 40.0 at%, and the concentration of the passivation species in the WFM layer 102 on the sidewalls of the channel region 58 is in the range of 1.0 at% to 40.0 at%. In some embodiments, the concentration of the passivation species in the gate dielectric layer 92 (e.g., in the high-k gate oxide layer 92B) on the top surface of the channel region 58 is in the range of 1.0 at% to 40.0 at%, and the concentration of the passivation species in the gate dielectric layer 92 (e.g., in the high-k gate oxide layer 92B) on the sidewalls of the channel region 58 is in the range of 1.0 at% to 40.0 at%. It has been observed that by having these concentrations of the passivation species, defects in the gate dielectric layer 92 can be advantageously improved, which improves device reliability and performance. For example, it has been observed that concentrations less than the above range result in insufficient passivation in the high-k dielectric layer 92, resulting in limited benefits in device performance and reliability. It has been further observed that concentrations greater than the above range result in reduced film quality of the WFM layer 102, resulting in reduced device performance and reliability.

[0065] Fig.19EThe profile of the passivation region 250 on the channel region 58 is shown. The passivation region 250 is a region including a passivation substance on the channel region 58. For example, the passivation region 250 may include the WFM layer 102 and the portion of the gate dielectric layer 92 including the passivation substance. In some embodiments, the passivation region 250 may be formed by all of the WFM layer 102, and may further be formed by all of the gate dielectric layer 92. The profile of the passivation region 250 may be determined by performing, for example, elemental mapping of the passivation substance (e.g., fluorine) using energy dispersive X-ray spectroscopy analysis of a transmission electron microscope (TEM) image or a scanning electron microscope (SEM) image of the relevant area.

[0066] In some embodiments, the thickness T1 of the passivation region 250 on the sidewalls of the channel region 58 may be in a range of about 2.0 nm to about 10.0 nm, and the thickness T2 of the passivation region 250 on the top surface of the channel region 58 may be in a range of about 2.0 nm to about 10.0 nm. In addition, the ratio of the average thickness of the passivation region 250 on the sidewalls of the channel region 58 to the average thickness of the passivation region 250 on the top surface of the channel region 58 may be in a range of about 0.8:1.0 to about 0.9:1.0. It has been observed that when the passivation region 250 has a thickness within the above range and / or satisfies the above ratio, sufficient uniformity of the passivation process is achieved to provide good defect treatment coverage and improved device performance.

[0067] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, a liner 106 is deposited over the WFM layer 102. The liner 106 may be a metal-containing material, such as TiN, TiO, TaN, TaC, combinations thereof, multiple layers thereof, etc. The formation of the liner 106 may include one or more deposition steps using CVD, ALD, PVD, etc. In some embodiments, the liner 106 may be provided as a barrier layer, an adhesion layer, a wetting layer, etc. The thickness of the liner 106 may be about 1000 Å. to about In the range of, for example, about It has been observed that when the liner 106 has this range of thickness, improved device performance can be achieved. For example, a thinner liner 106 may provide insufficient adhesion and unacceptably high resistance. Since the liner 106 is deposited after the passivation process, the liner 106 may be substantially free of passivating substances. Alternatively, the liner 106 may be deposited with a stoichiometric concentration of a common element (e.g., N) as a passivating substance. For example, in some embodiments, the liner 106 may be formed of stoichiometric TiN, and the passivating substance may also be nitrogen.

[0068] Next, in Fig.21A and Fig.21B In the process, a fill metal 108 is formed over the liner 106 . Fig. 21C and Fig.21D Shows Fig.21A Detailed view of area 200 in FIG. Fig. 21C Shows the corresponding Fig. 17C An embodiment of the invention, and Fig.21D Shows the corresponding Fig.17D The fill metal 108 may be a metal-containing material, for example, Co, Ru, Al, W, combinations thereof, multiple layers thereof, etc. The formation of the liner 108 may include one or more deposition steps using CVD, ALD, PVD, etc. Fig. 21C and Fig.21D As shown, the fill metal 108 may be a multilayer structure including, for example, a first layer 108A and a second layer 108B. For example, in an embodiment in which the fill metal 108 includes W, the first layer 108A may be a fluorine-free tungsten (FFW) layer, and the second layer 108B may be a low fluorine tungsten (LFW) layer. In other embodiments, the number of layers of the fill metal 108 may be more or less. Since the fill metal 108 is deposited after the passivation process, the fill metal 108 may be substantially free of passivating radicals. As a result, a gate electrode 110 including the WFM layer 102, the liner 106, and the fill metal 108 is formed. Alternatively, the fill metal 108 may be deposited with a common element as a passivating substance. For example, the fill metal 108 may include LFW, and the passivating substance may be fluorine.

[0069] After filling the gate electrode 110, a planarization process such as CMP may be performed to remove the material of the gate electrode 110 and the excess portion of the gate dielectric layer 92 that is above the top surface of the first ILD 88. The material of the gate electrode 110 and the remaining portion of the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 110 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0070] The formation of gate dielectric layer 92 in region 50N and region 50P may occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 110 may occur simultaneously, such that gate electrode 110 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process, such that gate dielectric layer 92 may be a different material, and / or gate electrode 110 in each region may be formed by a different process, such that gate electrode 110 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0071] exist Fig.22A and Fig. 22B , a second ILD 112 is deposited over the first ILD 88. In an embodiment, the second ILD 112 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 112 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0072] exist Fig.23A and Fig. 23B In some embodiments, a gate contact 114 and a source / drain contact 116 are formed by the second ILD 112 and the first ILD 88. An opening for the source / drain contact 116 is formed by the first ILD 88 and the second ILD 116, and an opening for the gate contact 114 is formed by the second ILD 112. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 112. The remaining liner and conductive material form a source / drain contact 116 and a gate contact 114 in the opening. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 116. The source / drain contacts 116 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contacts 114 are physically and electrically coupled to the gate electrode 110. The source / drain contacts 116 and the gate contacts 114 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 116 and the gate contacts 114 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0073] Various embodiments provide a passivation process for one or more gate dielectric layers of transistors formed on a wafer. The passivation process includes introducing a passivating substance (e.g., fluorine, nitrogen, etc.) into (one or more) gate dielectric layers using a remote plasma process. The passivating substance can be introduced by exposing the wafer to free radicals (e.g., fluorine radicals, nitrogen radicals, etc.). The passivating substance can help repair defects (e.g., dangling bonds, oxygen vacancies, etc.) in (one or more) gate dielectric layers, thereby improving device performance. In some embodiments, an n-type work function metal above (one or more) gate dielectric layers can promote the passivation process by attracting the passivating substance into (one or more) gate dielectric layers. By using a remote plasma process, improved consistency and desired doping concentration of the passivating substance can be achieved in (one or more) gate dielectric layers. In addition, the passivation process can be performed at a relatively low temperature (e.g., with a lower thermal budget), which reduces the risk of damaging the transistor due to the passivation process.

[0074] In one embodiment, a method includes: depositing a high-k gate dielectric layer over and along the sidewalls of a semiconductor fin; depositing an n-type work function metal layer over the high-k gate dielectric layer; performing a passivation process on the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation process includes a remote plasma process; and depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer, the metal gate stack including the n-type work function metal layer and the fill metal. Optionally, in one embodiment, the remote plasma process includes exposing the high-k gate dielectric layer to free radicals. Optionally, in one embodiment, the free radicals are fluorine free radicals, nitrogen free radicals, or a combination thereof. Optionally, in one embodiment, the n-type work function metal layer includes aluminum, and wherein the passivation process includes attracting free radicals into the high-k gate dielectric layer using the aluminum. Optionally, in one embodiment, depositing the high-k gate dielectric layer includes depositing a high-k gate dielectric layer including oxygen vacancies, dangling bonds, or a combination thereof. Optionally, in one embodiment, the passivation process provides a passivating substance in the high-k gate dielectric layer to fill oxygen vacancies, terminate dangling bonds, or a combination thereof. Optionally, in one embodiment, the method further comprises depositing an adhesion layer between the high-k gate dielectric layer and the n-type work function metal layer; and depositing a cap layer over the n-type work function metal layer. Optionally, in one embodiment, the method further comprises depositing a barrier layer between the n-type work function metal layer and the fill metal. Optionally, in one embodiment, the method further comprises depositing a p-type work function metal layer between the high-k gate dielectric layer and the n-type work function metal layer. Optionally, in one embodiment, depositing a fill metal over the n-type work function metal layer comprises depositing a fill metal over the n-type work function metal layer after the passivation process.

[0075] According to another embodiment, a method includes: forming a semiconductor fin extending above an isolation region in a semiconductor device; depositing a high-k gate dielectric layer above the semiconductor fin and along a sidewall of the semiconductor fin, the high-k gate dielectric layer including deposition defects; depositing a first work function metal layer above the high-k gate dielectric layer, wherein the first work function metal layer includes an n-type metal; introducing a passivating substance into the high-k gate dielectric layer through the first work function metal layer, wherein introducing the passivating substance includes: generating a plasma; filtering the plasma to provide free radicals from an afterglow of the plasma, wherein the semiconductor device is exposed to the free radicals; and depositing a fill metal above the first work function metal layer after introducing the passivating substance. Optionally, in one embodiment, generating the plasma includes generating the plasma from a precursor gas including fluorine, nitrogen, or a combination thereof. Optionally, in one embodiment, the method also includes forming a second work function metal layer between the high-k gate dielectric layer and the first work function metal layer, wherein the second work function metal layer is a p-type work function metal layer. Optionally, in one embodiment, introducing the passivating species into the high-k gate dielectric layer through the first work function metal layer comprises using an n-type metal of the first work function metal layer to attract free radicals. Optionally, in one embodiment, introducing the passivating species is performed at a temperature of less than 100° C. Optionally, in one embodiment, the free radicals are fluorine radicals, nitrogen radicals, or a combination thereof, and wherein the n-type metal is aluminum.

[0076] According to yet another embodiment, a device includes: a semiconductor fin extending over an isolation region; a high-k gate dielectric layer extending over the semiconductor fin and along a sidewall of the semiconductor fin, the high-k gate dielectric layer including fluorine; and a gate stack over the high-k gate dielectric layer and along a sidewall of the high-k gate dielectric layer. The gate stack includes: a first work function metal layer including an n-type metal and fluorine; and a first fill metal layer over the first work function metal layer, wherein the first fill metal layer does not contain fluorine. Optionally, in one embodiment, the gate stack further includes: an adhesion layer under the first work function metal layer; a cap layer over the first work function metal layer; a barrier layer over the cap layer and under the first fill metal layer; and a second fill metal layer over the first fill metal layer, wherein the second fill metal layer includes fluorine. Optionally, in one embodiment, the fluorine concentration of the portion of the high-k gate dielectric layer on the top surface of the semiconductor fin is in the range of 1.0 at % to 40.0 at %, and wherein the fluorine concentration of the portion of the high-k gate dielectric layer on the sidewall of the semiconductor fin is in the range of 1.0 at % to 40.0 at %. Optionally, in one embodiment, the fluorine concentration of the portion of the first work function metal layer on the top surface of the semiconductor fin is in the range of 1.0 at % to 40.0 at %, and wherein the fluorine concentration of the portion of the first work function metal layer on the sidewall of the semiconductor fin is in the range of 1.0 at % to 40.0 at %.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0078] Example 1 is a method for manufacturing a semiconductor device, comprising: depositing a high-k gate dielectric layer above a semiconductor fin and along the sidewalls of the semiconductor fin; depositing an n-type work function metal layer above the high-k gate dielectric layer; performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation treatment includes a remote plasma process; and depositing a fill metal above the n-type work function metal layer to form a metal gate stack above the high-k gate dielectric layer, the metal gate stack including the n-type work function metal layer and the fill metal.

[0079] Example 2 is the method of Example 1, wherein the remote plasma process includes exposing the high-k gate dielectric layer to free radicals.

[0080] Example 3 is the method of Example 2, wherein the free radical is a fluorine free radical, a nitrogen free radical, or a combination thereof.

[0081] Example 4 is the method of Example 2, wherein the n-type work function metal layer includes aluminum, and wherein the passivation process includes attracting the radicals into the high-k gate dielectric layer using the aluminum.

[0082] Example 5 is the method of Example 1, wherein depositing the high-k gate dielectric layer comprises depositing the high-k gate dielectric layer including oxygen vacancies, dangling bonds, or a combination thereof.

[0083] Example 6 is the method of Example 5, wherein the passivation process provides a passivation species in the high-k gate dielectric layer to fill the oxygen vacancies, terminate the dangling bonds, or a combination thereof.

[0084] Example 7 is the method of Example 1, further comprising: depositing an adhesion layer between the high-k gate dielectric layer and the n-type work function metal layer; and depositing a cap layer over the n-type work function metal layer.

[0085] Example 8 is the method of Example 1, further comprising: depositing a barrier layer between the n-type work function metal layer and the fill metal.

[0086] Example 9 is the method of Example 1, further comprising: depositing a p-type work function metal layer between the high-k gate dielectric layer and the n-type work function metal layer.

[0087] Example 10 is the method of Example 1, wherein depositing the fill metal over the n-type work function metal layer comprises: depositing the fill metal over the n-type work function metal layer after the passivation process.

[0088] Example 11 is a method for manufacturing a semiconductor device, comprising: forming a semiconductor fin extending above an isolation region in a semiconductor device; depositing a high-k gate dielectric layer above and along a sidewall of the semiconductor fin, the high-k gate dielectric layer comprising deposition defects; depositing a first work function metal layer above the high-k gate dielectric layer, wherein the first work function metal layer comprises an n-type metal; introducing a passivating substance into the high-k gate dielectric layer through the first work function metal layer, wherein introducing the passivating substance comprises: generating a plasma; filtering the plasma to provide free radicals from an afterglow of the plasma, wherein the semiconductor device is exposed to the free radicals; and depositing a fill metal above the first work function metal layer after introducing the passivating substance.

[0089] Example 12 is the method of Example 11, wherein generating the plasma includes generating the plasma from a precursor gas including fluorine, nitrogen, or a combination thereof.

[0090] Example 13 is the method described in Example 11, further comprising: forming a second work function metal layer between the high-k gate dielectric layer and the first work function metal layer, wherein the second work function metal layer is a p-type work function metal layer.

[0091] Example 14 is the method of Example 11, wherein introducing the passivation substance into the high-k gate dielectric layer through the first work function metal layer includes: using the n-type metal of the first work function metal layer to attract the free radicals.

[0092] Example 15 is the method of Example 11, wherein introducing the passivating substance is performed at a temperature less than 100°C.

[0093] Example 16 is the method of Example 11, wherein the radical is a fluorine radical, a nitrogen radical, or a combination thereof, and wherein the n-type metal is aluminum.

[0094] Example 17 is a semiconductor device comprising: a semiconductor fin extending above an isolation region; a high-k gate dielectric layer extending above the semiconductor fin and along a sidewall of the semiconductor fin, the high-k gate dielectric layer comprising fluorine; and a gate stack above the high-k gate dielectric layer and along a sidewall of the high-k gate dielectric layer, wherein the gate stack comprises: a first work function metal layer comprising an n-type metal and fluorine; and a first fill metal layer above the first work function metal layer, wherein the first fill metal layer does not contain fluorine.

[0095] Example 18 is the device described in Example 17, wherein the gate stack further includes: an adhesion layer below the first work function metal layer; a cap layer above the first work function metal layer; a barrier layer above the cap layer and below the first filling metal layer; and a second filling metal layer above the first filling metal layer, wherein the second filling metal layer includes fluorine.

[0096] Example 19 is the device of Example 17, wherein the fluorine concentration of the portion of the high-k gate dielectric layer on the top surface of the semiconductor fin is in the range of 1.0 at % to 40.0 at %, and wherein the fluorine concentration of the portion of the high-k gate dielectric layer on the sidewall of the semiconductor fin is in the range of 1.0 at % to 40.0 at %.

[0097] Example 20 is the device described in Example 17, wherein the fluorine concentration of the portion of the first work function metal layer on the top surface of the semiconductor fin is in the range of 1.0at% to 40.0at%, and wherein the fluorine concentration of the portion of the first work function metal layer on the side wall of the semiconductor fin is in the range of 1.0at% to 40.0at%.

Claims

1. A method for manufacturing a semiconductor device, comprising: depositing a high-k gate dielectric layer over and along sidewalls of the semiconductor fin; depositing an n-type work function metal layer over the high-k gate dielectric layer; performing a passivation process to implant a passivating substance into the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation process comprises a remote plasma process, wherein the passivation process forms a passivation region comprising the passivating substance in the high-k gate dielectric layer and the n-type work function metal layer, and wherein a ratio of a first average thickness of the passivation region on a sidewall of the semiconductor fin to a second average thickness of the passivation region on a top surface of the semiconductor fin is in a range of 0.8:1 to 0.9:1; and A fill metal is deposited over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer, the metal gate stack including the n-type work function metal layer and the fill metal.

2. The method according to claim 1, wherein: The remote plasma process includes exposing the high-k gate dielectric layer to radicals.

3. The method according to claim 2, wherein: The free radical is a fluorine free radical, a nitrogen free radical, or a combination thereof.

4. The method according to claim 2, wherein: The n-type work function metal layer includes aluminum, and wherein the passivation process includes attracting the radicals into the high-k gate dielectric layer using the aluminum.

5. The method according to claim 1, wherein: Depositing the high-k gate dielectric layer includes depositing the high-k gate dielectric layer including oxygen vacancies, dangling bonds, or a combination thereof.

6. The method according to claim 5, wherein: The passivation process provides a passivating species in the high-k gate dielectric layer to fill the oxygen vacancies, terminate the dangling bonds, or a combination thereof.

7. The method according to claim 1, further comprising: depositing an adhesion layer between the high-k gate dielectric layer and the n-type work function metal layer; as well as A capping layer is deposited over the n-type work function metal layer.

8. The method according to claim 1, further comprising: A barrier layer is deposited between the n-type work function metal layer and the fill metal.

9. The method according to claim 1, further comprising: A p-type work function metal layer is deposited between the high-k gate dielectric layer and the n-type work function metal layer.

10. The method according to claim 1, wherein: Depositing the fill metal over the n-type work function metal layer includes depositing the fill metal over the n-type work function metal layer after the passivation process.

11. A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin extending over an isolation region in a semiconductor device; depositing a high-k gate dielectric layer over the semiconductor fin and along sidewalls of the semiconductor fin, the high-k gate dielectric layer comprising deposition defects; depositing a first work function metal layer over the high-k gate dielectric layer, wherein the first work function metal layer comprises an n-type metal; Introducing a passivation substance into the high-k gate dielectric layer through the first work function metal layer, wherein introducing the passivation substance comprises: Producing plasma; filtering the plasma to provide free radicals from an afterglow of the plasma, wherein the semiconductor device is exposed to the free radicals; and After introducing the passivation material, depositing a filling metal over the first work function metal layer, wherein the passivation material is introduced into the high-k gate dielectric layer and the first work function metal layer to form a passivation region including the passivation material, and wherein a ratio of a first average thickness of the passivation region on the sidewalls of the semiconductor fin to a second average thickness of the passivation region on the top surface of the semiconductor fin is in a range of 0.8:1 to 0.9:

1.

12. The method according to claim 11, wherein: Generating the plasma includes generating the plasma from a precursor gas including fluorine, nitrogen, or a combination thereof.

13. The method according to claim 11, further comprising: A second work function metal layer is formed between the high-k gate dielectric layer and the first work function metal layer, wherein the second work function metal layer is a p-type work function metal layer.

14. The method according to claim 11, wherein: Introducing the passivation species into the high-k gate dielectric layer through the first work function metal layer includes using the n-type metal of the first work function metal layer to attract the free radicals.

15. The method according to claim 11, wherein: The introduction of the passivating substance is carried out at a temperature of less than 100°C.

16. The method according to claim 11, wherein: The radicals are fluorine radicals, nitrogen radicals, or a combination thereof, and wherein the n-type metal is aluminum.

17. A semiconductor device comprising: a semiconductor fin extending over the isolation region; a high-k gate dielectric layer over the semiconductor fin and extending along sidewalls of the semiconductor fin, the high-k gate dielectric layer comprising fluorine; as well as a gate stack above the high-k gate dielectric layer and along a sidewall of the high-k gate dielectric layer, wherein the gate stack comprises: A first work function metal layer including an n-type metal and fluorine; and A first filling metal layer is above the first work function metal layer, wherein the first filling metal layer does not contain fluorine, wherein a passivation process is performed to inject a passivation substance into the high-k gate dielectric layer through the first work function metal layer, wherein the passivation process forms a passivation region including the passivation substance in the high-k gate dielectric layer and the first work function metal layer, and wherein a ratio of a first average thickness of the passivation region on the sidewalls of the semiconductor fin to a second average thickness of the passivation region on the top surface of the semiconductor fin is in a range of 0.8:1 to 0.9:

1.

18. The device according to claim 17, wherein The gate stack further comprises: an adhesion layer, below the first work function metal layer; a cap layer, above the first work function metal layer; a barrier layer over the cap layer and under the first fill metal layer; and A second filling metal layer is above the first filling metal layer, wherein the second filling metal layer includes fluorine.

19. The device according to claim 17, wherein: The fluorine concentration of the portion of the high-k gate dielectric layer on the top surface of the semiconductor fin is in the range of 1.0 at % to 40.0 at %, and wherein the fluorine concentration of the portion of the high-k gate dielectric layer on the sidewall of the semiconductor fin is in the range of 1.0 at % to 40.0 at %.

20. The device according to claim 17, wherein A fluorine concentration of a portion of the first work function metal layer on the top surface of the semiconductor fin is in the range of 1.0 at % to 40.0 at %, and wherein a fluorine concentration of a portion of the first work function metal layer on the sidewall of the semiconductor fin is in the range of 1.0 at % to 40.0 at %.

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