Optical semiconductor device and method of assembling an optical semiconductor device

Abstract

The present invention relates to an optical semiconductor device and a method of assembling an optical semiconductor device. The optical semiconductor device includes a semiconductor light-receiving element, a capacitor, and a carrier. The carrier has a mounting surface on which the semiconductor light-receiving element and the capacitor are mounted. The optical semiconductor device includes a first conductive pattern including a first mounting region and a first bonding pad, a second conductive pattern including a second mounting region and a third mounting region, and a third conductive pattern including a second bonding pad. The first mounting region is connected to a first electrode of the semiconductor light-receiving element. The second mounting region is connected to a second electrode of the semiconductor light-receiving element. The third mounting region is connected to one electrode of the capacitor. The conductive patterns are separated from each other. The other electrode of the capacitor is electrically connected to the third conductive pattern via a wire.

Description

[0001] Cross-referencing of related applications

[0002] Priority is claimed to Japanese Patent Application No. 2019-177420, filed on September 27, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to an optical semiconductor device and a method for assembling an optical semiconductor device. Background Technology

[0004] JP2000-183369A discloses a coaxial optical receiver module attached to an optical fiber. The optical receiver module includes: a package, a photodiode disposed on the upper surface of the package, and a preamplifier IC disposed on the upper surface of the package. The photodiode and the preamplifier IC are electrically connected via bonding wires to a power supply terminal and a signal output terminal fixed to the package. Summary of the Invention

[0005] The optical semiconductor device disclosed herein includes a semiconductor light-receiving element, a capacitor, a carrier, a first conductive pattern, a second conductive pattern, and a third conductive pattern. The semiconductor light-receiving element has a first electrode and a second electrode, the second electrode having a conductivity type opposite to that of the first electrode. The capacitor has one electrode and another electrode. The carrier has a mounting surface on which the semiconductor light-receiving element and the capacitor are mounted. The carrier is made of a dielectric. The first conductive pattern, the second conductive pattern, and the third conductive pattern are disposed on the mounting surface of the carrier. The first conductive pattern includes a first mounting region connected to the first electrode. The first conductive pattern includes a first bonding pad disposed at one end of the mounting surface. The second conductive pattern includes a second mounting region connected to the second electrode. The second conductive pattern includes a third mounting region disposed at the other end of the mounting surface and connected to one electrode of the capacitor. The third conductive pattern includes a second bonding pad disposed side-by-side with the first bonding pad at one end of the mounting surface. The first conductive pattern, the second conductive pattern, and the third conductive pattern are separate from each other. The other electrode of the capacitor and the third conductive pattern are electrically connected to each other via wires. Attached Figure Description

[0006] The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0007] Figure 1 This is a cross-sectional view showing the configuration of the optical receiving module according to an embodiment.

[0008] Figure 2 This is an enlarged cross-sectional view showing the configuration of the light receiving unit near the optical semiconductor device.

[0009] Figure 3 This is a plan view of the optical receiving unit, with the encapsulation and lens removed.

[0010] Figure 4 This is a magnified plan view showing an optical semiconductor device.

[0011] Figure 5 This is a plan view showing the main surface of a photodiode.

[0012] Figure 6 It is a plan view of the mounting surface of the carrier.

[0013] Figure 7A This is a diagram illustrating an assembly method for an optical semiconductor device according to an embodiment.

[0014] Figure 7B This is a diagram illustrating an assembly method for an optical semiconductor device according to an embodiment.

[0015] Figure 7C This is a diagram illustrating an assembly method for an optical semiconductor device according to an embodiment.

[0016] Figure 8 This is a diagram illustrating an assembly method for an optical semiconductor device according to an embodiment.

[0017] Figure 9A This is a side view showing the shape of the tip of the probe used in this embodiment.

[0018] Figure 9B This is a front view showing the tip shape of the probe used in this embodiment.

[0019] Figure 10A This is a side view showing the tip shape of the probe of the comparative example.

[0020] Figure 10B This is a front view showing the tip shape of the probe of the comparative example.

[0021] Figure 11 This is a diagram showing the state of the probe contacting the second or third bonding pad.

[0022] Figure 12 This is a plan view showing the optical receiving unit according to the first modified example.

[0023] Figure 13 It is shown Figure 12 An enlarged plan view of the mounting surface of the carrier shown.

[0024] Figure 14 This is a plan view showing the optical receiving unit according to the second modified example.

[0025] Figure 15 is a plan view showing a configuration near a short side of the carrier. Figure 14 is an enlarged perspective view of a configuration near a short side of the carrier.

[0026] Figure 16 is a plan view showing a shape of the conductive film according to the comparative example provided on the mounting surface of the carrier.

[0027] Figure 17 is a view showing a configuration in which the third mounting region is isolated from the second mounting region and the probe contact pad.

[0028] Figure 18A is a view showing an assembly process of the optical semiconductor device according to the comparative example.

[0029] Figure 18B is a view showing an assembly process of the optical semiconductor device according to the comparative example.

[0030] Figure 18C is a view showing an assembly process of the optical semiconductor device according to the comparative example.

[0031] Figure 19 is a view showing an assembly process of the optical semiconductor device according to the comparative example. DETAILED DESCRIPTION

[0032] [Problem to be Solved by the Disclosure]

[0033] In order to convert the intensity of light into an electric signal, a semiconductor light-receiving element such as a photodiode is used in, for example, an optical receiving module for optical communication. In a case where the size of the semiconductor light-receiving element is very small, the semiconductor light-receiving element is mounted on a carrier having a conductive film on its surface (chip on carrier: CoC), and a test such as burn-in is performed in this state. The conductive film includes one conductive pattern connected to one electrode of the semiconductor light-receiving element and another conductive pattern connected to the other electrode of the semiconductor light-receiving element. During the test, one probe is brought into contact with the one conductive pattern, another probe is brought into contact with the other conductive pattern, and a test voltage is applied between these probes.

[0034] However, in recent years, with the miniaturization of the optical receiving module, the miniaturization of the carrier has been progressing. Therefore, the size of the conductive pattern provided on the surface of the carrier is also small, and the gap between the conductive patterns is also narrow. Therefore, it becomes difficult to bring the probes into contact with the conductive patterns with high positional accuracy. If one probe is brought into contact with two adjacent conductive patterns at the same time, the probe will be short-circuited to another probe of a different potential, and the test cannot be performed correctly. In particular, in a case where the probe needs to be brought into contact with one of two bonding pads to obtain contact with the electrodes of the semiconductor light-receiving element, and the two bonding pads are arranged side by side, such a problem is evident.

[0035] [Advantages of the Present Disclosure]

[0036] According to the present disclosure, an optical semiconductor device and a method of assembling the same can prevent a short circuit between probes when testing a semiconductor light-receiving element mounted on a carrier.

[0037] [Description of Embodiments of the Present Disclosure]

[0038] First, embodiments of the present disclosure will be listed and described. An optical semiconductor device according to an embodiment includes a semiconductor light-receiving element, a capacitor, a carrier, a first conductive pattern, a second conductive pattern, and a third conductive pattern. The semiconductor light-receiving element has a first electrode and a second electrode, the second electrode having an opposite conductive type to the first electrode. The capacitor has one electrode and another electrode. The carrier has a mounting surface on which the semiconductor light-receiving element and the capacitor are mounted. The carrier is made of a dielectric. The first conductive pattern, the second conductive pattern, and the third conductive pattern are provided on the mounting surface of the carrier. The first conductive pattern includes a first mounting region connected to the first electrode. The first conductive pattern includes a first bonding pad provided on one end of the mounting surface. The second conductive pattern includes a second mounting region connected to the second electrode. The second conductive pattern includes a third mounting region provided on the other end of the mounting surface and connected to the one electrode of the capacitor. The third conductive pattern includes a second bonding pad provided side by side with the first bonding pad on the one end of the mounting surface. The first conductive pattern, the second conductive pattern, and the third conductive pattern are separated from each other. The other electrode of the capacitor and the third conductive pattern are electrically connected to each other via a wire.

[0039] Generally, a semiconductor light-receiving element is tested in a state where the semiconductor light-receiving element is mounted on a carrier. In an optical semiconductor device, a first bonding pad is included in a first conductive pattern together with a first mounting region connected to a first electrode. A third mounting region is included in a second conductive pattern together with a second mounting region connected to a second electrode. Thus, when the semiconductor light-receiving element is tested, one probe can be brought into contact with the first bonding pad, and another probe can be brought into contact with the second conductive pattern, for example, the third mounting region. Here, the first bonding pad is provided side by side with a second bonding pad on one end of the mounting surface. Thus, when a probe is brought into contact with the first bonding pad, if the positional accuracy of the probe is low, the probe also comes into contact with the second bonding pad. If the second bonding pad is included in the second conductive pattern, this contact causes a short circuit between the probes.

[0040] On the other hand, in the optical semiconductor device described above, the second conductive pattern including the second mounting region connected to the second electrode and the third conductive pattern including the second bonding pad are separated from each other. Therefore, even in a case where a probe in contact with the first bonding pad is simultaneously in contact with the second bonding pad, short-circuiting between the probes can be prevented. Since the second conductive pattern and the third conductive pattern can be connected to each other via the capacitor after the test, there is no problem even if they are electrically separated from each other during the test.

[0041] The optical semiconductor device described above can include a fourth conductive pattern including a third bonding pad provided side by side with the first bonding pad and the second bonding pad on one end of the mounting surface. The first bonding pad is located between the second bonding pad and the third bonding pad. The fourth conductive pattern is separated from the first conductive pattern, the second conductive pattern, and the third conductive pattern. The other electrode of the capacitor and the fourth conductive pattern are electrically connected to each other via a wire. According to this configuration, it is possible to make the signal path including the third conductive pattern and the signal path including the fourth conductive pattern symmetrically close to each other with the signal path including the first conductive pattern interposed therebetween. In this case, it is possible to improve the signal transmission characteristics.

[0042] In the optical semiconductor device described above, the third conductive pattern and the fourth conductive pattern can have planar shapes that are line-symmetric to each other, and the first conductive pattern is interposed therebetween. According to this configuration, the signal path including the third conductive pattern and the signal path including the fourth conductive pattern are symmetric to each other with the signal path including the first conductive pattern interposed therebetween. Therefore, it is possible to further improve the signal transmission characteristics.

[0043] In the optical semiconductor device described above, the third conductive pattern can extend from the second bonding pad along one end of the mounting surface, and further include a third bonding pad provided side by side with the first bonding pad. The first bonding pad is located between the second bonding pad and the third bonding pad. In this case, compared to the case where the fourth conductive pattern described above is provided, the lateral width of the mounting surface of the carrier, i.e., the width of the mounting surface in the direction along one end and the other end thereof, can be smaller. This can contribute to reducing the size of the optical semiconductor device. Alternatively, another circuit component can be provided instead of the fourth conductive pattern.

[0044] The optical semiconductor device described above can include a third bonding pad provided side by side with the first bonding pad and the second bonding pad on one end of the mounting surface. The first bonding pad is located between the second bonding pad and the third bonding pad. The second bonding pad and the third bonding pad are electrically connected to each other via a conductive film provided on the side surface of the carrier. In this case, compared to the case where the fourth conductive pattern described above is provided, the lateral width of the mounting surface of the carrier, i.e., the width of the mounting surface in the direction along one end and the other end thereof, can be smaller. This can contribute to reducing the size of the optical semiconductor device. Alternatively, another circuit component can be provided instead of the fourth conductive pattern. Further, in the conductive film on the mounting surface, a portion of the third conductive pattern that connects the second bonding pad to the third bonding pad is not necessary, and thus the mounting surface of the carrier can be made smaller. Therefore, this can further contribute to reducing the size of the optical semiconductor device.

[0045] The method of assembling an optical semiconductor device according to the embodiment includes the steps of: preparing a carrier having a first conductive pattern, a second conductive pattern, and a third conductive pattern on a mounting surface, the first conductive pattern including a first bonding pad and a first mounting region, the second conductive pattern including a second mounting region and a third mounting region, wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are separated from each other; mounting a semiconductor light-receiving element on the carrier, and electrically connecting a first electrode of the semiconductor light-receiving element to the first mounting region of the carrier, and electrically connecting a second electrode of the semiconductor light-receiving element to the second mounting region of the carrier; performing a test in a state where one probe is in contact with the first bonding pad and another probe is in contact with the second conductive pattern, and a voltage is applied between the one probe and the another probe; after the test, mounting a capacitor on the carrier, and electrically connecting one electrode of the capacitor to the third mounting region; and performing wire bonding between the other electrode of the capacitor and the third conductive pattern using a first wire.

[0046] In this assembly method, the semiconductor light-receiving element is tested in a state where the semiconductor light-receiving element is mounted on the carrier. At this time, the second conductive pattern including the second mounting region connected to the second electrode is separated from the third conductive pattern including the second bonding pad. Therefore, even in the case where the probe in contact with the first bonding pad is in contact with the second bonding pad at the same time, short-circuiting between the probes can be prevented.

[0047] [Details of Embodiments of the Invention]

[0048] Specific examples of the optical semiconductor device and the method of assembling the optical semiconductor device of the present disclosure will be described below with reference to the drawings. The present invention is not limited to these examples, but is defined by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope. In the following description, in the description of the drawings, the same elements will be denoted by the same reference signs without repeated description.

[0049] Figure 1 is a cross-sectional view showing a configuration of an optical receiving module 1A according to an embodiment, and shows a cross section along an optical axis of incident light. The optical receiving module 1A constitutes a part of an optical receiver for long distance optical communication. As shown in Figure 1 the optical receiving module 1A of the present embodiment includes an optical receiver 10 connected to an optical fiber and an optical receiving unit 20A fixed to the optical receiver 10. The optical receiver 10 includes: an optical fiber stub, i.e., a stub ferrule 12; a metal member 14; a sleeve 16; and a housing member, i.e., a housing 18. The optical fiber stub 12 has a ferrule 11 and an optical fiber 13.

[0050] The ferrule 11 is a member having a cylindrical shape or a circular cylindrical shape. A central axis of the ferrule 11 extends in a direction D1, and a cross section of the ferrule 11 perpendicular to the central axis is circular. The ferrule 11 has a base end surface 11a and a top end surface 11b aligned in the direction D1. The top end surface 11b is in physical contact with a ferrule of an optical connector connected to the optical receptacle 10. For example, the top end surface 11b is polished to be spherical. The base end surface 11a is a surface opposite to the top end surface 11b, and faces the optical receiving unit 20A attached on the optical receptacle 10. The base end surface 11a is slightly inclined, for example, about 8°, with respect to a surface perpendicular to the central axis of the ferrule 11. The ferrule 11 also has an outer peripheral surface 11c which is a cylindrical surface.

[0051] The ferrule 11 also has an optical fiber holding hole 11d. The optical fiber holding hole 11d extends along the direction D1 and is formed on the central axis of the ferrule 11. A cross section of the optical fiber holding hole 11d is circular, and an inner diameter thereof is slightly larger than an outer diameter of the optical fiber 13. One opening of the optical fiber holding hole 11d is included in the top end surface 11b, and the other opening of the optical fiber holding hole 11d is included in the base end surface 11a. That is, the optical fiber holding hole 11d penetrates a space between the base end surface 11a and the top end surface 11b of the ferrule 11 in the direction D1. The ferrule 11 is made of, for example, zirconia (ZrO2). Since the ferrule 11 is made of zirconia having high tenacity and Young's modulus, physical contact can be appropriately made on the top end surface 11b.

[0052] The optical fiber 13 is, for example, a single-mode optical fiber, and is a bare optical fiber from which a resin coating is removed. The optical fiber 13 is made of, for example, quartz. The optical fiber 13 extends in a direction Dl as a length direction, that is, an optical axis direction. The optical fiber 13 has one end 13a and the other end 13b. The optical fiber 13 is inserted into the optical fiber holding hole 11d. Then, the one end 13a is exposed from an opening of the optical fiber holding hole 11d on the top end surface 11b, and the other end 13b is exposed from an opening of the optical fiber holding hole 11d on the base end surface 11a. The one end 13a is in contact with one end of an optical fiber in the vicinity of an optical connector connected to the optical receptacle 10. The other end 13b is optically coupled with a photodiode 21 of a light receiving unit 20A to be described later. The outer diameter of the optical fiber 13 is, for example, 125 μm.

[0053] The metal member 14 has a through-hole 14a extending in the direction Dl, and holds the optical fiber stub 12 in the through-hole 14a. The metal member 14 is made of, for example, a metal material such as stainless steel. The metal member 14 has a cylindrical shape extending in the direction Dl. The metal member 14 has a base end surface 14b, a top end surface 14c, and an outer peripheral surface 14d. The base end surface 14b and the top end surface 14c are arranged in the direction Dl. The through-hole 14a penetrates a space between the base end surface 14b and the top end surface 14c. A cross section of the through-hole 14a perpendicular to the direction Dl is circular. The base end surface 14b faces a package 22 of a light receiving unit 20A to be described later. The optical fiber stub 12 is pressed into the through-hole 14a of the metal member 14 in the direction Dl. That is, the outer peripheral surface 11c of the ferrule 11 is in contact with an inner surface of the through-hole 14a, and thus the optical fiber stub 12 is fixed to the metal member 14.

[0054] The sleeve 16 is a cylindrical member extending in the direction Dl, and is made of, for example, ceramic. In one example, the sleeve 16 is made of the same material as the ferrule 11 (for example, zirconia). An inner diameter of the sleeve 16 is substantially equal to an outer diameter of the optical fiber stub 12. The sleeve 16 has a base end 16a and a top end 16b arranged in the direction Dl. The sleeve 16 has an outer peripheral surface 16c and an inner peripheral surface 16d. The optical fiber stub 12 is inserted from an opening of the sleeve 16 on the base end 16a. In other words, a portion of the sleeve 16 close to the base end 16a is inserted into a gap between the outer peripheral surface 11c of the ferrule 11 and the metal member 14. Thus, the outer peripheral surface 16c of the sleeve 16 is in contact with the metal member 14, and the inner peripheral surface 16d of the sleeve 16 is in contact with the outer peripheral surface 11c of the ferrule 11. An optical connector ferrule is inserted from an opening of the sleeve 16 on the top end 16b. A top end surface of the ferrule 11 and a top end surface of the optical connector ferrule are in contact with each other in the sleeve 16. Thus, the optical fiber 13 held by the ferrule 11 and an optical fiber held by the optical connector ferrule are optically coupled with each other with high coupling efficiency.

[0055] The housing member 18 is fixed to the metal member 14 and connected to the optical connector. For example, the housing member 18 is a cylindrical member extending in direction D1 and is made of a metal such as stainless steel. The housing member 18 has a flange 18a and a through hole 18d extending in direction D1. The housing member 18 has a base end surface 18b and a top end portion 18c arranged in direction D1. The flange 18a is a disc-shaped portion protruding outward from the housing member 18. The flange 18a is provided near the base end surface 18b of the housing member 18. In this embodiment, one surface of the flange 18a constitutes the base end surface 18b. The through hole 18d penetrates the space between the base end surface 18b and the top end portion 18c. The cross-section of the through hole 18d perpendicular to direction D1 is circular, and its central axis overlaps with the central axis of the optical fiber stub 12 and the metal member 14. The housing member 18 includes a first portion 18e near the base end surface 18b and a second portion 18f near the top end portion 18c, which are part of a through hole 18d. The first portion 18e extends from the base end surface 18b to the second portion 18f in direction D1. The second portion 18f extends from the top end portion 18c to the first portion 18e in direction D1. The first portion 18e and the second portion 18f are connected to each other between the top end portion 16b and the top end portion 18c of the sleeve 16, in other words, they are in communication with each other. The inner diameter of the first portion 18e is approximately equal to or slightly larger than the outer diameter of the outer peripheral surface 16c of the sleeve 16. The inner diameter of the second portion 18f is slightly larger than the inner diameter of the inner peripheral surface 16d of the sleeve 16. Thus, the inner diameter of the first portion 18e is larger than the inner diameter of the second portion 18f, thereby forming a stepped surface 18g between the first portion 18e and the second portion 18f. The stepped surface 18g faces the top end portion 16b of the sleeve 16.

[0056] The optical receiving unit 20A includes an optical semiconductor device 2A, a package 22, a lens 23, a rod 24, an integrated circuit chip 26, and multiple lead pins 27a to 27f.

[0057] The rod 24 is a generally circular and flat insulating member. The rod 24 has a flat main surface 24a. The main surface 24a intersects the optical axis of the optical fiber connected to the optical socket 10, that is, the optical axis of the optical fiber 13. In one example, the main surface 24a is perpendicular to the optical axis of the optical fiber connected to the optical socket 10, that is, the optical axis of the optical fiber 13. For example, the rod 24 is made of a material such as ceramic.

[0058] The package 22 is a substantially cylindrical metal member, and a central axis thereof is along an optical axis of the optical fiber 13. One end 22a of the package 22 on a proximal end side in the direction of the optical axis of the optical fiber 13 is fixed to the main surface 24a of the stem 24 by the annular member 29. Specifically, the annular member 29 has one end surface 29a and another end surface 29b in the direction of the optical axis. The one end 22a of the package 22 on the proximal end side is engaged with the one end surface 29a of the annular member 29, and the main surface 24a of the stem 24 is fixed to the other end surface 29b of the annular member 29. The other end 22b of the package 22 on the distal end side in the direction of the optical axis of the optical fiber 13 is fixed to the metal member 14 via the cylindrical member 19. Specifically, the metal member 14 is inserted from one end of the cylindrical member 19 on the distal end side, and an outer peripheral surface of the metal member 14 and an inner peripheral surface of the cylindrical member 19 are engaged with each other. The other end 22b of the package 22 on the distal end side is engaged with a surface of the cylindrical member 19 on the proximal end side. The package 22 is made of a material such as iron-nickel alloy, for example.

[0059] The optical semiconductor device 2A has a carrier 25 and a photodiode 21 mounted on the carrier 25. The photodiode 21 is an example of a semiconductor light-receiving element in the present disclosure. The photodiode 21 is optically coupled to the other end 13b of the optical fiber 13. The photodiode 21 receives light from the optical fiber connected to the optical receptacle 10 and outputs a current signal having a magnitude corresponding to an intensity of the light. The photodiode 21 is mounted on the carrier 25 mainly containing a dielectric, and the carrier 25 is arranged on an integrated circuit chip 26. That is, the photodiode 21 is mounted on the integrated circuit chip 26 via the carrier 25. In one example, the carrier 25 is made of only a dielectric. As the photodiode 21, various photodiodes such as a PIN photodiode and an avalanche photodiode (APD) can be applied. The carrier 25 is a flat member made of ceramic or quartz, for example. The integrated circuit chip 26 is a semiconductor IC that receives the current signal from the photodiode 21 and converts the current signal into a voltage signal.

[0060] A plurality of lead pins 27 are stem-shaped metal members extending in a direction intersecting the main surface 24a of the stem 24. The lead pins 27 are provided so as to penetrate the stem 24 and be fixed to the stem 24. Through the lead pins 27, electric signals and electric power are transmitted to and received from the photodiode 21 and the integrated circuit chip 26 arranged in a space defined by the package 22, the stem 24, and the member 29.

[0061] Lens 23 is held inside package 22 and fixed to the inner circumferential surface of package 22 via resin 23a. Lens 23 is a condensing lens made of a light-transmitting component and is arranged on the optical axis of optical fiber 13. Lens 23 focuses light emitted from the other end 13b of optical fiber 13 onto photodiode 21. The optical axis of lens 23 is slightly offset relative to the optical axis of optical fiber 13 to prevent backlight from photodiode 21.

[0062] Figure 2 This is an enlarged cross-sectional view showing the configuration of the light receiving unit 2A near the optical semiconductor device 20A. (As shown) Figure 2 As shown, the integrated circuit chip 26 has a surface 26a and a surface 26b opposite to surface 26a. Surfaces 26a and 26b are arranged in the optical axis direction of the optical fiber 13 and extend along a plane intersecting (e.g., orthogonal) to the optical axis direction. Surface 26a of the integrated circuit chip 26 faces the main surface 24a of the rod 24. The carrier 25 has a surface 25a and a mounting surface 25b opposite to surface 25a. Surface 25a of the carrier 25 faces the surface 26b of the integrated circuit chip 26. The photodiode 21 has a main surface 21a and a rear surface 21b opposite to the main surface 21a, and receives light on the rear surface 21b. The photodiode 21 is mounted on the mounting surface 25b of the carrier 25 such that the mounting surface 25b faces the main surface 21a of the photodiode 21.

[0063] Figure 3 This is a plan view of the light receiving unit 20A without the package 22 and lens 23. (See diagram below.) Figure 3 As shown, a GND pattern 24b, adjusted to a reference potential, i.e., a ground potential, is provided on the main surface 24a of the rod 24. Lead pins 27a to 27f are provided on the peripheral portion of the rod 24.

[0064] The surface 26b of the integrated circuit chip 26 has a rectangular shape. Surface 26b has a pair of sides extending in the lateral direction of the integrated circuit chip 26, i.e., short sides, and a pair of sides extending in the longitudinal direction of the integrated circuit chip 26, i.e., long sides. The integrated circuit chip 26 has a plurality of electrode pads on surface 26b. Among these electrode pads, three electrode pads 28a to 28c arranged along one of the short sides are electrically connected to the photodiode 21. Specifically, two electrode pads 28a and 28c are connected to the cathode of the photodiode 21 via a capacitor 31. Electrode pad 28b is connected to the anode of the photodiode 21 and receives the current signal output from the photodiode 21.

[0065] Two electrode pads 28d are located near one of the long sides of surface 26b. Power supply voltage is input to the integrated circuit chip 26 from outside the optical receiving module 1A through the electrode pads 28d. Figure 3As shown, the electrode pad 28d is electrically connected to one electrode of a capacitor 41 mounted on the GND pattern 24b via a bonding wire. One electrode of the capacitor 41 is also electrically connected to the lead pin 27d through a bonding wire. The other electrode of the capacitor 41 is electrically connected to the GND pattern 24b via a conductive bonding material such as solder. The capacitor 41 functions as a bypass capacitor. The capacitor 41 is, for example, a chip capacitor.

[0066] The electrode pads 28g and 28h are arranged along the other short side of the surface 26b. A voltage signal generated based on a current signal from the photodiode 21 is output to the outside of the light-receiving module 1A through the electrode pads 28g and 28h. As shown, one electrode pad 28g is electrically connected to the lead pin 27e via a bonding wire. The other electrode pad 28h is electrically connected to the other lead pin 27f via a bonding wire. Figure 3

[0067] Figure 4 is an enlarged plan view showing the optical semiconductor device 2A. The mounting surface 25b of the carrier 25 has a rectangular shape. The mounting surface 25b has a pair of sides extending in the lateral direction, i.e., the short sides 25c and 25d, and a pair of sides extending in the longitudinal direction, i.e., the long sides 25e and 25f. As shown, the longitudinal direction of the carrier 25 coincides with the longitudinal direction of the integrated circuit chip 26. The area of the mounting surface 25b of the carrier 25 is equal to or greater than half the area of the surface 26b of the integrated circuit chip 26. In one example, the length of the carrier 25 in the longitudinal direction is 760 μm, and the length of the carrier 25 in the lateral direction is 530 μm. Figure 3

[0068] The optical semiconductor device 2A includes a capacitor 31 in addition to the carrier 25 and the photodiode 21. The capacitor 31 is mounted on the mounting surface 25b of the carrier 25 together with the photodiode 21. Specifically, the photodiode 21 is arranged at a position near the short side 25c in the length direction of the mounting surface 25b. The capacitor 31 is arranged at a position near the short side 25d in the length direction of the mounting surface 25b, i.e., between the photodiode 21 and the short side 25d. The capacitor 31 has a pair of electrodes facing in opposite directions, and a dielectric such as SiN interposed between the pair of electrodes, for example. Hereinafter, one electrode of the capacitor 31 is referred to as a back surface electrode, and the other electrode is referred to as a front surface electrode 31a. The back surface electrode of the capacitor 31 faces the mounting surface 25b. The front surface electrode 31a of the capacitor 31 faces the same direction as the mounting surface 25b. The capacitance value of the capacitor 31 is, for example, 100 pF. The planar shape of the capacitor 31 is, for example, a square with a side length of 250 μm.

[0069] Figure 5 ​​is a plan view showing the main surface 21a of the photodiode 21. The planar shape of the main surface 21a is rectangular or square. The photodiode 21 has a first electrode 211 and a second electrode 212 having an opposite conductive type to the first electrode 211 on the main surface 21a. For example, the first electrode 211 is an anode, and the second electrode 212 is a cathode. In one example, the first electrode 211 is arranged at the center of the main surface 21a of the photodiode 21. The second electrode 212 is arranged at each of the four corners of the main surface 21a of the photodiode 21. For example, the size of the main surface 21a is about 300 pm on one side.

[0070] Figure 6 is a plan view of the mounting surface 25b of the carrier 25. In Figure 6 , regions Al to A3 are indicated by dotted lines. The region Al is a region to which the first electrode 211 of the photodiode 21 is connected by a conductive joint. The region A2 is a region to which the second electrode 212 is connected by a conductive joint. The region A3 is a region to which the back surface electrode of the capacitor 31 is connected by a conductive joint.

[0071] As Figure 6 indicated, a conductive film 32 is provided on the mounting surface 25b of the carrier 25. The conductive film 32 is a metal film fixed to the mounting surface 25b. The conductive film 32 includes, for example, mainly a gold (Au) film based on titanium (Ti). The conductive film 32 includes a first conductive pattern 33, a second conductive pattern 34, a third conductive pattern 35, and a fourth conductive pattern 36. These conductive patterns 33 to 36 are separated from each other on the mounting surface 25b. The conductive patterns are separated from each other is that the conductive patterns are separated from each other by air or an insulating material, and the conductive patterns are electrically isolated from each other in a structure including the carrier 25 and the conductive film 32.

[0072] The first conductive pattern 33 is a wiring pattern extending in the length direction of the mounting surface 25b. The first conductive pattern 33 is provided at a position near the short side 25c in the lateral direction in the central portion of the mounting surface 25b. The first conductive pattern 33 includes a first mounting region 331 and a first bonding pad 332. The first mounting region 331 is a circular pattern constituting one end portion of the first conductive pattern 33 near the short side 25d. The first mounting region 331 is connected to the first electrode 211 of the photodiode 21 by a conductive joint using a conductive joining material such as an AuSn solder. The first bonding pad 332 is a polygonal pattern provided on one end of the mounting surface 25b. The first bonding pad 332 is provided between the short side 25c and the first mounting region 331. The first bonding pad 332 constitutes the other end portion of the first conductive pattern 33 near the short side 25c. From Figure 3 the electrode pad 28b of the integrated circuit chip 26 extends is connected to the first bonding pad 332.

[0073] The second conductive pattern 34 is a wiring pattern extending in the length direction of the mounting surface 25b. The second conductive pattern 34 is provided at a position near the short side 25d in the lateral direction of the central portion of the mounting surface 25b. The second conductive pattern 34 includes a second mounting region 341, a third mounting region 342, and a flow-stopping region 343. The second mounting region 341 is a U-shaped pattern constituting one end portion of the second conductive pattern 34 near the short side 25c. The second mounting region 341 is connected to the four second electrodes 212 of the photodiode 21 by a conductive joint using a conductive joining material such as AuSn solder. The first mounting region 331 of the first conductive pattern 33 is provided in a gap in the center of the second mounting region 341.

[0074] The third mounting region 342 is a rectangular pattern provided on the other end of the mounting surface 25b. The third mounting region 342 is provided between the short side 25d and the second mounting region 341. The third mounting region 342 constitutes the other end portion of the second conductive pattern 34 near the short side 25d. The third mounting region 342 is connected to the back surface electrode of the capacitor 31 by a conductive joint using a conductive joining material such as AuSn solder. The flow-stopping region 343 is provided between the second mounting region 341 and the third mounting region 342, and physically separates these regions 341 and 342 from each other. The flow-stopping region 343 inhibits inflow of the conductive joining material from the second mounting region 341 to the third mounting region 342, and inflow of the conductive joining material from the third mounting region 342 to the second mounting region 341. The flow-stopping region 343 is a film having a surface made of a material having lower wettability with respect to the conductive joining material than the wettability of the regions 341 and 342. The surface of the flow-stopping region 343 is made of, for example, chromium (Cr).

[0075] The region A3 is connected to the back surface electrode of the capacitor 31 by a conductive joint. The region A3 is provided at a position near the long side 25f in the third mounting region 342. As shown in FIG. 6, one end of the bonding wire 46 is bonded to a portion of the third mounting region 342 near the long side 25e. Referring again to FIG. 5, the other end of the bonding wire 46 is bonded to one electrode of the capacitor 42 mounted on the GND pattern 24b. That is, the third mounting region 342 is electrically connected to one electrode of the capacitor 42 via the bonding wire 46. One electrode of the capacitor 42 is also electrically connected to the lead pin 27a via a bonding wire. The other electrode of the capacitor 42 is electrically connected to the GND pattern 24b via a conductive joining material such as solder. The capacitor 42 functions as a bypass capacitor. The capacitor 42 is, for example, a chip capacitor. Figure 4 Figure 3 The region A3 is connected to the back surface electrode of the capacitor 31 by a conductive joint. The region A3 is provided at a position near the long side 25f in the third mounting region 342. As shown in FIG. 6, one end of the bonding wire 46 is bonded to a portion of the third mounting region 342 near the long side 25e. Referring again to FIG. 5, the other end of the bonding wire 46 is bonded to one electrode of the capacitor 42 mounted on the GND pattern 24b. That is, the third mounting region 342 is electrically connected to one electrode of the capacitor 42 via the bonding wire 46. One electrode of the capacitor 42 is also electrically connected to the lead pin 27a via a bonding wire. The other electrode of the capacitor 42 is electrically connected to the GND pattern 24b via a conductive joining material such as solder. The capacitor 42 functions as a bypass capacitor. The capacitor 42 is, for example, a chip capacitor.

[0076] Referring again to FIG. 5, Figure 6 ​The third conductive pattern 35 is a wiring pattern extending in the length direction of the mounting surface 25b. The third conductive pattern 35 is provided on portions of the mounting surface 25b near the short side 25c and near the long side 25e. The third conductive pattern 35 includes a second bonding pad 351 and a fourth bonding pad 352. The second bonding pad 351 constitutes one end portion of the third conductive pattern 35 near the short side 25c. From the second bonding pad 351, the third conductive pattern 35 extends toward the long side 25e. Figure 3 The other end of the bonding wire extending from the electrode pad 28a of the integrated circuit chip 26 shown in the drawing is connected to the second bonding pad 351. The fourth bonding pad 352 constitutes the other end portion of the third conductive pattern 35 near the short side 25d. The fourth bonding pad 352 is electrically connected to the front surface electrode 31a of the capacitor 31 through the third conductive pattern 35. Figure 4 The bonding wire 44 shown in the drawing is electrically connected to the front surface electrode 31a of the capacitor 31. That is, one end of the bonding wire 44 is bonded to the fourth bonding pad 352. The other end of the bonding wire 44 is bonded to the front surface electrode 31a.

[0077] The fourth conductive pattern 36 is a wiring pattern extending in the length direction of the mounting surface 25b. The fourth conductive pattern 36 is provided on portions of the mounting surface 25b near the short side 25c and near the long side 25f. The fourth conductive pattern 36 includes a third bonding pad 361 and a fifth bonding pad 362. The third bonding pad 361 constitutes one end portion of the fourth conductive pattern 36 near the short side 25c. From the third bonding pad 361, the fourth conductive pattern 36 extends toward the long side 25f. Figure 3 The other end of the bonding wire extending from the electrode pad 28c of the integrated circuit chip 26 shown in the drawing is connected to the third bonding pad 361. The fifth bonding pad 362 constitutes the other end portion of the fourth conductive pattern 36 near the short side 25d. The fifth bonding pad 362 is electrically connected to the front surface electrode 31a of the capacitor 31 through the fourth conductive pattern 36. Figure 4 The bonding wire 45 shown in the drawing is electrically connected to the front surface electrode 31a of the capacitor 31. That is, one end of the bonding wire 45 is bonded to the fifth bonding pad 362. The other end of the bonding wire 45 is bonded to the front surface electrode 31a.

[0078] The second bonding pad 351, the first bonding pad 332, and the third bonding pad 361 are provided side by side in this order on one end of the mounting surface 25b. That is, the first bonding pad 332 is positioned between the second bonding pad 351 and the third bonding pad 361 arranged along the short side 25c.

[0079] The third conductive pattern 35 and the fourth conductive pattern 36 have planar shapes that are line-symmetrical to each other, and the first conductive pattern 33 is interposed therebetween. Specifically, a distance from a center line of the first conductive pattern 33 to the third conductive pattern 35 is equal to a distance from the same center line to the fourth conductive pattern 36, and a planar shape of the third conductive pattern 35 is an inverted shape of a planar shape of the fourth conductive pattern 36. The first conductive pattern 33 is located between the third conductive pattern 35 and the fourth conductive pattern 36 in a lateral direction of the mounting surface 25b. The second mounting region 341 of the second conductive pattern 34 is also located between the third conductive pattern 35 and the fourth conductive pattern 36 in the lateral direction of the mounting surface 25b.

[0080] The operation of the light-receiving unit 20A having the above configuration will be described. During the operation of the light-receiving unit 20A, a power supply voltage for driving the integrated circuit chip 26 is applied from the lead pin 27d to the electrode pad 28d of the integrated circuit chip 26 via the bonding wire. The magnitude of the power supply voltage is, for example, 3.3 V. Noise included in the power supply voltage is removed by the capacitor 41. A bias voltage for driving the photodiode 21 is applied from the lead pin 27a to the third mounting region 342 of the second conductive pattern 34 via the bonding wire 46. The magnitude of the bias voltage is, for example, 20 V. Noise included in the bias voltage is removed by the capacitor 42.

[0081] The bias voltage supplied to the third mounting region 342 is applied to the second electrode 212 of the photodiode 21 through the second conductive pattern 34. In this state, when light is incident on the back surface 21b of the photodiode 21, a current is generated inside the photodiode 21. The current is output from the first electrode 211 of the photodiode 21 and reaches the first bonding pad 332 through the first conductive pattern 33. Then, the current is input to the electrode pad 28b of the integrated circuit chip 26 through the bonding wire. At this time, a return current having the same magnitude as the current is returned from the electrode pads 28a and 28c of the integrated circuit chip 26 to the third conductive pattern 35 and the fourth conductive pattern 36 through the bonding wire. The return current is absorbed by the photodiode 21 through the second electrode 212, the capacitor 31, and the second conductive pattern 34. The path from the electrode pads 28a and 28c to the second electrode 212 is referred to as a return path. The capacitor 31 prevents the bias voltage (for example, 20 V) applied to the photodiode 21 from being applied to the integrated circuit chip 26 having a withstand voltage of about 3 V, for example, via the return path. The integrated circuit chip 26 generates a voltage signal in accordance with the magnitude of the current input to the electrode pad 28b. The voltage signal is output from the electrode pads 28g and 28h of the integrated circuit chip 26 to the outside of the light-receiving unit 20A through the lead pins 27e and 27f.

[0082] Reference will be made to Figures 7A to 7C andFigure 8 A method of assembling the optical semiconductor device 2A of the present embodiment is described. First, a carrier 25 having a conductive film 32 on a mounting surface 25b is prepared. Next, as shown in Figure 7A In order to mount the photodiode 21 on the mounting surface 25b, the first electrode 211 of the photodiode 21 is connected to the first mounting region 331 through the conductive bump, and the second electrode 212 of the photodiode 21 is connected to the second mounting region 341 through the conductive bump.

[0083] Subsequently, as shown in Figure 7B The probe PI is brought into contact with the first bonding pad 332, and the other probe P2 is brought into contact with the second conductive pattern 34. More specifically, the probe P2 is brought into contact with the third mounting region 342 of the second conductive pattern 34. The probes PI and P2 are connected to a test device, respectively. Then, a test such as burn-in of the photodiode 21 is performed in a state in which a voltage is applied between the probe PI and the probe P2. Burn-in, also called burn-in test, is a test in which a device having an initial failure is looked for by applying a load such as a voltage and a temperature to the device. The power-on condition in the burn-in of the APD is, for example, a temperature of 250°C, a time of 24 hours, and a current of 120 μA.

[0084] Figure 9A and 9B are diagrams showing the tip shape of the probes PI and P2 used in the present embodiment. Figure 9A is a side view of the probes PI and P2. Figure 9B is a front view of the probes PI and P2. The probes PI and P2 have a cylindrical appearance, and have a circular flat end surface Pa at one end thereof in the axial direction. A plurality of (four in the figure) triangular pyramid-shaped protrusions Pb are arranged in the outer peripheral direction of the end surface Pa and protrude from the end surface Pa. The diameter of the end surface Pa is, for example, 0.2 mm.

[0085] Figure 10A and Figure 10B are diagrams showing the tip shape of the probe P3 as a comparative example. Figure 10A is a side view of the probe P3. Figure 10B is a front view of the probe P3. The probe P3 has a cylindrical appearance, and the end portion thereof in the axial direction is tapered into a conical shape. Then, the conical tip portion is brought into contact with the conductive pattern to conduct electricity between the test device and the conductive pattern. However, this tip shape of the probe P3 has a problem that it is difficult to make sufficient contact with the conductive pattern. On the other hand, according to the tip shapes of the probes PI and P2 shown in Figure 9A and 9B , since the contact area of the tip is increased, the contact performance with the conductive pattern can be improved.

[0086] Referring again toFigures 7A to 7C and Figure 8 Subsequently, as shown in Figure 7C , in order to mount the capacitor 31 on the mounting surface 25b, the back surface electrode of the capacitor 31 is connected to the third mounting region 342 through a conductive bump. Then, as shown in Figure 8 , the carrier 25 is placed on the surface 26b of the integrated circuit chip 26. Then, the front surface electrode 31a of the capacitor 31 is electrically connected to the fourth bonding pad 352 through the bonding wire 44, and the front surface electrode 31a is electrically connected to the fifth bonding pad 362 through the bonding wire 45. Before or after this, the second bonding pad 351 is electrically connected to the electrode pad 28a through the bonding wire, the first bonding pad 332 is electrically connected to the electrode pad 28b through the bonding wire, and the third bonding pad 361 is electrically connected to the electrode pad 28c through the bonding wire. The connection through the bonding wires 44 and 45 can be performed before the carrier 25 is placed on the integrated circuit chip 26.

[0087] The effect obtained by the optical semiconductor device 2A according to the present embodiment described above will be described. Generally, the photodiode 21 is tested in a state where the photodiode 21 is mounted on the carrier 25. In the optical semiconductor device 2A of the present embodiment, the first bonding pad 332 is contained in the first conductive pattern 33 together with the mounting region 331 connected to the first electrode 211. The third mounting region 342 is contained in the second conductive pattern 34 together with the second mounting region 341 connected to the second electrode 212. Therefore, when the photodiode 21 is tested, as shown in Figure 7B , one probe P1 can be brought into contact with the first bonding pad 332, and another probe P2 can be brought into contact with the second conductive pattern 34 (for example, the third mounting region 342). However, the first bonding pad 332 is provided side by side with the second bonding pad 351 and the third bonding pad 361 along the short side 25c of the mounting surface 25b. Therefore, when the probe P1 is brought into contact with the first bonding pad 332, if the positional accuracy of the probe P1 is low, as shown in Figure 11 , the probe P1 also comes into contact with the second bonding pad 351 or the third bonding pad 361. In particular, in the case of the probe shape of the present embodiment shown in Figure 9A and 9B , since the contact area is wider than that of the probe shape shown in Figure 10A and 10B , it is highly likely that such a phenomenon occurs. If the second bonding pad 351 or the third bonding pad 361 is included in the second conductive pattern 34, this contact causes a short circuit between the probes P1 and P2.

[0088] On the other hand, in the optical semiconductor device 2A of the present embodiment, the second conductive pattern 34 including the second mounting region 341 connected to the second electrode 212, the third conductive pattern 35 including the second bonding pad 351, and the fourth conductive pattern 36 including the third bonding pad 361 are separated from each other. Therefore, even in the case where the probe P1 in contact with the first bonding pad 332 is simultaneously in contact with the second bonding pad 351 or the third bonding pad 361, short-circuiting between the probes P1 and P2 can be prevented. Since the second conductive pattern 34 and the third conductive pattern 35 can be connected to each other via the capacitor 31 after the test, there is no problem even if they are electrically separated from each other during the test.

[0089] As in the present embodiment, the conductive film 32 can include the fourth conductive pattern 36. The fourth conductive pattern 36 includes the third bonding pad 361 disposed side by side with the first bonding pad 332 and the second bonding pad 351 along the short side 25c of the mounting surface 25b. The first bonding pad 332 is located between the second bonding pad 351 and the third bonding pad 361. The fourth conductive pattern 36 is separated from the first conductive pattern 33, the second conductive pattern 34, and the third conductive pattern 35. The front surface electrode 31a of the capacitor 31 is electrically connected to the fourth conductive pattern 36 via the bonding wire 45. According to this structure, it is possible to make the signal path including the third conductive pattern 35 and the signal path including the fourth conductive pattern 36 symmetrical to each other with the signal path including the first conductive pattern 33 interposed therebetween. In this case, it is possible to improve the signal transmission characteristics. In addition, since the first bonding pad 332 is located substantially at the center of the placement surface 25b in the lateral direction, the probe P1 can reliably come into contact with the first bonding pad 332 even in the case where the relative positions of the carrier 25 and the probe P1 in the same direction are significantly deviated.

[0090] As in the present embodiment, the third conductive pattern 35 and the fourth conductive pattern 36 can have planar shapes that are line-symmetrical to each other, and the first conductive pattern 33 is interposed therebetween. According to this configuration, the signal path including the third conductive pattern 35 and the signal path including the fourth conductive pattern 36 are symmetrical to each other with the signal path including the first conductive pattern 33 interposed therebetween. Therefore, it is possible to further improve the signal transmission characteristics.

[0091] In the assembling method of the optical semiconductor device 2A according to the present embodiment, the photodiode 21 is tested in a state where the photodiode 21 is mounted on the carrier 25. At this time, the second conductive pattern 34 including the second mounting region 341 connected to the second electrode 212 and the third conductive pattern 35 including the second bonding pad 351 and the fourth conductive pattern 36 including the third pad 361 are electrically separated from each other. Therefore, even in a case where the probe P1 in contact with the first bonding pad 332 is in contact with the second bonding pad 351 or the third bonding pad 361 at the same time, short-circuiting between the probes P1 and P2 can be prevented.

[0092] First modification example

[0093] Figure 12 is a plan view showing a light-receiving unit 20B according to a first modification example of the above-described embodiment. The light-receiving unit 20B includes an optical semiconductor device 2B. In the light-receiving unit 20B and the optical semiconductor device 2B, the configuration except for the shape of the conductive film on the carrier 25 is the same as that of the above-described embodiment. Figure 13 is a plan view showing Figure 12 is an enlarged plan view of the mounting surface 25b of the carrier 25 shown in Figure 13 In

[0094] As shown in Figure 13 instead of the conductive film 32 of the above-described embodiment, a conductive film 52 is provided on the mounting surface 25b of the carrier 25. The conductive film 52 is a metal film fixed on the mounting surface 25b. The constituent material of the conductive film 52 is the same as that of the conductive film 32 of the above-described embodiment. The conductive film 52 includes a first conductive pattern 53, a second conductive pattern 54, and a third conductive pattern 55. These conductive patterns 53 to 55 are separated from each other on the mounting surface 25b.

[0095] The first conductive pattern 53 is a wiring pattern extending in the length direction of the mounting surface 25b. The first conductive pattern 53 is provided at a position near the short side 25c of the central portion of the mounting surface 25b in the lateral direction. The first conductive pattern 53 includes a first mounting region 531 and a first land 532. The first mounting region 531 is a circular pattern constituting one end portion of the first conductive pattern 53 near the short side 25d. The first mounting region 531 is connected to the first electrode 211 of the photodiode 21 by a conductive bump using a conductive joining material such as AuSn solder. The first land 532 is a rectangular pattern provided on one end of the mounting surface 25b. The first land 532 is provided between the short side 25c and the first mounting region 531. The first land 532 constitutes the other end portion of the first conductive pattern 53 near the short side 25c. The other end portion of the first conductive pattern 53 near the short side 25c is connected to the electrode pad 28b of the integrated circuit chip 26 shown in Fig. 1. Figure 12 The other end of the joining wire extending from the electrode pad 28b of the integrated circuit chip 26 shown in Fig. 1 is connected to the first land 532.

[0096] The second conductive pattern 54 is a wiring pattern extending in the length direction of the mounting surface 25b and then in the lateral direction in an L shape. The second conductive pattern 54 includes a second mounting region 541, a third mounting region 542, a land 543, and current stopping regions 544 and 545.

[0097] The second mounting region 541 is a U-shaped pattern constituting one end portion of the second conductive pattern 54 near the short side 25c and is provided at a position near the long side 25f of the mounting surface 25b in the lateral direction. The second mounting region 541 is connected to the four second electrodes 212 of the photodiode 21 by conductive bumps using a conductive joining material such as AuSn solder. The first mounting region 531 of the first conductive pattern 53 is provided in a gap in the center of the second mounting region 541.

[0098] The third mounting region 542 is a square pattern provided on the other end of the mounting surface 25b. The third mounting region 542 is provided between the short side 25d and the second mounting region 541. The third mounting region 542 is connected to the back surface electrode of the capacitor 31 by a conductive bump using a conductive joining material such as AuSn solder. Figure 12 The other end of the joining wire 46 shown in Fig. 1 is joined to the land 543. That is, the land 543 is electrically connected to one electrode of the capacitor 42 via the joining wire 46. The land 543 is provided between the long side 25e and the third mounting region 542. That is, the land 543 is provided at positions near the short side 25d and near the long side 25e of the mounting surface 25b.

[0099] The flow-stopping region 544 is provided between the second mounting region 541 and the third mounting region 542, and physically separates these regions 541 and 542 from each other. The flow-stopping region 544 inhibits the flow of the conductive joining material from the second mounting region 541 into the third mounting region 542 and inhibits the flow of the conductive joining material from the third mounting region 542 into the second mounting region 541. The flow-stopping region 545 is provided between the third mounting region 542 and the joining pad 543, and physically separates the third mounting region 542 and the joining pad 543 from each other. The flow-stopping region 545 inhibits the flow of the conductive joining material from the third mounting region 542 into the joining pad 543. The flow-stopping regions 544 and 545 are films whose surfaces are made of a material having lower wettability with respect to the conductive joining material than the wettability of the regions 541 and 542 and the joining pad 543. The surfaces of the flow-stopping regions 544 and 545 are made of, for example, chromium (Cr).

[0100] The third conductive pattern 55 is a wiring pattern extending in an L shape along the length direction of the mounting surface 25b and then in the lateral direction, and includes a portion extending along the short side 25c of the mounting surface 25b and a portion extending along the long side 25e of the mounting surface 25b. Among these portions, the portion extending along the long side 25e includes the second joining pad 551 and the fourth joining pad 553. The second joining pad 551 constitutes one end portion of the above-described portion of the third conductive pattern 55 close to the short side 25c. From Figure 12 The other end portion of the above-described portion of the third conductive pattern 55 close to the short side 25d is constituted by the fourth joining pad 553. The fourth joining pad 553 is electrically connected to the front surface electrode 31a of the capacitor 31 through a joining wire.

[0101] The third conductive pattern 55 further includes a third joining pad 552 extending from the second joining pad 551 along the short side 25c of the mounting surface 25b. The third joining pad 552 is a square pattern provided between the long side 25f and the second joining pad 551. The third conductive pattern 55 is provided at a position close to the short side 25c and close to the long side 25f. The portion of the third conductive pattern 55 extending along the short side 25c is provided between the first joining pad 532 of the first conductive pattern 53 and the short side 25c. This portion extends from the second joining pad 551 to the third joining pad 552 in the lateral direction of the mounting surface 25b. That is, the second joining pad 551 forms one end of the above-described portion of the third conductive pattern 55. The third joining pad 552 forms the other end of the above-described portion of the third conductive pattern 55.

[0102] The second bonding pad 551, the first bonding pad 532, and the third bonding pad 552 are provided side by side along the short side 25c of the mounting surface 25b in this order and arranged. That is, the first bonding pad 532 is located between the second bonding pad 551 and the third bonding pad 552 in the lateral direction of the mounting surface 25b. From Figure 12 The end of the bonding wire extending from the electrode pad 28c of the integrated circuit chip 26 shown is connected to the third pad 552.

[0103] As in this modified example, the third conductive pattern 55 can include the third bonding pad 552 provided side by side with the first bonding pad 532 and the second bonding pad 551 along the short side 25c of the mounting surface 25b. The first bonding pad 532 is located between the second bonding pad 551 and the third bonding pad 552. In this case, compared to the case where the fourth conductive pattern 36 is provided as in the above-described embodiment, the width of the mounting surface 25b of the carrier 25 in the lateral direction, that is, the width of the mounting surface 25b in the direction along the short sides 25c and 25d can be made smaller. Therefore, this can contribute to reducing the size of the optical semiconductor device. Alternatively, another circuit component can be provided instead of the fourth conductive pattern 36.

[0104] Second Modified Example

[0105] Figure 14 is a plan view showing an optical receiving unit 20C according to a second modified example of the above-described embodiment. The optical receiving unit 20C includes an optical semiconductor device 2C. In the optical receiving unit 20C and the optical semiconductor device 2C, the configuration except for the shape of the conductive film on the carrier 25 is the same as that of the above-described embodiment. The shape of the conductive film on the carrier 25 is the same as that of the first modified example except for the parts to be described below.

[0106] Figure 15 is a plan view showing Figure 14An enlarged perspective view of the configuration near the short side 25c of the carrier 25 is shown. Like the first modification example, the conductive film 52 of the present modification example includes the third bonding pad 552 disposed side by side with the first bonding pad 532 and the second bonding pad 551 along the short side 25c of the mounting surface 25b. The first bonding pad 532 is located between the second bonding pad 551 and the third bonding pad 552. However, the third conductive pattern 55 on the mounting surface 25b does not have a portion extending along the short side 25c. Instead, a conductive film 56 is provided on the side of the carrier 25 including the short side 25c. The conductive film 56 is a metal film fixed to the side of the carrier 25, for example, formed of the same material as the conductive film 32. The conductive film 56 extends over the entire side of the carrier 25. The conductive film 56 is in contact with the second bonding pad 551 and the third bonding pad 552 on the short side 25c. Thus, the second bonding pad 551 is electrically connected to the third bonding pad 552 via the conductive film 56.

[0107] According to the present modification example, like the first modification example, the width of the mounting surface 25b of the carrier 25 in the lateral direction can be made smaller compared to the case where the fourth conductive pattern 36 is provided as in the above-described embodiment. Thus, this can contribute to reducing the size of the optical semiconductor device. Alternatively, another circuit component can be provided instead of the fourth conductive pattern 36. Further, in the conductive film 52 on the mounting surface 25b, the portion of the third conductive pattern 55 connecting the second bonding pad 551 and the third bonding pad 552 to each other is not necessary, and thus the mounting surface 25b of the carrier 25 can be made smaller. Thus, this can further contribute to reducing the size of the optical semiconductor device. It is also possible to electrically connect the third conductive pattern 55 to the electrode pads 28a and 28c of the integrated circuit chip 26 via the conductive film 56. In that case, the number of wires on the mounting surface 25b can be reduced.

[0108] Comparative Example

[0109] Figure 16 is a plan view showing the shape of a conductive film 60 according to the comparative example provided on the mounting surface 25b of the carrier 25. The conductive film 60 has a first conductive pattern 61 and a second conductive pattern 62 disposed apart from each other. The first conductive pattern 61 includes a first mounting region 611 and a first bonding pad 612. The first mounting region 611 constitutes one end portion of the first conductive pattern 61, and is connected to the first electrode 211 of the photodiode 21 by a conductive joint using a conductive bonding material such as an AuSn solder. The first bonding pad 612 constitutes the other end portion of the first conductive pattern 61. One end of a bonding wire extending from the electrode pad 28b of the integrated circuit chip 26 is connected to the first bonding pad 612.

[0110] The second conductive pattern 62 includes a second mounting area 621, a third mounting area 622, and a probe contact pad 623. The second mounting area 621 is a U-shaped pattern disposed on approximately the central portion of the mounting surface 25b. The second mounting area 621 is connected to the four second electrodes 212 of the photodiode 21 via a conductive junction using a conductive bonding material such as AuSn solder. The first mounting area 611 of the first conductive pattern 61 is disposed in the central gap of the second mounting area 621. The third mounting area 622 is disposed side-by-side with the first bonding pad 612 along one end of the mounting surface 25b. The third mounting area 622 is connected to the back electrode of the capacitor 31 via a conductive junction using a conductive bonding material such as AuSn solder. The probe contact pad 623 is disposed at the other end of the mounting surface 25b. The probe contact pad 623 is the area used to bring a probe into contact with it during testing.

[0111] In this comparative example, when testing photodiode 21, one probe is brought into contact with the first bonding pad 612, and another probe is brought into contact with a probe contact pad 623 positioned diagonally opposite to the first bonding pad 612. However, if the probe positioning accuracy is low, one probe may also come into contact with the third mounting area 622. In this case, probes with different potentials short-circuit with each other, and the test cannot be performed correctly. Therefore, as... Figure 17 As shown, the third mounting area 622 can be isolated from the second mounting area 621 and the probe contact pad 623. Therefore, even if one probe is in contact with the third mounting area 622, short circuits between probes can be prevented.

[0112] Figures 18A to 18C as well as Figure 19 A diagram showing the assembly process of the optical semiconductor device according to a comparative example is provided. First, as... Figure 18A As shown, with the photodiode 21 mounted on the mounting surface 25b, probe P1 is brought into contact with the first bonding pad 612, and probe P2 is brought into contact with the probe contact pad 623. Probes P1 and P2 are respectively connected to a test device. Then, a test such as aging is performed with a voltage applied between probes P1 and P2. Next, as... Figure 18B As shown, for example, a conductive resin 71 is used to electrically connect the second mounting region 621 to the third mounting region 622. Instead of the conductive resin 71, solder or wires can be used for bonding. Subsequently, as... Figure 18C As shown, capacitor 31 is mounted on the third mounting area 622. Finally, as Figure 19Wire bonding is performed between the electrode pad 28b of the integrated circuit chip 26 and the first bonding pad 612, as shown in the middle. Further, wire bonding is performed between the electrode pad 28a of the integrated circuit chip 26 and the front surface electrode 31a of the capacitor 31, and between the electrode pad 28c of the integrated circuit chip 26 and the front surface electrode 31a of the capacitor 31.

[0113] However, the optical semiconductor device according to the comparative example has the following problems. First, the third mounting region 622 is narrowed by the conductive resin 71 or the like. Therefore, in the process shown in the middle, the mounting area of the capacitor 31 is limited, and the degree of freedom in selecting the capacitor 31 is reduced. In the case where the second mounting region 621 is connected to the third mounting region 622 by wire bonding, the capacitor 31 is mounted in a region adjacent to the wire, and the wire can be cut when the capacitor is mounted. Figure 18C

[0114] To solve these problems, in the above-described embodiments and each modification example, the mounting region of the capacitor 31 is located near the short side 25d on the side opposite to the second bonding pad 351 and the third bonding pad 361. Therefore, the mounting area of the capacitor 31 is not limited, and the degree of freedom in selecting the capacitor 31 is not reduced. Since the region in which the capacitor 31 is mounted is not adjacent to the wire, the wire is not likely to be cut when the capacitor 31 is mounted.

[0115] The optical semiconductor device and the method of assembling an optical semiconductor device according to the present disclosure are not limited to the above-described embodiments, and various modifications can be made. For example, in the above-described embodiments and each modification example, a case where the optical semiconductor device of the present disclosure is applied to an optical receiving module for optical communication is shown, but the optical semiconductor device of the present disclosure can be applied to various modules other than this.​

Claims

1. An optical semiconductor device comprising: a semiconductor light-receiving element having a first electrode and a second electrode having a conductivity type opposite to that of the first electrode; a capacitor having one electrode and another electrode; a carrier having a mounting surface and made of a dielectric, the semiconductor light-receiving element and the capacitor being mounted on the mounting surface; and a first conductive pattern, a second conductive pattern, and a third conductive pattern provided on the mounting surface of the carrier, wherein the first conductive pattern includes a first mounting region connected to the first electrode, wherein the first conductive pattern includes a first bonding pad provided on one end of the mounting surface, wherein the second conductive pattern includes a second mounting region connected to the second electrode, wherein the second conductive pattern includes a third mounting region provided on the other end of the mounting surface and connected to the one electrode of the capacitor, wherein the third conductive pattern includes a second bonding pad provided side by side with the first bonding pad on the one end of the mounting surface, wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are separated from each other, wherein the another electrode of the capacitor and the third conductive pattern are electrically connected to each other via a wire, and wherein the semiconductor light-receiving element is interposed between the first bonding pad and the capacitor.

2. The optical semiconductor device according to claim 1, further comprising: a fourth conductive pattern including a third bonding pad provided side by side with the first bonding pad and the second bonding pad on the one end of the mounting surface, wherein the first bonding pad is located between the second bonding pad and the third bonding pad, wherein the fourth conductive pattern is separated from the first conductive pattern, the second conductive pattern, and the third conductive pattern, and wherein the another electrode of the capacitor and the fourth conductive pattern are electrically connected to each other via a wire. The third conductive pattern and the fourth conductive pattern have planar shapes that are line-symmetric to each other, and the first conductive pattern is interposed between the third conductive pattern and the fourth conductive pattern.

3. The optical semiconductor device according to claim 2, wherein 4. The optical semiconductor device according to claim 1, the third conductive pattern extends from the second bonding pad along the one end of the mounting surface, and further includes a third bonding pad provided side by side with the first bonding pad, and wherein, wherein the first bonding pad is located between the second bonding pad and the third bonding pad.

5. The optical semiconductor device according to claim 1, further comprising: a third bonding pad provided side by side with the first bonding pad and the second bonding pad on the one end of the mounting surface, wherein the first bonding pad is located between the second bonding pad and the third bonding pad, and wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are separated from each other. The second bonding pad and the third bonding pad are electrically connected to each other via a conductive film provided on a side surface of the carrier.

6. A method of assembling an optical semiconductor device, comprising the steps of: preparing a carrier having a first conductive pattern, a second conductive pattern, and a third conductive pattern on a mounting surface, the first conductive pattern including a first bonding pad and a first mounting region, the second conductive pattern including a second mounting region and a third mounting region, and wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are separated from each other; mounting a semiconductor light-receiving element on the carrier and electrically connecting a first electrode of the semiconductor light-receiving element to the first mounting region of the carrier and electrically connecting a second electrode of the semiconductor light-receiving element to the second mounting region of the carrier; performing a test in a state in which one probe is brought into contact with the first bonding pad and another probe is brought into contact with the second conductive pattern and a voltage is applied between the one probe and the another probe; after the test, mounting a capacitor on the carrier and electrically connecting one electrode of the capacitor to the third mounting region; and wire-bonding between the other electrode of the capacitor and the third conductive pattern using a first wire, wherein the semiconductor light-receiving element is interposed between the first bonding pad and the capacitor.

7. The method of assembling an optical semiconductor device according to claim 6, further comprising the steps of: wire-bonding between the other electrode of the capacitor and a fourth conductive pattern of the carrier using a second wire, wire-bonding between the first bonding pad and a first terminal using a third wire, wire-bonding between a second bonding pad and a second terminal using a fourth wire, and wire-bonding between a third bonding pad and a third terminal using a fifth wire, wherein the third conductive pattern includes the second bonding pad, the second bonding pad being placed side by side with the first bonding pad on one end of the mounting surface, and wherein the fourth conductive pattern includes the third bonding pad, the third bonding pad being placed side by side with the first bonding pad on the one end of the mounting surface.

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