Semiconductor device

Abstract

The present invention provides a semiconductor device capable of suppressing an increase in parasitic inductance or parasitic resistance of a path for a collector current or a drain current. Transistor columns are arranged in two columns on a substrate. Each of the two columns of transistor columns is composed of a plurality of transistors arranged in a first direction, and the two columns of transistor columns are arranged at intervals in a second direction orthogonal to the first direction. In a plan view, a first wiring is arranged in a region between the two columns of transistor columns. The first wiring is connected to the collectors or drains of the plurality of transistors in the two columns of transistor columns. In a plan view, a first bump overlaps the first wiring, is arranged between the two columns of transistor columns, and is connected to the first wiring.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] As a power amplifier circuit element for a mobile terminal or the like, a semiconductor chip provided with a heterojunction bipolar transistor is used. The semiconductor chip is flip-chip mounted on a mounting substrate via a plurality of bumps provided on its surface. Such a mounting method is called an inverted mounting. For example, a semiconductor chip for a power amplifier circuit that is flip-chip mounted is described in Patent Document 1 below.

[0003] For the semiconductor chip described in Patent Document 1, the transistor has a plurality of finger-like structures (sometimes referred to as "cells"). If one finger-like structure is regarded as one transistor, it can be said that a plurality of transistors can be arranged in at least two columns. The transistor columns are arranged in parallel with each other. Two emitter bumps are arranged so as to overlap the two columns of transistor columns respectively. A collector wiring is arranged in the region between the two columns of transistor columns. The collector wiring extends from the region between the two columns of transistor columns in the arrangement direction of the transistors to the outside thereof. A collector bump is arranged in the outside region, and the collector bump is connected to the collector wiring in the outside region.

[0004] Patent Document 1: U.S. Patent Publication No. 2019 / 0148172.

[0005] In the semiconductor chip described in Patent Document 1, the collector wiring connecting the collector bump and the collector of the transistor is arranged between the two columns of transistor columns, and the collector bump is arranged outside this region. The collector current flows from the collector bump through the collector wiring in the region between the two columns of transistor columns to the collector of each transistor. Since the collector current flows through the collector wiring in the arrangement direction of the plurality of transistors, the parasitic inductance or parasitic resistance of the path of the collector current is likely to increase. In the case of using a field effect transistor as the transistor and adopting the same structure, the parasitic inductance or parasitic resistance of the path of the drain current is likely to increase. The parasitic inductance or parasitic resistance is an important factor in reducing the maximum output of the amplifier circuit. Summary of the Invention

[0006] An object of the present invention is to provide a semiconductor device capable of suppressing an increase in parasitic inductance or parasitic resistance of a path of a collector current or a drain current.

[0007] According to one aspect of the present invention, there is provided a semiconductor device including:

[0008] a substrate; and

[0009] two columns of transistor columns provided on the substrate,

[0010] Each of the two columns of transistor columns described above is composed of a plurality of transistors arranged in a first direction, and the two columns of transistor columns are arranged at intervals in a second direction orthogonal to the first direction.

[0011] The semiconductor device further includes:

[0012] A first wiring, which is arranged in a region between the two columns of transistor columns in a top view and is connected to the collectors or drains of the plurality of transistors in the two columns of transistor columns; and

[0013] At least one first bump, which overlaps with the first wiring in a top view, is arranged between the two columns of transistor columns, and is connected to the first wiring.

[0014] The collector current or drain current flows to the transistor via the first bump and the first wiring. When the first wiring extends to the outside of the region between the two columns of transistor columns and the first bump is arranged in the extended portion, the collector current or drain current flows through the first wiring in the first direction from the first bump to the transistor. In contrast, if the structure according to the above aspect of the present application invention is adopted, the collector current or drain current flows through two layers, namely the first bump and the first wiring, in the first direction. Therefore, the flow path cross-section of the path of the collector current or drain current flowing in the first direction becomes larger. As a result, the parasitic resistance and parasitic inductance of the path of the collector current or drain current can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a diagram showing the positional relationship in a top view of a plurality of components of a semiconductor device according to a first embodiment.

[0016] Figure 2 is Figure 1 a cross-sectional view taken along the dotted line 2-2 of

[0017] Figure 3 It is a cross-sectional view of a power amplification module including Figure 1 and Figure 2 the semiconductor device shown in

[0018] Figure 4 It is a block diagram of a power amplification module including a semiconductor device based on a first embodiment.

[0019] Figure 5 It is an equivalent circuit diagram of an amplification circuit module including a semiconductor device based on a first embodiment.

[0020] Figure 6 It is a diagram showing the positional relationship in a top view of a plurality of components of a semiconductor device based on a comparative example.

[0021] Figure 7 is Figure 6 a cross-sectional view taken along the dash-dot line 7-7.

[0022] Figure 8 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a semiconductor device based on a second embodiment.

[0023] Figure 9 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a semiconductor device based on a third embodiment.

[0024] Figure 10 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a semiconductor device based on a fourth embodiment.

[0025] Figure 11 is an equivalent circuit diagram including an amplifier circuit module of a semiconductor device based on a fifth embodiment.

[0026] Figure 12 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a power stage amplifier circuit and its peripheral circuits of a semiconductor device based on a fifth embodiment.

[0027] Figure 13 is Figure 12 a cross-sectional view taken along the dash-dot line 13-13.

[0028] Figure 14 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a power stage amplifier circuit and its peripheral circuits of a semiconductor device based on a modified example of a fifth embodiment.

[0029] Figure 15 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a power stage amplifier circuit and its peripheral circuits of a semiconductor device based on a sixth embodiment.

[0030] Figure 16 is Figure 15 a cross-sectional view taken along the dash-dot line 16-16.

[0031] Figure 17 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a power stage amplifier circuit and its peripheral circuits of a semiconductor device based on a seventh embodiment.

[0032] Figure 18 is Figure 17 a cross-sectional view taken along the dash-dot line 18-18.

[0033] Figure 19 is Figure 17 a cross-sectional view taken along the dash-dot line 19-19.

[0034] Figure 20 This is a top view showing the positional relationship of multiple components of the power stage amplifier circuit and its peripheral circuits of the semiconductor device based on the eighth embodiment.

[0035] Figure 21 This is a top view showing the positional relationship of multiple components of the power stage amplifier circuit and its peripheral circuits of the semiconductor device based on the ninth embodiment.

[0036] Figure 22 is Figure 21 a cross-sectional view taken along the dashed line 22-22.

[0037] Description of Reference Numerals

[0038] 20… Substrate; 21… Subset electrode layer; 22… Element isolation region; 30… Bipolar transistor; 31… Collector layer; 32… Base layer; 33… Emitter layer; 34… Emitter mesa layer; 35… Transistor column; 40B… Base electrode; 40C… Collector electrode; 40E… Emitter electrode; 41B… Base electrode; 41C… Collector electrode; 41E… Emitter electrode; 42B… Base electrode; 42C… Collector electrode; 42E… Emitter electrode; 50B… Base wiring of the first layer; 50C… Collector lead-out wiring of the first layer; 50E… Emitter wiring of the first layer; 51B… Base wiring of the first layer; 51C… Collector wiring of the first layer (first wiring); 51E… Emitter wiring of the first layer; 51H… Higher harmonic terminal wiring of the first layer (third wiring); 51T… Output wiring of the first layer (second wiring); 52B… Base wiring of the first layer; 52C… Collector wiring of the first layer; 52H… Higher harmonic terminal wiring of the first layer (third wiring); 52T… Output wiring of the first layer (second wiring); 60C… Collector wiring of the second layer; 60E… Emitter wiring of the second layer; 60H… Higher harmonic terminal wiring of the second layer; 60T… Output wiring of the second layer; 70C… Collector bump (first bump); 70E… Emitter bump; 70H… Higher harmonic terminal bump (third bump); 70T… Output bump (second bump); 71C… Collector bump; 71T… Output bump (fourth bump); 75… Solder layer; 80… Input capacitor; 81… Lower electrode of the capacitor; 82… Resistance element; 83… Bias input wiring; 88… High-frequency signal input wiring; 90, 91, 92… Insulating film; 94… Opening; 95, 96, 97… Capacitor dielectric film; 100… Semiconductor chip; 110… Driver stage amplifier circuit; 111… Inter-stage impedance matching circuit; 112… Power stage amplifier circuit; 113… Driver stage bias circuit; 114… Power stage amplifier circuit; 115… Protection circuit; 120… Higher harmonic terminal circuit; 121… Higher harmonic terminal capacitor (second capacitor); 123… Higher harmonic terminal inductor; 125… Output capacitor (first capacitor); 129… Inductor; 130… Transistor; 131 Collector layer; 132… Base layer; 133… Emitter layer; 134… Emitter mesa layer; 135… Collector layer; 136… Base layer; 137… Emitter layer; 138… Emitter mesa layer; 150… Power amplifier module; 151… Input side impedance matching circuit; 152… Output side impedance matching circuit; 153, 154… Inductor; 200… Mounting substrate; 201C… Pad for collector; 201E… Pad for emitter; 202… Via conductor; 203… Inner layer ground plane; 205… Ground plane on the lower surface; 210… Mounting substrate 211… Output pad; 212… Pad for collector; 215… Via conductor; 216… Internal wiring;219…Ground plane.; Detailed implementation

[0039] [First embodiment]

[0040] Refer to Figures 1 to 5 the accompanying drawings, and a semiconductor device according to the first embodiment will be described.

[0041] Figure 1 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a semiconductor device according to the first embodiment. Two columns of transistor columns 35 are arranged on a substrate made of semiconductor. Each column of transistors in the two columns of transistor columns 35 includes a plurality of bipolar transistors 30 arranged in the first direction D1. In addition, the two columns of transistor columns 35 are arranged at intervals in a second direction D2 orthogonal to the first direction D1.

[0042] Each bipolar transistor 30 includes a collector layer 31, a base layer 32, and an emitter layer 33. In a plan view, the outer peripheral lines of the collector layer 31, the base layer 32, and the emitter layer 33 are substantially the same. In one bipolar transistor 30, two collector electrodes 40C are arranged at positions sandwiching the collector layer 31 in the first direction D1. The collector electrode 40C is electrically connected to the collector layer 31 via a subset collector layer provided in the surface layer portion of the substrate. Refer to Figure 2 for a description of the subset collector layer.

[0043] A base electrode 40B is electrically connected to the base layer 32, and an emitter electrode 40E is electrically connected to the emitter layer 33. In a plan view, each emitter electrode 40E has a shape that is long in the second direction D2 and is included in the emitter layer 33. In a plan view, the base electrode 40B has a U-shaped shape that surrounds the emitter electrode 40E from three directions and is open to the region between the two columns of transistor columns 35, and is included in the base layer 32. In Figure 1 relatively high-density upwardly inclined hatching is added to the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E.

[0044] A plurality of collector lead wirings 50C, collector wirings 51C (first wirings), a plurality of emitter wirings 50E, a plurality of base wirings 50B, a plurality of lower capacitor electrodes 81, and a bias input wiring 83 are arranged on the wiring layer of the first layer on the substrate. In Figure 1 relatively low-density downwardly inclined hatching is added to each wiring of the wiring layer of the first layer.

[0045] A plurality of collector lead wirings 50C are respectively led out from the collector electrodes 40C toward the region between the two columns of transistor columns 35. Further, the collector lead wirings 50C led out from the two collector electrodes 40C disposed between the collector layers 31 of two bipolar transistors 30 adjacent in the first direction D1 are gathered into one. The collector wiring 51C is disposed in the region between the two columns of transistor columns 35 and is connected to the plurality of collector lead wirings 50C respectively led out from the collector electrodes 40C of the plurality of bipolar transistors 30 included in the two columns of transistor columns 35.

[0046] A plurality of emitter wirings 50E are respectively disposed at positions overlapping the emitter electrodes 40E in a plan view corresponding to the emitter electrodes 40E. The emitter wirings 50E are connected to the corresponding emitter electrodes 40E. In this specification, unless otherwise specified, two components overlapping in a plan view means that at least a part of one component overlaps at least a part of the other component in a plan view.

[0047] A plurality of base wirings 50B are respectively led out from the base electrodes 40B in a direction away from the region between the two columns of transistor columns 35. A plurality of capacitor lower electrodes 81 are arranged side by side along the first direction D1 outside the two columns of transistor columns 35. The plurality of capacitor lower electrodes 81 are respectively connected to the base electrodes 40B of the bipolar transistors 30 via the base wirings 50B. Further, the plurality of base wirings 50B are respectively connected to a bias input wiring 83 via a resistor element 82. A base current is supplied to the base electrode 40B of the bipolar transistor 30 from the bias input wiring 83 via the resistor element 82 and the base wiring 50B.

[0048] Two emitter wirings 60E, one collector wiring 60C, and a high-frequency signal input wiring 88 are disposed on the wiring layer of the second layer on the substrate. The two emitter wirings 60E are respectively disposed at positions overlapping the two columns of transistor columns 35 and have a shape that is longer in the first direction D1 in a plan view. The collector wiring 60C is disposed between the two columns of transistor columns 35 and has a shape that is longer in the first direction D1 in a plan view.

[0049] The high-frequency signal input wiring 88 overlaps the plurality of capacitor lower electrodes 81. The overlapping portion of the two forms an input capacitor 80. The high-frequency input signal is supplied to the base electrode 40B via the high-frequency signal input wiring 88, the input capacitor 80, and the base wiring 50B.

[0050] Emitter bumps 70E are arranged so as to overlap each of the two emitter wirings 60E. A collector bump 70C (first bump) is arranged so as to overlap the collector wiring 60C. Each of the emitter bumps 70E and the collector bump 70C has a shape that is longer in the first direction D1 in plan view (e.g., oblong, elliptical, racetrack shape), etc.

[0051] The emitter electrodes 40E of the plurality of bipolar transistors 30 are grounded via the emitter wirings 50E, 60E, and the emitter bumps 70E. The collector electrodes 40C of the plurality of bipolar transistors 30 are connected to the collector bumps 70C via the collector lead-out wirings 50C, the collector wiring 51C, and the collector wiring 60C.

[0052] Figure 2 is Figure 1 A cross-sectional view taken along the dotted line 2-2. A subset collector layer 21 is arranged in a region of a part of the upper surface of the substrate 20. As the substrate 20, for example, a semi-insulating GaAs substrate is used. The subset collector layer 21 is, for example, an n-type GaAs layer epitaxially grown on the substrate 20. The portion other than the subset collector layer 21 in the n-type GaAs layer is set as an element isolation region 22 insulated by ion implantation.

[0053] On the subset collector layer 21, a collector layer 31, a base layer 32, and an emitter layer 33 are sequentially stacked. For example, the collector layer 31 is formed of n-type GaAs, the base layer 32 is formed of p-type GaAs, and the emitter layer 33 is formed of n-type InGaP. An emitter mesa layer 34 is arranged in a region of a part of the upper surface of the emitter layer 33. The emitter mesa layer 34 has a double-layer structure in which a cap layer and a contact layer are sequentially stacked. For example, the cap layer is formed of n-type GaAs, and the contact layer is formed of n-type InGaAs. The region of the emitter layer 33 that overlaps the emitter mesa layer 34 in plan view functions as the emitter region of the bipolar transistor 30, and the other regions are depleted. Sometimes the portion of the emitter layer 33 that functions as the emitter region is referred to as the intrinsic emitter layer, and the depleted portion is referred to as the flange layer.

[0054] A base electrode 40B is arranged in a region of the upper surface of the emitter layer 33 where the emitter mesa layer 34 is not arranged. The base electrode 40B is electrically connected to the base layer 32 via an alloyed region that penetrates the emitter layer 33 and reaches the base layer 32. An emitter electrode 40E is arranged on the emitter mesa layer 34. The emitter electrode 40E is electrically connected to the emitter layer 33 via the emitter mesa layer 34.

[0055] In two columns of transistor columns 35 ( Figure 1A semiconductor layer is left on the element separation region 22 between them and is formed by the same process as the collector layer 31, the base layer 32, and the emitter layer 33.

[0056] An insulating film 90 is disposed over the entire region of the substrate 20 so as to cover the base electrode 40B, the emitter electrode 40E, and the semiconductor layer left on the element separation region 22. On the insulating film 90, the first-layer emitter wiring 50E and the collector wiring 51C are disposed. The emitter wiring 50E is connected to the emitter electrode 40E through an opening provided in the insulating film 90. The collector wiring 51C is Figure 2 electrically connected to the collector electrode 40C ( Figure 1 ) through a collector lead-out wiring 50C in a region where it does not appear in the cross-section.

[0057] An insulating film 91 is disposed over the entire region of the substrate 20 so as to cover the first-layer emitter wiring 50E and the collector wiring 51C. The insulating film 91 includes, for example, two layers of a lower SiN film and a polyimide film thereon.

[0058] On the insulating film 91, the second-layer emitter wiring 60E and the collector wiring 60C are disposed. The second-layer emitter wiring 60E is connected to the first-layer emitter wiring 50E through an opening provided in the insulating film 91. The second-layer collector wiring 60C is connected to the first-layer collector wiring 51C through an opening provided in the insulating film 91.

[0059] An insulating film 92 is disposed over the entire region of the substrate 20 so as to cover the second-layer emitter wiring 60E and the collector wiring 60C. The insulating film 92 includes, for example, two layers of a lower SiN film and a polyimide film thereon.

[0060] Emitter bumps 70E and collector bumps 70C are disposed on the insulating film 92. The emitter bumps 70E are connected to the second-layer emitter wiring 60E through openings provided in the insulating film 92. The collector bumps 70C are connected to the second-layer collector wiring 60C through openings provided in the insulating film 92. Solder layers 75 are disposed on the emitter bumps 70E and the collector bumps 70C, respectively.

[0061] Figure 3 is a cross-sectional view of a power amplification module including the Figure 1 and Figure 2 shown semiconductor device. Provided are Figure 1 and Figure 2 shown semiconductor devices as one semiconductor chip 100. The semiconductor chip 100 is flip-chip mounted on a mounting substrate 200.

[0062] As the mounting substrate 200, a printed circuit board is used, for example. The mounting substrate 200 is sometimes also referred to as a module substrate or a package substrate. On one surface of the mounting substrate 200 (hereinafter referred to as the upper surface), a plurality of emitter pads 201E and collector pads 201C are provided. The emitter bumps 70E and collector bumps 70C of the semiconductor chip 100 are connected to the emitter pads 201E and collector pads 201C via solder layers 75, respectively.

[0063] A plurality of ground planes 203 are disposed in the inner layer of the mounting substrate 200. Also, a ground plane 205 is disposed on the lower surface of the mounting substrate 200 opposite to the upper surface. The emitter pads 201E are connected to the plurality of ground planes 203 in the inner layer and the ground plane 205 on the lower surface via a plurality of via conductors 202.

[0064] Figure 4 It is a block diagram of a power amplification module 150 including a semiconductor device based on the first embodiment. In this specification, a "semiconductor device" means a semiconductor chip configured with an amplification circuit, or an amplification circuit module including the semiconductor chip, circuit components, and a mounting substrate on which the semiconductor chip and circuit components are mounted. The power amplification module 150 includes a semiconductor chip 100, an input-side impedance matching circuit 151, an output-side impedance matching circuit 152, inductors 153, 154. These circuit components are mounted on the mounting substrate 200 ( Figure 3 ).

[0065] The semiconductor chip 100 includes a drive-stage amplification circuit 110, an inter-stage impedance matching circuit 111, and a power-stage amplification circuit 112. A power supply voltage Vcc is applied to the drive-stage amplification circuit 110 via the inductor 153. A power supply voltage Vcc is applied to the power-stage amplification circuit 112 via the inductor 154.

[0066] A high-frequency signal is input to the drive-stage amplification circuit 110 via the input-side impedance matching circuit 151. The high-frequency signal amplified by the drive-stage amplification circuit 110 is input to the power-stage amplification circuit 112 via the inter-stage impedance matching circuit 111. The high-frequency signal amplified by the power-stage amplification circuit 112 is input to an external device, such as an antenna element, via the output-side impedance matching circuit 152.

[0067] The power-stage amplification circuit 112 includes Figure 1 and Figure 2 a plurality of bipolar transistors 30 shown. The emitter bumps 70E ( Figure 1 , Figure 2 ) are grounded. A high-frequency signal is input to the high-frequency signal input wiring 88 ( Figure 1 ) via the inter-stage impedance matching circuit 111. The collector bumps 70C ( Figure 1 ,Figure 2 ) is connected to the output - side impedance - matching circuit 152 and is connected to the power - supply voltage Vcc via the inductor 154. The inductor 154 functions as a choke coil that blocks high - frequency signals.

[0068] Figure 5 is an equivalent circuit diagram of an amplifier - circuit module including the semiconductor device based on the first embodiment. The amplifier - circuit module according to the first embodiment includes a driver - stage amplifier circuit 110, a power - stage amplifier circuit 112, a driver - stage bias circuit 113, a power - stage bias circuit 114, inductors 153, 154, an input - side impedance - matching circuit 151, and an output - side impedance - matching circuit 152. In Figure 5 , the inductor enclosed by the cylindrical figure represents the parasitic inductor of the bump.

[0069] The power - stage amplifier circuit 112 includes a plurality of unit cells each composed of a bipolar transistor 30, an input capacitor 80, and a resistance element 82. The plurality of unit cells are connected in parallel with each other. In addition, in Figure 5 , one of the plurality of unit cells is representatively shown. A collector bump 70C is connected to the collector of the bipolar transistor 30. The power - supply voltage Vcc is applied to the collector of the bipolar transistor 30 via the inductor 154 acting as a choke coil and the collector bump 70C.

[0070] A bias current is supplied from the power - stage bias circuit 114 to the base of the bipolar transistor 30 via the resistance element 82. The power - stage bias circuit 114 includes a resistance element R1, transistors Q1, Q2, and a resistance element R2 connected in series between a bias - control terminal VBp and the ground line. The transistors Q1, Q2 are diode - connected and operate as diodes. The power - stage bias circuit 114 further includes an emitter - follower transistor Q3. The transistor Q1 and the emitter - follower transistor Q3 form a current mirror. A bias voltage Vbat is applied to the collector of the emitter - follower transistor Q3. The emitter of the emitter - follower transistor Q3 is connected to the base of the bipolar transistor 30 via the resistance element 82. The power - stage bias circuit 114 supplies a bias current corresponding to the control voltage given to the bias - control terminal VBp to the bipolar transistor 30.

[0071] The basic circuit configurations of the driver - stage amplifier circuit 110, the driver - stage bias circuit 113, and the inductor 153 are the same as those of the power - stage amplifier circuit 112, the power - stage bias circuit 114, and the inductor 154. However, the number of unit cells and the dimensions of each element are different between the driver - stage amplifier circuit 110 and the power - stage amplifier circuit 112. In addition, the driver - stage bias circuit 113 supplies a bias current corresponding to the control voltage given to the bias - control terminal VBd. In Figure 5The description of the collector bump disposed between the collector of the bipolar transistor in the driver-stage amplifier circuit 110 and the inductor 153 is omitted.

[0072] The high-frequency input signal is input to the driver-stage amplifier circuit 110 via the input-side impedance matching circuit 151. The high-frequency signal amplified by the driver-stage amplifier circuit 110 is input to the base of the bipolar transistor 30 via the input capacitor 80 of the power-stage amplifier circuit 112. The emitter of the bipolar transistor 30 is grounded via the parasitic inductance of the emitter bump 70E.

[0073] Next, Figure 6 and Figure 7 shown in the comparative example, the excellent effects of the semiconductor device according to the first embodiment will be described.

[0074] Figure 6 is a diagram showing the positional relationship in plan view of a plurality of components of the semiconductor device according to the comparative example, Figure 7 is Figure 6 a cross-sectional view taken along the dotted line 7-7 of Figure 1 , Figure 2 ). The differences from the semiconductor device based on the first embodiment (

[0075] ) will be described. In the comparative example, the collector wiring of the first layer includes a collector wiring 51C disposed between two columns of transistor columns 35, and a collector wiring 52C extending from the collector wiring 51C toward one side in the first direction D1.

[0076] The collector wiring of the second layer also includes a collector wiring 60C that overlaps the collector wiring 51C in plan view, and a collector wiring 61C that overlaps the extended portion of the collector wiring 52C. The collector bump 71C is disposed at a position overlapping the extended portion of the collector wiring 61C, and no collector bump is disposed between the two columns of transistor columns 35. Figure 7 In the structure of the comparative example, from the collector bump 71C to the collector electrode 40C, the collector current flows through the collector wiring 51C of the first layer and the collector wiring 60C of the second layer in the first direction D1. As

[0077] shown, the current path of the collector current flowing in the first direction D1 is composed of only two layers, namely the collector wiring 51C of the first layer and the collector wiring 60C of the second layer. Figure 3 ) and Figure 3 ) and Figure 2 ) and Figure 2), and then flows through the collector lead wiring 50C in the second direction D2 to reach the collector electrode 40C. The flow path of the collector current flowing in the first direction D1 includes four layers: the collector pad 201C, the collector bump 70C, the collector wiring 60C of the second layer, and the collector wiring 51C of the first layer. The dimensions in the thickness direction and the second direction D2 of this flow path are larger than those of the flow path of the semiconductor device according to the comparative example.

[0078] In the first embodiment, compared with the comparative example ( Figure 6 , Figure 7 ), since the flow path cross-section of the path of the collector current flowing in the first direction D1 is larger, excellent effects such as smaller parasitic resistance and parasitic inductance of the path of the collector current are obtained. In particular, by making the collector bump 70C have a shape that is longer in the first direction D1, it is possible to suppress the deviation of the parasitic resistance or parasitic inductance between the multiple bipolar transistors 30 and further reduce the parasitic resistance or parasitic inductance. Thereby, it is possible to suppress the decrease in the maximum output caused by the increase in the parasitic resistance or parasitic inductance of the path of the collector current.

[0079] In order to obtain the above-mentioned sufficient effects, it is preferable that the interval in the second direction between the two transistor columns 35 (the interval between the collector electrode 40C of one transistor column 35 and the collector electrode 40C of the other transistor column 35) is shorter than the length in the first direction D1 of each transistor column 35 of the two transistor columns 35 (the length from the outer edge of the outermost collector electrode 40C to the outer edge of the other collector electrode 40C). In addition, it is preferable that the dimension of the collector bump 70C in the first direction D1 is set to be 3 / 4 or more of the length of the transistor column 35 in the first direction D1.

[0080] Next, a modified example of the first embodiment will be described.

[0081] For example, as will be described later, there is a case where a high-order harmonic termination circuit is connected to the collectors of the multiple bipolar transistors 30 constituting the power stage amplifier circuit 112 ( Figure 11 ). The high-order harmonic termination circuit is constituted by, for example, a series circuit of a high-order harmonic termination capacitor and a high-order harmonic termination inductor. It is also possible to arrange a passive element having at least one of the high-order harmonic termination capacitor and the high-order harmonic termination inductor, that is, at least one of inductance and capacitance, on the inner layer of the mounting substrate 200 ( Figure 4 ). This passive element only needs to be arranged at a position that overlaps the collector pad 201C ( Figure 3 ) in a top view. Thereby, it is not necessary to ensure a dedicated area for arranging the high-order harmonic termination circuit in a top view, and it is possible to suppress the power amplifier module 150 ( Figure 3 ) Figure 4) increases in size.

[0082] Next, other modified examples of the first embodiment will be described. In the first embodiment, a bipolar transistor 30 is used as the active element of the amplifier circuit, but a field effect transistor may also be used. In this case, the "emitter", "base", and "collector" of the semiconductor device according to the first embodiment may be replaced with "source", "gate", and "drain", respectively.

[0083] [Second Embodiment]

[0084] Next, with reference to Figure 8 , a semiconductor device according to the second embodiment will be described. Hereinafter, the description of the same structure as that of the semiconductor device based on the first embodiment ( Figures 1 to 4 ) will be omitted.

[0085] Figure 8 is a diagram showing the positional relationship in plan view of the multiple components of the semiconductor device based on the second embodiment. In the first embodiment, the collector wiring 51C of the first layer and the collector wiring 60C of the second layer converge within the region of the transistor columns 35 sandwiched between two columns. In contrast, in the second embodiment, the collector wiring 52C of the first layer and the collector wiring 61C of the second layer are also arranged outside the region of the transistor columns 35 sandwiched between two columns. In plan view, the collector wiring 52C of the first layer and the collector wiring 61C of the second layer have a shape that is longer in the second direction D2.

[0086] The collector wiring 52C is continuous with the collector wiring 51C within the region of the transistor columns 35 sandwiched between two columns. Similarly, the collector wiring 61C of the second layer is continuous with the collector wiring 60C within the region of the transistor columns 35 sandwiched between two columns. If the two columns of transistor columns 35 are extended to one side in the first direction D1, they overlap a part of the collector wiring 51C of the first layer and the collector wiring 61C of the second layer in plan view.

[0087] The collector bump 71C is arranged so as to be included in the collector wiring 61C of the second layer in plan view. The collector bump 71C has a shape that is longer in the second direction D2 in plan view.

[0088] Next, the excellent effects of the semiconductor device based on the second embodiment will be described.

[0089] In the second embodiment, as the path of the collector current, a path including a collector bump 70C (first bump) in a region between transistor columns 35 arranged in two columns and a path including another collector bump 71C (other first bump) are formed. By connecting these two paths in parallel, the parasitic resistance and parasitic inductance of the path of the collector current can be further reduced. As a result, an excellent effect of suppressing a decrease in the maximum output is obtained.

[0090] [Third Embodiment]

[0091] Next, with reference to Figure 9 , a semiconductor device according to the third embodiment will be described. Hereinafter, description of the same structure as that of the semiconductor device based on the second embodiment ( Figure 8 ) will be omitted.

[0092] Figure 9 is a diagram showing the positional relationship in a plan view of a plurality of constituent elements of a semiconductor device based on the third embodiment. In the third embodiment, two circuit configurations having a planar configuration substantially the same as the planar configuration of a plurality of constituent elements in the semiconductor device based on the second embodiment ( Figure 8 ) are arranged side by side in the second direction D2. The collector wiring 52C of one first layer is continuous with the collector wiring 52C of the other first layer. Similarly, the collector wiring 61C of one second layer is continuous with the collector wiring 61C of the other second layer. The collector bump 71C is arranged separately.

[0093] In addition, the bias input wiring 83 of one side is continuous with the bias input wiring 83 of the other side, and the high-frequency signal input wiring 88 of one side is continuous with the high-frequency signal input wiring 88 of the other side.

[0094] Next, the excellent effects of the third embodiment will be described.

[0095] In the third embodiment, similarly to the second embodiment, the parasitic resistance and parasitic inductance of the path of the collector current can also be reduced. As a result, an excellent effect of being able to suppress a decrease in the maximum output is obtained.

[0096] [Fourth Embodiment]

[0097] Next, with reference to Figure 10 , a semiconductor device according to the fourth embodiment will be described. Hereinafter, description of the same structure as that of the semiconductor device based on the second embodiment ( Figure 8 ) will be omitted.

[0098] Figure 10This is a top view showing the positional relationship of the components of the semiconductor device based on the fourth embodiment. In the second embodiment, one collector bump 70C is disposed between two columns of transistor columns 35 ( Figure 8 ). In contrast, in the fourth embodiment, two collector bumps 70C are disposed in the region between two columns of transistor columns 35. Each of the two collector bumps 70C has a shape that is longer in the first direction D1 in a top view and is disposed at an interval in the second direction D2. In order to dispose two collector bumps 70C in the region between two columns of transistor columns 35, the interval in the second direction D2 between the two transistor columns 35 is made wider than that in the first embodiment.

[0099] The two collector bumps 70C are connected to each other via a first-layer collector wiring 51C and a second-layer collector wiring 60C disposed in the region between two columns of transistor columns 35. The number of collector bumps 71C that overlap with the collector wiring 61C disposed outside the region between two columns of transistor columns 35 in a top view is one, the same as in the second embodiment.

[0100] Next, the excellent effects of the fourth embodiment will be described.

[0101] In the fourth embodiment, two collector bumps 70C are disposed in the region between two transistor columns 35. Therefore, compared with the case of the second embodiment ( Figure 8 ), the effect of reducing the parasitic resistance and parasitic inductance of the path of the collector current is improved.

[0102] Next, a modification of the fourth embodiment will be described. In the fourth embodiment, two collector bumps 70C are disposed in the region between two columns of transistor columns 35, but three or more collector bumps 70C may be disposed.

[0103] [Fifth Embodiment]

[0104] Next, with reference to the accompanying drawings Figures 11 to 13 , the semiconductor device according to the fifth embodiment will be described. Hereinafter, the description of the same structure as that of the semiconductor device based on the first embodiment ( Figures 1 to 4 ) will be omitted.

[0105] Figure 11is an equivalent circuit diagram of an amplifier circuit module including a semiconductor device based on the fifth embodiment. The amplifier circuit module based on the fifth embodiment includes a driver stage amplifier circuit 110, a power stage amplifier circuit 112, a driver stage bias circuit 113, a power stage bias circuit 114, inductors 153, 154, a protection circuit 115, a high-order harmonic termination circuit 120, an output capacitor 125, an inductor 129, an input-side impedance matching circuit 151, and an output-side impedance matching circuit 152. In Figure 11 the inductor enclosed by the cylindrical figure represents the parasitic inductor of the bump.

[0106] The power stage amplifier circuit 112 includes a plurality of unit cells each composed of a bipolar transistor 30, an input capacitor 80, and a resistance element 82. The plurality of unit cells are connected in parallel with each other. In addition, in Figure 11 one of the plurality of unit cells is representatively shown. A power supply voltage Vcc is applied to the collector of the bipolar transistor 30 via an inductor 154 that functions as a choke coil.

[0107] A bias current is supplied from the power stage bias circuit 114 to the base of the bipolar transistor 30 via the resistance element 82. The power stage bias circuit 114 includes a resistance element R1, transistors Q1, Q2, and a resistance element R2 connected in series between a bias control terminal VBp and the ground line. The transistors Q1, Q2 are respectively diode-connected and operate as diodes. The power stage bias circuit 114 further includes an emitter follower transistor Q3. The transistor Q1 and the emitter follower transistor Q3 form a current mirror. A bias voltage Vbat is applied to the collector of the emitter follower transistor Q3. The emitter of the emitter follower transistor Q3 is connected to the base of the bipolar transistor 30 via the resistance element 82. The power stage bias circuit 114 supplies a bias current corresponding to the control voltage given to the bias control terminal VBp to the bipolar transistor 30.

[0108] The basic circuit configurations of the driver stage amplifier circuit 110, the driver stage bias circuit 113, and the inductor 153 are the same as those of the power stage amplifier circuit 112, the power stage bias circuit 114, and the inductor 154. However, the number of unit cells and the dimensions of each element are different between the driver stage amplifier circuit 110 and the power stage amplifier circuit 112. In addition, the driver stage bias circuit 113 supplies a bias current corresponding to the control voltage given to the bias control terminal VBd.

[0109] A high-frequency input signal is input to the driver stage amplifier circuit 110 via the input-side impedance matching circuit 151. The high-frequency signal amplified by the driver stage amplifier circuit 110 is input to the base of the bipolar transistor 30 via the input capacitor 80 of the power stage amplifier circuit 112. The emitter of the bipolar transistor 30 is grounded via the parasitic inductance of the emitter bump 70E.

[0110] The protection circuit 115 is inserted between the collector of the bipolar transistor 30 of the power stage amplifier circuit 112 and the ground line. The protection circuit 115 is composed of a plurality of diodes connected in series, and the diodes are connected in the direction in which the direction from the collector toward the ground line is forward. If the collector voltage of the bipolar transistor 30 exceeds the allowable maximum value, the protection circuit 115 conducts to protect the bipolar transistor 30.

[0111] A high-order harmonic termination circuit 120 is also connected between the collector of the bipolar transistor 30 of the power stage amplifier circuit 112 and the ground line. The high-order harmonic termination circuit 120 is composed of a series circuit of a high-order harmonic termination capacitor 121, the parasitic inductance of the high-order harmonic termination bump 70H, and a high-order harmonic termination inductor 123.

[0112] The collector of the bipolar transistor 30 of the power stage amplifier circuit 112 is connected to the output-side impedance matching circuit 152 via the output capacitor 125 and the parasitic inductance of the output bump 70T (second bump). The connection point between the output bump 70T and the output-side impedance matching circuit 152 is grounded via an inductor 129.

[0113] Figure 12 is a diagram showing the positional relationship in plan view of the components of the power stage amplifier circuit 112 ( Figure 11 ) and its peripheral circuits of the semiconductor device according to the fifth embodiment. Hereinafter, the description of the positional relationship that is the same as the positional relationship in plan view of the components of the semiconductor device according to the second embodiment ( Figure 8 ) is omitted.

[0114] In the second embodiment, the collector wiring 51C of the first layer is disposed in substantially the entire area of the region between the two columns of transistor columns 35. In contrast, in the fifth embodiment, two collector wirings 51C of the first layer are disposed corresponding to the two columns of transistor columns 35. The two collector wirings 51C are respectively connected to a plurality of collector lead-out wirings 50C connected to the collector electrodes 40C of the corresponding transistor columns 35. The two collector wirings 51C are connected to the collector wiring 52C at their ends.

[0115] In the region between the two collector wirings 51C, a plurality of transistors 130 constituting the protection circuit 115 ( Figure 11 ) are disposed. Each transistor 130 is diode-connected. Each transistor 130 includes a collector layer 131, a base layer 132, an emitter layer 133, an emitter mesa layer 134, a collector electrode 41C, a base electrode 41B, and an emitter electrode 41E. The emitter wiring 51E of the first layer is disposed so as to overlap each emitter electrode 41E.

[0116] The shapes of the collector wirings 60C and 61C in the second layer when viewed from above are the same as those of the collector wirings 60C and 61C in the second layer of the second embodiment ( Figure 8 ). Therefore, when viewed from above, the collector wiring 60C in the second layer overlaps with a plurality of transistors 130. Near the edge of the collector wiring 60C in the second layer that is disposed between the two transistor columns 35 and is parallel to the first direction D1, it overlaps with the collector wiring 51C in the first layer. At this overlapping portion, the collector wiring 60C in the second layer is connected to the collector wiring 51C in the first layer. Further, similarly to the case of the second embodiment ( Figure 8 ), the collector wiring 61C in the second layer is connected to the collector wiring 52C in the first layer.

[0117] Figure 13 is Figure 12 a cross-sectional view taken along the dotted line 13-13. Hereinafter, the description of the same structure as that of the cross-sectional structure ( Figure 2 ) of the semiconductor device based on the first embodiment will be omitted.

[0118] In the first embodiment, the collector wiring 51C in the first layer is disposed in substantially the entire region between the two bipolar transistor columns 35 ( Figure 2 ). In contrast, in the fifth embodiment, the collector wiring 51C in the first layer is divided into left and right and two are disposed. Between the two collector wirings 51C, the transistor 130 is disposed. When viewed from above, the transistor 130 is included in the sub-collector layer 21.

[0119] On the sub-collector layer 21, a collector layer 131, a base layer 132, and an emitter layer 133 are sequentially stacked. When viewed from above, the outer peripheral lines of the collector layer 131, the base layer 132, and the emitter layer 133 substantially coincide. On a part of the upper surface region of the emitter layer 133, an emitter mesa layer 134 is disposed. On the emitter mesa layer 134, an emitter electrode 41E is disposed. On the insulating film 90 covering the emitter electrode 40E of the bipolar transistor 30 and the emitter electrode 41E of the transistor 130, the emitter wiring 51E in the first layer is disposed. The emitter wiring 51E in the first layer is connected to the emitter electrode 41E through an opening provided in the insulating film 90.

[0120] On the insulating film 91 covering the emitter wirings 51E and 50E in the first layer, the collector wiring 60C in the second layer is disposed. The collector wiring 60C in the second layer is connected to the two collector wirings 51C in the first layer through an opening provided in the insulating film 91. When viewed from above, the collector wiring 60C in the second layer overlaps with the transistor 130 and is disposed above the transistor 130 via the insulating film 91.

[0121] The cross-sectional structure above the collector wiring 60C of the second layer and the emitter wiring 60E of the second layer is the same as that of the semiconductor device according to the first embodiment ( Figure 2 ).

[0122] Next, the excellent effects of the fifth embodiment will be described.

[0123] In the fifth embodiment, similarly to the case of the first embodiment, the collector bumps 70C having a size in the thickness direction larger than that of the collector wirings 60C and 51C are arranged between two transistor columns 35, and the shape thereof in a plan view is longer in the first direction. The collector bump 70C is connected to the collector pad 201C ( Figure 3 ) having a larger size in the second direction D2. Therefore, the size in the thickness direction and the second direction D2 of the flow path of the collector current flowing in the first direction D1 becomes larger. As a result, the parasitic resistance and the parasitic inductance of the path of the collector current are reduced. Thereby, a decrease in the maximum output of the bipolar transistor 30 can be suppressed.

[0124] Moreover, in the fifth embodiment, since the protection circuit 115 is arranged under the collector wiring 60C of the second layer, the area occupied by the entire amplifier circuit in the substrate 20 can be reduced.

[0125] Next, with reference to Figure 14 , a semiconductor device according to a modification of the fifth embodiment will be described.

[0126] Figure 14 is a diagram showing the positional relationship in a plan view of a plurality of components of a power stage amplifier circuit and its peripheral circuits of a semiconductor device according to a modification of the fifth embodiment. In this modification, circuits having a planar configuration substantially the same as the planar configuration of a plurality of components of the semiconductor device according to the fifth embodiment ( Figure 12 ) are arranged side by side in the second direction D2. One high-frequency signal input wiring 88 is connected to the other high-frequency signal input wiring 88. Also, one bias input wiring 83 is connected to the other bias input wiring 83. Thus, by arranging a plurality of Figure 12 the semiconductor devices of the fifth embodiment shown, high output can be achieved.

[0127] [Sixth Embodiment]

[0128] Next, with reference to Figure 15 and Figure 16 , a semiconductor device according to the sixth embodiment will be described. Hereinafter, the description of the same structure as that of the semiconductor device according to the fifth embodiment ( Figure 12 , Figure 13 ) will be omitted.

[0129] Figure 15 is a diagram showing the positional relationship in plan view of the components of the power stage amplifier circuit 112 ( Figure 11 ) of the semiconductor device according to the sixth embodiment and its peripheral circuits. In the fifth embodiment, a protection circuit 115 is arranged in the region between the collector wirings 51C of the two first layers ( Figure 11 , Figure 12 ). In contrast, in the sixth embodiment, a plurality of resistor elements 82 and the emitter follower transistor Q3 of the power stage bias circuit 114 are arranged in the region between the collector wirings 51C of the two first layers ( Figure 11 ).

[0130] In the sixth embodiment, the base electrode 40B ( Figure 12 ) of the bipolar transistor 30 has a U-shaped configuration in plan view. In contrast, in the sixth embodiment, the base electrode 40B surrounds the periphery of the emitter electrode 40E in a ring shape in plan view. The first-layer base wiring 51B is led out from the base electrode 40B toward the region between the two transistor columns 35. The first-layer collector wiring 51C is divided at the position where it crosses the first-layer base wiring 51B, and the collector wiring 51C is electrically insulated from the base wiring 51B. In addition, the divided first-layer collector wirings 51C are connected to each other via the second-layer collector wiring 60C.

[0131] The emitter follower transistor Q3 includes a collector layer 135, a base layer 136, an emitter layer 137, an emitter mesa layer 138, a collector electrode 42C, a base electrode 42B, and an emitter electrode 42E. The plurality of first-layer base wirings 51B are respectively connected to one end of the corresponding resistor elements 82. The other ends of the plurality of resistor elements 82 are connected to the emitter electrode 42E of the emitter follower transistor Q3 via the bias input wiring 83.

[0132] The first-layer collector wiring 52C is connected to the collector electrode 42C, and the first-layer base wiring 52B is connected to the base electrode 42B. A bias voltage Vbat ( Figure 11 ) is applied to the collector electrode 42C via the collector wiring 52C. The base wiring 52B is connected to the base of the transistor Q1 ( Figure 11 ) of the power stage bias circuit 114.

[0133] Figure 16 is Figure 15 a cross-sectional view taken along the dash-dot line 16-16. Hereinafter, the description of the same structure as the cross-sectional structure ( Figure 13 ) of the semiconductor device according to the fifth embodiment will be omitted. In the fifth embodiment, a transistor 130 is arranged between the two bipolar transistor columns 35 ( Figure 13), but in the sixth embodiment, an emitter follower transistor Q3 is disposed between the two bipolar transistor columns 35.

[0134] When viewed from above, the emitter follower transistor Q3 is included in the subset electrode layer 21. A collector layer 135, a base layer 136, and an emitter layer 137 are disposed on the subset electrode layer 21. Further, a collector electrode 42C is disposed in a region of the upper surface of the subset electrode layer 21 where the collector layer 135 is not disposed. The collector electrode 42C is electrically connected to the collector layer 135 via the subset electrode layer 21. An emitter mesa layer 138 and a base electrode 42B are disposed on the emitter layer 137. The base electrode 42B is electrically connected to the base layer 136 via an alloying region that penetrates the emitter layer 137 in the thickness direction. An emitter electrode 42E is disposed on the emitter mesa layer 138. The emitter electrode 42E is electrically connected to the emitter layer 137 via the emitter mesa layer 138.

[0135] An insulating film 90 covers the emitter electrode 40E of the bipolar transistor 30, the emitter electrode 42E of the emitter follower transistor Q3, the base electrode 42B, and the collector electrode 42C. A first layer of base wiring 51B, a bias input wiring 83, and a first layer of emitter wiring 50E are disposed on the insulating film 90. The base wiring 51B is connected to the base electrode 40B through an opening provided in the insulating film 90. Further, the base wiring 51B extends from the connection position with the base electrode 40B toward the region between the two transistor columns 35. The bias input wiring 83 is connected to the emitter electrode 42E of the emitter follower transistor Q3 through an opening provided in the insulating film 90.

[0136] An insulating film 91 covers the first layer of emitter wiring 50E and the bias input wiring 83. The structure above the insulating film 91 is the same as that of the semiconductor device based on the fifth embodiment ( Figure 13 ). Further, the second layer of collector wiring 60C is connected to the first layer of collector wiring 51C in a structure same as the connection structure shown in Figure 16 in a portion other than the cross section shown. Figure 13

[0137] Next, the excellent effects of the sixth embodiment will be described.

[0138] In the sixth embodiment, similarly to the case of the first embodiment, a collector bump 70C having a size in the thickness direction larger than that of the collector wirings 60C and 51C is disposed between the two transistor columns 35, and its shape when viewed from above is longer in the first direction. The collector bump 70C and the collector pad 201C having a larger size in the second direction D2 ( Figure 3 ​) connection. Therefore, the thickness direction of the flow path of the collector current flowing in the first direction D1 and the size in the second direction D2 become larger. As a result, the parasitic resistance and parasitic inductance of the path of the collector current are reduced. Thereby, a decrease in the maximum output of the bipolar transistor 30 can be suppressed.

[0139] Moreover, in the sixth embodiment, since the emitter follower transistor Q3 and the resistance element 82 of the power stage bias circuit 114 ( Figure 11 ) are arranged under the collector wiring 60C of the second layer, the area occupied by the entire amplifier circuit in the substrate 20 can be reduced.

[0140] [Seventh Embodiment]

[0141] Next, refer to Figure 17 、 Figure 18 and Figure 19 to describe the semiconductor device according to the seventh embodiment. Hereinafter, the description of the same structure as that of the semiconductor device according to the first embodiment ( Figures 1 to 4 ) will be omitted. In addition, the amplifier circuit module based on the semiconductor device of the seventh embodiment is also represented by the equivalent circuit diagram shown in Figure 11 in the same manner as the amplifier circuit module based on the fifth embodiment.

[0142] Figure 17 is a diagram showing the positional relationship in plan view of a plurality of components of the power stage amplifier circuit 112 ( Figure 11 ) and its peripheral circuits of the semiconductor device according to the seventh embodiment. In the first embodiment, the collector wiring 51C ( Figure 1 ) of the first layer is arranged in substantially the entire area of the region between the two columns of transistor columns 35. In contrast, in the seventh embodiment, in a part of the region between the two columns of transistor columns 35, excluding the collector wiring 51C, an output wiring 51T (second wiring) is arranged instead. An output wiring 52T (second wiring) is also arranged closer to the outside than the region between the two columns of transistor columns 35, and the output wiring 51T is continuous with the output wiring 52T. In plan view, the output wiring 52T arranged closer to the outside than the region between the two columns of transistor columns 35 has a shape that is longer in the second direction D2.

[0143] In a plan view, the collector wiring 60C of the second layer in the region between the transistor columns 35 arranged in two columns overlaps both the collector wiring 51C of the first layer and the output wiring 51T of the first layer. The collector wiring 60C of the second layer is connected to the collector wiring 51C of the first layer. Here, "connected" means "dc-connected". Further, in this specification, unless otherwise specified, "connected" means dc-connected. A capacitor dielectric film 95 is disposed between the collector wiring 60C of the second layer and the output wiring 51T of the first layer. The output capacitor 125 is constituted by the collector wiring 60C of the second layer and the output wiring 51T of the first layer disposed above and below the capacitor dielectric film 95( Figure 11 ).

[0144] The output wiring 60T of the second layer is arranged so as to overlap the output wiring 52T of the first layer in a plan view. And the output bump 70T is arranged so as to overlap the output wiring 60T of the second layer in a plan view. The output bump 70T( Figure 11 ) is connected to the output wiring 51T that functions as the lower electrode of the output capacitor 125 via the output wiring 60T of the second layer and the output wiring 52T of the first layer.

[0145] Figure 18 is Figure 17 a cross-sectional view taken along the dash-dot line 18-18. Hereinafter, the description of the same structure as the cross-sectional structure( Figure 2 ) of the semiconductor device according to the first embodiment will be omitted. In the first embodiment, the collector wiring 51C of the first layer is arranged in substantially the entire region of the region between the two bipolar transistor columns 35. In contrast, in the seventh embodiment, in the cross-section shown in Figure 18 , the collector wiring 51C of the first layer is divided into two parts. The output wiring 51T of the first layer is disposed between the two parts of the collector wiring 51C. Further, a semiconductor layer formed in the same process as the collector layer 31, the base layer 32, and the emitter layer 33 of the bipolar transistor 30 is left in the region that overlaps the output wiring 51T in a plan view.

[0146] The insulating film 91 covers the collector wiring 51C, the output wiring 51T, and the emitter wiring 50E of the first layer. An opening 94 reaching from the upper surface to the bottom surface of the insulating film 91 is provided in the region that overlaps the output wiring 51T in a plan view. The capacitor dielectric film 95 is disposed on the surface of the output wiring 51T located inside the opening 94 in a plan view.

[0147] On the insulating film 91 and the capacitor dielectric film 95, the second-layer collector wiring 60C is disposed. The collector wiring 60C and the output wiring 51T, which are opposed to each other in the vertical direction with the capacitor dielectric film 95 interposed therebetween, constitute the output capacitor 125. The collector wiring 60C is connected to the first-layer collector wiring 51C through openings provided in the insulating film 91 on both sides of the output wiring 51T. Further, on the insulating film 91, the second-layer emitter wiring 60E is disposed. The second-layer emitter wiring 60E is connected to the first-layer emitter wiring 50E through an opening provided in the insulating film 91.

[0148] The structure above the second-layer collector wiring 60C and the emitter wiring 60E is the same as that of the semiconductor device ( Figure 2 ) according to the first embodiment.

[0149] Figure 19 is Figure 17 a cross-sectional view taken along the dash-dot line 19-19 in. On the element isolation region 22, a semiconductor layer formed by the same process as the collector layer 31, the base layer 32, and the emitter layer 33 of the bipolar transistor 30 ( Figure 18 ) is left. On the semiconductor layer and the element isolation region 22, an insulating film 90 is disposed. On the insulating film 90, the first-layer collector wiring 51C and the output wirings 51T, 52T are disposed. The insulating film 91 covers the collector wiring 51C and the output wirings 51T, 52T.

[0150] On the insulating film 91, the second-layer collector wiring 60C and the output wiring 60T are disposed. The second-layer collector wiring 60C is connected to the first-layer collector wiring 51C through an opening provided in the insulating film 91. Further, the second-layer collector wiring 60C is opposed to the first-layer output wiring 51T via the capacitor dielectric film 95 disposed in the opening of the insulating film 91. The second-layer collector wiring 60C and the first-layer output wiring 51T, which are opposed to each other in the vertical direction with the capacitor dielectric film 95 interposed therebetween, constitute the output capacitor 125.

[0151] The second-layer output wiring 60T is connected to the first-layer output wiring 52T through an opening provided in the insulating film 91. The insulating film 92 is disposed so as to cover the second-layer collector wiring 60C and the output wiring 61T. On the insulating film 91, a collector bump 70C and an output bump 70T are disposed. The collector bump 70C is connected to the second-layer collector wiring 60C through an opening provided in the insulating film 92. The output bump 70T is connected to the second-layer output wiring 60T through an opening provided in the insulating film 92. Solder layers 75 are respectively disposed on the collector bump 70C and the output bump 70T.

[0152] The bipolar transistor 30 ( Figure 17 ,Figure 18 )'s collector electrode 40C Figure 17 ) is connected to the output bump 70T via the collector lead wiring 50C Figure 17 ), the collector wiring 51C of the first layer, the collector wiring 60C of the second layer, the output capacitor 125, the output wirings 51T, 52T of the first layer, the output wiring 60T of the second layer, and the output bump 70T in a high-frequency manner.

[0153] Next, the excellent effects of the seventh embodiment will be described.

[0154] In the seventh embodiment, the collector bump 70C is arranged in the region between the two columns of transistor columns 35. In Figure 18 and Figure 19 , since the power supply voltage Vcc ( Figure 3 ) is supplied from the collector pad 201C ( Figure 11 ) and the upper surface of the collector bump 70C, the DC component of the collector current, similarly to the case of the first embodiment, generally does not have a component flowing in the first direction. Therefore, it is possible to reduce the parasitic resistance and parasitic inductance with respect to the DC component of the collector current.

[0155] In Figure 19 , the AC component of the collector current passes through the output bump 70T, the output wiring 60T of the second layer, the output wirings 51T of the first layer, the output capacitor 125, the collector wiring 60C of the second layer, and the collector wiring 51C of the first layer. The collector pad 201C ( Figure 3 ) having a large size in the thickness direction and the second direction D2, and the collector bump 70C having a large size in the thickness direction are connected in parallel to the path through which the collector wiring 60C of the second layer flows in the first direction D1. Therefore, the path cross-section of the AC component of the collector current becomes larger. As a result, it is also possible to suppress an increase in the parasitic resistance and parasitic inductance with respect to the AC component of the collector current. Thereby, it is possible to suppress a decrease in the maximum output of the bipolar transistor 30.

[0156] Moreover, in the seventh embodiment, since the output capacitor 125 is assembled in the semiconductor chip, there is no need to mount a separate circuit component that operates as the output capacitor 125 on the mounting substrate. And since the output capacitor 125 overlaps with the collector bump 70C in a top view, it is possible to suppress an increase in the size of the semiconductor chip.

[0157] [Eighth Embodiment]

[0158] Next, with reference to Figure 20 , a semiconductor device according to the eighth embodiment will be described. Hereinafter, the description of the same structure as that of the semiconductor device based on the seventh embodiment ( Figures 17 to 19 ) will be omitted.

[0159] Figure 20 is a diagram showing the positional relationship in a plan view of the power stage amplifier circuit 112 ( Figure 11 ) and multiple components of its peripheral circuits of the semiconductor device based on the eighth embodiment. In the eighth embodiment, instead of the output wirings 51T, 52T ( Figure 17 ) of the first layer of the semiconductor device based on the seventh embodiment, the high-order harmonic terminal wirings 51H, 52H (third wirings) of the first layer having the same shape in a plan view are arranged. The high-order harmonic terminal wiring 51H is arranged in the region between two columns of transistor columns 35, and the continuous high-order harmonic terminal wiring 52H is arranged closer to the outside than the region between two columns of transistor columns 35.

[0160] The collector wiring 61C of the second layer is arranged so as to overlap with the high-order harmonic terminal wiring 52H in a plan view. The collector wiring 61C is continuous with the collector wiring 60C of the second layer arranged in the region between two columns of transistor columns 35. Also, the high-order harmonic terminal wiring 60H of the second layer is arranged so as to overlap with the high-order harmonic terminal wiring 52H.

[0161] The collector wiring 60C of the second layer is directly connected to the collector wiring 51C of the first layer. In addition, the collector wiring 60C of the second layer is connected to the high-order harmonic terminal wirings 51H, 52H of the first layer at high frequencies via the high-order harmonic terminal capacitor 121 (second capacitor) including the capacitor dielectric film 96. The high-order harmonic terminal wiring 60H of the second layer is directly connected to the high-order harmonic terminal wiring 52H of the first layer.

[0162] The collector bumps 70C, 71C are respectively arranged so as to overlap with the collector wirings 60C, 61C of the second layer in a plan view. The collector bump 70C has a shape that is longer in the first direction D1 in a plan view. The collector bumps 70C, 71C are connected to the collector wirings 60C, 61C of the second layer. The high-order harmonic terminal bump 70H (third bump) is arranged so as to overlap with the high-order harmonic terminal wiring 60H of the second layer. The high-order harmonic terminal bump 70H is connected to the high-order harmonic terminal wiring 60H of the second layer.

[0163] The collector electrode 40C of the bipolar transistor 30 is connected to the collector bumps 70C, 71C via the collector lead-out wiring 50C, collector wiring 51C, collector wirings 60C, 61C of the second layer. Also, the collector electrode 40C is connected to the high-order harmonic terminal bump 70H at high frequencies via the collector lead-out wiring 50C, collector wiring 51C, collector wirings 60C, 61C of the second layer, high-order harmonic terminal capacitor 121, high-order harmonic terminal wirings 51H, 52H of the first layer, and high-order harmonic terminal wiring 60H of the second layer.

[0164] The high-order harmonic terminal capacitor 121 and the high-order harmonic terminal bump 70H respectively correspond to Figure 11 the high-order harmonic terminal capacitor 121 and the high-order harmonic terminal bump 70H shown. The power supply voltage Vcc is applied to the collector bumps 70C and 71C via an inductor 154 ( Figure 11 ). And, the high-frequency signals output from the collector bumps 70C and 71C are output to an external device via an output capacitor 125 and an output-side impedance matching circuit 152 ( Figure 11 ) mounted on a mounting substrate.

[0165] Next, the excellent effects of the eighth embodiment will be described. In the eighth embodiment, the collector bump 70C having a relatively large dimension in the thickness direction is also arranged in the region between two transistor columns 35, and is connected to the collector pad 201C ( Figure 3 ) having relatively large dimensions in the thickness direction and the second direction D2. Therefore, the dimensions of the flow path of the collector current flowing in the first direction D1 become larger in the thickness direction and the second direction D2. As a result, similar to the case of the first embodiment, the parasitic resistance and the parasitic inductance of the path of the collector current can be reduced. As a result, an excellent effect of suppressing the decrease in the maximum output of the bipolar transistor 30 is obtained.

[0166] And, in the eighth embodiment, since the high-order harmonic terminal capacitor 121 is assembled in the semiconductor chip, it is not necessary to mount the high-order harmonic terminal capacitor 121 as a separate circuit component on the mounting substrate. And, since the high-order harmonic terminal capacitor 121 is arranged so as to overlap the collector wirings 60C and 61C in a top view, an increase in the size of the semiconductor chip is suppressed.

[0167] [Ninth Embodiment]

[0168] Next, with reference to Figure 21 , Figure 22 , an amplifier circuit module mounting a semiconductor device according to the ninth embodiment will be described. Hereinafter, the description of the same structure as that of the semiconductor device according to the second embodiment ( Figure 8 ) will be omitted.

[0169] Figure 21 is a diagram showing the positional relationship in a top view of a plurality of components of a power stage amplifier circuit 112 ( Figure 11 ) and its peripheral circuits of a semiconductor device according to the ninth embodiment. In the second embodiment, the second-layer collector wiring 60C ( Figure 8 ) arranged in the region between two transistor columns 35 and the second-layer collector wiring 61C ( Figure 8)Continuous. In contrast, in the ninth embodiment, in the region between the two columns of transistor columns 35, the output wiring 60T of the second layer is arranged instead of the collector wiring 60C. The output wiring 60T converges within the region between the two columns of transistor columns 35. The collector wiring 61C of the second layer is arranged at a position that overlaps with the collector wiring 52C of the first layer in a plan view.

[0170] A capacitor dielectric film 97 is arranged between the collector wiring 51C of the first layer and the output wiring 60T of the second layer. The collector wiring 51C of the first layer and the output wiring 60T of the second layer that face each other with the capacitor dielectric film 97 interposed therebetween constitute an output capacitor 125 (first capacitor). The collector wiring 61C of the second layer is directly connected to the collector wiring 52C of the first layer in DC.

[0171] The collector bump 71C is arranged so as to overlap with the collector wiring 61C of the second layer in a plan view. The collector bump 71C is directly connected in DC to the collector electrode 40C of the bipolar transistor 30 via the collector wiring 61C of the second layer, the collector wirings 52C and 51C of the first layer, and the collector lead wiring 50C.

[0172] The output bump 71T (fourth bump) is arranged so as to overlap with the output wiring 60T of the second layer in a plan view. The output bump 71T is connected in high frequency to the collector electrode 40C of the bipolar transistor 30 via the output wiring 60T of the second layer, the output capacitor 125, the collector wiring 51C of the first layer, and the collector lead wiring 50C.

[0173] Figure 22 Yes Figure 21 is a cross-sectional view taken along the dotted line 22-22. The semiconductor chip 100 including the Figure 21 shown power stage amplifier circuit 112 is flip-chip mounted on the mounting substrate 210. An output pad 211 and a collector pad 212 are provided on the mounting surface of the mounting substrate 210. The output bump 71T and the collector bump 71C of the semiconductor chip 100 are respectively connected to the output pad 211 and the collector pad 212 via the solder layer 75.

[0174] The mounting substrate 210 includes a plurality of wirings 216 arranged in the inner layer, an inductor 129, and a ground plane 219 arranged on the surface (lower surface) opposite to the mounting surface. A plurality of via conductors 215 connect the plurality of conductor layers in the thickness direction. The output pad 211 is connected to the inductor 129 via the plurality of via conductors 215 and the wiring 216. The via conductor 215 connecting the output pad 211 and the inductor 129 has a shape that is longer in one direction in a plan view. Such a via conductor is sometimes referred to as an oblong via.

[0175] The inductor 129 is connected to the ground plane 219 via the via conductor 215. That is, the output pad 211 is grounded via the inductor 129. The inductor 129 is configured to overlap the output pad 211 in a top view. In addition, in a state where the semiconductor chip is mounted on the mounting substrate 210, the inductor 129 overlaps the output bump 71T and the output capacitor 125 in a top view.

[0176] The output capacitor 125, the output bump 71T, and the inductor 129 respectively correspond to Figure 11 the output capacitor 125, the output bump 71T, and the inductor 129 in the equivalent circuit diagram shown.

[0177] Next, the excellent effects of the ninth embodiment will be described. In the ninth embodiment, the output capacitor 125 is assembled in the semiconductor chip 100, and the inductor 129 is arranged in the inner layer of the mounting substrate 210. Therefore, there is no need to mount separate circuit components that function as the output capacitor 125 and the inductor 129 on the mounting substrate 210. And, in the ninth embodiment, the output capacitor 125 and the inductor 129 are arranged so as to overlap the output pad 211 or the output bump 71T in a top view, so that the exclusive area of the amplifier circuit module in a top view can be reduced.

[0178] Next, a modification of the ninth embodiment will be described.

[0179] In the ninth embodiment, the inductor 129 is arranged in the inner layer of the mounting substrate 210, but capacitors may be arranged in addition to the inductor, or both the inductor and the capacitors may be arranged. In other words, passive elements having at least one of inductance and capacitance may be arranged in the inner layer. In this case, the pad on the mounting substrate side connected to the bump of the semiconductor chip and the passive element are arranged to overlap in a top view.

[0180] The above-described embodiments are illustrative, and of course, partial replacement or combination of the structures shown in different embodiments can be performed. The same effects of the same structures based on multiple embodiments are not sequentially mentioned in each embodiment. And, the present invention is not limited to the above-described embodiments. For example, various changes, improvements, combinations, etc. can be made, which are obvious to those skilled in the art.

Claims

1. A semiconductor device, comprising: a substrate; and transistor columns provided in two columns on the above-mentioned substrate, each of the two columns of transistor columns is composed of a plurality of transistors arranged in a first direction, and the two columns of transistor columns are arranged at intervals in a second direction orthogonal to the first direction, the above-mentioned semiconductor device further has: a first wiring, which is arranged in a region between the two columns of transistor columns in a top view and is connected to the collectors or drains of the above-mentioned plurality of transistors in the two columns of transistor columns; and at least one first bump, which overlaps with the above-mentioned first wiring in a top view and is arranged in a region sandwiched between the two columns of transistor columns and is connected to the above-mentioned first wiring, in a top view, the above-mentioned first bump does not overlap with the two columns of transistor columns.

2. The semiconductor device according to claim 1, wherein, the above-mentioned first bump has a shape that is longer in the first direction in a top view.

3. The semiconductor device according to claim 1 or 2, wherein, in a top view, the above-mentioned first wiring extends to the outside of the region sandwiched between the two columns of transistor columns on at least one side in the first direction, and the extended part extends in the second direction, the above-mentioned semiconductor device further has other first bumps, which overlap with the above-mentioned extended part in a top view and are connected to the above-mentioned extended part.

4. The semiconductor device according to claim 1 or 2, wherein, a plurality of the above-mentioned first bumps are arranged, and each of the plurality of above-mentioned first bumps has a shape that is longer in the first direction in a top view and is arranged at intervals in the second direction.

5. The semiconductor device according to claim 1 or 2, wherein, the above-mentioned semiconductor device further includes at least one element selected from the group consisting of transistors, diodes, resistive elements, capacitors, and inductors, which is arranged in a region between the two columns of transistor columns in a top view and is closer to the substrate side than the above-mentioned first bump.

6. The semiconductor device according to claim 1 or 2, wherein, the above-mentioned semiconductor device further has: a second wiring, which is arranged on the same wiring layer as the above-mentioned first wiring, and in a top view, a part of it is arranged in a region between the two columns of transistor columns, overlaps with the above-mentioned first bump partially, and the remaining part extends to the outside of the region between the two columns of transistor columns; a first capacitor, which is arranged in a region where the above-mentioned second wiring overlaps with the above-mentioned first bump in a top view; and a second bump, which is directly connected to the above-mentioned second wiring.

7. The semiconductor device according to claim 1, wherein, the above-mentioned semiconductor device further has: a third wiring, which is arranged on the same wiring layer as the above-mentioned first wiring, and in a top view, a part of the above-mentioned third wiring is arranged in a region between the two columns of transistor columns and overlaps with the above-mentioned first bump partially, and the remaining part of the third wiring extends to the outside of the region between the two columns of transistor columns; a second capacitor, which is arranged at a position where it overlaps with the above-mentioned third wiring in a top view and connects the above-mentioned first bump and the above-mentioned third wiring; and The third bump is disposed at a position overlapping the third wiring in a top view and is connected to the third wiring.

8. The semiconductor device according to claim 1 or 2, wherein, the semiconductor device further includes: a mounting substrate on which a semiconductor chip including the substrate is mounted; a pad disposed on a surface of the mounting substrate facing the semiconductor chip and connected to the first bump; and a passive element disposed in an inner layer of the mounting substrate and having at least one of a capacitor and an inductor, the capacitor and the inductor being disposed at positions partially overlapping the pad in a top view.

9. A semiconductor device includes: a substrate; and two columns of transistor columns disposed on the substrate, each of the two columns of transistor columns being composed of a plurality of transistors arranged in a first direction and being disposed at intervals in a second direction orthogonal to the first direction, the semiconductor device further includes: a first wiring disposed in a region between the two columns of transistor columns in a top view and connected to collectors or drains of the plurality of transistors in the two columns of transistor columns; at least one fourth bump overlapping the first wiring in a top view, disposed in a region sandwiched between the two columns of transistor columns, and connected to the first wiring, the fourth bump not overlapping the two columns of transistor columns in a top view; a first capacitor including a capacitor dielectric film disposed between the fourth bump and the first wiring and connecting the fourth bump and the first wiring; a mounting substrate on which a semiconductor chip including the substrate is mounted; a pad disposed on a surface of the mounting substrate facing the semiconductor chip and connected to the fourth bump; a ground plane disposed on the mounting substrate; and an inductor disposed on the mounting substrate, connecting the pad and the ground plane, and disposed at a position partially overlapping the pad in a top view.

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