Semiconductor device and method of forming a semiconductor device

Abstract

The present invention describes a semiconductor device, which includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer located on the first gate dielectric layer. The first gate structure also includes a first gate electrode located on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, wherein the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration, and the second dopant concentration is lower than the first dopant concentration. The second gate structure also includes a second work function layer located on the second gate dielectric layer and a second gate electrode located on the second work function layer. Embodiments of the present invention also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down has increased power consumption and parasitic capacitance in semiconductor devices. Summary of the invention

[0003] Some embodiments of the present invention provide a semiconductor device, including: a first transistor, including a first gate structure, wherein the first gate structure includes: a first gate dielectric layer, doped with a first dopant of a first atomic doping ratio; a first work function layer, located on the first gate dielectric layer; and a first gate electrode, located on the first work function layer; a second transistor, including a second gate structure, wherein the second gate structure includes: a second gate dielectric layer, doped with a second dopant of a second atomic doping ratio, the second atomic doping ratio being lower than the first atomic doping ratio; a second work function layer, located on the second gate dielectric layer; and a second gate electrode, located on the second work function layer.

[0004] Other embodiments of the present invention provide a semiconductor device, including: a first all-around gate field effect transistor (GAA FET), including: a first plurality of nanowires; a first doped gate dielectric layer surrounding the first plurality of nanowires; and a first work function layer surrounding the first gate dielectric layer; and a first gate electrode located on the first work function layer; and a second all-around gate field effect transistor, including: a second plurality of nanowires; a second doped gate dielectric layer located on the second plurality of nanowires, wherein the first doped gate dielectric layer includes a first atomic doping ratio, the first atomic doping ratio is greater than the second atomic doping ratio of the second doped gate dielectric layer; a second work function layer located on the gate dielectric layer; and a second gate electrode located on the second work function layer.

[0005] Still other embodiments of the present invention provide a method for forming a semiconductor device, comprising: depositing a first gate dielectric material on a plurality of nanowires, the plurality of nanowires being formed in a first device region and a second device region; forming a first dopant layer on the first gate dielectric material in the first device region; forming a second dopant layer on the first dopant layer in the first device region and on the first gate dielectric material in the second device region; performing an annealing process on the first gate dielectric material and the first and second dopant layers; removing the first and second dopant layers; depositing a second gate dielectric material on the first gate dielectric material; forming a first work function layer on the second gate dielectric material; forming a second work function layer on the first work function layer; and forming a gate electrode on the second work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A and Figures 1B to 1D An isometric view and a cross-sectional view are respectively shown of a semiconductor device according to some embodiments.

[0008] Figure 2 is a flow chart of a method for fabricating a multi-threshold voltage semiconductor device according to some embodiments.

[0009] FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5D , FIG. 6A to FIG. 6D , 7A to 7C and FIG. 8A to FIG. 8C Various views of a semiconductor device having multiple threshold voltages at various stages of its fabrication process are shown in accordance with some embodiments.

[0010] Fig. 9 is a flow chart of a method for forming a doped gate dielectric layer and multiple work function layers of a multi-threshold semiconductor device according to some embodiments.

[0011] FIG. 10A to FIG. 11J Various cross-sectional views of a semiconductor device having a doped gate dielectric layer and multiple work function layers at various stages of its fabrication process are shown in accordance with some embodiments.

[0012] FIG. 12A to FIG. 12B are various views of a semiconductor device having a multiple threshold voltage device according to some embodiments.

[0013] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally identical, and / or structurally identical elements. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, a first component is formed on a second component, meaning that the first component is formed to be in direct contact with the second component. In addition, the present invention may repeat reference numerals and / or characters in various embodiments. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "an example," etc., mean that the described embodiment may include a particular component, structure, or characteristic, but not every embodiment necessarily includes a particular component, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular component, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments.

[0017] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, such that those skilled in the art will interpret the phraseology or terminology of this specification based on the teachings herein.

[0018] As used herein, the term "selectivity" refers to the ratio of the etching rates of two materials under the same etching conditions.

[0019] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (eg, greater than 3.9).

[0020] As used herein, the term "p-type" is defined as a structure, layer, and / or region that is doped with a p-type dopant, such as boron.

[0021] As used herein, the term "n-type" is defined as a structure, layer, and / or region that is doped with an n-type dopant, such as phosphorus.

[0022] In some embodiments, the terms "about" and "substantially" may refer to a value of a given number that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value).

[0023] The present disclosure provides exemplary multi-threshold voltage field effect transistor (FET) devices (e.g., gate all around (GAA) FETs, fin FETs (finFETs), horizontal or vertical GAAfinFETs, or planar FETs) in semiconductor devices and / or integrated circuits (ICs) and exemplary methods of manufacturing the same.

[0024] Multi-threshold voltage integrated circuit (IC) devices can be used in the semiconductor IC industry to optimize delay or power. Multi-threshold voltage IC devices may include several different devices, each having a different threshold voltage (e.g., operating voltage). For example, a multi-threshold voltage IC device may include one or more low threshold voltage devices and one or more high threshold voltage devices. Methods for achieving different threshold voltages on semiconductor devices include work function layer thickness variation and ion implantation modulation. However, with the continuous reduction of technology nodes, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometric dimensions (e.g., the minimum component (or line) that can be produced using a manufacturing process) have decreased. For example, in a full-ring gate FET (GAAFET), increasing the thickness of the work function layer to accommodate different threshold voltages consumes valuable IC device space, thereby limiting the number of devices that can be manufactured on a single chip. On the other hand, changing the ion implantation in the GAA FET to achieve different threshold voltages is also challenging and may result in non-conformance due to, for example, ion implantation shadowing effects.

[0025] Various embodiments in the present disclosure describe methods for forming a multi-threshold voltage device. The embodiments described herein use GAA FET as an example and can be applied to other semiconductor structures, such as finFET and planar FET. Various embodiments herein describe a multi-step deposition and patterning process to form a doped gate dielectric layer with different dopant concentrations and a multilayer metal work function material as a work function layer. For example, multiple devices having doped gate dielectric layers and work function layers of different components can be formed on a substrate to form a semiconductor device with a multi-threshold voltage. The doped gate dielectric layer can be a hafnium-based high-k (e.g., a dielectric constant greater than about 3.9) dielectric layer doped with a suitable material (such as lanthanum or magnesium). Changes in dopant concentration may cause changes in the crystal structure of the hafnium-based gate dielectric layer and form an electric dipole at the interface between the gate dielectric layer and the work function layer, which may affect the spontaneous polarization and internal bias field and cause changes in the device threshold voltage. The gate dielectric layer can be doped by depositing an intrinsic gate dielectric layer and depositing one or more dopant-containing dielectric films on the intrinsic gate dielectric layer. In some embodiments, an annealing process may be used to drive dopants from the dopant-containing film into the intrinsic gate dielectric layer.

[0026] According to some embodiments, reference Figures 1A to 1D A semiconductor device 100 having finFETs 102A- 102F is depicted. Figure 1A An isometric view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1B Shown along Figure 1A A cross-sectional view of the semiconductor device 100 taken along line AA′. Figure 1C Shows Figure 1B An enlarged area C of the cross-sectional view. Figure 1D Shown along Figure 1A A cross-sectional view of the semiconductor device 100 taken along line BB′ in FIG.

[0027] In some embodiments, finFETs 102A-102F may be both p-type finFETs (PFETs) or n-type finFETs (NFETs) or one of each conductivity type. For example, finFETs 102A-102C may be NFETs, and finFETs 102D-102F may be PFETs. In some embodiments, finFETs 102A-102F may have different threshold voltages by incorporating different doped gate dielectric layers and work function layers. In some embodiments, finFETs 102A and 102F may be ultra-low threshold voltage (uLVT) devices, finFETs 102B and 102E may be low threshold voltage (LVT) devices, and finFETs 102C and 102D may be standard threshold voltage (SVT) devices. In some embodiments, the ultra-low threshold voltage may be a threshold voltage between about 0.08V and about 0.18V. In some embodiments, the low threshold voltage may be a threshold voltage between about 0.15V and about 0.25V. The standard threshold voltage may be a threshold voltage between about 0.21V and about 0.31V. In some embodiments, the voltage difference between the ultra-low and low threshold voltage devices can be between about 50 mV and about 70 mV. In some embodiments, the voltage difference between the low threshold voltage device and the standard threshold voltage device can be between about 50 mV and about 70 mV. Figure 1A and Figure 1B Six finFETs are shown in FIG. 1 , but semiconductor device 100 may have any number of finFETs. Discussions of elements of finFETs 102A- 102F with the same annotations apply to each other unless otherwise noted. Isometric and cross-sectional views of semiconductor device 100 are shown for illustration purposes and may not be drawn to scale.

[0028] refer to Figure 1A to Figure 1B , finFETs 102A-102F may be formed on a substrate 106. Substrate 106 may be a semiconductor material, such as silicon. In some embodiments, substrate 106 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 106 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) a combination thereof. In addition, substrate 106 may be doped (e.g., a p-type substrate or an n-type substrate) according to design requirements. In some embodiments, substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0029] The semiconductor device 100 may also include a fin structure 108 extending along the x-axis and through the finFETs 102A-102F. The fin structure 108 may include a fin base 108A and a fin top 108B disposed on the fin base 108A. In some embodiments, the fin base 108A may include a material similar to the substrate 106. The fin base 108A may be formed by photolithographic patterning and etching of the substrate 106. In some embodiments, the fin top 108B may include stacked fin portions 108B1-108B6 and an epitaxial region 110. Each of the stacked fin portions 108B1-108B6 may include a stack of semiconductor layers 122, which may be in the form of nanowires. Each semiconductor layer 122 may form a channel region below the gate structure 112 of the finFETs 102A-102F.

[0030] In some embodiments, semiconductor layers 122 may include semiconductor materials similar to or different from substrate 106. In some embodiments, each of semiconductor layers 122 may include silicon germanium (SiGe), wherein Ge is in a range from about 25 atomic percent to about 50 atomic percent, with any remaining atomic percent being Si or may include Si without any substantial amount of Ge.

[0031] The semiconductor materials of the semiconductor layer 122 may be undoped or may be in-situ doped during their epitaxial growth process using: (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors may be used. For n-type in-situ doping, n-type doping precursors such as phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors may be used. The semiconductor layer 122 may have a corresponding vertical dimension 122t (e.g., thickness) along the z-axis, each vertical dimension being in the range of about 6 nm to about 10 nm. Other dimensions and materials of the semiconductor layer 122 are within the scope and spirit of the present disclosure. Although in Figure 1A and Figure 1B Four semiconductor layers 122 are shown in FIG. 1 , but the semiconductor device 100 may have any number of semiconductor layers 122 .

[0032] Reference Figure 1A to Figure 1B, the epitaxial fin region 110 can be grown on an area of ​​the fin base 108A that is not located under the gate structure 112. In some embodiments, the epitaxial fin region 110 can have any geometric shape, such as a polygon or a circle. The epitaxial fin region 110 may include an epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the material of the substrate 106. In some embodiments, the epitaxially grown semiconductor material includes a material different from the material of the substrate 106. The epitaxially grown semiconductor material may include: (i) a semiconductor material such as germanium or silicon; (ii) a compound semiconductor material such as gallium arsenide and / or aluminum gallium arsenide; (iii) a semiconductor alloy such as silicon germanium and / or gallium arsenide phosphide.

[0033] Reference Figure 1C In some embodiments, the epitaxial fin regions 110 may each have a height 110t. In some embodiments, the epitaxial fin height 110t may be equal to or different from the vertical dimension H2 of the fin top 108B. In some embodiments, the epitaxial fin height 110t may be in a range from about 10 nm to about 100 nm. Other dimensions for the epitaxial fin regions 110 are within the scope and spirit of the present disclosure.

[0034] In some embodiments, the epitaxial fin region 110 may be grown by: (i) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin region 110 may be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. This repeated deposition / partial etching process is also referred to as a cyclic deposition etching (CDE) process.

[0035] The epitaxial fin region 110 may be n-type for NFETs 102A-102C, and p-type for PFETs 102D-102F. In some embodiments, the epitaxial fin regions 110 of the finFETs 102A-102F may be of the same or opposite doping type relative to each other. The p-type epitaxial fin region 110 may include SiGe and may be in-situ doped using a p-type dopant such as boron, indium, or gallium during the epitaxial growth process. For p-type in-situ doping, a p-type doping precursor such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors may be used. In some embodiments, the n-type epitaxial fin region 110 may include Si and may be in-situ doped using an n-type dopant such as phosphorus or arsenic during the epitaxial growth process. For n-type in-situ doping, an n-type doping precursor such as phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors may be used.

[0036] Reference Figure 1B , epitaxial fin region 110 may form source / drain (S / D) regions of finFETs 102A-102F. Each channel region in semiconductor layer 122 of stacked fin portions 108B1-108B6 may be interposed between a pair of S / D regions. Although finFETs 102A-102F are illustrated as having fin structures 108 with stacked fin portions 108B1-108B6 on fin base 108A, other fin structures of finFETs 102A-102F (e.g., a single-layer fin structure etched from substrate 106 or epitaxially grown on substrate 106) are within the scope and spirit of the present disclosure.

[0037] In some embodiments, the fin base 108A and the fin top 108B may have respective vertical dimensions H1 and H2 (e.g., heights) along the z-axis, each ranging from about 40 nm to about 60 nm. The vertical dimensions H1 and H2 may be equal to or different from each other, and may have a height such that the sum of H1 and H2 (i.e., the total height H1 of the fin structure 108) is equal to or different from the total height H2 of the fin structure 108. T ) in a value ranging from about 80 nm to about 120 nm. In some embodiments, the fin structure 108 may have a horizontal dimension L1 (e.g., length) along the x-axis in a range from about 100 nm to about 1 μm. The horizontal dimension L1 of the fin structure 108 may be at least 100 nm to prevent strain relaxation in the fin structure 108, and therefore, prevent strain relaxation in the channel region of the semiconductor layer 122 formed under the gate structure 112. Other dimensions and materials for the fin structure 108 are within the scope and spirit of the present disclosure.

[0038] In some embodiments, finFETs 102A-102F may further include gate structures 112 and spacers 114. Figures 1A to 1D, the gate structure 112 may be a multi-layer structure and may wrap the stacked fin portions 108B1 to 108B6. In some embodiments, each semiconductor layer 122 of the stacked fin portions 108B1 to 108B6 may be wrapped by a gate structure 112 or one or more layers of a gate structure 112, the gate structure 112 may also be referred to as a "gate-all-around (GAA) structure" or a "horizontal gate-all-around structure" and the finFETs 102A-102F may also be referred to as "GAA FETs" or "GAAfinFETs".

[0039] Each gate structure 112 may include a gate dielectric layer disposed on the semiconductor layer 122 and a work function layer disposed on the gate dielectric layer. For example, NFET 102A includes a work function layer 130A formed on the gate dielectric layer 120A. In some embodiments, each gate dielectric layer 120A-120F may include a doped gate dielectric layer. For example, the gate dielectric layer 120A may be a hafnium-based high-k (e.g., a dielectric constant greater than about 3.9) dielectric layer doped with a nominal level of lanthanum. In some embodiments, each work function layer 130A-130F may include one or more work function layers. For example, the work function layer 130A may include one or more n-type work function layers and one or more p-type work function layers. For simplicity, each work function layer and metal fill layer may be collectively referred to as a gate electrode 112B.

[0040] To prevent short circuits between the gate structure 112 and the S / D regions during operation of the finFETs 102A-102F, each gate dielectric layer 120A-120F may wrap each semiconductor layer 122. Taking the PFET 102D as an example, Figure 1D As shown, the gate dielectric layer 120D may wrap around each semiconductor layer 122 and thereby electrically isolate the semiconductor layers 122 from each other and from the conductive gate electrode 112B. In some embodiments, the gate dielectric layers 120A-120F may include (i) a layer of silicon oxide, silicon nitride and / or silicon oxynitride formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation or other suitable processes; (ii) a high-k dielectric material such as HfO2, titanium oxide (TiO2), tantalum oxide (Ta2O3), HfSiO4, zirconium oxide (ZrO2) and zirconium silicate (ZrSiO2), (iii) a high-k dielectric material having an oxide of lithium (Li), beryllium (Be), magnesium (Mg), Ca, Sr, Sc, Y, Zr, Al, La, Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), Gd, terbium (Tb), Dy, holmium (Ho), Er, thulium (Tm), ytterbium (Yb) or lutetium (Lu), or (iv) a combination thereof. The high-k dielectric layer may be formed by ALD and / or other suitable methods.

[0041] Figure 1D 1 shows a cross-sectional view of PFET 102D observed from the BB' cross-sectional surface. In some embodiments, PFET 102D may be a standard threshold voltage p-type FET. PFET 102D may include a gate electrode 112B, and gate electrode 112B includes a gate dielectric layer 120D, a gate work function layer 130D, and a gate metal filling layer 132. PFET 102D may further include a gate barrier layer and a gate interface layer. For simplicity, Figure 1D Not shown. Figure 1D As shown, each semiconductor layer 122 may be wrapped by a gate barrier layer and a gate work function layer 130D. Depending on the spacing between adjacent semiconductor layers 122 and the thickness of the layers included in the gate structure 112, the semiconductor layer 122 may be wrapped by one or more layers of the gate electrode 112B to fill the spacing between adjacent semiconductor layers 122. Figure 1D The gate metal filling layer 132 is shown to partially wrap the semiconductor layer 122 , but according to some embodiments, the gate metal filling layer 132 may also wrap the semiconductor layer 122 to fill the space (not shown) between adjacent semiconductor layers 122 .

[0042] Each gate dielectric layer 120A-120F may include a high-k gate dielectric layer having various dopant levels. In some embodiments, the high-k dielectric gate layer may be a hafnium-based dielectric layer, such as hafnium dioxide. In some embodiments, the gate dielectric layers 120A-120F may be in a crystalline state. In some embodiments, the gate dielectric layers 120A-120F may exhibit suitable electrical properties, such as ferroelectric properties. In some embodiments, the gate dielectric layers 120A-120F may be doped with a suitable material, such as lanthanum, magnesium, silicon, yttrium, gadolinium, strontium, any suitable material, and / or combinations thereof.

[0043] Each gate work function layer 130A-130F may include a single work function layer or a stack of work function layers. Multiple threshold voltages may be achieved by configuring the work function layers of the finFETs 102A-102F so that the threshold voltages between devices may be different. In some embodiments, the stack of work function layers may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and / or combinations thereof. In some embodiments, each gate work function layer 130A-130F may include an Al-doped metal, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. The gate work function layers 130A-130F can be formed using a suitable process, such as ALD, CVD, PVD, plating, or a combination thereof. In some embodiments, the thickness of each gate work function layer 130A-130F can be in the range from about 2 nm to about 15 nm. Other materials, formation methods, and thicknesses for the gate work function layers 130A-130F are within the scope and spirit of the present disclosure.

[0044] Each gate metal filling layer 132 may be a gate electrode including a single metal layer or a stack of metal layers. The stack of metal layers may include metals that are different from each other. In some embodiments, each gate metal filling layer 132 may include a suitable conductive material, such as Ti, silver (Ag), Al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), Zr, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys and / or combinations thereof. The gate metal filling layer 132 may be formed by ALD, PVD, CVD or other suitable deposition processes. Other materials and formation methods for the gate metal filling layer 132 are within the scope and spirit of the present disclosure. Although the gate structures 112 of the finFETs 102A-102F are shown to be similar, the finFETs 102A-102F may have gate structures with different materials and / or electrical characteristics (e.g., threshold voltage, work function value) from each other. Likewise, although the gate structure 112 is shown to have a horizontal GAA structure, other gate structures (e.g., a vertical GAA structure or a gate structure without a GAA structure) are also within the scope and spirit of the present disclosure.

[0045] Reference Figures 1A to 1C According to some embodiments, the spacer 114 may form a sidewall of the gate structure 112 and be in physical contact with a portion of the gate dielectric layer 120A-120F. The spacer 114 may include an insulating material such as silicon oxide, silicon nitride, a low-k material, or a combination thereof. The spacer 114 may include a single layer or a stack of insulating layers. The spacer 114 may have a low-k material having a dielectric constant less than about 3.9. In some embodiments, the spacer 114 may include a material composed of silicon, oxygen, carbon, and / or nitrogen. The concentration of silicon, oxygen, carbon, and nitrogen in the material used for the spacer 114 may depend on the desired dielectric constant of the spacer 114. The varying concentrations of silicon, oxygen, carbon, and nitrogen in the material may change the desired dielectric constant of the spacer 114. In some embodiments, each spacer 114 may include a silicon oxycarbonitride layer (SiOCN), a silicon carbonitride layer (SiCN), a silicon oxycarbon layer (SiOC), or a combination thereof. In some embodiments, each spacer 114 may include a stack of SiOCN layers disposed on a SiOC layer, the SiOC layer disposed on a SiOCN layer. In some embodiments, each spacer 114 may have a thickness S in a range from about 5 nm to about 12 nm. t Other materials and dimensions for the spacer 114 are within the scope and spirit of the present disclosure.

[0046] Figure 1C to Figure 1D is a cross-sectional view of PFET102D. Figure 1C As shown, an internal spacer structure 127 can be formed between the epitaxial fin region 110 and the work function layer 130D. The internal spacer structure 127 can reduce the parasitic capacitance of the finFETs 102A-102F. Each internal spacer structure 127 can have a low-k material with a dielectric constant less than about 3.9 or a high-k material with a dielectric constant in a range from about 4 to about 7. In some embodiments, the internal spacer structure 127 can include a single layer or a stack of dielectric layers. In some embodiments, the internal spacer structure 127 can include a suitable dielectric material composed of silicon, oxygen, carbon and / or nitrogen. The concentration of silicon, oxygen, carbon and nitrogen in the dielectric material used for the internal spacer structure 127 can depend on the desired dielectric constant. The varying concentrations of silicon, oxygen, carbon and nitrogen in the internal spacer structure 127 can change its desired dielectric constant. SiOC, SiCN, SiOCN, SiN, silicon oxide (SiO x ), silicon oxynitride (SiO y N) and / or a combination thereof, by ALD, flowable CVD (FCVD) or other suitable deposition methods to form the internal spacer structure 127.

[0047] Reference Figures 1A to 1D, the semiconductor device 100 may further include an etch stop layer (ESL) (not shown), an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The ESL may protect the gate structure 112 and / or the epitaxial fin region 110. Such protection may be achieved, for example, in the ILD layer 118 and / or the S / D contact structure ( Figures 1A to 1D The ESL may be provided during the formation of the spacer 114 (not shown). The ESL may be provided on the sidewalls of the spacer 114. In some embodiments, the ESL may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), or a combination thereof. In some embodiments, the ESL may include silicon nitride or silicon oxide formed by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or silicon oxide formed by a high aspect ratio process (HARP). In some embodiments, the ESL may have a thickness in a range from about 3 nm to about 30 nm. Other materials, formation methods, and thicknesses for the ESL are within the scope and spirit of the present disclosure.

[0048] The ILD layer 118 may be disposed on the ESL and may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). For example, flowable silicon oxide may be deposited using flowable CVD (FCVD). In some embodiments, the dielectric material is silicon oxide. In some embodiments, the ILD layer 118 may have a thickness 118t in a range from about 50 nm to about 200 nm. Other materials, thicknesses, and formation methods for the ILD layer 118 are within the scope and spirit of the present disclosure.

[0049] The STI regions 138 may provide electrical isolation between the finFETs 102A-102F having the fin structure 108 and adjacent finFETs (not shown) on the substrate 106 having different fin structures and / or adjacent active and passive elements (not shown) integrated with or deposited on the substrate 106. In some embodiments, the STI regions 138 may include a first protection liner 138A and a second protection liner 138B and an insulating layer 138C disposed on the second protection liner 138B. The first protection liner 138A and the second protection liner 138B may include materials different from each other. Each of the first protection liner 138A and the second protection liner 138B may include an oxide or nitride material. In some embodiments, the first protection liner 138A may include a nitride material and the second protection liner 138B may include an oxide material, and oxidation of the sidewalls of the fin top 108B may be prevented during the formation of the insulating layer 138C. In some embodiments, insulating layer 138C may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. In some embodiments, each of first protective liner 138A and second protective liner 138B may have a thickness in a range from about 1 nm to about 2 nm. In some embodiments, STI region 138 may have a vertical dimension 138 along the z-axis in a range from about 40 nm to about 60 nm. H (e.g., height). In some embodiments, the vertical dimension 138 H The total height H of the fin structure 108 may be T half.

[0050] The cross-sectional shapes of the semiconductor device 100 and its elements (eg, the fin structure 108 , the gate structure 112 , the epitaxial fin region 110 , the spacers 114 , the inner spacer structures 127 , and / or the STI regions 138 ) are illustrative and are not intended to be limiting.

[0051] Figure 2 1 is a flow chart of a method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to a method 200 for manufacturing a semiconductor device 100. FIG. 3A to FIG. 12B The exemplary manufacturing process of the semiconductor device 100 is described as follows. Figure 2 The operations shown are described in detail. Depending on the particular application, the operations may be performed in a different order or not performed. It should be noted that the method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after the method 200, and only some other processes are briefly described herein. For simplicity, FIG. 3A to FIG. 12B and Figures 1A to 1D The same components are marked with the same annotations.

[0052] Reference Figure 2 According to some embodiments, in operation 205, a fin structure is formed on a substrate. For example, a fin structure 108 having a fin base 108A and a fin top 108B* can be formed on a substrate 106, as shown in FIG. FIG. 3A to FIG. 3C The formation of the fin structure 108 may include forming a fin base 108A and a fin top 108B* on the substrate 106, such as FIG. 3A to FIG. 3C shown. Figure 3B and Figure 3C Observed through the C-C' and D-D' cross sections respectively Figure 3A As described below, the processing of the fin top 108B* can form a cross-sectional view as shown in FIG. Figures 1A to 1D The fin top 108B.

[0053] The fin top 108B* may include a first semiconductor layer 320 and a second semiconductor layer 122 stacked in an alternating configuration. Each of the first semiconductor layer 320 and the second semiconductor layer 122 may be epitaxially grown on a layer below it and may include semiconductor materials that are different from each other. In some embodiments, the first semiconductor layer 320 and the second semiconductor layer 122 may include semiconductor materials that are similar to or different from the substrate 106. In some embodiments, the first semiconductor layer 320 and the second semiconductor layer 122 may include semiconductor materials that have different oxidation rates and / or etching selectivities from each other. In some embodiments, each of the first semiconductor layer 320 and the second semiconductor layer 122 may include silicon germanium (SiGe), wherein Ge is in a range from about 25 atomic percent to about 50 atomic percent, any remaining atomic percent being Si, or may include Si without any substantial amount of Ge.

[0054] The first semiconductor layer 320 and / or the second semiconductor layer 122 may be undoped or may be in-situ doped using the following dopants during their epitaxial growth process: (i) a p-type dopant, such as boron, indium, or gallium; and / or (ii) an n-type dopant, such as phosphorus or arsenic. For p-type in-situ doping, a p-type doping precursor such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors may be used. For n-type in-situ doping, an n-type doping precursor such as phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors may be used. The first semiconductor layer 320 and the second semiconductor layer 122 may have corresponding vertical dimensions 320t and 122t (e.g., thickness) along the z-axis, each vertical dimension being in a range from about 6 nm to about 10 nm. The vertical dimensions 320t and 122t may be equal to or different from each other. Although in FIG. 3A to FIG. 3C Four semiconductor layers 320 and 122 are shown in FIG. 1 , but the semiconductor device 100 may have any number of semiconductor layers 320 and 122 .

[0055] Forming the fin base 108A and the fin top 108B* may include forming a stack of materials for the first semiconductor layer 320 and the second semiconductor layer 122 on the substrate 106, and etching portions of the substrate 106 and the stack of materials by patterned hard mask layers 340 and 342 formed on the stack of materials. In some embodiments, the hard mask layer 340 may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. In some embodiments, the hard mask layer 342 may be formed of silicon nitride using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD). The etching of the stack of materials may include dry etching, wet etching processes, or combinations thereof. The dry etching process may include using an etchant having an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, other suitable etching gases and / or plasmas, or combinations thereof. The wet etching process may include etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, aqueous ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), or a combination thereof.

[0056] In some embodiments, the fin base 108A and the fin top 108B* may have respective vertical dimensions H1 and H2 (e.g., heights) along the z-axis, each vertical dimension being in a range from about 40 nm to about 60 nm. The vertical dimensions H1 and H2 may be equal to or different from each other, and may be such that the sum of H1 and H2 (i.e., the total height H of the fin structure 108) is T ) in a range from about 80 nm to about 120 nm. In some embodiments, the fin structure 108 may have a horizontal dimension L1 (e.g., length) along the x-axis in a range from about 100 nm to about 1 μm. In some embodiments, the fin structure 108 may have a tapered cross-section along the yz plane, wherein a horizontal dimension W1 (e.g., width) of the fin base 108A along the y-axis is greater than a horizontal dimension W2 of the fin top 108B* along the y-axis. The horizontal dimensions W1 and W2 may be in a range from about 6 nm to about 20 nm.

[0057] Reference Figure 2 In operation 210, according to some embodiments, an STI region is formed on a substrate. FIG. 4A to FIG. 4C , an STI region 138 having a first protection liner 138A, a second protection liner 138B and an insulating layer 138C may be formed on the substrate 106. Forming the STI region 138 may include (i) Figure 3AThe present invention further comprises the steps of: (i) depositing a nitride material layer (not shown) for a first protective liner 138A on the structure of the present invention; (ii) depositing an oxide material layer (not shown) for a second protective liner 138B on the nitride material layer; (iii) depositing an insulating material layer for an insulating layer 138C on the oxide material layer; (iv) annealing the insulating material layer of the insulating layer 138C; (v) chemically mechanically polishing (CMP) the nitride and oxide material layers and the annealed layer of the insulating material; and (vi) etching back the polished structure to form Figure 4A structure. Figure 4B and Figure 4C They are along lines E-E' and F-F' respectively. Figure 4A Cross-sectional view of .

[0058] The nitride and oxide material layers may be deposited using a suitable method for depositing oxide and nitride materials such as ALD or CVD. These oxide and nitride material layers may prevent oxidation of the sidewalls of the fin top 108B* during deposition and annealing of the insulating material for the insulating layer 138C.

[0059] In some embodiments, the insulating material layer for the insulating layer 138C may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the insulating material layer may be deposited using a CVD process, a high-density plasma (HDP) CVD process, using silane (SiH4) and oxygen (O2) as reaction precursors. In some embodiments, the insulating material layer may be formed using a sub-atmospheric pressure CVD (SACVD) process or a high aspect ratio process (HARP), wherein the process gas may include tetraethoxysilane (TEOS) and / or ozone (O3).

[0060] In some embodiments, the insulating material layer may be formed by depositing a flowable silicon oxide using a flowable CVD (FCVD) process. The FCVD process may be followed by a wet annealing process. The wet annealing process may include annealing the deposited layer of insulating material in steam at a temperature from about 200° C. to about 700° C. for a duration in a range of about 30 minutes to about 120 minutes. The wet annealing process may be followed by a CMP process to remove the patterned hard mask layers 340 and 342 and portions of the nitride, oxide, and insulating material layers for layers 138A-138C so that the top surfaces of the nitride, oxide, and insulating material layers are aligned with the top surface 108s ( FIG. 4A to FIG. 4C ) are substantially coplanar. The CMP process may be followed by an etching process to etch the nitride, oxide, and insulating material layers to form Figure 4A structure.

[0061] The etching of the nitride, oxide and insulating material layers can be implemented by a dry etching process, a wet etching process or a combination thereof. In some embodiments, the dry etching process may include plasma dry etching using a gas mixture of the following gases at a pressure ranging from about 1mTorr to about 5mTorr: octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2) and helium (He), fluoroform (CHF3) and He, carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2) and O2, hydrogen bromide (HBr), O2 and He or a combination thereof. In some embodiments, the wet etching process may include treatment with diluted hydrofluoric acid (DHF), ammonium peroxide mixture (APM), sulfur peroxide mixture (SPM), hot deionized water (DI water) or a combination thereof. In some embodiments, the wet etching process may include using ammonia (NH3) and hydrofluoric acid (HF) as an etchant and an inert gas such as Ar, xenon (Xe), He or a combination thereof. In some embodiments, the flow rates of HF and NH3 used in the wet etching process may be in the range of from about 10 sccm to about 100 sccm, respectively. In some embodiments, the wet etching process may be performed at a pressure of from about 5 mTorr to about 100 mTorr and a high temperature of from about 50°C to about 120°C.

[0062] In some embodiments, the first protection liner 138A and the second protection liner 138B may have respective thicknesses 138At and 138Bt ranging from about 1 nm to about 2 nm. In some embodiments, the STI region 138 may have a vertical dimension 138A along the z-axis ranging from about 40 nm to about 60 nm. H (e.g., height). In some embodiments, the vertical dimension 138 H The total height H of the fin structure 108 may be T Other materials, formation methods, and dimensions for STI region 138 are within the scope and spirit of the present disclosure.

[0063] Reference Figure 2 In operation 215, according to some embodiments, a protective oxide layer is formed on the fin structure, and a polysilicon structure is formed on the protective oxide layer. FIG. 5A to FIG. 5D A protective oxide layer 134 * may be formed on the fin structure 108 and the STI region 138 , and polysilicon structures 112A*- 112F* may be formed on the protective oxide layer 134 *. FIG. 5B to FIG. 5D Observed from lines G-G', H-H' and I-I' respectively Figure 5A The formation of the protective oxide layer 134* may include Figure 4AA blanket deposit of an oxide material layer is performed on the structure, followed by a high temperature annealing process. The protective oxide layer 134* may include a suitable oxide material, such as silicon oxide, and may be blanket deposited using a suitable deposition process (such as CVD, ALD, plasma enhanced ALD (PEALD), physical vapor deposition (PVD), or electron beam evaporation). In some embodiments, the oxide material layer may be deposited using PEALD at an energy in a range from about 400 W to about 500 W and at a temperature in a range from about 300° C. to about 500° C. The deposition of the oxide material layer may be followed by a dry annealing process performed under an oxygen flow at a temperature in a range from about 800° C. to about 1050° C. The oxygen precursor concentration may be in a range from about 0.5% to about 5% of the total gas flow rate. In some embodiments, the annealing process may be a flash evaporation process, wherein the annealing time may be between about 0.5 s and about 5 s.

[0064] In some embodiments, the protective oxide layer 134* may have a vertical dimension 134t* along the z-axis (e.g., thickness on the top surface of the fin structure 108) and a horizontal dimension 134s* along the y-axis (e.g., thickness on the sidewalls of the fin top 108B*), each in a range from about 1 nm to about 3 nm. In some embodiments, dimension 134t* may be equal to or greater than dimension 134s*. Other oxide materials, formation methods, and thicknesses for the protective oxide layer 134* are within the scope and spirit of the present disclosure. The presence of the protective oxide layer 134* allows for the protective oxide layer 134* to be formed from the fin structure 108. Figure 5A The high aspect ratio spaces 646 (eg, aspect ratios greater than 1:15, 1:18, or 1:20) between adjacent polysilicon structures 112A*- 112F shown in FIG. 1 , etch the polysilicon without substantially etching and / or damaging the fin structure 108 during formation of the polysilicon structures 112A*- 112F.

[0065] In some embodiments, when the finFETs 102A-102F are used as non-input / output (non-I / O) devices in core circuits (also referred to as "logic circuits" or "memory circuits") formed in a core region (also referred to as "logic region" or "memory region") of an integrated circuit (IC), the protective oxide layer 134* may be removed during a subsequent gate replacement process. In some embodiments, the non-I / O devices may be core devices, logic devices, and / or memory devices that are not configured to directly process input / output voltages / currents. In some embodiments, the non-I / O devices include logic gates such as NAND, NOR, INVERTER, or a combination thereof. In some embodiments, the non-I / O devices include memory devices such as static random access memory (SRAM) devices. In some embodiments, when the finFETs are used as I / O devices in peripheral circuits (e.g., IO circuits) formed in a peripheral region (also referred to as "I / O region" or "high voltage region") of an IC, the protective oxide layer 134* may not be removed and may form a portion of a gate dielectric layer of the gate structure 112. I / O devices can be configured to handle the input / output voltage / current of the IC and can withstand larger voltage or current swings than non-I / O devices.

[0066] The formation of the protective oxide layer 134* may be followed by FIG. 5A to FIG. 5D During subsequent processing, the polysilicon structures 112A*-112F* may be replaced in a gate replacement process to form the polysilicon structures 112A*-112F* as shown. Figure 1A The gate structures 112 of the finFETs 102A-102F are shown. In some embodiments, the formation of the polysilicon structures 112A*-112F* may include blanket depositing a polysilicon material layer on the deposited protective oxide layer 134*, and patterning a hard mask layer 644 (in the embodiment of FIG. 6 ) on the polysilicon material layer. FIG. 5A to FIG. 5D 644). In some embodiments, the polysilicon material may not be doped, and the hard mask layer 644 may include an oxide layer and / or a nitride layer. The oxide layer may be formed using a thermal oxidation process, and the nitride layer may be formed by LPCVD or PECVD. The hard mask layer 644 may protect the polysilicon structures 112A*-112F* from subsequent processing steps (e.g., during the formation of the spacers 114, the epitaxial fin regions 110, and / or the ILD layer 118).

[0067] The blanket deposition of the polysilicon material layer may include CVD, PVD, ALD or other suitable deposition processes. In some embodiments, the etching of the deposited layer of polysilicon material may include dry etching, wet etching or a combination thereof. In some embodiments, etching the deposited layer of polysilicon material to form the polysilicon structure 112A*-112F* may include four etching steps. The first polysilicon etching step may include using a gas mixture with hydrogen bromide (HBr), oxygen (O2), fluoroform (CHF3) and chlorine (Cl2). The second polysilicon etching step may include using a gas mixture with HBr, O2, Cl2 and nitrogen (N2) at a pressure of about 45mTorr to about 60mTorr. The third polysilicon etching step may include using a gas mixture with HBr, O2, Cl2, N2 and argon (Ar) at a pressure of about 45mTorr to about 60mTorr. The fourth polysilicon etching step may include using a gas mixture with HBr, O2, Cl2 and N2 at a pressure of about 45mTorr to about 60mTorr. The first polysilicon etch step may have a higher polysilicon etch rate than the second, third, and / or fourth polysilicon etch steps. The first polysilicon etch step is used to etch undesired portions of the blanket deposited layer of polysilicon material over the fin structure 108. The second, third, and fourth polysilicon etch steps are used to etch undesired portions of the blanket deposited layer of polysilicon material within the high aspect ratio spaces 646.

[0068] In some embodiments, the vertical dimension G of the polysilicon structures 112A*-112F* along the z-axis is H The horizontal dimension G of the polysilicon structures 112A*-112F* along the x-axis may be in the range of about 100 nm to about 150 nm. L The polysilicon structures 112A*-112F* may have a high aspect ratio equal to or greater than about 9, where the aspect ratio is the dimension G. H With size G L In some embodiments, the horizontal dimension 648 (e.g., spacing) along the x-axis between adjacent polysilicon structures 112A*-112F* can be in a range from about 40 nm to about 90 nm. In some embodiments, the horizontal dimension 648 between adjacent polysilicon structures can be different. The value of dimension 648 and dimension G L The sum of the values ​​of is referred to as “one contact polysilicon pitch (1 CPP)”. In some embodiments, the horizontal dimension L1 of the fin structure along the x-axis may be at least 3 CPP to prevent strain relaxation in the fin structure 108 and, therefore, prevent strain relaxation in a channel region formed in a stacked fin portion of the second semiconductor layer 122 under the gate structure 112 as described above.

[0069] Reference Figure 2 In operation 220, according to some embodiments, spacers are formed on the sidewalls of the polysilicon structure and the top of the fin is etched. FIG. 6A to FIG. 6D , spacers 114 may be formed on sidewalls of the polysilicon structures 112A*- 112F*. FIG. 6B to FIG. 6D They are from lines J-J', K-K' and L-L' respectively. Fig. 6A The formation of the spacer 114 may include forming the spacer 114 by CVD, PVD or ALD process. Figure 5A The structure of the present invention is characterized in that a layer of insulating material (e.g., oxide, nitride and / or silicon oxycarbonitride material) is blanket deposited on the structure, and a subsequent photolithography and etching process (e.g., reactive ion etching using a chlorine-based or fluorine-based etchant or other dry etching process) is performed. According to some embodiments, each of the spacers 114 may have a horizontal dimension S in the range from about 5 nm to about 12 nm along the x-axis. t The formation of the spacers 114 may be followed by etching the protective oxide layer 134* from areas not covered by the polysilicon structures 112A*-112F* and the spacers 114 to form an oxide layer 134* located below the polysilicon structures 112A*-112F*. FIG. 6A to FIG. 6D ). The etching process may include a wet etching process using, for example, diluted HF.

[0070] Vertical etching of a portion of the fin top 108B* may be performed after forming the oxide layer 134. The vertical etching includes etching the fin top 108B* that is not located below the spacer 114 and the polysilicon structures 112A*-112F*, and may include a biased etching process. The biased etching process may be performed at a pressure in a range of about 1 mTorr to about 1000 mTorr, a power in a range of about 50 W to about 1000 W, a bias voltage of about 20 V to about 500 V, at a temperature in a range of about 40° C. to about 60° C., and using HBr and / or Cl2 as an etching gas. During the biased etching process, the polysilicon structures 112A*-112F* may be protected from etching by the hard mask layer 644 and the spacer 114.

[0071] Reference Figure 2 In operation 225, according to some embodiments, a horizontal etching process is performed and an internal spacer structure is formed in the fin structure. 7A to 7C The vertical etching of the portion of the fin top 108B* may be followed by a horizontal etching of the portion of the first semiconductor layer 320 beneath the polysilicon structures 112A*- 112F* and the spacers 114 to form a recessed region. Figure 7B yes Fig. 7A An enlarged view of area 720 is shown. Figure 7C Observed from the M-M' line Figure 7B 2. A cross-sectional view of the structure shown. Horizontal etching can be implemented by a dry etching process, a wet etching process, or a combination thereof. The etching process may include multiple cycles of etching and purification processes, such as about 3 to about 20 cycles of etching and purification processes. The etching process in each cycle may include the use of a gas mixture with hydrogen fluoride (HF), nitrogen trifluoride (NF3), fluorine-based gas, and chlorine-based gas. The gas ratio of the gas mixture of HF and NF3 to the fluorine-based gas may be in the range of from about 2 to about 30. The gas ratio of the gas mixture of HF and NF3 to the chlorine-based gas may be in the range of from about 2 to about 40. The purification process in each cycle may include the use of a gas mixture with HF and nitrogen (N2). The HF in the purification process may remove byproducts and / or clean the surface of the etched portion for subsequent cycles. In each cycle, the purification process may be longer than the etching process.

[0072] The process of forming the recessed area may be followed by blanket deposition of a dielectric material layer and horizontal etching of the blanket deposited dielectric material layer to form the internal spacer structure 127 within the recessed area. In some embodiments, the blanket deposition process may include multiple cycles of deposition and etching processes. In each cycle, an etching process may be performed after the deposition process to prevent the formation of voids within the internal spacer structure 127 by removing seams that may be formed during the deposition of the dielectric material layer within the recessed area.

[0073] The internal spacer structure 127 may include a single layer or a stack of dielectric layers deposited by ALD, FCVD or other suitable methods. The etching process in each cycle of the blanket deposition process of the dielectric material layer may include a dry etching process using a gas mixture of HF and NH3. The gas ratio of HF to NH3 may be in the range of from about 1 to about 20. The internal spacer structure 127 may include a suitable dielectric material composed of silicon, oxygen, carbon and / or nitrogen. The carbon concentration in the dielectric material may be low and may be in the range of from about 1% to about 15%, because a carbon concentration in the dielectric material above this range may result in a longer etching time and reduced etching selectivity.

[0074] The horizontal etching process of the blanket-deposited dielectric material layer for forming the inner spacer structure 127 can be implemented by a dry etching process using a gas mixture of HF and NH3. The gas ratio of HF to NH3 can be in a range from about 1 to about 20. In some embodiments, the inner spacer structure 127 may have a dimension 127t1 (e.g., thickness) in a range from about 3 nm to about 12 nm along the x-axis. Other deposition methods and horizontal etching processes for forming the inner spacer structure 127 and other suitable dimensions of the inner spacer structure 127 are within the scope and spirit of the present disclosure.

[0075] Reference Figure 2 In operation 230, an epitaxial fin region is formed on the fin structure, and nanowires are formed between the epitaxial fin regions. FIG. 8A to FIG. 8C , may be on the exposed surface of the fin base 108A and on Fig. 7A An epitaxial fin region 110 is grown on the exposed surface of the second semiconductor layer 122 of the structure. Figure 8B yes Fig. 8A An enlarged view of area 820 is shown. Figure 8C It is along the line N-N' Figure 8B Cross-sectional view of the structure in .

[0076] In some embodiments, portions of the epitaxial fin region 110 may be located below the spacer 114 and / or extend into the fin base 108A. In some embodiments, the epitaxial fin region 110 may be grown by (i) CVD, such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) a molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin region 110 may be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. In some embodiments, the epitaxial fin region 110 may be grown by selective epitaxial growth (SEG), wherein an etching gas is added to promote selective growth of semiconductor material on the exposed surfaces of the second semiconductor layer 122 and the fin base 108A, but not on the insulating material.

[0077] In some embodiments, the epitaxial fin region 110 may be p-type or n-type. In some embodiments, the p-type epitaxial fin region 110 may include SiGe and may be in-situ doped using a p-type dopant such as boron, indium, or gallium during the epitaxial growth process. For p-type in-situ doping, a p-type doping precursor such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors may be used. In some embodiments, the n-type epitaxial fin region 110 may include Si without any substantial amount of Ge and may be in-situ doped using an n-type dopant such as phosphorus or arsenic during the epitaxial growth process. For n-type in-situ doping, an n-type doping precursor such as phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors may be used.

[0078] Each epitaxial fin region 110 may form an S / D region for a finFET 102A-102F. A second semiconductor layer 122 located below the polysilicon structures 112A*-112F* and between adjacent S / D regions may form a channel region for the finFETs 102A-102F. In subsequent processing, the first semiconductor layer 320 (at the end of the gate structure 112) of the stacked fin portions 108B1-108B6 below the polysilicon structures 112A*-112F* may be replaced with one or more layers of the gate structure 112. FIG. 7A to FIG. 7B ) to wrap each channel region to form a full-all-around (GAA) structure.

[0079] In some embodiments, the fin base 108A below the etched portion of the fin top 108B* between the spacers 114 may be recessed during the vertical etching process described in operation 225. The interface 848 between the epitaxial fin region 110 and the fin bottom 108A may be the same plane as the top surface of the STI region 138, or may be below the plane of the top surface of the STI region 138. Other dimensions and structures for the epitaxial fin region 110 are within the scope and spirit of the present disclosure.

[0080] After the process of forming the epitaxial region 110, the first semiconductor layer 320 of the stacked fin portions 108B1-108B6 may be removed to form a nanowire-shaped second semiconductor layer 122, such as FIG. 8A to FIG. 8C As shown. The first semiconductor layer 320 can be removed by an etching process performed at a pressure in a range of about 1 mTorr to about 1000 mTorr, a power in a range of about 50 W to about 1000 W, a bias voltage in a range of about 20 V to about 500 V, and a temperature in a range of about 40° C. to about 60° C. using HBr and / or Cl2 as an etching gas. Other etching methods are within the scope and spirit of the present disclosure.

[0081] After removing the first semiconductor layer 320, an etch stop layer (ESL) (not shown) may be formed on the spacers 114 and on the epitaxial fin region 110. The formation of the ILD layer 118 on the ESL may use a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). For example, the flowable silicon oxide may be deposited using an FCVD process. After the deposition process, the deposited layer of the dielectric material may be thermally annealed in steam at a temperature of about 200° C. to about 700° C. for a duration in a range from about 30 minutes to about 120 minutes.

[0082] After the process of forming the ILD layer 118, the polysilicon structures 112A*-112F* may be removed using a dry etching process (e.g., reactive ion etching) or a wet etching process. In some embodiments, the gas etchant used in the dry etching process may include chlorine, fluorine, bromine, or a combination thereof. In some embodiments, the polysilicon structures 112A*-112F* may be removed using ammonium hydroxide (NH4OH), sodium hydroxide (NaOH), and / or potassium hydroxide (KOH) wet etching or the polysilicon structures 112A*-112F* may be removed using dry etching and a subsequent wet etching process. The exposed portion of the oxide layer 134 may be removed using a dry etching process (e.g., reactive ion etching), a wet etching process (e.g., using diluted HF), or a combination thereof. In some embodiments, the gas etchant used in the dry etching process may include chlorine, fluorine, bromine, or a combination thereof. In some embodiments, the oxide layer 134 may not be removed.

[0083] refer to Figure 2 According to some embodiments, in operation 235, a gate dielectric layer and a work function layer are formed on the nanowires. The gate dielectric layers 120A-120F may be wrapped on the exposed nanowires, such as the nanowire-shaped second semiconductor layer 122 of the stacked fin portions 108B1-108B6. In some embodiments, the selected gate dielectric layers 120A-120F may be intrinsic or doped with a suitable material. The work function layers 130A-130F are formed in the finFETs 102A-102F, respectively. The combination of the respective gate dielectric layers and the work function layers may provide respective threshold voltages on the finFETs 102A-102F. Fig. 9 2 is a flow chart of a method 900 for forming a work function layer on a gate dielectric layer according to some embodiments. The method 900 is an example for implementing operation 235. For illustrative purposes, reference will be made to FIG. 10A to FIG. 11J The exemplary manufacturing process shown is used to describe the operations shown in Figure 900. FIG. 10A to FIG. 11J yes Fig. 10A 1030A-1030D in the embodiment of the present invention to illustrate an exemplary manufacturing process of the method 900 for forming the gate dielectric layers 120A-120F and the work function layers 130A-130F, and for simplicity, the FIG. 10A to FIG. 11J Other structures are omitted. The operations in method 900 may be implemented or not implemented in different orders depending on the specific application. It should be noted that method 900 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after method 900, and only some other processes are briefly described here.

[0084] Each gate dielectric layer 120A-120F formed using method 900 may include a doped or intrinsic gate dielectric layer. In some embodiments, selected gate dielectric layers may be doped with different dopant concentrations to form individual electric dipoles between the gate dielectric layer and the work function layer. Each subsequently formed work function layer 130A-130D may include one or more work function metal layers. The gate dielectric layer and the work function layer may provide multiple threshold voltages on the finFETs 102A-102F so that the device formed on the substrate 106 may have different threshold voltages. In some embodiments, the finFETs 102A-102C may be NFETs, and the finFETs 102D-102F may be PFETs. In some embodiments, the finFETs 102A and 102F may be ultra-low threshold voltage devices, the finFETs 102B and 102E may be low threshold voltage devices, and the finFETs 102C and 102D may be standard threshold voltage devices.

[0085] Reference Fig. 9 In operation 902, according to some embodiments, a first gate dielectric layer is deposited in the gate region. The first gate dielectric material 1102 may be formed of a high-k dielectric material. For example, the first gate dielectric material 1102 may be formed using a hafnium-based dielectric material such as hafnium dioxide. In some embodiments, the first gate dielectric material 1102 may be formed using other suitable gate dielectric materials, such as silicon oxide or any other suitable dielectric material. The first gate dielectric material 1102 may be deposited using ALD, CVD, PVD, any suitable deposition method, and / or a combination thereof. In some embodiments, the first gate dielectric material 1102 may be deposited using ALD and using hafnium chloride and water as precursors. In some embodiments, other suitable precursors may be used. The first gate dielectric material 1102 may be formed on exposed surfaces of the semiconductor layer 122, the spacer 114, and the ILD 118. The deposition process may be a timed deposition process, wherein the process continues for a specified time until a nominal thickness is reached. In some embodiments, the thickness 1102t of the first gate dielectric material 1102 may be about Peace For example, the thickness 1102t may be between about Peace Between Peace Between, or about Peace In some embodiments, the thickness 1102t may be between about Peace In some embodiments, a greater thickness 1102t may provide a greater adjustment of the threshold voltage. For example, a greater thickness 1102t may provide a greater change in the threshold voltage. An interfacial layer may be formed on the exposed semiconductor layer 122 before depositing the first gate dielectric layer (between 102 and 1102t). FIG. 10A to FIG. 10C Not shown, but in FIG. 11A to FIG. 11J ). The interface layer can provide multiple functions, such as serving as an adhesion layer and / or a barrier layer. In some embodiments, the interface layer can be formed using silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, titanium nitride, any suitable dielectric material, and / or a combination thereof.

[0086] refer to Fig. 9 At operation 904, a first dopant layer is formed on the first gate dielectric layer in first selected n-type and p-type device regions according to some embodiments. FIG. 11A to FIG. 11B , forming a first dopant layer 1104A in the first selected n-type and p-type device regions. The dopant layer can be used as a dopant source, and such dopant can be provided to other suitable layers in contact with the dopant layer during suitable processing. The first dopant layer 1104A can be formed by first depositing a first dopant material in all exposed device regions and removing portions of the first dopant material so that the remaining first dopant material forms the first dopant layer 1104A in the first selected n-type and p-type device regions. For example, the first selected device regions may include regions for forming ultra-low threshold voltage n-type devices and / or standard threshold voltage p-type devices. These devices will subsequently include a gate dielectric layer having a higher dopant concentration level than other devices (such as low threshold voltage n-type or p-type devices).

[0087] like Fig.11A As shown, a first dopant material 1104 is deposited in all exposed device regions 1030A-1030F by a blanket deposition process. In some embodiments, the first dopant material 1104 can be deposited on an interface layer 112A formed on the semiconductor layer 122. The interface layer 112A can be formed using any suitable dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, titanium nitride, tantalum nitride, and / or combinations thereof. In some embodiments, the interface layer 112A can have a thickness between about Peace The thickness between . The interfacial layer 112A can be used as an adhesion layer, a barrier layer, or any suitable purpose. The first dopant material 1104 may include a material containing a suitable dopant that can be driven into the first gate dielectric and subsequently form an electric dipole. For example, the first dopant material 1104 may be a dielectric material containing lanthanum, magnesium, silicon, yttrium, gadolinium, strontium, any suitable material, and / or a combination thereof. In some embodiments, the first dopant material 1104 may include lanthanum oxide (La2O3). In some embodiments, the first dopant material 1104 may include magnesium oxide, silicon oxide, yttrium oxide, and / or any other suitable material. In some embodiments, ALD can be used and tris(N,N'-diisopropylformamido)lanthanum (III) (La(FAMD)3) can be used as a precursor to deposit the first dopant material 1104 containing lanthanum oxide. In some embodiments, the first dopant material 1104 comprising lanthanum oxide can be deposited using ALD and using a metal precursor such as La(thd)3, wherein the thd compound comprises 2,2,6,6-tetramethyl-3,5-heptanedione and an oxygen precursor such as ozone (O3). In some embodiments, the first dopant material 1104 can be deposited to about Peace For example, the thickness of the first dopant material 1104 may be between about Peace between Peace In some embodiments, the dopant material 1104 may have a value greater than about A greater thickness of the dopant material 1104 may provide a greater dopant source, so that a greater dopant concentration level may be obtained in the underlying first gate dielectric material 1102 after a driving process.

[0088] The barrier layer 1106 may be formed on the first dopant material 1104 and used to pattern the first dopant material 1104 below so that the first dopant material 1104 may be formed in regions 1030A and 1030D. The barrier layer 1106 may be formed by blanket depositing a barrier material on the first dopant material 1104 and then performing a patterning process. For example, the barrier layer 1106 may be formed of a hard mask material such as aluminum oxide. In some embodiments, the barrier layer 1106 comprising aluminum oxide may be formed by an ALD process using trimethylamine (TMA) and water as precursors. In some embodiments, the ALD process may be performed using about 20 to about 30 processing cycles. In some embodiments, the barrier layer 1106 may be deposited at a temperature between about 200° C. and about 250° C., between about 250° C. and about 300° C., or at any suitable temperature. The blocking layer 1106 may be patterned using a patterning process, such as depositing a photoresist material on the blocking layer 1106, exposing the deposited photoresist material to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element 1108, thereby protecting the hard mask layer 1106 in the underlying regions 1030A and 1030D.

[0089] like Fig. 11B As shown, an etching process is performed to remove portions of the deposited first dopant material to form a first dopant layer over the first gate dielectric layer in first selected n-type and p-type device regions. Fig. 11B , an appropriate etching process is performed to remove the portion of the first dopant material 1104 that is not protected by the barrier layer 1106 and the mask element 1108. In some embodiments, the portion of the first dopant material 1104 can be removed by a wet etching process. A chemical solution (such as hydrochloric acid, hydrogen peroxide, any suitable etching solution, and / or a combination thereof) can be used to etch away the first dopant material 1104. The hard mask layer 1104 can also be removed by dry etching. In some embodiments, the etching process continues until the underlying first gate dielectric material 1102 is exposed. The remaining first dopant material 1104 forms a first dopant layer 1104A in the first selected n-type and p-type device regions, such as the device region 1030A for n-type devices and the device region 1030D for p-type devices.

[0090] Reference Fig. 9 At operation 906, a second dopant material is formed in second selected n-type and p-type device regions according to some embodiments. Fig. 11C ,exist Fig. 11BA second dopant material 1104B* is deposited on the exposed surface of the structure shown. The second dopant material 1104B* can be different from or similar to the first dopant material 1104. For example, both the first dopant material 1104 and the second dopant material 1104B* can be formed of lanthanum oxide or magnesium oxide. In some embodiments, the first dopant material 1104 and the second dopant material 1104B* can be formed of lanthanum oxide and magnesium oxide, respectively. In some embodiments, the thickness of the second dopant material 1104B* can be less than the thickness of the first dopant material 1104. For example, the thickness of the second dopant material 1104B* can be about 100 Å. Peace Between. Fig. 11C As shown, the second dopant material 1104B* can be deposited in regions 1030A-1030F. For example, the second dopant material 1104B* can be deposited using a substantially conformal deposition method such as ALD or CVD. In some embodiments, the second dopant material 1104B* can be deposited using a deposition process similar to that of the first dopant material 1104, and for simplicity, it is not described here.

[0091] like Fig.11D As shown, an etching process is performed to remove a portion of the deposited second dopant material, thereby Fig. 11C A second dopant layer is formed on the exposed surface of the semiconductor structure shown. After the etching process, a second dopant layer 1104B is formed in the second selected n-type and p-type device regions. The patterning and etching of the second dopant material 1104B* used to form the second dopant layer 1104B can be similar to the patterning and etching process of the first dopant material 1104 used to form the first dopant layer 1104A. For example, the barrier layer and masking elements can be patterned to protect the second dopant material 1104B* in the second selected n-type and p-type device regions below (such as, device regions 1030A-1030B for n-type devices and device regions 1030D-1030E for p-type devices). The remaining second dopant material 1104B* forms the second dopant layer 1104B in the device regions 1030A, 1030B, 1030D, and 1030E.

[0092] Reference Fig. 9 In operation 908, according to some embodiments of the present disclosure, an annealing process is performed to drive dopants from the first and / or second dopant layers into the first gate dielectric layer. Fig.11E, an annealing process 1150 is performed to drive dopants, such as lanthanum, from the first and / or second dopant layers 1104A and 1104B into the underlying first gate dielectric material 1102. In some embodiments, if a sufficient supply of dopants is available from the upper dopant layer, the underlying gate dielectric can receive a larger amount of dopant, which can result in a greater dopant concentration. In some embodiments, a greater number of dopant layers or dopant layers having a greater thickness can provide a greater supply of dopants to the underlying gate dielectric layer, thereby resulting in a greater dopant concentration. For example, a device region having a first dopant layer 1104A and a second dopant layer 1104B (such as 1030A and 1030D) can have a greater dopant concentration than a device region having a layer of the second dopant layer 1104B (such as 1030B and 1030E). In some embodiments, the annealing process 1150 can be a rapid thermal annealing (RTA) process. In some embodiments, the annealing process 1150 may be a stepwise thermal process, a spike annealing process, a rapid annealing, any suitable annealing process, and / or a combination thereof. The annealing process 1150 may be a single-step annealing process or a multi-step annealing process. In some embodiments, the annealing process 1150 may be implemented at a temperature between about 600°C and about 800°C. Higher temperatures may drive dopants in a shorter time, but the upper temperature limit may be determined by the thermal budget of the semiconductor device to be annealed. The annealing process 1150 may be implemented for an appropriate amount of time, for example, the annealing process may be a spike annealing process that implements a time period such as a few seconds or less than one second. In some embodiments, the annealing process may be implemented between about 0.5s and about 1s or between about 1s and about 5s. In some embodiments, the annealing process 1150 may be implemented in a nitrogen-rich environment to prevent oxidation or contamination of the layer. For example, the annealing process may be implemented in a chamber filled with nitrogen.

[0093] After the annealing process 1150, first gate dielectric layers 1102A-1102F are formed in the device regions 1030A-1030F, respectively. The first gate dielectric layers 1102A and 1102D formed in the device regions 1030A and 1030D, respectively, may have a greater dopant concentration than the first gate dielectric layers 1102B and 1102E formed in the device regions 1030B and 1030E, respectively. The higher dopant concentration may be attributed to the formation of more layers of dopant layers in the device regions 1030A and 1030D compared to the device regions 1030B and 1030E. In some embodiments, the first gate dielectric layers 1102A, 1102B, 1102D, and 1102E may be formed of a hafnium oxide material doped with lanthanum. In some embodiments, the atomic doping ratio of lanthanum to hafnium of the first gate dielectric layers 1102A and 1102D may be between about 0.25 and about 0.35. In some embodiments, the atomic doping ratio of lanthanum to hafnium of the first gate dielectric layers 1102B and 1102E may be between about 0.10 and about 0.20. In some embodiments, the first gate dielectric layers 1102A-1102B and 1102D-1102E may be doped with a suitable dopant, such as lanthanum, silicon, yttrium, gadolinium, strontium, any suitable material, and / or combinations thereof. In some embodiments, the first gate dielectric layers 1102C and 1102F may be intrinsic (e.g., undoped) materials. After performing the annealing process 1150, the first dopant layer 1104A and the second dopant layer 1104B may be removed using a suitable etching process that has a high dopant layer selectivity relative to the underlying first gate dielectric layers 1102A-1102F. For example, the etching process may be a wet chemical etching process using a solution such as hydrochloric acid, hydrogen peroxide, and any other suitable etchant.

[0094] Reference Fig. 9 In operation 910, according to some embodiments of the present disclosure, a second gate dielectric layer is deposited in the n-type and p-type device regions, and a treatment process is performed on the first gate dielectric layer and the second gate dielectric layer. FIG. 11F to FIG. 11G, a second gate dielectric layer 1122 is deposited in the device regions 1030A-1030F. The second gate dielectric layer 1122 can be used to achieve a nominal total thickness of the combined first gate dielectric layer and the second gate dielectric layer. The second gate dielectric layer 1122 can be an intrinsic dielectric layer formed using an intrinsic high-k (e.g., a dielectric constant greater than about 3.9) dielectric material. For example, the second gate dielectric layer 1122 can be formed using hafnium dioxide. In some embodiments, the second gate dielectric layer 1122 can be formed using a material similar to the first gate dielectric material 1102. In some embodiments, the thickness of the second gate dielectric layer 1122 can be greater than the thickness of the first gate dielectric layers 1102A-1102F. For example, the second gate dielectric layer 1122 can have a thickness of about Peace In some embodiments, the second gate dielectric layer 1122 may have a thickness between about Peace Between Peace For device reliability and performance purposes, the combined thickness of the first and second gate dielectric layers may be between about Peace For example, the total thickness of the first gate dielectric layer and the second gate dielectric layer can be between about Peace Therefore, the thickness of the second gate dielectric layer 1122 can be used to supplement the thickness of the first gate dielectric layers 1102A-1102F, so that the total thickness of the first gate dielectric layer and the second gate dielectric layer is sufficient to ensure the reliability and performance of the device. In some embodiments, the thickness ratio of the first gate dielectric layer to the second gate dielectric layer can be between about 1.5 and about 3.

[0095] A first capping layer 1130 and a second capping layer 1132 may be deposited on the first gate dielectric layers 1102A-1102F and the second gate dielectric layer 1122. A first treatment process 1160 may be performed between the deposition of the first capping layer 1130 and the second capping layer 1132. A second treatment process 1170 may be performed on the deposited first capping layer 1130 and the second capping layer 1132. The first treatment process 1160 and the second treatment process 1170 may be used to improve the quality of the first gate dielectric layer and the second gate dielectric layer by improving the crystal quality through annealing, and the first capping layer 1130 and the second capping layer 1132 may be used to protect the underlying gate dielectric layer from being directly exposed to the treatment process.

[0096] like Fig.11FAs shown, a first capping layer 1130 is deposited on the second gate dielectric layer 1122 in the n-type and p-type device regions to provide physical protection and prevent oxidation of underlying layers such as the gate dielectric layer and the interface layer. In some embodiments, the first capping layer 1130 can be formed using titanium silicon nitride (TiSiN), titanium nitride, or any suitable material. In some embodiments, the first capping layer 1130 can be formed using any suitable dielectric material including a high-k dielectric material. A treatment process 1160 can be performed on the deposited first capping layer 1130. The first treatment process 1160 can be a post-metal annealing (PMA) process performed in situ after the deposition of the first capping layer 1130. In some embodiments, the first treatment process 1160 can be performed at a temperature between about 850°C and about 900°C. In some embodiments, depending on device requirements and thermal budgets, the first treatment process 1160 can be performed at other suitable temperatures, such as less than about 850°C or greater than 900°C. In some embodiments, the first treatment process can be performed in a nitrogen-rich environment, such as in a chamber filled with nitrogen.

[0097] like Fig.11G As shown, a second capping layer 1132 may be deposited on the first capping layer 1130. A second treatment process 1170, such as an annealing process, may be implemented. In some embodiments, the second capping layer 1132 may be formed using any suitable material, such as silicon. In some embodiments, the second treatment process 1170 may be a post-capping annealing (PCA) process implemented at a higher temperature than the first treatment process 1160. In some embodiments, the second treatment process 1170 may be implemented at a temperature between about 890° C. and about 910° C. In some embodiments, the second treatment process 1170 may be used to further improve the quality of the underlying gate dielectric layer and the interface layer. In some embodiments, the second treatment process 1170 may be used to improve the quality of the interface between the first gate dielectric layer 1102A-1102F and the interface layer 112A.

[0098] Reference Fig. 9 In operation 912, according to some embodiments of the present disclosure, a first work function layer and a capping layer are formed in the n-type device region. Fig.11H, forming a first work function layer 1140 and a capping layer 1142 in an n-type device region such as device regions 1030A-1030C. The first work function layer 1140 and the capping layer 1142 can be formed by blanket depositing the first work function material and the capping material in all exposed device regions (such as device regions 1030A-1030F) and then performing a patterning process. The patterning process may include forming a barrier layer and a mask element in the n-type device region while exposing the first work function material and the capping layer in the p-type device region. The capping layer and the first work function material can be removed from the p-type device region using an etching process. In some embodiments, the etching process may be a wet chemical etching process. For example, the etching process may be an etching process using ammonium hydroxide, hydrogen peroxide, any other suitable solution, and / or a combination thereof. In some embodiments, the etching process may be a dry plasma etching process. The remaining portions of the first work function material and the capping material in the n-type device regions 1030A-1030C form the first work function layer 1140 and the capping layer 1142, respectively. In some embodiments, the first work function layer 1140 may be formed using a material containing aluminum and / or nitrogen. For example, the first work function layer 1140 may be formed using titanium aluminum nitride, titanium aluminum carbonitride, tantalum aluminum nitride, tantalum aluminum carbonitride, any suitable material, and / or a combination thereof. In some embodiments, the first work function layer 1140 may be an n-type work function layer. In some embodiments, the thickness of the first work function layer 1140 may be about 1000 nm. Peace between.

[0099] By performing a treatment process on the first work function layer 1140, a capping layer 1142 may be formed on the first work function layer 1140. In some embodiments, the treatment process may include an in-situ thermal plasma treatment process using titanium chloride and silane as precursors. In some embodiments, the treatment process may be performed at a temperature between about 420° C. and about 480° C. In some embodiments, the treatment temperature may be about 450° C. to prevent oxidation of the first work function layer 1142. In some embodiments, the thickness of the silicon capping layer 1142 may be about 1000 nm. Peace In some embodiments, cover layer 1142 may be optional.

[0100] refer to Fig. 9 In operation 914, according to some embodiments of the present disclosure, a second work function layer and an adhesion layer are formed in the n-type and p-type device regions. Fig.11I, the second work function layer 1180 can be formed in the n-type and p-type device regions 1030A-1030F. The adhesion layer 1190 can be formed on the second work function layer 1180. In some embodiments, the second work function layer 1180 can be formed using any suitable material. For example, the second work function layer 1180 can be a p-type or n-type work function material. In some embodiments, the second work function layer 1180 can be formed using any suitable work function material, such as ruthenium oxide. The second work function layer 1180 can be formed using a substantially conformal deposition process such as ALD or CVD. In some embodiments, the second work function layer 1180 can be formed using an ALD process using dimethylbutadienetricarbonylruthenium (Ru(DMBD)(CO)3) and oxygen as precursors. In some embodiments, the deposition process for forming the second work function layer 1180 can be performed at any suitable temperature, such as between about 180°C and about 250°C. In some embodiments, the thickness of the second work function layer 1180 can be about Peace In some embodiments, adhesion layer 1190 may be formed of titanium nitride, titanium, tantalum, tantalum nitride, any suitable adhesive material, and / or combinations thereof. Adhesion layer 1190 may prevent delamination of underlying layers and promote adhesion of subsequently formed gate electrodes. In some embodiments, adhesion layer 1190 may be formed using a substantially conformal deposition process such as ALD or CVD. In some embodiments, adhesion layer 1190 may also affect the finFET threshold voltage and be considered another work function layer. In some embodiments, the thickness of adhesion layer 1190 may be about Peace In some embodiments, adhesive layer 1190 may be optional.

[0101] Dopants such as lanthanum or magnesium in the doped gate dielectric layer can form an electric dipole structure between the doped gate dielectric layer and the first or second gate dielectric layer, which in turn affects the threshold voltage. The dopant concentration level can affect the threshold voltage. For example, in a doped gate dielectric layer formed of a lanthanum-doped hafnium oxide layer, a larger ratio of lanthanum to hafnium can provide a larger change in the threshold voltage. In some embodiments, an atomic doping ratio of lanthanum to hafnium between about 0.10 and about 0.20 can change the threshold voltage between about 70 mV and about 90 mV. In some embodiments, an atomic doping ratio of lanthanum to hafnium between about 0.25 and about 0.35 can change the threshold voltage between about 140 mV and about 180 mV. Therefore, the exemplary method 900 forms gate dielectric layers 120A-120F and work function layers 130A-130F in regions 1030A-1030F, respectively, which can provide multiple threshold voltages for finFETs 102A-102F. As shown in FIG. Fig.11IAs shown, each device may include different stacks of gate dielectric layers and work function layers that can provide different threshold voltages between devices. Taking n-type device 102A as an example, it can be an ultra-low threshold voltage device including a gate dielectric layer 120A having a first gate dielectric layer 1102A and a second gate dielectric layer 1122. The first gate dielectric layer 1102A can be doped with a suitable dopant, such as lanthanum or magnesium. N-type device 102A can further include a work function layer stack 130A, which includes a first work function layer 1140, a capping layer 1142, a second work function layer 1180, and an adhesion layer 1190. Similarly, n-type device 102B can be a low threshold voltage device having a gate dielectric layer 120B and a work function layer stack 130B, wherein the former includes a first gate dielectric 1102B, which has a lower dopant concentration than the first gate dielectric 1102A of n-type device 102A. Changes in dopant concentrations such as lanthanum or magnesium concentrations in gate dielectric layers 1102A and 1102B may cause changes in the crystal structure of the hafnium-based gate dielectric layer and form electric dipoles at the interface between the gate dielectric layer and the work function layer, which may affect the spontaneous polarization and internal bias field and cause changes in the device threshold voltage.

[0102] Fig.11J The gate dielectric layers 120A-120F and the work function layers 130A-130F formed between the spacers 114 and between each layer of the stack of semiconductor layers 122 are shown. Each of the gate dielectric layers 120A-120F and the work function layers 130A-130F may wrap the nanowire-shaped semiconductor layer 122 formed by removing the first semiconductor layer 320. Depending on the available space between adjacent semiconductor layers 122, the semiconductor layer 122 may be wrapped by the gate dielectric layers 120A-120F and the work function layers 130A-130F, thereby filling the space between adjacent semiconductor layers 122.

[0103] refer to Figure 2 In operation 240, according to some embodiments, a gate electrode is formed on the work function layer. FIG. 12A to FIG. 12B, a conductive material layer for a gate metal filling layer 132 is formed on the work function layers 130A-130F. The conductive material layer for the gate metal filling layer 132 may include a suitable conductive material, such as titanium, silver, aluminum, tungsten, copper, ruthenium, molybdenum, tungsten nitride, cobalt, nickel, titanium carbide, titanium aluminum carbide, manganese, zirconium, metal alloys and / or combinations thereof. The gate metal filling layer 132 may be formed by ALD, PVD, CVD or other suitable deposition processes. The deposition of the gate metal filling layer 132 may continue until the openings between the opposing spacers are filled with the gate metal filling layer 132. The chemical mechanical polishing process may remove excess gate metal filling layer 132, so that the top surfaces of the gate metal filling layer 132 and the ILD 118 are substantially coplanar. In some embodiments, other structures may be formed, such as barrier layers, gate contact structures, and S / D contact structures. One or more barrier layers may be formed before the gate metal filling layer 132 is deposited to prevent diffusion and oxidation of the gate metal filling layer 132. The gate and S / D contact structures can be formed by forming openings in the gate metal filling layer 132 and the ILD 118. A gate contact structure and an S / D contact structure connected to the gate metal filling layer 132 and the epitaxial fin region 110 can be formed. The formation of the contact structure can include depositing a contact metal, followed by CMP of the deposited contact metal. The formation of the contact metal can include depositing a metal layer in the opening and silicide of the deposited metal layer. Conductive materials for the metal layer and / or the contact metal can include titanium, aluminum, silver, tungsten, cobalt, copper, ruthenium, zirconium, nickel, titanium nitride, tungsten nitride, metal alloys and / or combinations thereof, and can be formed by ALD, PVD, CVD or other suitable deposition processes.

[0104] Various embodiments in the present disclosure describe methods for forming a multi-threshold voltage device by multiple deposition and patterning processes to form a doped gate dielectric layer and a multilayer metal work function material as a work function layer in different device regions. A device having a doped gate dielectric layer and a work function layer of different components can be formed on a substrate to form a semiconductor device with a multi-threshold voltage. The doped gate dielectric layer can be a hafnium-based high-k (e.g., a dielectric constant greater than about 3.9) dielectric layer doped with a suitable material such as lanthanum. Changes in dopant concentration can cause changes in the crystal structure of the hafnium-based gate dielectric layer and form an electric dipole at the interface between the gate dielectric layer and the work function layer, which can cause changes in the device threshold voltage. The gate dielectric layer can be doped by depositing an intrinsic gate dielectric layer and depositing one or more dopant-containing films on the intrinsic gate dielectric layer. In some embodiments, an annealing process can be used to drive dopants from the dopant-containing film into the intrinsic gate dielectric layer.

[0105] In some embodiments, a semiconductor device includes a first transistor having a first gate structure, wherein the first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer located on the first gate dielectric layer. The first gate structure also includes a first gate electrode located on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, wherein the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration, the second dopant concentration being lower than the first dopant concentration. The second gate structure also includes a second work function layer located on the second gate dielectric layer and a second gate electrode located on the second work function layer. In the above semiconductor device, the first gate dielectric layer and the second gate dielectric layer include hafnium oxide. In the above semiconductor device, the first dopant includes lanthanum and the second dopant includes magnesium. In the above semiconductor device, the first dopant and the second dopant include lanthanum. The above semiconductor device also includes a third transistor, the third transistor including: a third gate dielectric layer, wherein the third gate dielectric layer includes an intrinsic dielectric material; a third work function layer located on the third gate dielectric layer; and a third gate electrode located on the third work function layer. In the above-mentioned semiconductor device, the third work function layer includes intrinsic hafnium oxide. In the above-mentioned semiconductor device, the first transistor includes an ultra-low threshold voltage n-type transistor. In the above-mentioned semiconductor device, the second transistor includes a low threshold voltage n-type transistor. In the above-mentioned semiconductor device, the first gate dielectric layer also includes a doped dielectric layer and an intrinsic dielectric layer formed on the doped dielectric layer. In the above-mentioned semiconductor device, the first work function layer includes: an n-type work function layer, located on the first gate dielectric layer; a capping layer, located on the n-type work function layer; a p-type work function layer, located on the capping layer; and an adhesive layer, located on the p-type work function layer.

[0106] In some embodiments, a semiconductor device includes a first all-around gate field effect transistor (GAAFET) including a first plurality of nanowires and a first doped gate dielectric layer surrounding the first plurality of nanowires. The first GAA FET has a first work function layer surrounding the first gate dielectric layer and a first gate electrode located on the first work function layer. The semiconductor device also includes a second GAA FET, which includes a second plurality of nanowires and a second doped gate dielectric layer located on the second plurality of nanowires. The first doped gate dielectric layer includes a first dopant concentration that is greater than a second dopant concentration of the second doped gate dielectric layer. A second work function layer is formed on the gate dielectric layer, and a second gate electrode is formed on the second work function layer. In the above semiconductor device, the first doped gate dielectric layer and the second doped gate dielectric layer include hafnium oxide. In the above semiconductor device, the first atomic doping ratio is between about 0.25 and about 0.35. In the above semiconductor device, the second atomic doping ratio is between about 0.10 and about 0.20. In the above semiconductor device, the first doped gate dielectric layer and the second doped gate dielectric layer include lanthanum.

[0107] In some embodiments, a method includes depositing a first gate dielectric material on a plurality of nanowires. The plurality of nanowires are formed in a first device region and a second device region. The method includes forming a first dopant layer on the first gate dielectric material in the first device region, and forming a second dopant layer on the first gate dielectric material in the first device region and on the first gate dielectric material in the second device region. The method includes performing an annealing process on the first gate dielectric material and the first and second dopant layers. The method also includes removing the first and second dopant layers, and depositing the second gate dielectric material on the first gate dielectric material. The method also includes forming a first work function layer on the second gate dielectric material and forming a second work function layer on the first work function layer. The method also includes forming a gate electrode on the second work function layer. In the above method, depositing the first gate dielectric material and the second gate dielectric material includes depositing hafnium oxide. In the above method, forming the first dopant layer and the second dopant layer includes depositing lanthanum oxide. In the above method, performing the annealing process includes performing a rapid thermal anneal (RTA) on the first gate dielectric material and the first dopant layer and the second dopant layer at a temperature between about 600° C. and about 800° C. The method further includes performing a plasma treatment process on the first work function layer using titanium chloride and silane as precursors.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising an N-type device region and a P-type device region, wherein the N-type device region and the P-type device region both comprise: A first transistor includes a first gate structure, wherein the first gate structure includes: a first gate dielectric layer doped with a first dopant having a first atomic doping ratio; a first work function layer, located on the first gate dielectric layer; and A first gate electrode, located on the first work function layer; A second transistor includes a second gate structure, wherein the second gate structure includes: a second gate dielectric layer doped with a second dopant at a second atomic doping ratio, the second atomic doping ratio being lower than the first atomic doping ratio; a second work function layer, located on the second gate dielectric layer; and a second gate electrode, located on the second work function layer; The first work function layer in the N-type device region includes an n-type work function layer and a p-type work function layer, the first work function layer in the P-type device region is an n-type work function layer or a p-type work function layer, and the number of work function layers included in the first work function layer in the N-type device region and the P-type device region is different. The first gate dielectric layer of the first transistor includes a first doped dielectric layer and a first intrinsic dielectric layer formed on the first doped dielectric layer, the second gate dielectric layer of the second transistor includes a second doped dielectric layer and an intrinsic dielectric layer formed on the second doped dielectric layer, and in the N-type device region and the P-type device region, the first doped dielectric layer has a greater dopant concentration than the second doped dielectric layer.

2. The semiconductor device according to claim 1, wherein The first gate dielectric layer and the second gate dielectric layer include hafnium oxide.

3. The semiconductor device according to claim 1, wherein The first dopant includes lanthanum, and the second dopant includes magnesium.

4. The semiconductor device according to claim 1, wherein: The first dopant and the second dopant include lanthanum.

5. The semiconductor device according to claim 1, further comprising a third transistor, the third transistor comprising: a third gate dielectric layer, wherein the third gate dielectric layer comprises an intrinsic dielectric material; a third work function layer, located on the third gate dielectric layer; and The third gate electrode is located on the third work function layer.

6. The semiconductor device according to claim 5, wherein: The third work function layer includes intrinsic hafnium oxide.

7. The semiconductor device according to claim 1, wherein The first transistor comprises an ultra-low threshold voltage N-type transistor.

8. The semiconductor device according to claim 1, wherein The second transistor comprises a low threshold voltage N-type transistor.

9. The semiconductor device according to claim 1, wherein: The first work function layer includes aluminum-doped metal.

10. The semiconductor device according to claim 1, wherein In the N-type device region: The n-type work function layer is located on the first gate dielectric layer; The capping layer is located on the n-type work function layer; The p-type work function layer is located on the cover layer; The adhesive layer is located on the p-type work function layer.

11. A semiconductor device, comprising an N-type device region and a P-type device region, wherein the N-type device region and the P-type device region both comprise: A first all-around gate field effect transistor, comprising: The first multiple nanowires; a first doped gate dielectric layer surrounding the first plurality of nanowires; and a first work function layer surrounding the first doped gate dielectric layer; and A first gate electrode, located on the first work function layer; and The second all-around gate field effect transistor comprises: a second plurality of nanowires; a second doped gate dielectric layer disposed on the second plurality of nanowires, wherein the first doped gate dielectric layer comprises a first atomic doping ratio that is greater than a second atomic doping ratio of the second doped gate dielectric layer; a second work function layer, located on the second doped gate dielectric layer; and a second gate electrode, located on the second work function layer; The first work function layer in the N-type device region includes an n-type work function layer and a p-type work function layer, the first work function layer in the P-type device region is an n-type work function layer or a p-type work function layer, and the number of work function layers included in the first work function layer in the N-type device region and the P-type device region is different. The first doped gate dielectric layer of the first full-ring gate field effect transistor includes a first doped dielectric layer and a first intrinsic dielectric layer formed on the first doped dielectric layer, the second doped gate dielectric layer of the second full-ring gate field effect transistor includes a second doped dielectric layer and an intrinsic dielectric layer formed on the second doped dielectric layer, and in the N-type device region and the P-type device region, the first doped dielectric layer has a greater dopant concentration than the second doped dielectric layer.

12. The semiconductor device according to claim 11, wherein The first doped gate dielectric layer and the second doped gate dielectric layer include hafnium oxide.

13. The semiconductor device according to claim 11, wherein The first atomic doping ratio is between 0.25 and 0.

35.

14. The semiconductor device according to claim 11, wherein The second atomic doping ratio is between 0.10 and 0.

20.

15. The semiconductor device according to claim 11, wherein The first doped gate dielectric layer and the second doped gate dielectric layer include lanthanum.

16. A method of forming a semiconductor device, comprising: depositing a first gate dielectric material on a plurality of nanowires formed in a first device region and a second device region; forming a first dopant layer on the first gate dielectric material in the first device region and in the second device region; performing a first removal operation to remove the first dopant layer in the second device region to expose the first gate dielectric material in the second device region; forming a second dopant layer on the first dopant layer in the first device region and on the first gate dielectric material in the second device region exposed by the first removal operation; performing an annealing process on the first gate dielectric material and the first dopant layer and the second dopant layer; removing the first dopant layer and the second dopant layer; depositing a second gate dielectric material on the first gate dielectric material; forming a first work function layer on the second gate dielectric material; forming a second work function layer on the first work function layer; and A gate electrode is formed on the second work function layer.

17. The method according to claim 16, wherein: Depositing the first gate dielectric material and the second gate dielectric material includes depositing hafnium oxide.

18. The method according to claim 16, wherein: Forming the first dopant layer and the second dopant layer includes depositing lanthanum oxide.

19. The method according to claim 16, wherein: Performing the annealing process includes performing a rapid thermal annealing at a temperature between 600° C. and 800° C. on the first gate dielectric material and the first and second dopant layers. 20 . The method according to claim 16 , further comprising performing a plasma treatment process on the first work function layer using titanium chloride and silane as precursors.

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