Method of forming a semiconductor device structure

Abstract

Methods of forming semiconductor device structures are provided herein. A method includes forming a first gate stack and a second gate stack on a substrate. The substrate has a base and a first fin structure and a second fin structure on the base, and the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure uncovered by the first gate stack and the second fin structure uncovered by the second gate stack. The method includes forming an inner spacer layer on the first fin structure uncovered by the first gate stack. The method includes forming a first stressor and a second stressor on the inner spacer layer and the second fin structure uncovered by the second gate stack, respectively.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to methods of forming semiconductor device structures, and more particularly to spacer layers between fin structures and stressors. BACKGROUND

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in semiconductor integrated circuit materials, design, and manufacturing have produced increasingly sophisticated devices. However, these advances have increased the complexity of processing and manufacturing semiconductor integrated circuits. For

[0003] In the evolution of semiconductor devices, functional density (e.g., the number of interconnected devices per chip area) typically has increased with each successive generation of integrated circuits. Such increasing functional densities have generally been achieved by shrinking the dimensions of features (e.g., transistors) on the chips, and by increasing the density of features on the chips.

[0004] However, as the dimensions of features shrink, fabrication processes become increasingly difficult. As a result, forming reliable semiconductor devices with increasingly smaller dimensions presents challenges. SUMMARY

[0005] One embodiment of the present application provides a method of forming a semiconductor device structure, comprising: forming a first gate stack and a second gate stack on a substrate, wherein the substrate has a base and a first fin structure and a second fin structure on the base, the second fin structure is wider than the first fin structure, the first gate stack covers a first upper side portion of the first fin structure, and the second gate stack covers a second upper side portion of the second fin structure; partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack; forming an inner spacer layer on the first fin structure not covered by the first gate stack; and forming a first stressor and a second stressor on the inner spacer layer and the second fin structure not covered by the second gate stack, respectively.

[0006] A method of forming a semiconductor device structure is provided. The method includes forming a first gate stack on a substrate, wherein the substrate has a base and a first fin structure on the base, the first fin structure includes a first bottom and a first multi-layer stack on the first bottom, the first multi-layer stack includes a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer stacked sequentially on the first bottom, and the first gate stack covers the first multi-layer stack. The method also includes partially removing the first multi-layer stack not covered by the first gate stack. The method further includes partially removing the first sacrificial layer and the second sacrificial layer to form a first recess and a second recess in the first multi-layer stack. The method also includes forming a first inner spacer layer in the first recess and the second recess, and forming a first bottom spacer on the first bottom, wherein the first bottom spacer covers a first sidewall of the first channel layer. The method further includes forming a first stressor on the first bottom spacer, wherein the first bottom spacer separates the first stressor and the first channel layer.

[0007] A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure on the base, wherein the fin structure includes a bottom and a multi-layer stack on the bottom, the multi-layer stack includes a first channel layer and a second channel layer on the first channel layer, and the first channel layer and the second channel layer are separated; a gate stack on the substrate, wherein the gate stack covers the multi-layer stack; an inner spacer layer between the second channel layer and the first channel layer, and between the first channel layer and the bottom; a bottom spacer on the bottom and covering a first sidewall of the first channel layer; and a stressor on the bottom spacer and connected to the second channel layer, wherein the stressor is electrically insulated from the first channel layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1A to 1H Perspective views of various stages of a method of forming a semiconductor device structure in some embodiments.

[0009] Figures 1A-1 to 1H-1 Perspective views of various stages of a method of forming a semiconductor device structure in some embodiments. Figures 1A to 1H Cross-sectional views of the semiconductor device structure along section line I-I’ in

[0010] Figures 1A-2 to 1H-2 Cross-sectional views of the semiconductor device structure along section line II-II’ in Figures 1A to 1H

[0011] Figure 1A-3 Figure 1A Top view of the semiconductor device structure of

[0012] Figure 1F-3 Cross-sectional views of the semiconductor device structure along section line III-III’ in Figure 1F

[0013] Figure 1G-3 ​​​In some embodiments, a semiconductor device structure along Figure 1G Cross-sectional view along section line III-III' of

[0014] Figure 1H-3 In some embodiments, a semiconductor device structure along Figure 1H Cross-sectional view along section line III-III' of

[0015] Figure 1H-4 In some embodiments, a semiconductor device structure along Figure 1H Cross-sectional view along section line IV-IV' of

[0016] Figures 2A to 2M In some embodiments, a top view of various stages of a process of forming a semiconductor device structure.

[0017] Figures 2A-1 to 2M-1 In some embodiments, a cross-sectional view of a semiconductor device structure along Figures 2A to 2M section line I-I' of

[0018] Figures 2A-2 to 2M-2 In some embodiments, a cross-sectional view of a semiconductor device structure along Figures 2A to 2M section line II-II' of

[0019] Figures 2A-3 to 2M-3 In some embodiments, a cross-sectional view of a semiconductor device structure along Figures 2A to 2M section line III-III' of

[0020] Figure 2C-4 In some embodiments, a perspective view of a semiconductor device structure of Figure 2C

[0021] In some embodiments, a perspective view of a semiconductor device structure of Figure 2M-4 Figure 2M

[0022] Figure 2M-5 In some embodiments, a cross-sectional view of a semiconductor device structure along Figure 2M section line IV-IV' of

[0023] Figure 2M-6 In some embodiments, a cross-sectional view of a semiconductor device structure along Figure 2M section line V-V' of

[0024] Figures 3A to 3C In some embodiments, cross-sectional views of various stages of a process of forming a semiconductor device structure.

[0025] Figure 4A In some embodiments, cross-sectional views of various stages of a process of forming a semiconductor device structure. Figure 4B In some embodiments, cross-sectional views of various stages of a process of forming a semiconductor device structure.​​

[0026] Figure 5 is a cross-sectional view of a semiconductor device structure in some embodiments.

[0027] In which the reference signs are explained as follows:

[0028] A1, A2: transistor

[0029] B1: (100) surface

[0030] B2: (110) surface

[0031] D1, D2: distance

[0032] DE1, DE2: depth

[0033] G1, G2, 130, 180, 240: gate stack

[0034] H1: height

[0035] I-I', II-II', III-III': section line

[0036] M1, M2, M11, M12, M13, M31: mask layer

[0037] R1, R2, 114r, 116r, 140a, 140b, 141a, 216a, 217a: recess

[0038] S1, S2, S3, S4, S5, S6, S7: sidewall

[0039] TR, 140t, 211: trench

[0040] T1: thickness

[0041] W1, W2, W3, W4, W5: width

[0042] 100, 300, 400, 500: semiconductor device structure

[0043] 110, 210: substrate

[0044] 112, 213: base

[0045] 114, 116, 216, 217: fin structure

[0046] 114a, 116a, 215: bottom

[0047] 114b, 116b, 114S, 116s, 214S: multilayer stack

[0048] 114b1, 116b1, 214a: sacrificial layer

[0049] 114b2, 116b2, 214b: channel layer

[0050] 114b2', 214b': bottommost channel layer

[0051] 120, 170, 230, 320: dielectric layer

[0052] 122: upper surface

[0053] 132, 182, 242, 330a, 330b: gate dielectric layer

[0054] 134: 244: gate

[0055] 140, 250: spacer layer

[0056] 142, 144: layer

[0057] 150, 270: inner spacer layer

[0058] 150m: inner spacer material layer

[0059] 162, 164, 290, 310: stressor

[0060] 184: work function layer

[0061] 186, 350a, 350b: gate layer

[0062] 212: lower portion

[0063] 214: multilayer structure

[0064] 215a: upper surface

[0065] 220: patterned mask layer

[0066] 260: spacer material layer

[0067] 280, 360: bottom spacer

[0068] 340a, 340b: work function metal layer

[0069] 360a: bottom spacer material layer DETAILED DESCRIPTION

[0070] The following embodiments or examples provide different structures for implementing the present application. The following described embodiments of specific structures and arrangements are not meant to be limiting and that the present application can be practiced in other ways. For example, the description of forming a first structure on a second structure includes embodiments where the two are in direct contact, or embodiments where additional structures are between the two. Also, structures of embodiments of the present application can be formed on, connected to, and / or coupled to another structure, where the structure can be in direct contact with another structure, or additional structures can be formed between the structure and another structure (i.e., the structure is not in direct contact with another structure). Furthermore, numerous examples of the present application can use the same numbers to denote like elements in different embodiments and / or arrangements, but the elements having the same numbers can not necessarily be in corresponding relation to one another.

[0071] Also, structures of embodiments of the present application can be formed on, connected to, and / or coupled to another structure, where the structure can be in direct contact with another structure, or additional structures can be formed between the structure and another structure. Furthermore, relative terms such as "below," "under," "lower," "above," "upper," or the like can be used herein to describe one element's or another's relationship to another element(s) as illustrated in the figures. The relative terms are intended to encompass different orientations of the elements in their implementation or use, for example, in their implementation or working, relative the other elements. The elements can be rotated 90° or at other orientation, and the orientation-might be changed with respect to that shown. The terms of degree such as "substantially", "approximately", and the like, can be used herein in connection with appreciable quantitative differences. The terms of degree can refer to less than or equal to a given value, or to a range of values. The terms of degree are intended to account for variations associated with measurement uncertainty, manufacturing tolerances, measurement error, and other factors that can result in minor variations. The terms of degree are not intended to account only for variations specifically identified in the disclosure. Additional steps can be provided before, during, and after the described stages, and some of these described stages can be replaced or eliminated. Some of these stages can be performed in different sequences. Although some embodiments are described with respect to a particular order of steps, these steps can be performed in another logical order.

[0072] Some embodiments of the present application are described below. Additional steps can be provided before, during, and after the described stages, and some of these described stages can be replaced or eliminated. Some of these stages can be performed in different sequences. Although some embodiments are described with respect to a particular order of steps, these steps can be performed in another logical order.

[0073] The wrap-around gate transistor structure can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including a double patterning or multiple patterning process. Generally, a double patterning process or a multiple patterning process combines photolithography with a self-alignment process that produces a pattern pitch that is smaller than the pattern pitch that would be produced using a single, direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and uses a photolithography process to pattern the sacrificial layer. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the wrap-around gate structure.

[0074] Figures 1A to 1His a perspective view of various stages of a process of forming a semiconductor device structure in some embodiments. Figures 1A-1 to 1H-1 is a cross-sectional view of the semiconductor device structure along Figures 1A to 1H line I-I' in some embodiments. Figures 1A-2 to 1H-2 is a cross-sectional view of the semiconductor device structure along Figures 1A to 1H line II-II' in some embodiments.

[0075] Figure 1A-3 is a top view of the semiconductor device structure in some embodiments. Figure 1A is a top view of the semiconductor device structure in some embodiments. Figure 1A-1 is a cross-sectional view of the semiconductor device structure along Figure 1A-3 line I-I' in some embodiments. Figure 1A-2 is a cross-sectional view of the semiconductor device structure along Figure 1A-3 line II-II' in some embodiments.

[0076] As shown in some embodiments of Figure 1A , Figure 1A-1 , Figure 1A-2 , and Figure 1A-3 , a substrate 110 is provided. In some embodiments, the substrate 110 has a base 112 and fin structures 114 and 116. For example, the base 112 includes a semiconductor substrate. For example, the semiconductor substrate can include a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the base 112 is composed of a semiconductor elemental material, including silicon or germanium in single-crystalline, polycrystalline, or amorphous structures.

[0077] In some embodiments, the base 112 is composed of a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, and / or indium arsenide), a semiconductor alloy (e.g., silicon germanium and / or gallium phosphide arsenide), or a combination thereof. The base 112 can also include multiple layers of semiconductors, a semiconductor-on-insulator (e.g., silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0078] In some embodiments, the base 112 is a device wafer that includes multiple device units. In some embodiments, the multiple device units are formed in and / or on the base 112. The device units are not shown in the figures to simplify the figures and to make the figures clear. Examples of the multiple device units include active devices, passive devices, other suitable units, or a combination thereof. The active devices can include transistors or diodes (not shown). The passive devices include resistors, capacitors, or other suitable passive devices.

[0079] For example, the transistors can be metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar junction transistors, high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors, or the like. Various processes, such as front-end semiconductor fabrication processes, are performed to form various device units. The front-end semiconductor fabrication processes can include deposition, etching, implantation, photolithography, annealing, planarization, one or more other possible processes, or a combination thereof.

[0080] In some embodiments, isolation structures (not shown) are formed in the substrate 112. The isolation structures are used to define active regions and electrically isolate various device units formed in and / or on the substrate 112 in the active regions. In some embodiments, the isolation structures include shallow trench isolation structures, local oxidation of silicon structures, other suitable isolation structures, or a combination thereof.

[0081] In some embodiments, the fin structures 114 and 116 are located on the substrate 112. In some embodiments, the fin structure 116 is wider than the fin structure 114. In some embodiments, the fin structure 114 has a width Wl. In some embodiments, the fin structure 116 has a width W2. In some embodiments, a ratio (W2 / Wl) of the width W2 to the width Wl is greater than about 2. In some embodiments, the ratio (W2 / Wl) is about 2 to about 20.

[0082] In some embodiments, each of the fin structures 114 includes a bottom portion 114a and a multilayer stack 114b. In some embodiments, the multilayer stack 114b is located on the bottom portion 114a. In some embodiments, the multilayer stack 114b includes a sacrificial layer 114bl and a channel layer 114b2. As shown in some embodiments, the sacrificial layer 114bl and the channel layer 114b2 are interleaved. Figure 1A

[0083] It is noted that for simplicity of the drawings, Figure 1A Four layers of the sacrificial layer 114bl and four layers of the channel layer 114b2 are shown for illustration, but embodiments of the present application are not limited thereto. In some embodiments, the number of the sacrificial layer 114bl or the channel layer 114b2 is between 2 and 10.

[0084] In some embodiments, the sacrificial layer 114bl is composed of a first material, such as a first semiconductor material. In some embodiments, the channel layer 114b2 is composed of a second material, such as a second semiconductor material.

[0085] In some embodiments, the first material is different from the second material. In some embodiments, the first material has an etch selectivity with respect to the second material. In some embodiments, the sacrificial layer 114bl is composed of silicon germanium, and the channel layer 114b2 is composed of silicon.​

[0086] In some other embodiments, the composition of the sacrificial layer 114b1 or the channel layer 114b2 is other materials such as germanium, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0087] In some embodiments, the composition of the channel layer 114b2, the bottom 114a, and the substrate 112 can be the same material such as silicon, and the composition of the sacrificial layer 114b1 and the bottom 114a (or the substrate 112) can be different materials. In some other embodiments, the composition of the sacrificial layer 114b1, the channel layer 114b2, and the bottom 114a (or the substrate 112) are different materials. The formation of the sacrificial layer 114b1 and the channel layer 114b2 can employ a molecular beam epitaxy process, an organometallic chemical vapor deposition process, and / or another suitable epitaxial growth process.

[0088] In some embodiments, each fin structure 116 includes a bottom 116a and a multilayer stack 116b. In some embodiments, the multilayer stack 116b is on the bottom 116a. In some embodiments, the multilayer stack 116b includes a sacrificial layer 116b1 and a channel layer 116b2. In some embodiments, the multilayer stack 116b includes a plurality of sacrificial layers 116b1 and a plurality of channel layers 116b2. Figure 1A In some embodiments, the sacrificial layers 116b1 and the channel layers 116b2 are interleaved.

[0089] It is noted that for simplicity of the drawings, Figure 1A Four layers of the sacrificial layers 116b1 and four layers of the channel layers 116b2 are shown for illustration, but embodiments of the application are not limited thereto. In some embodiments, the number of the sacrificial layers 116b1 and the channel layers 116b2 is between 2 and 10.

[0090] In some embodiments, the composition of the sacrificial layers 116b1 is a first material such as a first semiconductor material. In some embodiments, the composition of the channel layers 116b2 is a second material such as a second semiconductor material.

[0091] In some embodiments, the first material is different from the second material. In some embodiments, the first material has an etch selectivity with respect to the second material. In some embodiments, the composition of the sacrificial layers 116b1 is silicon germanium, and the composition of the channel layers 116b2 is silicon.

[0092] In some other embodiments, the sacrificial layers 116b1 and the channel layers 116b2 are composed of other materials (e.g., germanium), semiconductor compounds (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (e.g., gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0093] In some embodiments, the channel layers 116b2, the bottom portions 116a, and the substrate 112 are composed of the same material (e.g., silicon), and the sacrificial layers 116b1 are composed of a different material than the bottom portions 116a (or the substrate 112). In some embodiments, the sacrificial layers 116b1, the channel layers 116b2, and the bottom portions 116a (or the substrate 112) are composed of different materials. In some embodiments, the sacrificial layers 114b1 and 116b1 can be composed of the same material (e.g., silicon germanium). In some embodiments, the channel layers 114b2 and 116b2 can be composed of the same material (e.g., silicon).

[0094] Methods of forming the sacrificial layers 116b1 and the channel layers 116b2 can employ molecular beam epitaxy processes, organometallic chemical vapor deposition processes, and / or another suitable epitaxial growth process.

[0095] As shown in some embodiments, Figure 1A A dielectric layer 120 is formed on the substrate 112. The dielectric layer 120 can be composed of an oxide (e.g., silicon oxide), a fluorosilicate glass, a low-k dielectric material, and / or another suitable dielectric material. The dielectric layer 120 can be formed by an atomic layer deposition process, a chemical vapor deposition process, or another suitable process.

[0096] As shown in some embodiments, Figure 1A , Figure 1A-1 , Figure 1A-3 In some embodiments, the gate stacks 130 are formed on the fin structures 114 and 116 and the dielectric layer 120. In some embodiments, the gate stacks 130 cover the upper portions (e.g., the multi-layer stacks 114b and 116b) of the fin structures 114 and 116.

[0097] In some embodiments, each of the gate stacks 130 includes a gate dielectric layer 132 and a gate 134. In some embodiments, the gate dielectric layer 132, the gate 134, and the mask layers M1 and M2 are sequentially stacked on the fin structures 114 and 116.

[0098] In some embodiments, the gate dielectric layer 132 conformally covers the fin structures 114 and 116 and the dielectric layer 120. In some embodiments, the gate dielectric layer 132 is composed of an insulating material, such as an oxide, e.g., silicon oxide. In some embodiments, the gate 134 is composed of a semiconductor material (e.g., polysilicon) or a conductive material (e.g., a metal or an alloy).

[0099] In some embodiments, the method of forming the gate dielectric layer 132 and the gate 134 includes depositing a layer of gate dielectric material (not shown) on the fin structures 114 and 116 and the dielectric layer 120, depositing a layer of gate material (not shown) on the layer of gate dielectric material, sequentially forming mask layers Ml and M2 on the layer of gate material, wherein the mask layers Ml and M2 expose portions of the layer of gate material, and removing the exposed portions of the layer of gate material and the layer of gate dielectric material thereunder.

[0100] In some embodiments, the mask layer Ml acts as a buffer or adhesion layer between the underlying gate 134 and the overlying mask layer M2. The mask layer Ml can also act as an etch stop layer when the mask layer M2 is removed or etched.

[0101] In some embodiments, the mask layer Ml is composed of an oxide-containing insulating material (e.g., silicon oxide), a nitride-containing insulating material (e.g., silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride), or a metal oxide material (e.g., aluminum oxide).

[0102] In some embodiments, the mask layer Ml is formed by a deposition process, such as a chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma- assisted chemical vapor deposition process, a high density plasma chemical vapor deposition process, a spin-on coating process, or another feasible process.

[0103] In some embodiments, the mask layer M2 is composed of an oxide-containing insulating material (e.g., silicon oxide), a nitride-containing insulating material (e.g., silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride), a metal carbide, or a metal oxide material (e.g., aluminum oxide). In some embodiments, the mask layers Ml and M2 can be composed of different materials.

[0104] In some embodiments, the mask layer M2 is formed by a deposition process, such as a chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma- assisted chemical vapor deposition process, a high density plasma chemical vapor deposition process, a spin-on coating process, or another feasible process.

[0105] After the mask layer Ml and the mask layer M2 are formed, the mask layer Ml and the overlying mask layer M2 are patterned by a photolithography process and an etching process to expose portions of the layer of gate material.

[0106] As Figure 1B、 Figure 1B-1 With some embodiments as shown in FIG. 1A, a spacer layer 140 is conformally formed on the fin structures 114 and 116, the dielectric layer 120, the gate stack 130, and the mask layers Ml and M2. Figure 1B-2 With some embodiments as shown in FIG. 1A, the spacer layer 140 is a multi-layer structure. Figure 1B With some embodiments as shown in FIG. 1A, the spacer layer 140 is a multi-layer structure.

[0107] In some embodiments, the spacer layer 140 includes layers 142 and 144. In some embodiments, the layer 144 is on the layer 142. In some embodiments, the layers 142 and 144 are composed of different materials. In some other embodiments (not shown), the spacer layer 140 is a single layer structure.

[0108] In some embodiments, the layers 142 or 144 are composed of an oxide-containing insulating material, such as silicon oxide. In some other embodiments, the layers 142 or 144 are composed of a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. In some embodiments, the layers 142 and 144 are formed by a deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process.

[0109] As shown in FIG. 1A, the spacer layer 140 is conformally formed on the fin structures 114 and 116, the dielectric layer 120, the gate stack 130, and the mask layers Ml and M2. Figure 1B 、 Figure 1C 、 Figure 1C-1 With some embodiments as shown in FIG. 1A, the spacer layer 140 is a multi-layer structure. Figure 1C-2 With some embodiments as shown in FIG. 1A, the spacer layer 140 is a multi-layer structure.

[0110] In some embodiments, the removal process forms recesses 114r and 116r in the fin structures 114 and 116. In some embodiments, the recess 114r separates each multi-layer structure 114b into a multi-layer stack 114s.

[0111] In some embodiments, each multi-layer stack 114s includes four layers of the sacrificial layer 114bl and four layers of the channel layer 114b2.

[0112] In some embodiments, the recess 116r separates each multi-layer structure 116b into a multi-layer stack 116s.

[0113] In some embodiments, each multi-layer stack 116s includes four laminates of a sacrificial layer 116b1 and four laminates of a via layer 116b2. In some embodiments, the removal process used to form the recesses 114r and 116r includes an etching process, such as an isotropic etching process (e.g., a dry etching process).

[0114] In some embodiments, the removal process forms recesses 140a and 140b in the spacer layer 140.

[0115] In some embodiments, the recesses 140a are formed on and expose the bottoms 114a of the fin structures 114, respectively. In some embodiments, the recesses 140b are formed on and expose the bottoms 116a of the fin structures 116. In some embodiments, the recesses 140a are narrower than the recesses 140b.

[0116] As shown in some embodiments, Figure 1D , Figure 1D-1 and Figure 1D-2 , portions of the sacrificial layers 114b1 are removed from the sidewalls S1 of the sacrificial layers 114b1 to form recesses R1 in the multi-layer stacks 114s. In some embodiments, a corresponding sacrificial layer 114b1 and a corresponding via layer 114b2 surround each of the recesses R1.

[0117] As shown in some embodiments, Figure 1D , portions of the sacrificial layers 116b1 are removed from the sidewalls S2 of the sacrificial layers 116b1 to form recesses R2 in the multi-layer stacks 116s. In some embodiments, a corresponding sacrificial layer 116b1 and a corresponding via layer 116b2 surround each of the recesses R2. In some embodiments, the process of removing the sacrificial layers 114b1 and 116b1 can include an etching process, such as an isotropic etching process (e.g., a dry etching process or a wet etching process).

[0118] As shown in some embodiments, Figure 1D , Figure 1E , Figure 1E-1 and Figure 1E-2 , an inner spacer material layer 150m is formed in the recesses 140a, 140b, R1, and R2. In some embodiments, because the recesses 140a are narrower than the recesses 140b, the inner spacer material layer 150m fills the recesses 140a, and the inner spacer material layer 150m conformably covers the inner sidewalls and the lower surfaces of the recesses 140b.

[0119] The composition of the inner spacer material layer 150m and the spacer layer 140 can be different materials. In some embodiments, the composition of the inner spacer material layer 150m is an oxide-containing insulating material such as silicon oxide. In some other embodiments, the composition of the inner spacer material layer 150m is a nitride-containing insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide nitride, or silicon carbide nitride. In some embodiments, the formation method of the inner spacer material layer 150m can employ a deposition process such as a chemical vapor deposition process or a physical vapor deposition process.

[0120] Figure 1F-3 In some embodiments, the semiconductor device structure is along the cross-sectional view of the cross-sectional line III-III’ in FIG. 1C. Figure 1F Figure 1F , Figure 1F-1 , Figure 1F-2 In some embodiments, the inner spacer material layer 150m is partially removed as shown in some embodiments in FIG. 1D. In some embodiments, the removal process can remove the inner spacer material layer 150m covering the sidewalls S3 and S4 and the bottom 116a of the channel layers 114b2 and 116b2. Figure 1F-3 In some embodiments, the remaining inner spacer material layer 150m forms an inner spacer layer 150. In some embodiments, the inner spacer layer 150 is located in the recesses 140a of the spacer layer 140 and the recesses R1 and R2 of the multi-layer stacks 114S and 116s. In some embodiments, the inner spacer layer 150 is located on the bottom 114a and the spacer layer 140. In some embodiments, the inner spacer layer 150 is located on the bottom 116a and the spacer layer 140.

[0121] In some embodiments, the inner spacer layer 150 and the spacer layer 140 surround the recesses 141a as shown in some embodiments in FIG. 1E. Figure 1F-2

[0122] In some embodiments, the semiconductor device structure is along the cross-sectional view of the cross-sectional line III-III’ in FIG. 2C. Figure 1G-3 Figure 1G , Figure 1G , Figure 1G-1 , Figure 1G-2 In some embodiments, the stressors 162 and 164 are formed on the inner spacer layer 150 and the bottom 116a, respectively, as shown in some embodiments in FIG. 2D. Figure 1G-3 In some embodiments, the stressor 162 is partially located in the corresponding recess 141a as shown in some embodiments in FIG. 2E. In some embodiments, the stressor 164 is partially located in the recess 140b. In some embodiments, the stressor 164 directly contacts the bottom 116a.

[0123] Figure 1G-2 In some embodiments, due to the formation of the stressors 162 and 164 (see FIG. 2D), the inner spacer material layer 150m is removed from the sidewalls S3 and S4 of the channel layers 114b2 and 116b2 and the bottom 116a as shown in some embodiments in FIG. 2E.

[0124] In some embodiments, the inner spacer material layer 150m is removed from the sidewalls S3 and S4 of the channel layers 114b2 and 116b2 and the bottom 116a due to the formation of the stressors 162 and 164 (see FIG. 2D) as shown in some embodiments in FIG. 2E. Figure 1G-2 ​​​) time, the spacer layer 140 originally located on the sidewalls of the multi-layer stacks 114b and 116b (see Figure 1B-2 ), the remaining spacer layer 140 can limit the size (e.g., width) of the stressors 162 and 164 to avoid bridging between adjacent stressors 162 and 164. Thus, in some embodiments, the yield of the stressors 162 and 164 can be improved.

[0125] In some embodiments, the stressors 162 and 164 are composed of a semiconductor material (e.g., silicon germanium) and a p-type dopant (e.g., a Group IIIA element). The Group IIIA element includes boron or another suitable material.

[0126] In some other embodiments, the stressors 162 and 164 are composed of a semiconductor material (e.g., silicon) and an n-type dopant (e.g., a Group VA element). The Group VA element includes phosphorus, antimony, or another suitable Group VA material. In some embodiments, the method of forming the stressors 162 and 164 employs an epitaxial process.

[0127] Figure 1H-3 In some embodiments, the semiconductor device structure is along a cross-sectional view of the cross-sectional line III-III’ in Figure 1H As shown in some embodiments in Figure 1H , Figure 1H-1 , Figure 1H-2 and Figure 1H-3 , a dielectric layer 170 is formed on the stressors 162 and 164 and the spacer layer 140. In some embodiments, the dielectric layer 170 can be composed of an oxide-containing insulating material (e.g., silicon oxide) or a nitride-containing insulating material (e.g., silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride).

[0128] As shown in some embodiments in Figure 1H , Figure 1H-1 , Figure 1H-2 and Figure 1H-3 , the gate 134 is removed to form a trench 140t in the spacer layer 140. In some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0129] As shown in some embodiments in Figure 1H , Figure 1H-1 and Figure 1H-3 , the gate dielectric layer 132 is removed via the trench 140t. In some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0130] As shown in some embodiments in Figure 1H-1 and Figure 1H-3 , the sacrificial layers 114b1 and 116b1 are removed via the trench 140t. In some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0131] As Figure 1H , Figure 1H-1 With Figure 1H-3 some embodiments, a gate stack 180 is formed in the trench 140t. In some embodiments, this step substantially forms the semiconductor device structure 100. In some embodiments, each gate stack 180 includes a gate dielectric layer 182, a work function layer 184, and a gate layer 186.

[0132] In some embodiments, the gate dielectric layer 182, the work function layer 184, and the gate layer 186 are sequentially stacked on the channel layers 114b2 and 116b2. In some embodiments, the gate stack 180 covers the channel layers 114b2 and 116b2.

[0133] In some embodiments, the inner spacer layer 150 can prevent leakage current between the stressor 162 and the bottom 114a because the inner spacer layer 150 electrically isolates the stressor 162 on top of it and the bottom 114a underneath it.

[0134] Leakage current is positively related to the voltage across the stressor, which is positively related to the resistance of the channel layer, which is negatively related to the channel area. Because the fin 116 is wider than the fin 114, the channel layer 116b2 of the fin 116 is wider than the channel layer 114b2 of the fin 114 (see Figure 1H-4 ), and the channel area of the channel layer 116b2 is larger than that of the channel layer 114b2. In some embodiments, the voltage across the stressor 164 is therefore lower than that across the stressor 162. In some embodiments, the leakage current between the stressor 164 and the bottom 116a is therefore significantly smaller than that between the stressor 162 and the bottom 114a. As such, even if the inner spacer layer 150 is not present between the stressor 164 and the bottom 116a, the leakage current between the stressor 164 and the bottom 116a is small and acceptable.

[0135] Figures 2A to 2M is a top view of various stages of a process of forming a semiconductor device structure in some embodiments. Figures 2A-1 to 2M-1 is a cross-sectional view of a semiconductor device structure along the cross-sectional line I-I’ in Figures 2A to 2M some embodiments. Figures 2A-2 to 2M-2 is a cross-sectional view of a semiconductor device structure along the cross-sectional line II-II’ in Figures 2A to 2M some embodiments. Figures 2A-3 to 2M-3 is a cross-sectional view of a semiconductor device structure along the cross-sectional line III-III’ in Figures 2A to 2M some embodiments.

[0136] As Figure 2A , Figure 2A-1 , Figure 2A-2 With Figure 2A-3 As shown in some embodiments, a substrate 210 is provided. In some embodiments, the substrate 210 includes an underside portion 212 and a multilayer structure 214. In some embodiments, the multilayer structure 214 is formed on the underside portion 212.

[0137] For example, the underside portion 212 includes a semiconductor substrate. For example, the semiconductor substrate includes a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the underside portion 212 is composed of a semiconductor elemental material, which includes single-crystalline, polycrystalline, or amorphous structures of silicon or germanium.

[0138] In some other embodiments, the underside portion 212 is composed of a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, and / or indium arsenide), a semiconductor alloy (e.g., silicon germanium and / or gallium phosphide arsenide), or a combination thereof. The underside portion 212 can also include a multilayer semiconductor, a semiconductor-on-insulator (e.g., silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0139] In some embodiments, the underside portion 212 is a device wafer that includes a plurality of device units. In some embodiments, the plurality of device units is formed in and / or on the underside portion 212. The device units are not shown in the figures to simplify and clarify the figures. Examples of the plurality of device units can include active devices, passive devices, other suitable units, or a combination thereof. The active devices can include transistors or diodes (not shown). The passive devices can include resistors, capacitors, or other suitable passive devices.

[0140] For example, the transistors can be metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar junction transistors, high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors, or the like. A plurality of processes such as front-end semiconductor fabrication processes can be performed to form the plurality of device units. The front-end semiconductor fabrication processes can include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0141] In some embodiments, an isolation structure (not shown) is formed in the underside portion 212. The isolation structure is used to define an active region and electrically isolate the plurality of device units formed in and / or on the underside portion 212 in the active region. In some embodiments, the isolation structure includes a shallow trench isolation structure, a local silicon oxide structure, other suitable isolation structures, or a combination thereof.

[0142] In some embodiments, the multilayer structure 214 includes a sacrificial layer 214a and a channel layer 214b. As shown in some embodiments, the sacrificial layer 214a is formed on the underside portion 212. In some embodiments, the channel layer 214b is formed on the sacrificial layer 214a. Figure 2A-1In some embodiments, the sacrificial layers 214a and the channel layers 214b are interleaved. It is noted that the figures are simplified for illustration purposes, Figure 2A-1 Four of the sacrificial layers 214a and four of the channel layers 214b are shown for illustration, but embodiments of the application are not limited thereto. In some embodiments, the number of sacrificial layers 214a or channel layers 214b is between 2 and 10.

[0143] In some embodiments, the sacrificial layers 214a are composed of a first material, such as a first semiconductor material. In some embodiments, the channel layers 214b are composed of a second material, such as a second semiconductor material.

[0144] In some embodiments, the first material is different from the second material. In some embodiments, the first material has an etch selectivity with respect to the second material. In some embodiments, the sacrificial layers 214a are composed of silicon germanium, and the channel layers 214b are composed of silicon.

[0145] In some embodiments, the sacrificial layers 214a or the channel layers 214b are composed of other materials, such as germanium, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0146] In some embodiments, the channel layers 214b and the lower portion 212 are composed of the same material, such as silicon, and the sacrificial layers 214a and the lower portion are composed of a different material. In some other embodiments, the sacrificial layers 214a, the channel layers 214b, and the lower portion 212 are composed of different materials. The sacrificial layers 214a and the channel layers 214b can be formed using a molecular beam epitaxy process, an organometallic chemical vapor deposition process, and / or another suitable epitaxial growth process.

[0147] As shown in FIG. 2A, a plurality of layers 214 is formed on the substrate 210. In some embodiments, the plurality of layers 214 includes a plurality of sacrificial layers 214a and a plurality of channel layers 214b. In some embodiments, the plurality of layers 214 includes a plurality of sacrificial layers 214a and a plurality of channel layers 214b interleaved with the plurality of sacrificial layers 214a. Figure 2A Figure 2A-1 Figure 2A-2 As shown in FIG. 2B, a patterned mask layer 220 is formed on the plurality of layers 214. In some embodiments, the patterned mask layer 220 exposes portions of the substrate 210 (or the plurality of layers 214). Figure 2A-3 In some embodiments, the patterned mask layer 220 is composed of an oxide material, such as silicon oxide, a nitride material, such as silicon nitride, or another suitable material, which is different from the material of the substrate 210 (or the plurality of layers 214). In some embodiments, the patterned mask layer 220 is formed using a deposition process (such as a physical vapor deposition process or a chemical vapor deposition process), a photolithography process, and an etching process (such as a dry etching process).

[0148] In some embodiments, the patterned mask layer 220 is composed of an oxide material, such as silicon oxide, a nitride material, such as silicon nitride, or another suitable material, which is different from the material of the substrate 210 (or the plurality of layers 214). In some embodiments, the patterned mask layer 220 is formed using a deposition process (such as a physical vapor deposition process or a chemical vapor deposition process), a photolithography process, and an etching process (such as a dry etching process).​​

[0149] As Figure 2A , Figure 2B , Figure 2B-1 , Figure 2B-2 With Figure 2B-3 some embodiments, portions of the substrate 210 exposed by the removal of the patterned masking layer 220 are removed. As Figure 2B , Figure 2B-2 With Figure 2B-3 some embodiments, a removal process forms the trench 211 in the substrate 210.

[0150] In some embodiments, the substrate 210 after the removal process has remaining portions including the base 213 and the fin structures 216 and 217. In some embodiments, the fin structures 216 and 217 are on the base 213. As Figure 2A-1 , Figure 2A-2 With Figure 2A-3 some embodiments, the base 213 is formed from the lower portion 212.

[0151] In some embodiments, the fin structure 216 or 217 includes a bottom 215 and a portion of the multilayer structure 214, which includes a sacrificial layer 214a and a channel layer 214b. As Figure 2A-1 , Figure 2A-2 With Figure 2A-3 some embodiments, the bottom 215 is formed from the lower portion 212. In some embodiments, the fin structures 216 and 217 are separated from each other. To simplify the drawings and make the drawings clear, some structures between the fin structures 216 and 217 are omitted in some embodiments as Figure 2B and Figure 2B-1 .

[0152] As Figure 2A With Figure 2B some embodiments, the patterned masking layer 220 is then removed. As Figure 2B , Figure 2B-2 With Figure 2B-3 some embodiments, a dielectric layer 230 is formed in the trench 211. The composition of the dielectric layer 230 can be an oxide (such as silicon oxide), a fluorosilicate glass, a low-k dielectric material, and / or another suitable dielectric material.

[0153] Figure 2C-4 is a perspective view of a semiconductor device structure in some embodiments, Figure 2C As Figure 2C , Figure 2C-1 , Figure 2C-2 , Figure 2C-3 and Figure 2C-4In some embodiments, the gate stacks 240 are formed on the fin structures 216 and 217 and the dielectric layer 230. In some embodiments, the gate stacks 240 wrap around the multilayer structures 214 of the fin structures 216 and 217, respectively.

[0154] In some embodiments, each of the gate stacks 240 includes a gate dielectric layer 242 and a gate 244. In some embodiments, the gate dielectric layer 242 and the gate 244 are sequentially stacked on the fin structures 216 and 217.

[0155] In some embodiments, the gate dielectric layer 242 is between the gate 244 and the fin structure 216 or 217. In some embodiments, the gate dielectric layer 242 is composed of an insulating material, such as an oxide (e.g., silicon oxide). In some embodiments, the gate 244 is composed of a semiconducting material (e.g., polysilicon) or a conductive material (e.g., a metal or an alloy).

[0156] In some embodiments, the method of forming the gate dielectric layer 242 and the gate 244 includes conformally depositing a layer of a gate dielectric material (not shown) on the fin structures 216 and 217 and the dielectric layer 230, depositing a layer of a gate material (not shown) on the layer of the gate dielectric material, forming a mask layer (not shown) on the layer of the gate material, wherein the mask layer exposes portions of the layer of the gate material, removing the exposed portions of the layer of the gate material and the underlying layer of the gate dielectric material, and removing the mask layer.

[0157] As shown in FIG. 2B, Figure 2C , Figure 2C-1 , Figure 2C-2 , Figure 2C-3 and Figure 2C-4 In some embodiments, the spacer layer 250 is formed on the sidewalls of the gate stacks 240. In some other embodiments (not shown), the spacer layer 250 is a multilayer structure. The spacer layer 250 can be composed of a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride. In some embodiments, the method of forming the spacer layer 250 can employ a deposition process (e.g., a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process) and an etching process.

[0158] As shown in FIG. 2C, Figure 2D , Figure 2D-1 , Figure 2D-2 and Figure 2D-3 In some embodiments, the upper portions (e.g., the multilayer structures 214) of the fin structures 216 and 217 that are not covered by the gate stacks 240 and the spacer layer 250 are removed.

[0159] In some embodiments, a removal process forms recesses 216a and 217a in the fin structures 216 and 217, respectively. In some embodiments, the recesses 216a and 217a divide each multi-layer structure 214 into a multi-layer stack 214S. In some embodiments, each multi-layer stack 214S includes four layers of the sacrificial layer 214a and four layers of the channel layer 214b. In some embodiments, the removal process used to form the recesses 216a and 217a includes an etching process, such as an isotropic etching process (e.g., a dry etching process).

[0160] As shown in some embodiments, Figure 2D , Figure 2D-1 , Figure 2D-2 and Figure 2D-3 , portions of the sacrificial layer 214a are removed from the sidewalls S5 of the sacrificial layer 214a to form recesses R1 in the multi-layer stacks 214S. In some embodiments, a corresponding sacrificial layer 214a and a corresponding channel layer 214b surround each recess R1. In some embodiments, the removal process includes an etching process, such as an isotropic etching process (e.g., a dry etching process or a wet etching process).

[0161] As shown in some embodiments, Figure 2E , Figure 2E-1 , Figure 2E-2 and Figure 2E-3 , a spacer material layer 260 is deposited on the multi-layer stacks 214S, the bottom 215, the gate stack 240, and the spacer layer 250. In some embodiments, the spacer material layer 260 fills the recesses R1 of the multi-layer stacks 214S. The composition of the spacer material layer 260 can be an oxide-containing insulating material, such as silicon oxide. In some other embodiments, the composition of the spacer material layer 260 is a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride.

[0162] As shown in some embodiments, Figure 2F , Figure 2F-1 , Figure 2F-2 and Figure 2F-3 , portions of the spacer material layer 260 are removed. In some embodiments, the removal process can remove the spacer material layer 260 that covers the sidewalls S6 of the top three channel layers 214b of the multi-layer stacks 214S.

[0163] In some embodiments, the spacer material layer 260 that remains in the recesses R1 forms an inner spacer layer 270. In some embodiments, the spacer material layer 260 that remains in the recesses 216a and 217a (or the spacer material layer 260 that remains on the bottom 215) forms a bottom spacer 280.

[0164] In some embodiments, the channel layers 214b of the fin structures 216 and 217 include a bottommost channel layer 214b'. In some embodiments, the bottom spacers 280 cover sidewalls S6 of both sides of each of the bottommost channel layers 214b' of the fin structures 216 and 217. In some embodiments, the bottommost channel layer 214b' of the fin structure 216 is between the bottom spacers 280 in the recess 216a. In some embodiments, the bottommost channel layer 214b' of the fin structure 217 is between the bottom spacers 280 in the recess 217a.

[0165] In some other embodiments (not shown), the bottom spacers 280 cover sidewalls S6 of two or three bottommost channel layers 214b', as desired. In some embodiments, the removal process includes an isotropic etching process, such as a dry etching process or a wet etching process.

[0166] As shown in some embodiments, Figure 2G , Figure 2G-1 , Figure 2G-2 and Figure 2G-3 , a mask layer M11 is formed over the bottom spacers 280 in the recess 217a, the fin structure 217, and the gate stack 240 on the fin structure 217. In some embodiments, the mask layer M11 is composed of a polymeric material (such as a photoresist material) or another suitable material that is different from the materials of the bottom spacers 280, the inner side spacer layer 270, the spacer layer 250, the fin structures 216 and 217, and the gate stack 240.

[0167] As shown in some embodiments, Figure 2H , Figure 2H-1 , Figure 2H-2 and Figure 2H-3 , the bottom spacers 280 in the recess 216a are removed. In some embodiments, the removal process includes an etching process that employs the mask layer M11 as an etching mask. In some embodiments, the etching process includes a dry etching process and / or a wet etching process. As shown in embodiments, Figure 2H , Figure 2H-1 , Figure 2H-2 and Figure 2H-3 , the mask layer M11 is removed.

[0168] As shown in some embodiments, Figure 2I , Figure 2I-1 , Figure 2I-2 and Figure 2I-3 , a mask layer M12 is formed over the fin structure 216 and the gate stack 240 on the fin structure 216. In some embodiments, the mask layer M12 is composed of a polymeric material (such as a photoresist material) or another suitable material that is different from the materials of the inner side spacer layer 270, the spacer layer 250, the fin structures 216 and 217, and the gate stack 240.

[0169] As Figure 2I , Figure 2I-1 , Figure 2I-2 With Figure 2I-3 some embodiments, a stressor 290 is formed on the sidewall S6 of the channel layer 214b of the fin structure 217. In some embodiments, the stressor 290 directly contacts the channel layer 214b of the fin structure 217. In some embodiments, the stressor 290 is located in the recess 217a and on the bottom spacer 280.

[0170] In some embodiments, the stressor 290 is composed of a semiconductor material (e.g., silicon) and n-type dopants (e.g., a VA group element). The VA group element can include phosphorus, antimony, or another suitable VA group material. In some embodiments, the stressor 290 is formed using an epitaxial process.

[0171] As Figure 2J , Figure 2J-1 , Figure 2J-2 With Figure 2J-3 some embodiments, a mask layer M13 is formed on the stressor 290, the fin structure 217, and the gate stack 240 on the fin structure 217. In some embodiments, the mask layer M13 is composed of a polymer material (e.g., a photoresist material) or another suitable material that is different from the materials of the stressor 290, the gate stack 240, the spacer layer 250, and the fin structures 216 and 217.

[0172] As Figure 2J , Figure 2J-1 , Figure 2J-2 With Figure 2J-3 some embodiments, a stressor 310 is formed on the sidewall S6 of the channel layer 214b of the fin structure 216. In some embodiments, the stressor 310 directly contacts the channel layer 214b of the fin structure 216. In some embodiments, the stressor 310 is located in the recess 216a.

[0173] In some embodiments, the stressor 310 is composed of a semiconductor material (e.g., silicon germanium) and p-type dopants (e.g., a IIIA group element). The IIIA group element can include boron or another suitable material.

[0174] As Figure 2K , Figure 2K-1 , Figure 2K-2 With Figure 2K-3 some embodiments, the mask layer M13 is removed. As Figure 2L , Figure 2L-1 , Figure 2L-2 With Figure 2L-3In some embodiments shown, dielectric layer 320 is formed on stress sources 290 and 310 and dielectric layer 230. In some embodiments, dielectric layer 320 is composed of an oxide-containing insulating material (such as silicon oxide) or a nitride-containing insulating material (such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride).

[0175] like Figure 2L and Figure 2L-1 In some embodiments shown, the gate stack 240 is removed to form a trench TR in the spacer layer 250. In some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0176] like Figure 2L and Figure 2L-1 In some embodiments shown, the sacrificial layer 214a is removed via a trench TR. In some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0177] Figure 2M-4 In some embodiments, Figure 2M A perspective view of the structure of a semiconductor device. (e.g.) Figure 2M , Figure 2M-1 , Figure 2M-2 , Figure 2M-3 and Figure 2M-4 In some embodiments shown, gate stacks G1 and G2 are formed in trench TR. In some embodiments, gate stack G1 is formed on channel layer 214b of fin structure 216. In some embodiments, gate stack G2 is formed on channel layer 214b of fin structure 217.

[0178] like Figure 2M-1 In some embodiments shown, each gate stack G1 includes a gate dielectric layer 330a, a work function metal layer 340a, and a gate layer 350a. In some embodiments, the gate dielectric layer 330a, the work function metal layer 340a, and the gate layer 350a are sequentially stacked on the channel layer 214b of the fin structure 216.

[0179] In some embodiments, each gate stack G2 includes a gate dielectric layer 330b, a work function metal layer 340b, and a gate layer 350b. In some embodiments, the gate dielectric layer 330b, the work function metal layer 340b, and the gate layer 350b are sequentially stacked on the channel layer 214b of the fin structure 217.

[0180] In some embodiments, the dielectric constant of the gate dielectric layers 330a and 330b is greater than the dielectric constant of silicon oxide. In some embodiments, the gate dielectric layers 330a and 330b can also be considered high-k layers. The gate dielectric layers 330a and 330b can be composed of a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloys, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-k material, or combinations of the above.

[0181] In some embodiments, the work function metal layers 340a and 340b are composed of different materials. In some embodiments, the gate stack G1 is used to form a p-type metal oxide semiconductor transistor, and thus the work function metal layer 340a is used to provide a work function suitable for the device, such as greater than or equal to about 4.8 eV. The work function metal layer 340a can be composed of a metal, a metal carbide, a metal nitride, another suitable material, or combinations of the above. For example, the work function metal layer 340a can be composed of titanium, titanium nitride, another suitable material, or combinations of the above.

[0182] In some embodiments, the gate stack G2 is used to form an n-type metal oxide semiconductor transistor, and thus the work function metal layer 340b is used to provide a work function suitable for the device, such as less than or equal to about 4.5 eV. The work function metal layer 340b can be composed of a metal, a metal carbide, a metal nitride, or combinations of the above. For example, the work function metal layer 340b can be composed of tantalum, tantalum nitride, or combinations of the above.

[0183] In some embodiments, the gate layers 350a and 350b are composed of a suitable conductive material such as a metal (such as aluminum, tungsten, gold, platinum, or cobalt), an alloy of the above, or combinations of the above. In some embodiments, the bottom spacer 280 in the recess 217a electrically isolates the "stressor 290 and the underlying bottom 215" and the "bottommost channel layer 214b' of the fin structure 217." In some embodiments, the bottom spacer 280 separates the stressor 290 from the bottommost channel layer 214b'.

[0184] As shown in some embodiments, Figure 2M-1 The gate stack G1 together with the stressor 310 adjacent thereto can form a transistor Al. In some embodiments, the transistor Al includes a p-type field effect transistor. In some embodiments, the gate stack G2 together with the stressor 290 adjacent thereto can form a transistor A2. In some embodiments, the transistor A2 includes an n-type field effect transistor.

[0185] As shown in some embodiments, Figure 2M-5 and Figure 2M-6In some embodiments shown, electrons have high mobility on the (100) surface B1 of channel layer 214b, while holes have high mobility on the (110) surface B2 of channel layer 214b. In some embodiments, because the width W3 of the (100) surface B1 is greater than the height H1 of the (110) surface B2, the drive current of the n-type field-effect transistor is higher than that of the p-type field-effect transistor, causing a current mismatch between the n-type and p-type field-effect transistors, thus reducing the performance of the n-type and p-type field-effect transistors. In some embodiments, the bottom spacer 280 is used to reduce the number of channel layers 214b connected to the stress source 290. In some embodiments, this can therefore reduce the drive current of transistor A2 (e.g., an n-type field-effect transistor) to match the drive current of transistor A1 (e.g., a p-type field-effect transistor). In some embodiments, this thus improves the performance of transistors A1 and A2.

[0186] Reducing the number of channel layers connected to stress sources can meet various needs, such as reducing transistor drive current, lowering capacitor values, and improving the speed of input / output devices. The speed of input / output devices is negatively correlated with parasitic capacitance.

[0187] like Figure 2M-1 In some embodiments shown, the width W4 or W5 of the gate stack G1 or G2 is about 5 nm to about 20 nm. In some embodiments, the thickness T1 of each channel layer 214b is about 2 nm to about 10 nm. In some embodiments, the distance D1 between two adjacent channel layers 214b of the fin structure 216 is about 5 nm to about 15 nm. In some embodiments, the distance D2 between two adjacent channel layers 214b of the fin structure 217 is about 5 nm to about 18 nm. In some embodiments, the depth DE1 of the recess 216a extending into the bottom 215 is about 1 nm to about 15 nm. In some embodiments, the depth DE2 of the recess 217a extending into the bottom 215 is about 1 nm to about 15 nm. In some other embodiments (not shown), the recesses 216a and 217a do not extend into the bottom 215.

[0188] Figures 3A-3C These are cross-sectional views of various stages in the fabrication process that forms the semiconductor device structure in some embodiments. For example... Figure 3A Some of the embodiments shown are in Figure 2E After the steps, the spacer material layer 260 outside the recess R1 can be removed. In some embodiments, the spacer material layer 260 retained in the recess R1 may form an inner spacer layer 270.

[0189] like Figure 3AIn some embodiments shown, the bottom spacer material layer 360a is formed in the recesses 216a and 217a. In some embodiments, the inner spacer layer 270 and the bottom spacer material layer 360a are composed of different materials. In some other embodiments, the inner spacer layer 270 and the bottom spacer material layer 360a are composed of the same material.

[0190] The bottom spacer material layer 360a may be composed of an oxide-containing insulating material, such as silicon oxide. In some other embodiments, the bottom spacer material layer 360a may be composed of a nitride-containing insulating material, such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride.

[0191] In some embodiments, the bottom spacer material layer 360a may be formed by a deposition process (such as a chemical vapor deposition process or a physical vapor deposition process) and a planarization process (such as a chemical mechanical polishing process).

[0192] like Figure 3B In some embodiments shown, the upper portion of the bottom spacer material layer 360a is removed. In some embodiments, the bottom spacer material layer 360a retained in the recesses 216a and 217a forms the bottom spacer 360. In some embodiments, the bottom spacer 360 covers the sidewall S7 of the lower portion of the inner spacer layer 270 and the sidewall S6 of the bottommost channel layer 214b' of the fin structures 216 and 217. In some embodiments, the removal process includes an etching process such as a dry etching process or a wet etching process.

[0193] like Figure 3B In some embodiments shown, a mask layer M31 is then formed over the bottom spacer 360, fin structure 217, gate stack 240 on fin structure 217, and spacer layer 250 on fin structure 217 in recess 217a. In some embodiments, the mask layer M31 is composed of a polymer material (such as a photoresist material) or another suitable material that differs from the material of the bottom spacer 360, inner spacer layer 270, spacer layer 250, fin structures 216 and 217, and gate stack 240.

[0194] like Figure 3B and Figure 3C In some embodiments shown, the bottom spacer 360 in the recess 216a is removed. In some embodiments, the removal process includes an etching process using a mask layer M31 as an etching mask. In some embodiments, this is followed by... Figures 2I-2M The steps are to form stress sources 290 and 310, dielectric layer 320, and gate stacks G1 and G2. In some embodiments, this step substantially forms semiconductor device structure 300.

[0195] Figure 4A andFigure 4B These are cross-sectional views of various stages in the fabrication process that forms the semiconductor device structure in some embodiments. For example... Figure 4A Some of the embodiments shown are in Figure 2E After the step, the spacer material layer 260 covering the sidewalls S6 of the three highest channel layers 214b of the fin structures 216 and 217 is removed.

[0196] In some embodiments, the spacer material layer 260 retained in the recess R1 forms an inner spacer layer 270. In some embodiments, the inner spacer layer 270 covers the upper surface 215a of the bottom 215 and the sidewall S6 of the bottom channel layer 214b' of the fin structures 216 and 217.

[0197] like Figure 4B In some embodiments shown, the inner spacer layer 270 covering the upper surface 215a of the bottom of the fin structure 216 and the sidewall S6 of the bottom channel layer 214b' is removed. In some embodiments, the retained inner spacer layer 270 covers the upper surface 215a of the bottom of the fin structure 217 and the sidewall S6 of the bottom channel layer 214b'.

[0198] In some embodiments, then proceed Figure 3A and Figure 3B The step involves forming a bottom spacer 360 on the inner spacer layer 270 of the fin structure 217. In some embodiments, this is then performed... Figures 2I-2M The steps are to form stress sources 290 and 310, dielectric layer 320, and gate stacks G1 and G2. In some embodiments, this step substantially forms semiconductor device structure 400.

[0199] Figure 5 These are cross-sectional views of the semiconductor device structure in some embodiments. For example... Figure 5 In some embodiments shown, the semiconductor device structure 500 and Figure 1H-1 Similar to the semiconductor device structure 100, the difference is that the inner spacer layer 150 of the semiconductor device structure 500 further covers the sidewall S3 of the bottom channel layer 114b2' of the multilayer stack 114S. Therefore, in some embodiments, the inner spacer layer 150 can electrically insulate the stress source 162 from the bottom channel layer 114b2'. In some embodiments, the "bottom 114a and other channel layers 114b2" are electrically insulated from the "bottom channel layer 114b2'".

[0200] In some embodiments, a semiconductor device structure and a method of forming the same are provided. The method of forming the semiconductor device structure may form a spacer layer between a fin structure and a stress source, thereby electrically insulating the fin structure from the stress source. Therefore, the spacer layer can prevent leakage current between the stress source and the fin structure.

[0201] In some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack on a substrate. The substrate has a base and a first fin structure and a second fin structure on the base, and the second fin structure is wider than the first fin structure. The first gate stack covers a first upper portion of the first fin structure, and the second gate stack covers a second upper portion of the second fin structure. The method includes partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack. The method includes forming an inner spacer layer on the first fin structure not covered by the first gate stack. The method includes forming a first stressor and a second stressor on the inner spacer layer and the second fin structure not covered by the second gate stack, respectively.

[0202] In some embodiments, the second stressor directly contacts the second fin structure.

[0203] In some embodiments, the first fin structure includes a first bottom, a first layer, and a second layer, the first layer is between the second layer and the first bottom, and the first layer and the second layer are composed of different materials; the second fin structure includes a second bottom, a third layer, and a fourth layer, the third layer is between the fourth layer and the second bottom, and the third layer and the fourth layer are composed of different materials; and the step of partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack includes removing the first layer and the second layer not covered by the first gate stack and the third layer and the fourth layer not covered by the second gate stack.

[0204] In some embodiments, the above method further includes partially removing the first layer and the third layer to form a first recess and a second recess in the first fin structure and the second fin structure, respectively, wherein the inner spacer layer is further formed in the first recess and the second recess.

[0205] In some embodiments, the step of forming the inner spacer layer includes, after partially removing the first layer and the third layer, depositing an inner spacer material layer on the first fin structure and the second fin structure and in the first recess and the second recess; and removing the inner spacer material layer on a first sidewall of the second layer, a second sidewall of the fourth layer, and the second bottom, wherein the remaining inner spacer material layer forms the inner spacer layer.

[0206] In some embodiments, the above method further includes forming a dielectric layer on the substrate, the first stressor, and the second stressor; removing the first gate stack, the second gate stack, the first layer, and the third layer to form a first trench and a second trench in the dielectric layer; and forming a third gate stack and a fourth gate stack in the first trench and the second trench, respectively.

[0207] In some embodiments, after the first gate stack, the second gate stack, the first layer, and the third layer are removed, the inner side spacer electrically insulates the first stressor from the first bottom.

[0208] In some embodiments, the method further comprises, before partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack, forming a spacer layer on the first gate stack, the second gate stack, the first fin structure, and the second fin structure, wherein after partially removing the first fin structure and the second fin structure, a first recess and a second recess are formed in the spacer layer and on the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack, respectively, the inner side spacer layer is formed in the first recess, and the first stressor and the second stressor are formed in the first recess and the second recess, respectively.

[0209] In some embodiments, the inner side spacer layer and the spacer layer surround a third recess, and the first stressor is partially located in the third recess.

[0210] In some embodiments, the inner side spacer layer and the spacer layer are composed of different materials.

[0211] In some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first gate stack on a substrate. The substrate has a base and a first fin structure on the base, the first fin structure including a first bottom and a first multi-layer stack on the first bottom; the first multi-layer stack including a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer stacked in sequence on the first bottom, and the first gate stack covering the first multi-layer stack. The method includes partially removing the first multi-layer stack not covered by the first gate stack. The method includes partially removing the first sacrificial layer and the second sacrificial layer to form a first recess and a second recess in the first multi-layer stack. The method includes forming a first inner side spacer layer in the first recess and the second recess, and forming a first bottom spacer on the first bottom, wherein the first bottom spacer covers a first sidewall of the first channel layer. The method includes forming a first stressor on the first bottom spacer. The first bottom spacer separates the first stressor from the first channel layer.

[0212] In some embodiments, the steps of forming the first inner side spacer layer and the first bottom spacer include: forming a spacer material layer on the first multi-layer stack and the first bottom, wherein the spacer material layer fills the first recess and the second recess; and removing the spacer material layer between a second sidewall of the second channel layer, wherein the spacer material layer remaining in the first recess and the second recess forms the first inner side spacer layer, and the spacer material layer remaining on the first bottom forms the first bottom spacer.

[0213] In some embodiments, the step of forming the first inner side spacer layer and the first bottom spacer includes: forming the first inner side spacer layer in the first recess and the second recess; and after forming the first inner side spacer layer in the first recess and the second recess, forming the first bottom spacer on the first bottom portion, wherein the first bottom spacer further covers the second sidewall of the first inner side spacer layer.

[0214] In some embodiments, the first inner side spacer layer covers the sidewall of the first channel layer and the upper surface of the first bottom portion, and the first bottom spacer is formed on the first inner side spacer layer covering the upper surface.

[0215] In some embodiments, the step of partially removing the first sacrificial layer and the second sacrificial layer further forms a third recess and a fourth recess in the first multi-layer stack, the first sacrificial layer is between the first recess and the third recess, the second sacrificial layer is between the second recess and the fourth recess, and the first inner side spacer layer is further formed in the third recess and the fourth recess. The above method further includes: when forming the first bottom spacer on the first bottom portion, forming a second bottom spacer on the first bottom portion, wherein the first channel layer is between the first bottom spacer and the second bottom spacer; when forming the first stressor on the first bottom spacer, forming a second stressor on the second bottom spacer; forming a dielectric layer on the substrate, the first stressor, and the second stressor; removing the first gate stack, the first sacrificial layer, and the second sacrificial layer to form a trench in the dielectric; and forming a second gate stack in the trench, wherein the first bottom spacer and the second bottom spacer electrically insulate the "first stressor and the second stressor" and the "first channel layer".

[0216] In some embodiments, the above method further includes: when forming the first gate stack on the substrate, forming a second gate stack on the substrate, wherein the substrate further has a second fin structure on the base, the second fin structure includes a second bottom portion and a second multi-layer stack on the second bottom portion, the second multi-layer stack includes a third sacrificial layer, a third channel layer, a fourth sacrificial layer, and a fourth channel layer stacked in sequence on the second bottom portion, and the second gate stack covers the second multi-layer stack; when partially removing the first layer stack not covered by the first gate stack, partially removing the second multi-layer stack not covered by the second gate stack; when partially removing the first sacrificial layer and the second sacrificial layer, partially removing the third sacrificial layer and the fourth sacrificial layer to form a third recess and a fourth recess in the second multi-layer stack, wherein the first inner side spacer layer is further formed in the third recess and the fourth recess, and the second bottom spacer is formed on the second bottom portion and covers a second sidewall of the third channel layer; removing the second bottom spacer to expose the second sidewall; and forming a second stressor on the second sidewall.

[0217] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure on the base. The fin structure includes a bottom and a multilayer stack on the bottom, the multilayer stack including a first channel layer and a second channel layer on the first channel layer, and the first channel layer and the second channel layer are separated. The semiconductor device structure includes a gate stack on the substrate. The gate stack encloses the multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer, and between the first channel layer and the bottom. The semiconductor device structure includes a bottom spacer on the bottom and covering a first sidewall of the first channel layer. The semiconductor device structure includes a stressor on the bottom spacer and connected to the second channel layer. The stressor is electrically insulated from the first channel layer.

[0218] In some embodiments, the bottom spacer covers a second sidewall of the inner spacer layer.

[0219] In some embodiments, the bottom spacer and the inner spacer layer are composed of the same material.

[0220] In some embodiments, the inner spacer layer covers a first sidewall of the first channel layer and an upper surface of the bottom, and the bottom spacer is on the inner spacer layer on the upper surface.

[0221] The features of the above-described embodiments are advantageous for those skilled in the art to understand the present application. Those skilled in the art should understand that other processes and structures can be designed and changed based on the present application to achieve the same purpose and / or the same advantages of the above-described embodiments. Those skilled in the art should also understand that these equivalent substitutions do not deviate from the spirit and scope of the present application, and can be changed, replaced, or varied without deviating from the spirit and scope of the present application.

Claims

1. A method for forming a semiconductor device structure, comprising: A first gate stack and a second gate stack are formed on a substrate, wherein the substrate has a base and a first fin structure and a second fin structure on the base, the second fin structure being wider than the first fin structure, the first gate stack covering a first upper portion of the first fin structure, and the second gate stack covering a second upper portion of the second fin structure. Partially remove the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack; An inner spacer layer is formed on the first fin structure not covered by the first gate stack; and A first stress source and a second stress source are respectively formed on the inner spacer layer and on the second fin structure not covered by the second gate stack, wherein the first stress source extends into the inner spacer layer.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the second stress source is in direct contact with the second fin structure.

3. The method for forming a semiconductor device structure as claimed in claim 1, wherein the first fin structure includes a first bottom, a first layer, and a second layer, the first layer being located between the second layer and the first bottom, and the first layer and the second layer being composed of different materials; The second fin-like structure includes a second bottom layer, a third layer, and a fourth layer, wherein the third layer is located between the fourth layer and the second bottom layer, and the third layer and the fourth layer are composed of different materials; and The step of partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack includes: Remove the first and second layers not covered by the first gate stack, and the third and fourth layers not covered by the second gate stack.

4. The method for forming a semiconductor device structure as described in claim 3, further comprising: The first layer and the third layer are partially removed to form a first recess and a second recess in the first fin structure and the second fin structure, respectively, wherein the inner spacer layer is further formed in the first recess and the second recess.

5. The method for forming a semiconductor device structure as claimed in claim 4, wherein the step of forming the inner spacer layer includes: After partially removing the first and third layers, an inner spacer material layer is deposited on the first and second fin structures and in the first and second recesses; and Remove the first sidewall of the second layer, the second sidewall of the fourth layer, and the inner spacer material layer on the second bottom, wherein the remaining inner spacer material layer forms the inner spacer layer.

6. The method for forming a semiconductor device structure as described in claim 4, further comprising: A dielectric layer is formed on the substrate, the first stress source, and the second stress source; Remove the first gate stack, the second gate stack, the first layer, and the third layer to form a first trench and a second trench in the dielectric layer; as well as A third gate stack and a fourth gate stack are respectively formed in the first trench and the second trench.

7. The method of forming a semiconductor device structure as claimed in claim 6, wherein after removing the first gate stack, the second gate stack, the first layer, and the third layer, the inner spacer layer electrically insulates the first stress source from the first bottom.

8. The method for forming a semiconductor device structure as described in claim 1, further comprising: Before partially removing the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack, a spacer layer is formed on the first gate stack, the second gate stack, the first fin structure, and the second fin structure. After partially removing the first fin structure and the second fin structure, a first recess and a second recess are formed in the spacer layer and on the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack, respectively. The inner spacer layer is formed in the first recess, and the first stress source and the second stress source are formed in the first recess and the second recess, respectively.

9. The method of forming a semiconductor device structure as claimed in claim 8, wherein the inner spacer layer and the spacer layer surround a third recess, and the first stress source is partially located in the third recess.

10. The method of forming a semiconductor device structure as claimed in claim 8, wherein the inner spacer layer and the spacer layer are composed of different materials.

11. A method for forming a semiconductor device structure, comprising: A gate stack is formed on a substrate, wherein the substrate has a base and a first fin structure and a second fin structure located on the base, and the gate stack covers a first upper portion of the first fin structure and a second upper portion of the second fin structure. Partially remove the first fin structure and the second fin structure that are not covered by the gate stack; An inner spacer layer is formed on the first fin structure not covered by the gate stack; and A first stress source and a second stress source are respectively formed on the second fin structure not covered by the inner spacer layer and the gate stack, wherein the first average width of the first stress source is smaller than the second average width of the second stress source, and wherein the first stress source extends into the inner spacer layer.

12. The method of forming a semiconductor device structure as claimed in claim 11, wherein the lower portion of the inner spacer layer is embedded in the first fin structure not covered by the gate stack.

13. The method for forming a semiconductor device structure as described in claim 11, further comprising: Before partially removing the first fin structure and the second fin structure not covered by the gate stack, a spacer layer is formed on the gate stack, the first fin structure, and the second fin structure. After partially removing the first fin structure and the second fin structure, a first recess and a second recess are formed in the spacer layer and respectively on the first fin structure and the second fin structure not covered by the gate stack. The first recess is narrower than the second recess. The inner spacer layer is formed in the first recess, and the first stress source and the second stress source are formed in the first recess and the second recess, respectively.

14. The method of forming a semiconductor device structure as claimed in claim 13, wherein a first portion of the inner spacer layer is formed on the spacer layer, and a second portion of the spacer layer is formed between the first stress source and the first portion of the inner spacer layer.

15. The method of forming a semiconductor device structure as described in claim 14, further comprising: A dielectric layer is formed on the first stress source, the second stress source, the spacer layer, and a first portion of the inner spacer layer, wherein the first portion of the inner spacer layer is located between the dielectric layer and the spacer layer.

16. The method of forming a semiconductor device structure as claimed in claim 11, wherein the first fin structure is narrower than the second fin structure.

17. A method for forming a semiconductor device structure, comprising: A first gate stack and a second gate stack are formed on a substrate, wherein the substrate has a base and a first fin structure and a second fin structure are located on the base, the first gate stack covers a first upper portion of the first fin structure, and the second gate stack covers a second upper portion of the second fin structure. Partially remove the first fin structure not covered by the first gate stack and the second fin structure not covered by the second gate stack; An inner spacer layer is formed on the first fin structure not covered by the first gate stack; and A first stress source and a second stress source are respectively formed on the second fin structure not covered by the inner spacer layer and the second gate stack, wherein the first bottom of the first stress source is narrower than the second bottom of the second stress source, and the first stress source extends into the inner spacer layer.

18. The method of forming a semiconductor device structure as claimed in claim 17, wherein the inner spacer layer electrically insulates the first stress source from the first fin structure.

19. The method of forming a semiconductor device structure as claimed in claim 17, wherein the first sidewall of the inner spacer layer and the second sidewall of the first bottom of the first stress source are substantially flush with each other.

20. A semiconductor device structure, comprising: A substrate having a base; A first multilayer stack is located on the substrate, wherein the first multilayer stack includes a first channel layer and a second channel layer located on the first channel layer, and the first channel layer and the second channel layer are separated. A gate stack is located on the substrate, wherein the gate stack covers the first multilayer stack; An inner spacer layer is located between the second channel layer and the first channel layer, and between the first channel layer and the substrate; A bottom spacer, located on the substrate; and A first source / drain structure is located on the bottom spacer and connected to the second channel layer, wherein the bottom spacer separates the first source / drain structure from the substrate, and the bottom spacer and the inner spacer layer are made of the same material, wherein the first source / drain structure extends into the bottom spacer.

21. The semiconductor device structure of claim 20, wherein the bottom spacer is connected to the inner spacer layer.

22. The semiconductor device structure of claim 20, further comprising: A second multilayer stack is located on the substrate, wherein the gate stack further covers the second multilayer stack, and the second multilayer stack is wider than the first multilayer stack.

23. The semiconductor device structure of claim 22, further comprising: A second source / drain structure is connected to the second multilayer stack, wherein the second source / drain structure is wider than the first source / drain structure.

24. The semiconductor device structure of claim 23, wherein the substrate has a first fin structure and a second fin structure on the substrate, the first fin structure includes a first bottom, the first multilayer stack is located on the first bottom, the second fin structure includes a second bottom, the second multilayer stack is located on the second bottom, the bottom spacer separates the first source / drain structure from the first bottom, and the second source / drain structure is located on the second bottom.

25. The semiconductor device structure of claim 24, wherein the second source / drain structure is in direct contact with the second bottom.

26. The semiconductor device structure of claim 24, wherein the bottom spacer extends into the first bottom.

27. The semiconductor device structure of claim 20, wherein the first upper surface of the bottom spacer is higher than the second upper surface of the first channel layer.

28. A semiconductor device structure, comprising: A substrate having a base; A multilayer stack is located on the substrate, wherein the multilayer stack includes a first channel layer and a second channel layer located on the first channel layer, and the first channel layer and the second channel layer are separated. A gate stack is located on the substrate, wherein the gate stack covers the multilayer stack; An inner spacer layer is located between the second channel layer and the first channel layer, and between the first channel layer and the substrate; A bottom spacer is located on the substrate and covers the first sidewall of the first channel layer; as well as A source / drain structure is located on the bottom spacer and connected to the second channel layer, wherein the source / drain structure is electrically insulated from the first channel layer, and wherein the source / drain structure extends partially into the bottom spacer.

29. The semiconductor device structure of claim 28, wherein the bottom spacer covers the second sidewall of the inner spacer layer.

30. The semiconductor device structure of claim 28, wherein the bottom spacer and the inner spacer layer together form a continuous structure.

31. The semiconductor device structure of claim 28, wherein the inner spacer layer continuously covers the first sidewall of the first channel layer, the second sidewall of the gate stack, and the upper surface of the substrate.

32. The semiconductor device structure of claim 31, wherein the bottom spacer is embedded in the inner spacer layer.

33. A method for forming a semiconductor device structure, comprising: A multilayer structure is formed on a substrate having a base. A gate stack is formed on the substrate, wherein the gate stack covers the multilayer structure; Partially remove the multilayer structure not covered by the gate stack, wherein the multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a first sacrificial layer and a first channel layer located on the first sacrificial layer; The first sacrificial layer is partially removed to form a first recess in the multilayer stack; An inner spacer layer is formed in the first recess, and a bottom spacer is formed on the first sidewall of the first channel layer; and A source / drain structure is formed on the bottom spacer, wherein the bottom spacer separates the source / drain structure from the first channel layer, and wherein the source / drain structure extends into the bottom spacer.

34. The method for forming a semiconductor device structure as described in claim 33, wherein the multilayer stack further comprises a second sacrificial layer and a second channel layer sequentially stacked on the first channel layer. The step of partially removing the first sacrificial layer further includes partially removing the second sacrificial layer to form a second recess in the multilayer stack, and The inner spacer layer is further formed in the second recess.

35. The method for forming a semiconductor device structure as claimed in claim 34, wherein the step of forming the inner spacer layer and the bottom spacer includes: A spacer material layer is formed on the multilayer stack and the substrate, wherein the first recess and the second recess are filled with the spacer material layer; as well as Remove the spacer material layer covering the second sidewall of the second channel layer, wherein the spacer material layer retained in the first recess and the second recess forms the inner spacer layer, and the spacer material layer retained on the first sidewall of the first channel layer forms the bottom spacer.

36. The method of forming a semiconductor device structure as claimed in claim 35, wherein the source / drain structure directly contacts the second sidewall of the second channel layer.

37. The method of forming a semiconductor device structure as claimed in claim 35, wherein the bottom spacer has a recessed upper surface.

38. The method of forming a semiconductor device structure as claimed in claim 34, wherein the step of forming the inner spacer layer and the bottom spacer includes: The inner spacer layer is formed in the first recess and the second recess; as well as After the inner spacer layer is formed in the first recess and the second recess, the bottom spacer is formed on the first sidewall of the first channel layer, wherein the bottom spacer further covers the second sidewall of the inner spacer layer.

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