Semiconductor structure

Abstract

A semiconductor structure includes a fin protruding from a semiconductor substrate, a first metal gate stack and a second metal gate stack disposed on the fin, and a dielectric feature defining sidewalls of each of the first metal gate stack and the second metal gate stack. Further, the dielectric feature includes a bilayer structure, wherein the sidewalls of a first layer are defined by a second layer, and wherein the first layer is compositionally different from the second layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and particularly to a field-effect transistor device and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned several generations of ICs, each generation featuring smaller and more complex circuits than the previous one. In general, IC development has seen an increase in functional density (i.e., the number of interconnects per chip area) and a decrease in geometry (i.e., the smallest component (or line) that can be created using manufacturing processes). This miniaturization typically benefits production efficiency and reduces associated costs. However, this miniaturization also increases the complexity of the processes and manufacturing of ICs.

[0003] This miniaturization also increases the complexity of IC manufacturing processes, and similar advancements are needed in IC processes and manufacturing to achieve these progresses. For example, various methods have been developed to cut (or separate) metal gate stacks to form advanced ICs. While they are generally sufficient to isolate the metal gate stacks, they are not satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor structure including: a fin protruding from a semiconductor substrate; a first metal gate stack and a second metal gate stack disposed on the fin; and a dielectric component disposed on the semiconductor substrate, wherein the dielectric component defines the sidewalls of the first metal gate stack and the second metal gate stack, wherein the dielectric component includes a first layer disposed on a second layer, wherein the sidewalls of the first layer are defined by the second layer, and wherein the first layer is composed differently from the second layer.

[0005] Other embodiments of the present invention provide a semiconductor structure comprising: a semiconductor layer disposed on a substrate and oriented in a first direction; a metal gate stack disposed on the semiconductor layer and oriented in a second direction perpendicular to the first direction; a source / drain component disposed in the semiconductor layer and adjacent to the metal gate stack; and a dielectric component extending into the semiconductor layer, wherein the source / drain component is disposed between the metal gate stack and the dielectric component, wherein the dielectric component includes a first layer encapsulated by a second layer, and wherein the dielectric constant of the first layer is different from the dielectric constant of the second layer.

[0006] Some embodiments of the present invention provide a method for constructing a semiconductor structure, comprising: forming a high-dielectric-constant metal gate stack on a semiconductor layer; forming a trench to separate the high-dielectric-constant metal gate stack into two portions; forming a first dielectric layer in the trench; forming a second dielectric layer on the first dielectric layer to fill the trench, wherein the second dielectric layer is different from the first dielectric layer; removing a portion of the second dielectric layer to form a notch; forming a third dielectric layer in the notch, wherein the third dielectric layer is different from the second dielectric layer; and planarizing the third dielectric layer to form a gate isolation component. Attached Figure Description

[0007] The present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly demonstrate the features of the present disclosure.

[0008] Figure 1A , Figure 1B , Figure 1C and Figure 1D According to certain aspects of this disclosure, flowcharts of methods for forming a semiconductor structure or a portion thereof are shown respectively.

[0009] Figure 2A According to some aspects of this disclosure, implementation is shown Figure 1A , Figure 1B , Figure 1C and / or Figure 1D A three-dimensional perspective view of the semiconductor structure in an embodiment of the method.

[0010] Figure 2B According to some aspects of this disclosure, it is shown Figure 2A A plan view of the semiconductor structure.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 4A , Figure 4B and Figure 4C According to some aspects of this disclosure, it is shown that in implementation Figure 1A , Figure 1B , Figure 1C and / or Figure 1D During intermediate steps in the method embodiments, along Figure 2A and / or Figure 2B A cross-sectional view of the semiconductor structure taken along line A-A'.

[0012] Figure 3H According to some aspects of this disclosure, for Figure 2A , Figure 2B and / or Figure 3F A plan view of a semiconductor structure, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0013] Figure 3I According to some aspects of this disclosure, in order to follow Figure 2A , Figure 2B , Figure 3F and / or Figure 3G A cross-sectional view of the semiconductor structure taken along line C-C', showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0014] Figure 4D According to some aspects of this disclosure, for Figure 2A , Figure 2B and / or Figure 4C A plan view of a semiconductor structure, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0015] Figure 4E According to some aspects of this disclosure, in order to follow Figure 2A , Figure 2B and / or Figure 4C A cross-sectional view of the semiconductor structure taken along line C-C', showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0016] Figure 5 According to some aspects of this disclosure, the effects of various components on reducing the effective capacitance of a semiconductor structure are illustrated, wherein the semiconductor structure is implemented. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0017] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I , Figure 6J , Figure 6K, Figure 7A and Figure 7B According to some aspects of this disclosure, it is shown that in implementation Figure 1A , Figure 1B , Figure 1C and / or Figure 1D During intermediate steps in the method embodiments, along Figure 2A and / or Figure 2B A cross-sectional view of the semiconductor structure taken from line B-B'.

[0018] Figure 6L According to some aspects of this disclosure, for Figure 2A , Figure 2B and / or Figure 6I A plan view of a semiconductor structure, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0019] Figure 6M According to some aspects of this disclosure, in order to follow Figure 2A , Figure 2B , Figure 6I and / or Figure 6K A cross-sectional view of the semiconductor structure taken along line C-C', showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0020] Figure 7C According to some aspects of this disclosure, for Figure 2A , Figure 2B and / or Figure 7B A plan view of a semiconductor structure, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0021] Figure 7D According to some aspects of this disclosure, in order to follow Figure 2A , Figure 2B and / or Figure 7B A cross-sectional view of the semiconductor structure taken along line C-C', showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0022] Figure 8A According to some aspects of this disclosure, for Figure 2A , Figure 2B , Figure 3F and / or Figure 6I A plan view of a semiconductor structure, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0023] Figure 8B According to some aspects of this disclosure, in order to follow Figure 2A , Figure 2B , Figure 3F , Figure 3G , Figure 6I and / or Figure 6K A cross-sectional view of the semiconductor structure taken along the C-C' line, showing the implementation of the semiconductor structure. Figure 1A , Figure 1B , Figure 1C and / or Figure 1D Method implementation examples.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 100: Method

[0026] 102: Operation

[0027] 104: Operation

[0028] 106: Operation

[0029] 108: Operation

[0030] 120: Operation

[0031] 122: Operation

[0032] 124: Operation

[0033] 126: Operation

[0034] 128: Operation

[0035] 140: Operation

[0036] 142: Operation

[0037] 144: Operation

[0038] 160: Method

[0039] 162: Operation

[0040] 164: Operation

[0041] 166: Operation

[0042] 168: Operation

[0043] 200: Device

[0044] 202: Substrate

[0045] 204: Semiconductor layer / fin

[0046] 206: Dummy Gate Stack

[0047] 207: Gate Trench

[0048] 208: Isolation Structure

[0049] 210: High Dielectric Constant Metal Gate (HKMG)

[0050] 212: Gate spacer

[0051] 213: Trench

[0052] 214: Source / Drain Components

[0053] 218: Interlayer Dielectric (ILD) Layer

[0054] 220: Dielectric layer

[0055] 222: Dielectric layer

[0056] 224: Notch

[0057] 226: Dielectric layer

[0058] 228: Air gap

[0059] 230: Dielectric components

[0060] 234: Trench

[0061] 240: Dielectric component

[0062] 210A: High Dielectric Constant Metal Gate (HKMG)

[0063] 210B: High Dielectric Constant Metal Gate (HKMG)

[0064] 212a: Gate spacer

[0065] 212b: Gate spacer

[0066] D1: Altitude

[0067] D2: Altitude

[0068] D3: height

[0069] S1: Thickness

[0070] S2: Thickness

[0071] X: Direction

[0072] Y: direction

[0073] Z: Direction

[0074] A-A': Cutoff line

[0075] B-B': Cutoff line

[0076] C-C': Cutoff line Detailed Implementation

[0077] The following provides numerous different embodiments or examples to implement different components of the embodiments of this disclosure. Specific examples of components and configurations are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, the following description, referring to the formation of a first component on or above a second component, may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of the embodiments of this disclosure. This repetition is for simplification and clarity and is not in itself intended to specify relationships between the various embodiments and / or configurations discussed.

[0078] Furthermore, reference numerals and / or letters may be repeated in various examples of the embodiments disclosed herein. This repetition is for simplification and clarity purposes and is not in itself intended to specify the relationship between the various embodiments and / or configurations discussed. Additionally, in the embodiments of this disclosure, forming a component on, connecting to, and / or coupling to another component may include embodiments where the components are in direct contact, and may also include embodiments where additional components are formed between these components such that these components are not in direct contact. Furthermore, to facilitate the description of the relationship between one component and another illustrated in the accompanying drawings of the embodiments of this disclosure, spatially related terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc., and derived spatially related terms (e.g., “horizontally,” “downward,” “upward,” etc.) are intended to cover different orientations of the device containing these components. Furthermore, when terms such as “about” or “approximately” are used to describe numbers or ranges of numbers, the intended scope of such terms is a value that includes the described number within a reasonable range, such as within + / - 10% of the described number, or other values ​​understood by one of ordinary skill in the art to which this disclosure pertains. For example, the term “about 5nm” covers a size range from 4.5nm to 5.5nm.

[0079] This disclosure relates to semiconductor devices and manufacturing methods, and more particularly to manufacturing gate isolation components in semiconductor devices.

[0080] As component sizes continue to shrink, replacing polysilicon gates with high-k metal gate (HKMG) structures has led to improved device performance. Generally, after forming the HKMG structure in a three-dimensional field-effect transistor (e.g., fin-like field-effect transistor, FinFET, gate-all-around FET, GAA FET), various methods can be used individually or in combination to further process the HKMG structure according to specific design requirements. In one example, the HKMG structure can be cut into two or more sections and subsequently separated by gate isolation components in a process known as cut-metal-gate (CMG). The gate isolation components are oriented longitudinally perpendicular to the HKMG structure. In another example, a dielectric gate known as continuous poly on diffusion edge (CPODE) can be implemented to reduce the gate spacing between adjacent HKMG structures, thus its lengthwise configuration is generally parallel to the HKMG structure. While these methods are generally sufficient, they are not entirely satisfactory in all aspects. For example, using a high dielectric constant dielectric material with a dielectric constant greater than that of silicon oxide (approximately 3.9) in a gate isolation component (also known as a gate cleavage component) typically increases the effective capacitance (C) of the gate isolation component. eff This increases the parasitic capacitance between the HKMG structures separated by the isolation components. In many cases, the increase in parasitic capacitance can lead to degraded device performance because it typically increases the device's RC delay. Additionally, high dielectric constant dielectric materials applied to CPODEs can also result in high parasitic capacitance for similar reasons. Unless otherwise stated below, the capacitance or C of different structures... eff Comparisons between these structures are typically equivalent to comparing the dielectric constants of the materials contained within them, assuming that other factors influence the capacitance value (e.g., the area of ​​conductive components and the spacing between them). Therefore, there is a need to improve the treatment of HKMG structures to achieve reduced parasitic capacitance.

[0081] Figure 1A , Figure 1B and Figure 1CAccording to some embodiments of this disclosure, a process flow for a method 100 for forming apparatus 200 is illustrated together. Method 100 is merely an example and is not intended to limit the scope of this disclosure or the claims. Additional operations may be performed before, during, and after method 100, and some described operations may be replaced, removed, or moved for additional embodiments of the method. The following is in conjunction with... Figures 2A-4E Description method 100, wherein, Figures 2A-3G and Figures 4A-4C Show along Figure 2A and Figure 2B The line A-A' shown intercepts multiple cross-sectional views of the apparatus 200 during an intermediate step of method 100; Figure 3H and Figure 4D A plan view of the device 200 is shown. Figure 3I and Figure 4E Show along Figure 2A The cross-sectional view of device 200 taken by line C-C' is shown.

[0082] Device 200 may be an intermediate device manufactured during the IC process, or a portion thereof, and may include static random-access memory (SRAM) and / or other logic circuitry, passive components (such as resistors, capacitors, and inductors), and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, gate-all-around (GAA) FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. This disclosure is not limited to any particular number of devices or device regions, or any particular device configuration. For example, although the illustrated device 200 is a three-dimensional FinFET device, this disclosure may also provide embodiments for manufacturing planar FET devices or GAA devices. Additional components may be added to device 200, and some of the components described below may be replaced, modified, or removed in other embodiments of device 200.

[0083] In operation 102, refer to Figure 1A , Figure 2A , Figure 2B and Figure 3AMethod 100 provides an apparatus 200, which includes: a substrate 202 having at least one semiconductor layer 204 (e.g., an active region, such as a three-dimensional fin; hereinafter referred to as fin 204) disposed thereon; an isolation structure 208 disposed above the substrate 202, the isolation structure 208 separating a plurality of components of the apparatus 200; a high-k metal gate (HKMG) structure 210 disposed above the fin 204; a gate spacer 212 disposed above the sidewalls of the HKMG structure 210; a source / drain member 214 disposed above the fin 204 and inserted into the HKMG structure 210; and an interlayer dielectric (ILD) layer 218 disposed above the source / drain member 214. As described in this disclosure, the apparatus 200 may include a plurality of fins 204 longitudinally oriented in the X direction and a plurality of HKMG structures 210 longitudinally oriented in the Y direction, i.e., substantially perpendicular to the fins 204. The device 200 may further include many other components, such as a hard mask layer, an etch stop layer, a barrier layer, other suitable layers, or combinations thereof. For simplicity, a cross-sectional view of the device 200 taken along the length of the HKMG structure 210 (i.e., the dashed line A-A' in the Y direction) will be referenced below. Figures 3A-4C Describe the intermediate steps of method 100.

[0084] Substrate 202 may include elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 may be a single-layer material with a uniform composition. Alternatively, substrate 202 may include multiple material layers with similar or different compositions suitable for IC device fabrication. In one example, substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, substrate 202 may include conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof.

[0085] The fins 204 can be manufactured using suitable processes, including photolithography and etching. The photolithography process may include: forming a photoresist layer over the substrate 202; exposing the photoresist to a pattern; performing a post-exposure baking process; and developing the photoresist to form a mask element (not shown) including the photoresist. The mask element is then used to etch notches into the substrate 202, leaving the fins 204 on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0086] Several other suitable methods exist for forming the fin 204. For example, a dual-patterning or multi-patterning process can be used to pattern the fin 204. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin.

[0087] The isolation structure 208 may include silicon oxide, silicon nitride, silicon oxynitride, a low-dielectric-constant dielectric material, and / or other suitable materials. The isolation structure 208 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 208 is formed during the formation of the fin 204 by etching trenches in the substrate 202. The trenches can then be filled with the aforementioned isolation material by a subsequent chemical mechanical planarization (CMP) process using a deposition process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 208. Alternatively, the isolation structure 208 may include a multilayer structure, for example, having one or more thermal oxide liner layers. The isolation structure 208 can be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.

[0088] Continue to refer to Figure 2A and Figure 2BDevice 200 includes source / drain components 214 disposed within or above fins 204 and adjacent to each HKMG structure 210. The source / drain components 214 can be formed using any suitable technique, such as an etching process followed by one or more epitaxial processes. In one example, one or more etching processes are performed to remove a portion of fin 204 to form a notch (not shown). A cleaning process can be performed using a hydrofluoric acid (HF) solution and / or other suitable solutions to clean the notch. Subsequently, one or more epitaxial growth processes are performed to grow an epitaxial component in the notch. Each source / drain component 214 may be adapted to form a p-type FinFET device (e.g., including p-type epitaxial material) or, alternatively, an n-type FinFET device (e.g., including n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon-germanium (e.g., epi SiGe) doped with p-type dopants, such as boron, germanium, indium, and / or other p-type dopants. n-type epitaxial materials may include one or more epitaxial layers of silicon (e.g., epi Si) or epitaxial layers of silicon carbon (e.g., epi SiC), wherein the silicon or silicon carbon is doped with n-type dopants, such as arsenic, phosphorus, and / or other n-type dopants.

[0089] The device 200 may further include a plurality of HKMG structures 210 disposed above the fin 204. Each HKMG structure 210 may include a high-dielectric-constant dielectric layer (not shown) disposed above the fin 204 and a metal gate (not shown) disposed above the high-dielectric-constant dielectric layer. The metal gate may further include at least one work function metal layer and a bulk conductive layer disposed thereon. The work function metal layer may be a p-type or n-type work function metal layer. Example work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The bulk conductive layer may include Cu, W, Al, Co, Ru, other suitable materials, or combinations thereof. The HKMG structure 210 may further include other layers (not shown), such as an interface layer, capping layer, barrier layer, other suitable layers, or combinations thereof disposed between the fin 204 and the high dielectric constant layer. The multiple layers of the HKMG structure 210 may be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), electroplating, other suitable methods, or combinations thereof.

[0090] The device 200 may further include a gate spacer 212 disposed above the sidewall of the HKMG structure 210. In some embodiments, the gate spacer 212 includes one or more of the following elements: silicon, oxygen, nitrogen, and carbon. For example, the gate spacer 212 may include a dielectric material such as silicon oxide, carbon-doped silicon oxide, silicon nitride, carbon and / or oxygen-doped silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, other suitable dielectric materials, or combinations thereof. The gate spacer 212 can be formed on the sidewall of the HKMG structure 210 by first depositing a blanket layer of spacer material on the device 200, followed by performing an anisotropic etching process to remove a portion of the spacer material.

[0091] In some embodiments, the HKMG structure 210 is formed after other components of the fabrication device 200 (e.g., source / drain components 214). The process, typically referred to as a gate replacement process, includes: first forming a dummy gate structure (not shown) as a placeholder for the HKMG structure 210; forming the source / drain components 214; forming an ILD layer 218 over the source / drain components 214; planarizing the ILD layer 218 to expose the top surface of the dummy gate structure; removing the dummy gate structure to form a trench exposing the channel region of the fin 204; and forming the HKMG structure 210 in the trench to complete the gate replacement process. Subsequently, a polishing process, such as a CMP process, may be performed to remove excess material from the top surface of the HKMG structure 210, planarizing the top surface of the device 200. In some embodiments, the ILD layer 218 includes a dielectric material, such as silicon oxide, a low dielectric constant dielectric material, tetraethyl orthosilicate (TES), doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), other suitable dielectric materials, or combinations thereof. The ILD layer 218 may include a multilayer or monolayer structure and may be formed by deposition processes such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. The device 200 may further include an etch stop layer (not shown) disposed between the HKMG structure 210 and the ILD layer 218, and may include silicon nitride, silicon oxynitride, silicon nitride having oxygen and / or carbon, aluminum oxide, aluminum nitride, other suitable materials, or combinations thereof. Etching stop layers can be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof.

[0092] In some embodiments, as discussed in detail below, method 100 performs a cut-metal-gate (CMG) process, during which a dummy gate structure is first replaced with an HKMG structure (e.g., HKMG structure 210), and then the HKMG structure is cleaved using gate isolation components (e.g., dielectric components 230). In an alternative embodiment (not shown), method 100 performs a cut-poly-gate (CPG) process, during which the dummy gate structure is cleaved into two parts using the same (or substantially similar) gate isolation components, and then the resulting dummy gate structure is replaced with two HKMG structures. Notably, method 100 performs the same (or substantially similar) operations to form gate isolation components for both CMG and CPG processes.

[0093] Now for reference Figure 3B In operation 104, method 100 forms a trench 213 in the HKMG structure 210. In this embodiment, the trench 213 extends toward the substrate 202 to divide the HKMG structure 210 into two parts. In the depicted embodiment, the trench 213 extends below the top surface of the substrate 202. In some embodiments, the trench 213 extends above the top surface of the substrate 202 but below the bottom surface of the HKMG structure 210. Method 100 forms the trench 213 by performing a series of patterning and etching processes. For example, a masking element (not shown) may be formed over the HKMG structure 210 and then patterned to expose a portion of the HKMG structure 210. Subsequently, method 100 performs any suitable etching method (e.g., wet etching, dry etching, RIE, and / or other suitable etching methods) to use the patterned masking element as an etching mask to remove the exposed portion of the HKMG structure 210. In this embodiment, method 100 employs an etchant to perform a dry etching process. The etchant includes chlorine-containing gases (e.g., Cl2, SiCl4, and / or BCl3), bromine-containing gases (e.g., HBr), fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, NF3, and / or C2F6), nitrogen-containing gases (e.g., N2), oxygen-containing gases (e.g., O2), other suitable gases, or combinations thereof. Subsequently, the patterned masking elements are removed from the apparatus 200 by any suitable method, such as wet etching or resist stripping.

[0094] Subsequently, in operation 106, method 100 forms a multilayer dielectric component 230 (hereinafter referred to as "dielectric component 230"); see Figure 3G and Figure 4C In this embodiment, method 100 is performed on one of two paths, A and B, to form dielectric component 230. Referring to path A, referring to... Figure 1B and Figures 3B-3GThe process flow described herein, method 100, forms a dielectric component 230, wherein the dielectric component 230 includes a dielectric layer (e.g., dielectric layer 222) embedded within one or two different dielectric layers (e.g., dielectric layers 220 and / or 226). Regarding path B, see reference [link to reference]. Figure 1C and Figures 4A-4C The process flow depicted in method 100 forms a dielectric component 230, which includes an air gap (e.g., air gap 228) embedded in a dielectric layer (e.g., dielectric layer 220). Details of paths A and B will be discussed below with reference to their respective process flows. Subsequently, in operation 108, method 100 performs additional process steps on device 200. For example, additional vertical interconnect components, such as contacts and / or vias, and / or horizontal interconnect components, such as wires, and multilayer interconnect components, such as metal layers and interlayer dielectric layers, may be formed above device 200.

[0095] Regarding path A, please refer to... Figure 1B and Figure 3B In method 100, during operation 120, a dielectric layer 220 is formed in trench 213. As described in this disclosure, a portion of the dielectric layer 220 may be formed on the top surface of the HKMG structure 210. In this embodiment, the dielectric layer 220 comprises a high-dielectric-constant dielectric material with a dielectric constant greater than that of silicon oxide. In some examples, the dielectric layer 220 may comprise a nitrogen-containing dielectric material (e.g., silicon nitride or carbon and / or oxygen-doped silicon nitride), an oxygen-containing dielectric material (e.g., hafnium oxide, zirconium oxide, titanium oxide, etc.), other high-dielectric-constant dielectric materials, or combinations thereof. In some embodiments, the dielectric layer 220 serves as a barrier layer to prevent oxygen atoms from diffusing into the HKMG structure 210. In some embodiments, the dielectric layer 220 is free of silicon oxide and is a low-dielectric-constant dielectric material (i.e., with a dielectric constant less than that of silicon oxide, approximately 3.9), such as air, porous silicon oxide, doped silicon oxide (e.g., carbon-doped silicon oxide (SiOC), BPSG, FSG, PSG, BSG, etc.), other low-dielectric-constant dielectric materials, or combinations thereof. The dielectric layer 220 can be deposited by any suitable method, including ALD, CVD, other suitable methods, or combinations thereof. In this embodiment, the dielectric layer 220 is deposited using an ALD process.

[0096] Now for reference Figure 3CIn method 100, in operation 122, a dielectric layer 222 is formed over dielectric layer 220 to fill trench 213. It should be noted that the composition of dielectric layer 222 differs significantly from that of dielectric layer 220 in that the dielectric constant of dielectric layer 222 is lower than that of dielectric layer 220. In this disclosure, the dielectric constant of a given dielectric layer refers to the composite dielectric constant based on the composition of the dielectric layer. For example, if dielectric layer 220 includes more than one dielectric material, the dielectric constant of dielectric layer 220 reflects the average dielectric constant of the materials included in dielectric layer 220. In some embodiments, the composite dielectric constant can be calculated based on the properties and relative quantities of the different materials included in dielectric layer 220. In some embodiments, the compositional difference between dielectric layer 220 and dielectric layer 222 ensures that a selective etching process can be performed to remove one layer without removing or substantially removing the other layer.

[0097] In this embodiment, dielectric layer 222 includes silicon oxide, a low-dielectric-constant dielectric material, or a combination thereof. The low-dielectric-constant dielectric material may include porous silicon oxide, doped silicon oxide (e.g., SiOC, BPSG, FSG, PSG, BSG, etc.), other low-dielectric-constant dielectric materials, or combinations thereof. In some embodiments, the porosity of dielectric layer 222 is greater than that of dielectric layer 220. In other words, the density of dielectric layer 222 is less than the density of dielectric layer 220.

[0098] The dielectric layer 222 can be formed by any suitable method, including CVD, FCVD, ALD, or combinations thereof. In embodiments implementing FCVD, the dielectric layer 222 can subsequently be cured and, optionally afterwards, annealed. In some embodiments, depending on the composition of the dielectric layer 222, ultraviolet light of any suitable wavelength can be used to perform the curing process. In some embodiments, the annealing process can be performed at any suitable temperature, as long as it does not thermally degrade other components of the device 200 (e.g., source / drain components 214, HKMG structure 210, etc.).

[0099] Reference Figure 3DIn method 100, in operation 124, a portion of dielectric layer 222 is subsequently removed to form notch 224. In this embodiment, dielectric layer 222 is selectively etched relative to dielectric layer 220, so that dielectric layer 220 is not etched or is only minimally etched in operation 124. Dielectric layer 222 can be selectively etched using any suitable etching process, such as dry etching, wet etching, RIE, or combinations thereof. In this embodiment, dielectric layer 222 is etched using a dry etching process, utilizing etchants including fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, NF3, and / or C2F6), nitrogen-containing gases (e.g., N2), hydrogen-containing gases (e.g., H2), oxygen-containing gases (e.g., O2, CO2, COS), other suitable gases, or combinations thereof. As described above, the composition of dielectric layer 220 and dielectric layer 222 is selected to ensure etch selectivity between the two layers when the etching process is applied in operation 124.

[0100] Subsequently, reference Figure 3E In method 100, in operation 126, a dielectric layer 226 is formed over dielectric layer 222 to fill recess 224. In the depicted embodiment, the bottom of dielectric layer 226 disposed in recess 224 is defined by dielectric layers 220 and 222, while the top of dielectric layer 222 is disposed on the top surface of HKMG structure 210. In this embodiment, dielectric layer 226 has a higher dielectric constant than dielectric layer 222. In some embodiments, the composition of dielectric layer 226 is the same as (or substantially similar to) dielectric layer 220. Dielectric layer 226 may include a nitrogen-containing dielectric material (e.g., silicon nitride), an oxygen-containing dielectric material (e.g., hafnium oxide, zirconium oxide, or titanium oxide), other dielectric materials, or combinations thereof. In some embodiments, the density of dielectric layer 226 is greater than the density of dielectric layer 222. In this embodiment, compared to dielectric layer 226, since dielectric layer 222 has a porous structure, dielectric layer 226 is configured to protect dielectric layer 222 from being unintentionally etched during subsequent process steps.

[0101] Dielectric layer 226 can be formed by any suitable method, including CVD, FCVD, ALD, or combinations thereof. In some embodiments, dielectric layer 226 is formed using a process similar to that discussed above with respect to dielectric layer 222. Then, refer to... Figure 3FIn operation 128, method 100 removes the top of the dielectric layer 226 formed on the top surface of the HKMG structure 210, thereby planarizing the top surface of the device 200. As provided in this disclosure, the resulting dielectric component 30 may be a gate isolation component configured to divide the HKMG structure 210 into two portions 210A and 210B. In other words, forming the dielectric component 230 results in the formation of HKMG structures 210A and 210B, each having a sidewall defined by the dielectric component 230.

[0102] Continue to refer to Figure 3F The ratio of the thickness S2 of dielectric layer 222 to the thickness S1 of dielectric layer 220 can be greater than 0 and less than about 30, and the ratio of the height D3 of dielectric layer 222 to the height D1 of dielectric component 230 can be greater than about 0.3 and less than about 0.8. On the one hand, if the ratio of S2 / S1 is greater than about 30, or if the ratio of D3 / D1 is greater than about 0.8, then dielectric layer 220 is not thick enough to protect HKMG structure 210 from diffusion of impurity atoms (e.g., oxygen atoms) from dielectric layer 222. On the other hand, if the ratio of D3 / D1 is less than about 0.3, it may not have the effect of reducing effective capacitance and thus improving device performance. In some examples, S1 can be greater than 0 nm and less than about 3 nm, S2 can be about 15 nm to about 25 nm, D1 can be about 50 nm to about 200 nm, and D3 can be about 35 nm to about 145 nm. The height D2 of dielectric layer 226 (i.e., the difference between D1 and D3) can be as small as about 2 nm. It should be noted that if D2 is less than about 2 nm, dielectric layer 226 may not provide sufficient protection for dielectric layer 222 against subsequent process steps (e.g., etching processes). Of course, these are merely example dimensions and do not limit the embodiments provided in this disclosure.

[0103] In some embodiments, reference Figure 3G The dielectric layer 226 has the same composition as the dielectric layer 220, such that the dielectric layer 222 is completely embedded within the dielectric layer 220. Therefore, if the dielectric layer 226 and the dielectric layer 220 have the same composition, the multilayer dielectric component 230 can be a two-layer structure; alternatively, if the dielectric layer 226 has a different composition than the dielectric layer 220, the dielectric component 230 can be a three-layer structure. To better illustrate this embodiment, Figure 3H and Figure 3I Depicting along Figure 2A The plan view of device 200 intercepted by line C-C' shown ( Figure 3H ) and cross-sectional view ( Figure 3I It should be noted that, for example... Figure 3F The three-layer structure shown, the plan view of device 200, shows dielectric component 230, which includes... Figure 3H The dielectric layer 226 in the middle, and Figure 3I The cross-sectional view shows dielectric component 230, which includes dielectric layer 222 embedded in dielectric layer 220. For example, Figure 3G The two-layer structure shown, in a plan view (not depicted), shows dielectric component 230, which comprises only dielectric layer 220, while a cross-sectional view along line C-C' (not depicted) will depict a structure similar to... Figure 3I The structure described in the text.

[0104] In some embodiments, reference Figure 1C and Figures 4A-4E In path B, method 100 forms a dielectric component 230, including an air gap 228 embedded in a dielectric layer 220, the dielectric constant of which is approximately 1. (See reference) Figure 4A In method 100, in operation 140, a dielectric layer 220 is conformally formed in trench 213 during a first deposition process. The first deposition process in operation 140 can be any suitable process, including ALD, CVD, FCVD, other suitable processes, or combinations thereof. Subsequently, refer to... Figure 4B In method 100, a second deposition process is performed in operation 142, during which the same dielectric material (i.e., the composition of dielectric layer 220) deposited in the first deposition process is deposited, but at a different deposition rate. In this embodiment, the rate at which the second deposition process is performed is higher than the rate at which the first deposition process is performed.

[0105] It should be noted that due to the high aspect ratio (at least about 1:10) of trench 213, a higher deposition rate allows the dielectric material to accumulate rapidly and bridge the openings of trench 213, thereby preventing additional material deposition in trench 213 and forming air gaps 228 in dielectric layer 220. In operation 142, the second deposition process can be any suitable process, including ALD, CVD, FCVD, other suitable processes, or combinations thereof. In some embodiments, the first deposition process in operation 140 is substantially the same as the second deposition process in operation 142, but implemented at different deposition rates as provided in this disclosure. In some embodiments, the first deposition process is an ALD process and the second deposition process is a CVD process. Reference then to... Figure 4C In operation 144, method 100 performs a planarization process (e.g., CMP process) on device 200, similar to that discussed above with respect to operation 128. Therefore, refer to Figure 4D and Figure 4E Figure 200, plan view (top view) Figure 4D The diagram shows dielectric component 23, which includes a dielectric layer 220, and along... Figure 2A A cross-sectional view of the device 200 with the C-C' line cut off ( Figure 4EThe diagram shows a dielectric component 230, which includes an air gap 228 embedded in or surrounded by a dielectric layer 220.

[0106] Therefore, this disclosure provides a gate isolation component, such as dielectric component 230, which includes an inner layer embedded in at least one outer layer, the composition of which differs from that of the inner layer. In some embodiments, such as Figure 3G As shown, the dielectric component 230 includes a dielectric layer 222 embedded in an outer layer, i.e., dielectric layer 220, forming a two-layer structure. In some embodiments, such as Figure 4C As shown, the dielectric component 230 includes an air gap 228 embedded in the dielectric layer 220. In some embodiments, such as Figure 3F As shown, the dielectric component 230 includes a dielectric layer 222 embedded within two outer layers, namely dielectric layers 220 and 226, forming a three-layer structure. It should be noted that the dielectric constant of dielectric layer 222 is less than that of dielectric layers 220 and / or 226. Therefore, regardless of whether the dielectric component 230 has a two-layer or three-layer structure, dielectric layer 222 is configured to reduce the overall effective capacitance (C) of the dielectric component 230. eff Its overall effective capacitance varies proportionally to the dielectric constant of each material layer included in the dielectric component 230. Figure 5 The effective capacitance (negative effective capacitance difference) of the two-layer structure shown is illustrated by multiple components of dielectric layer 222. C eff The reduction effect of dielectric constant is illustrated in an example two-layer structure comprising silicon nitride as the outer layer (i.e., dielectric layer 220). The dashed arrows indicate the decrease in dielectric constant from silicon oxide to air. In dielectric layer 222 of a fixed thickness (shown on the x-axis), the material with the smallest dielectric constant produces the largest reduction in effective capacitance, i.e., the largest negative effective capacitance difference, and as the thickness increases, the effect of reducing effective capacitance becomes less pronounced, resulting in a larger positive effective capacitance difference.

[0107] Now for reference Figure 1D (combined) Figure 1B and Figure 1C According to some embodiments of this disclosure, a process flow for a method 160 for forming apparatus 200 is shown. Method 160 is merely an example and is not intended to limit the scope of this disclosure or the claims. Additional operations may be performed before, during, and after method 160, and some described operations may be replaced, removed, or moved for additional embodiments of the method. For example, in some embodiments, method 160 may perform operation 164 before performing operation 166. Alternatively, in some embodiments, method 160 may perform operation 166 before performing operation 164. References are made below. Figures 6A-7D Description method 160; Figures 6A-6K , Figure 7A and Figure 7B It is shown that during the intermediate steps of method 160, along Figure 2A and Figure 2B Multiple cross-sectional views of device 200 taken by line A-A' are shown; Figure 6L and Figure 7C A plan view of the device 200 is shown; and Figure 6M and Figure 7D Show along Figure 2A The cross-sectional view of the device 200 taken by the C-C' line is shown.

[0108] Method 100 generally relates to forming a gate isolation member for an HKMG structure 210 in device 200, while method 160 generally relates to forming a CPODE in device 200. As described above, the dielectric member 230 is configured to divide or cut the HKMG structure into multiple HKMG structures, and thus its longitudinal direction is configured to be substantially perpendicular to the length direction of the HKMG structure 210. On the other hand, the CPODE is configured to reduce the gate spacing between two adjacent HKMG structures, and thus it is longitudinally oriented substantially parallel to the HKMG structure 210. Because the CPODE typically comprises a dielectric material, this embodiment of the method for forming a gate isolation member with reduced effective capacitance can also be applied to forming a CPODE with reduced effective capacitance. It should be noted that components of device 200 discussed below with reference to method 160 will be referred to by the same reference numerals as components of device 200 discussed above with reference to method 100.

[0109] refer to Figure 6A In operation 162, method 160 provides an apparatus 200, which includes: a substrate 202; a dummy gate stack 206 disposed over a fin 204 and in an ILD layer; a gate spacer 212 disposed over the sidewalls of the dummy gate stack 206; and a source / drain component 214 disposed over the fin 204 and inserted into the dummy gate stack 206. Of course, the apparatus 200 may include many other components as discussed in detail above. In this embodiment, the gate spacer 212 includes two spacer layers 212a and 212b with different compositions. In some embodiments, spacer layer 212a includes silicon oxide, a low-dielectric-constant dielectric material, or a combination thereof, and spacer layer 212b includes a high-dielectric-constant dielectric material, such as a nitrogen-containing dielectric material (e.g., silicon nitride, carbon and / or oxygen-doped silicon nitride, or similar materials), an oxygen-containing dielectric material (e.g., hafnium oxide, zirconium oxide, titanium oxide, or similar materials), other high-dielectric-constant dielectric materials, or combinations thereof.

[0110] refer to Figure 6B and Figure 6C In operation 164, method 160 follows the above-mentioned operation 102 of method 100. Figure 2A , Figure 2B and Figure 3A The discussed and described process is largely similar, replacing one of the dummy gate stacks 206 with an HKMG structure 210. In short, method 160, in operation 164, removes the dummy gate structure 206 to form a gate trench 207 exposing the channel region of the fin 204, and deposits various material layers in the gate trench 207, such as interface layers, high-dielectric-constant gate dielectric layers, work-function metal layers, barrier layers, capping layers, bulk conductive layers, other suitable layers, or combinations thereof, to form the HKMG structure 210. The various material layers of the HKMG structure 210 can be deposited by any suitable method, such as chemical oxidation, thermal oxidation, ALD, CVD, PVD, electroplating, other suitable methods, or combinations thereof. Subsequently, a CMP process can be performed to planarize the top surface of the device 200.

[0111] Now for reference Figures 6D to 6I In operation 166, method 160 replaces a portion of one of the dummy gate stacks 206 with a multilayer dielectric component 240 (hereinafter referred to as dielectric component 240). In this embodiment, method 160 replaces the dummy gate stack 206 disposed between the two HKMG structures 210 in operation 166. (See reference...) Figure 6D In method 160, dummy gate stack 206 is removed in operation 166 to form a trench 234 disposed between the two HKMG structures 210. Forming trench 234 may include a series of patterning and etching processes similar to those discussed above with respect to forming trench 213 in operation 104. In the depicted embodiment, forming trench 234 removes a portion of fin 204 such that trench 234 extends below the top surface of fin 204. In some embodiments, method 160 completely removes a portion of fin 204 in operation 166 such that trench 234 extends below the top surface of substrate 202. In some embodiments, removing dummy gate stack 206 removes a portion of gate spacer 212. As depicted herein, method 160 may completely remove spacer layer 212a and partially remove spacer 212b. Therefore, the sidewalls of trench 234 may be partially defined by spacer layer 212b. Of course, this disclosure is not limited to this configuration, and spacer layers 212a and 212b can be completely removed.

[0112] Subsequently, referencing the whole Figures 6E to 6I Method 160 is implemented at operation 166 as follows: Figure 1B and Figure 1CPath A or path B is shown to form dielectric component 240 in trench 234. Subsequently, in operation 168, similar to operation 108, method 160 performs additional process steps on device 200. For example, additional vertical interconnect components, such as contacts and / or vias, and / or horizontal interconnect components, such as wires, and multilayer interconnect components, such as metal layers and interlayer dielectrics, may be formed above device 200.

[0113] Regarding path A, for example, refer to Figure 1B and Figure 6E Method 160 is similar to the above reference. Figure 3B The process of operation 120 discussed forms a dielectric layer 220 in trench 234. In short, the dielectric layer 220 may comprise a nitrogen-containing dielectric material (e.g., silicon nitride, carbon and / or oxygen-doped silicon nitride, etc.), an oxygen-containing dielectric material (e.g., hafnium oxide, zirconium oxide, titanium oxide, etc.), other high-dielectric-constant dielectric materials, or combinations thereof. The dielectric layer 220 may be deposited by any suitable method, including ALD, CVD, other suitable methods, or combinations thereof. In this embodiment, an ALD process is used to deposit the dielectric layer 220.

[0114] refer to Figure 6F Method 160 forms a dielectric layer 222 above the dielectric layer 220, thereby achieving a dielectric layer similar to the reference layer described above. Figure 3C The process of operation 122 discussed fills trench 234. In short, dielectric layer 222 may comprise silicon oxide, a low-dielectric-constant dielectric material, or a combination thereof. The low-dielectric-constant dielectric material may comprise porous silicon oxide, doped silicon oxide (e.g., SiOC, BPSG, FSG, PSG, BSG, etc.), other low-dielectric-constant dielectric materials, or combinations thereof. Dielectric layer 222 may be formed by any suitable method, including CVD, FCVD, ALD, or combinations thereof.

[0115] Now for reference Figure 6G Method 160 then uses a method similar to the one described above. Figure 3D The process of operation 124 discussed removes a portion of dielectric layer 222 to form notch 224. For example, dielectric layer 222 is selectively etched relative to dielectric layer 220 such that dielectric layer 220 is not etched by any suitable etching process, such as dry etching, wet etching, RIE, or combinations thereof, or is etched only minimally. In this embodiment, dielectric layer 222 is etched by dry etching using an etchant, which includes fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, NF3, and / or C2F6), nitrogen-containing gases (e.g., N2), hydrogen-containing gases (e.g., H2), oxygen-containing gases (e.g., O2, CO2, COS), other suitable gases, or combinations thereof.

[0116] refer to Figure 6H Method 160 forms a dielectric layer 226 above the dielectric layer 222, thereby achieving a similar effect to the aforementioned reference layer. Figure 3E The process of operation 126 discussed fills the notch 224. For example, dielectric layer 226 may include a nitrogen-containing dielectric material (e.g., silicon nitride, carbon and / or oxygen-doped silicon nitride, etc.), an oxygen-containing dielectric material (e.g., hafnium oxide, zirconium oxide, titanium oxide, etc.), other dielectric materials, or combinations thereof. Dielectric layer 226 may be formed by any suitable method, including CVD, FCVD, ALD, or combinations thereof. In some embodiments, the composition of dielectric layer 226 is the same as (or substantially similar to) the composition of dielectric layer 220.

[0117] Afterwards, refer to Figure 6I Method 160 (e.g., via a CMP process) removes a portion of the dielectric layer 226 formed above the top surface of the HKMG structure 210, thereby planarizing the top surface of the device 200 using a process similar to operation 128 discussed above. The resulting dielectric component 240 may be a CPODE configured to reduce the gate spacing between the HKMG structures 210 disposed on both sides of the dielectric component 240. Generally, in the absence of the dielectric component 240, the spacing between adjacent source / drain components 214 disposed on both sides of the active edge is typically increased (defining two adjacent active regions of the device 200) to prevent short circuits and ensure proper device performance. To reduce component size (e.g., reduce SRAM cell size), a CPODE, such as the dielectric component 240, can be performed at the active edge to provide sufficient insulation without increasing the spacing between the source / drain components 214. However, using a high dielectric constant dielectric material in a CPODE increases the parasitic capacitance between the source / drain components 214 adjacent to the active region. This disclosure provides a method for forming a CPODE with reduced effective capacitance, such that the parasitic capacitance between two conductive components can be reduced while maintaining a relatively small separation distance between them.

[0118] Continue to refer to Figure 6I The various dimensions of the dielectric component 240 are similar to those discussed above regarding Figure 3FThe dielectric component 230 is shown. For example, the ratio of the thickness S2 of dielectric layer 222 to the thickness S1 of dielectric layer 220 can be greater than 0 and less than about 30, and the ratio of the height D3 of dielectric layer 222 to the height D1 of dielectric component 230 can be greater than about 0.3 and less than about 0.8. Therefore, the sum of S1 and S2 is greater than the width of HKMG structure 210 plus twice the thickness of spacer layer 212a. In some examples, S1 can be greater than 0 nm and less than about 3 nm, S2 can be about 15 nm to about 25 nm, D1 can be about 50 nm to about 200 nm, D2 can be at least about 2 nm, and D3 can be about 35 nm to about 145 nm. Of course, these are merely example dimensions and do not limit the embodiments provided in this disclosure.

[0119] In some embodiments, reference Figure 6J and Figure 6K The composition of dielectric layer 226 is the same as that of dielectric layer 220, such that dielectric layer 222 is completely embedded within dielectric layer 220. Therefore, similar to dielectric component 230, if dielectric layer 226 and dielectric layer 220 have the same composition, dielectric component 240 can be a two-layer structure; or, alternatively, if dielectric layer 226 has a different composition than dielectric layer 220, dielectric component 240 can be a three-layer structure. Furthermore, similar to... Figure 3H and Figure 3I , Figure 6L and Figure 6M Plan view (top view) Figure 6L ) and along Figure 2A The cross-sectional view of line C-C' shown ( Figure 6M Depict apparatus 200 separately. It should be noted that for, for example... Figure 6I The three-layer structure shown Figure 6L A plan view of the device 200 shows that it includes Figure 3H The dielectric component 240 of the dielectric layer 226 in the middle, and Figure 6M The cross-sectional view shows a dielectric component 240 including a dielectric layer 222 embedded in a dielectric layer 220. For example... Figure 6K The two-layer structure shown has a plan view (not shown) of dielectric component 240 that includes only dielectric layer 220, while a cross-sectional view taken along line C-C' (not shown) includes the dielectric layer 220. Figure 6M The structures shown are largely similar.

[0120] In some embodiments, similar to the above regarding Figures 4A-4E The method discussed, implementation of method 160 Figure 1C The path B depicted is used to form a dielectric component 240 including an air gap 228 at operation 166. For example, refer to... Figure 7AMethod 160 conformally forms a dielectric layer 220 in trench 234 using a first deposition process similar to operation 140 described above. The first deposition process can be any suitable process, including ALD, CVD, FCVD, other suitable processes, or combinations thereof. Reference then continues. Figure 7A Method 160 employs a second deposition process similar to operation 142 described above, but at a different deposition rate than the first deposition process, to deposit the dielectric layer 220. In this embodiment, the deposition rate of the second deposition process is higher than that of the first deposition process. The second deposition process can be any suitable process, including ALD, CVD, FCVD, other suitable processes, or combinations thereof. As described above, the higher deposition rate allows the dielectric material to accumulate rapidly and bridge the openings of the trench 234, preventing other materials from depositing in the trench 234, thereby embedding the air gap 228 within the dielectric layer 220.

[0121] Afterwards, refer to Figure 7B Method 160 performs a planarization process (e.g., CMP process) on the apparatus 200 similar to operation 144 described above. Therefore, the plan view of the apparatus 200 (…) Figure 7C The diagram shows a dielectric component 240 including a dielectric layer 220, while along... Figure 2A A cross-sectional view of the device 200 with the C-C' line cut off ( Figure 7D The diagram shows a dielectric component 240, which includes an air gap 228 embedded in or surrounded by a dielectric layer 220.

[0122] In some embodiments, the order of the metal gate replacement process (i.e., operation 164) and the CPODE formation process (i.e., operation 166) can be reversed. Method 160 first replaces the dummy gate stack 206 with dielectric component 240, and then replaces the adjacent dummy gate stack 206 with HKMG structure 210. In some examples, refer to... Figure 8A and Figure 8B Methods 100 and 160 can be implemented in the same apparatus, i.e., dielectric member 230 is configured to separate HKMG structure 210 and dielectric member 240, which are longitudinally oriented approximately parallel to HKMG structure 210. Therefore, dielectric members 230 and 240 are configured to intersect each other. More specifically, this can be seen in a plan view (top view). Figure 8A The dielectric layer 226 is shown, which is connected to... Figure 3H and Figure 6L The described embodiments are consistent and can be followed along Figure 2A A cross-sectional view taken from the C-C' line ( Figure 8B The diagram shows dielectric layer 222 embedded in dielectric layer 220, which is related to... Figure 3I and Figure 6M The described embodiments are consistent.

[0123] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. This disclosure provides dielectric components for isolating HKMG structures and for adjusting the spacing between active regions comprising the HKMG structure. In some embodiments, the dielectric component is configured to include a two-layer structure, wherein an inner layer is embedded within an outer layer, the outer layer having a higher dielectric constant than the inner layer. In some examples, the inner layer may have a void, i.e., an air gap. In some embodiments, the dielectric component is configured to include a three-layer structure, wherein an inner layer is embedded within two outer layers, each of the two outer layers having a higher dielectric constant than the inner layer. It should be noted that the multilayer structure provided by this disclosure can be beneficial in reducing the overall effective capacitance of the dielectric component, thereby improving device performance, such as parameters related to RC delay.

[0124] In some embodiments, this disclosure provides a semiconductor structure including: a fin protruding from a semiconductor substrate; a first metal gate stack and a second metal gate stack disposed on the fin; and a dielectric component disposed on the semiconductor substrate, wherein the dielectric component defines the sidewalls of the first metal gate stack and the second metal gate stack, wherein the dielectric component includes a first layer disposed on a second layer, wherein the sidewalls of the first layer are defined by the second layer, and wherein the first layer is compositionally different from the second layer.

[0125] In some embodiments, the dielectric constant of the first layer is less than that of the second layer.

[0126] In some embodiments, the porosity of the first layer is greater than that of the second layer.

[0127] In some embodiments, the first layer comprises air.

[0128] In some embodiments, the dielectric component further includes a third layer disposed on the first layer, wherein the sidewalls of the third layer are defined by the second layer.

[0129] In some embodiments, the composition of the second layer is the same as that of the third layer.

[0130] In some embodiments, the composition of the second layer differs from that of the third layer.

[0131] In some embodiments, the dielectric component extends below the top surface of the semiconductor substrate.

[0132] In other embodiments, this disclosure provides a semiconductor structure including: a semiconductor layer disposed on a substrate and oriented in a first direction; a metal gate stack disposed on the semiconductor layer and oriented in a second direction perpendicular to the first direction; a source / drain component disposed in the semiconductor layer and adjacent to the metal gate stack; and a dielectric component extending into the semiconductor layer, wherein the source / drain component is disposed between the metal gate stack and the dielectric component, wherein the dielectric component includes a first layer encapsulated by a second layer, and wherein the dielectric constant of the first layer is different from the dielectric constant of the second layer.

[0133] In other embodiments, the dielectric constant of the first layer is lower than that of the second layer.

[0134] In other embodiments, the bottom surface of the dielectric component is below the top surface of the substrate.

[0135] In other embodiments, the first layer comprises air.

[0136] In other embodiments, a first gate spacer is also included, disposed on a sidewall of the metal gate stack, and a second gate spacer is disposed on the first gate spacer, wherein a portion of the dielectric component is defined by the second gate spacer.

[0137] In other embodiments, the dielectric component is a first dielectric component, and the semiconductor structure further includes a second dielectric component, the second dielectric component being longitudinally oriented in a first direction, wherein each of the second dielectric components separates a metal gate stack from the first dielectric component into two parts, and wherein the second dielectric component includes a first layer embedded in a second layer.

[0138] In some other embodiments, this disclosure provides a method for constructing a semiconductor structure, comprising: forming a high-dielectric-constant metal gate stack on a semiconductor layer; forming a trench to separate the high-dielectric-constant metal gate stack into two portions; forming a first dielectric layer in the trench; forming a second dielectric layer on the first dielectric layer to fill the trench, wherein the second dielectric layer is different from the first dielectric layer; removing a portion of the second dielectric layer to form a notch; forming a third dielectric layer in the notch, wherein the third dielectric layer is different from the second dielectric layer; and planarizing the third dielectric layer to form a gate isolation component.

[0139] In some other embodiments, the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer, respectively.

[0140] In some other embodiments, the composition of the third dielectric layer is the same as that of the first dielectric layer.

[0141] In some other embodiments, the step of forming the second dielectric layer includes performing a flow chemical vapor deposition process.

[0142] In some other embodiments, the second dielectric layer is further cured after it is formed and before the notch is formed.

[0143] In some other embodiments, the steps of forming the first dielectric layer and the third dielectric layer each include performing an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof.

[0144] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the concept and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, comprising: A fin protrudes from a semiconductor substrate; A first metal gate stack and a second metal gate stack are disposed on the fin; as well as A dielectric component is disposed on the semiconductor substrate and spans the first metal gate stack and the second metal gate stack, wherein the dielectric component extends longitudinally parallel to the fin, wherein the dielectric component includes a first layer disposed on a second layer, wherein a plurality of sidewalls of the first layer are defined by the second layer, wherein the first layer is different in composition from the second layer, and wherein the porosity of the first layer is greater than the porosity of the second layer.

2. The semiconductor structure of claim 1, wherein the dielectric constant of the first layer is less than the dielectric constant of the second layer.

3. The semiconductor structure of claim 1, wherein the first layer comprises air.

4. The semiconductor structure of claim 1, wherein the dielectric component further comprises a third layer disposed on the first layer, and wherein a plurality of sidewalls of the third layer are defined by the second layer.

5. The semiconductor structure of claim 4, wherein the composition of the second layer is the same as that of the third layer.

6. The semiconductor structure of claim 4, wherein the composition of the second layer is different from the composition of the third layer.

7. The semiconductor structure of claim 1, wherein the dielectric component extends below a top surface of the semiconductor substrate.

8. A semiconductor structure, comprising: A semiconductor layer is disposed on a substrate and oriented along a first direction; A metal gate stack is disposed on the semiconductor layer and oriented along a second direction perpendicular to the first direction; A first dielectric component is oriented along the first direction and passes through the substrate; as well as A second dielectric component extends into the semiconductor layer and is oriented along the second direction, wherein the second dielectric component intersects with the first dielectric component, wherein the second dielectric component includes a first layer encapsulated by a second layer, wherein the dielectric constant of the first layer is different from that of the second layer, and wherein the porosity of the first layer is greater than that of the second layer.

9. The semiconductor structure of claim 8, wherein the dielectric constant of the first layer is lower than that of the second layer.

10. The semiconductor structure of claim 8, wherein the first layer comprises air.

11. The semiconductor structure of claim 8, further comprising a plurality of first gate spacers disposed on a plurality of sidewalls of the metal gate stack, and a plurality of second gate spacers disposed on the plurality of first gate spacers, wherein a plurality of portions of the second dielectric member are defined by the plurality of second gate spacers.

12. The semiconductor structure of claim 8, wherein the first dielectric component separates the metal gate stack and the second dielectric component into two portions, and wherein the first dielectric component includes the first layer embedded in the second layer.

13. The semiconductor structure of claim 8, wherein the second dielectric component further comprises a third layer disposed above the first layer, and wherein the third layer directly contacts the second layer.

14. A method for forming a semiconductor structure, comprising: A high-dielectric-constant metal gate stack is formed on a semiconductor layer; A trench is formed to separate the high dielectric constant metal gate stack into two parts; A first dielectric layer is formed in the trench; A second dielectric layer is formed on the first dielectric layer to fill the trench, wherein the second dielectric layer is different from the first dielectric layer, and wherein the porosity of the second dielectric layer is greater than that of the first dielectric layer; A portion of the second dielectric layer is removed to form a notch; A third dielectric layer is formed within the notch, wherein the third dielectric layer is different from the second dielectric layer; and The third dielectric layer is planarized to form a gate isolation component.

15. The method of forming a semiconductor structure as claimed in claim 14, wherein the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer, respectively.

16. The method of forming a semiconductor structure as claimed in claim 14, wherein the composition of the third dielectric layer is the same as that of the first dielectric layer.

17. The method of forming a semiconductor structure as claimed in claim 14, wherein the step of forming the second dielectric layer includes performing a flow chemical vapor deposition process.

18. The method of forming a semiconductor structure as claimed in claim 17, further comprising curing the second dielectric layer after forming the second dielectric layer and before forming the notch.

19. The method of forming a semiconductor structure as claimed in claim 17, wherein the steps of forming the first dielectric layer and the third dielectric layer each include performing an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof.

20. A semiconductor structure comprising: A fin protrudes from a semiconductor substrate and is oriented along a first direction; A metal gate stack is stacked above the fin and oriented along a second direction perpendicular to the first direction; and A dielectric component is disposed adjacent to the fin and oriented along the first direction, wherein the dielectric component extends through the metal gate stack to pass through the semiconductor substrate, thereby dividing the metal gate stack into a first portion and a second portion, wherein the dielectric component includes a first dielectric layer disposed on a second dielectric layer, wherein the sidewalls of the first dielectric layer are defined by the second dielectric layer, wherein the composition of the first dielectric layer is different from that of the second dielectric layer, and wherein the porosity of the first dielectric layer is greater than that of the second dielectric layer.

21. The semiconductor structure of claim 20, wherein the dielectric component further comprises a third dielectric layer disposed on the first dielectric layer, and wherein the sidewalls of the third dielectric layer are defined by the second dielectric layer.

22. The semiconductor structure of claim 21, wherein the composition of the second dielectric layer is the same as that of the third dielectric layer.

23. The semiconductor structure of claim 21, wherein the composition of the second dielectric layer is different from the composition of the third dielectric layer.

24. The semiconductor structure of claim 20, wherein the first dielectric layer comprises air.

25. A method for forming a semiconductor structure, comprising: A high-dielectric-constant metal gate stack is formed above a semiconductor fin; A trench is formed to divide the high dielectric constant metal gate stack into two parts; A first dielectric layer is formed in the trench; A second dielectric layer is formed above the first dielectric layer to fill the trench, wherein the composition of the second dielectric layer is different from that of the first dielectric layer, and wherein the porosity of the second dielectric layer is greater than that of the first dielectric layer. A portion of the second dielectric layer was etched. A third dielectric layer is formed above the etched second dielectric layer, wherein the composition of the third dielectric layer is different from that of the second dielectric layer; and The third dielectric layer is planarized to form a gate isolation component.

26. The method of forming a semiconductor structure as claimed in claim 25, wherein the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer, respectively.

27. The method of forming a semiconductor structure as claimed in claim 25, wherein the composition of the third dielectric layer is the same as the composition of the first dielectric layer.

28. The method of forming a semiconductor structure as claimed in claim 25, wherein forming the second dielectric layer comprises performing a flow chemical vapor deposition process.

29. The method for forming a semiconductor structure as described in claim 28, further comprising: The second dielectric layer is cured after it is formed and before that portion of it is etched.

30. The method of forming a semiconductor structure as claimed in claim 28, wherein forming the first dielectric layer and the third dielectric layer each comprises performing an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof.

31. The method of forming a semiconductor structure as claimed in claim 25, wherein a bottom surface of the trench is lower than a bottom surface of the fin.

32. A method for forming a semiconductor structure, comprising: A workpiece is provided, including a first fin and a second fin, protruding from a substrate; The first fin and the second fin extend longitudinally along a first direction; A gate structure is formed above the first fin and the second fin; the gate structure extends longitudinally along a second direction, which is substantially perpendicular to the first direction. An etching process is performed to form a trench that extends vertically through the gate structure and is disposed between the first fin and the second fin, wherein the trench extends longitudinally along the first direction; A first dielectric layer is deposited in the trench; A second dielectric layer is formed above the first dielectric layer, wherein the composition of the second dielectric layer is different from that of the first dielectric layer, and wherein the porosity of the second dielectric layer is greater than that of the first dielectric layer; and A third dielectric layer is formed, wherein the third dielectric layer directly contacts a top of the second dielectric layer and a sidewall of the first dielectric layer.

33. The method for forming a semiconductor structure as described in claim 32, further comprising: After the second dielectric layer is formed, the second dielectric layer is cured.

34. The method of forming a semiconductor structure as claimed in claim 32, wherein the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer, respectively.

35. The method of forming a semiconductor structure as described in claim 32, wherein the composition of the third dielectric layer is the same as that of the first dielectric layer.

36. The method of forming a semiconductor structure as claimed in claim 32, wherein forming the second dielectric layer comprises performing a flow chemical vapor deposition process.

37. The method of forming a semiconductor structure as claimed in claim 32, wherein the workpiece further includes an isolation member configured to isolate the first fin from the second fin, wherein the trench further extends through the isolation member.

38. The method of forming a semiconductor structure as claimed in claim 32, wherein forming the third dielectric layer comprises: Remove a portion of the second dielectric layer to partially expose the sidewall of the first dielectric layer; as well as The third dielectric layer is formed on the second dielectric layer to directly contact the exposed sidewall of the first dielectric layer.

39. The method of forming a semiconductor structure as claimed in claim 32, wherein the second dielectric layer includes a void, and wherein forming the third dielectric layer includes depositing a dielectric material over the first dielectric layer to seal an opening of the trench to form the void.

40. The method of forming a semiconductor structure as claimed in claim 39, wherein the dielectric material is a first dielectric material and is deposited on the workpiece at a first deposition rate, and wherein forming the first dielectric layer includes depositing a second dielectric material at a second deposition rate different from the first deposition rate.

41. A method for forming a semiconductor structure, comprising: A semiconductor fin is formed above a substrate; A first metal gate structure and a second metal gate structure separate from the first metal gate structure are formed above the semiconductor fin; as well as Forming a gate dicing component, comprising: A trench is formed in the first and second metal gate structures; A first dielectric layer is deposited in the trench; A second dielectric layer is formed above the first dielectric layer, wherein the composition of the second dielectric layer is different from that of the first dielectric layer, and wherein the porosity of the second dielectric layer is greater than that of the first dielectric layer; and A third dielectric layer is formed above the second dielectric layer, wherein the third dielectric layer directly contacts the sidewall of the first dielectric layer.

42. The method of forming a semiconductor structure as claimed in claim 41, wherein the dielectric constant of the second dielectric layer is less than the dielectric constants of the first dielectric layer and the third dielectric layer, respectively.

43. The method of forming a semiconductor structure as claimed in claim 41, wherein the composition of the third dielectric layer is the same as the composition of the first dielectric layer.

44. The method of forming a semiconductor structure as claimed in claim 41, wherein forming the second dielectric layer comprises performing a flow chemical vapor deposition process.

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