A trimming circuit and a battery protection circuit

Abstract

The present invention provides a trimming circuit, including a trimming network connected to a signal to be trimmed, the trimming network including a plurality of trimming units connected in series, each trimming unit including a trimming set point; a single-line communication circuit, the input end of which is connected to a clock signal output end, and the output end is connected to the trimming set point of each trimming unit; the single-line communication circuit is used to generate a bit address according to the input clock signal, and to burn according to the bit address to change the access state of the trimming unit. Through the trimming circuit provided by the present invention, the signal to be trimmed can be trimmed after the chip is packaged, and the accuracy deviation caused by factors such as packaging stress can be effectively corrected, greatly improving the trimming accuracy; and the signal to be trimmed can be increased or decreased.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a trimming circuit and a battery protection circuit. Background Art

[0002] Most existing battery protection circuits use laser trimming of metal to trim the reference voltage or battery voltage inside the battery protection circuit. For example, a number of trimming resistors connected in series are reserved, and each trimming resistor is connected in parallel with a metal sheet. When the resistance needs to be adjusted, the metal sheet connected in parallel with the trimming resistor can be cut off by laser.

[0003] However, this trimming method mainly uses laser to cut off the metal sheet connected in parallel with the trimming resistor to connect the trimming resistor to the resistor network. The resistor can only be adjusted upward, not downward, and the default value of the resistor needs to be set to the minimum value at the beginning of the design. In addition, laser trimming needs to be performed at the wafer level before chip packaging, and the packaging process will inevitably introduce stress and other effects. The accuracy deviation caused by this stress cannot be effectively calibrated, resulting in drift in the trimming accuracy. Summary of the invention

[0004] The present invention provides a trimming circuit and a battery protection circuit to solve the problem that the existing trimming circuit has poor trimming accuracy and can only perform trimming in one direction.

[0005] The present invention is implemented in such a way that a trimming circuit comprises:

[0006] A trimming network, wherein a first end of the trimming network serves as an output end of a trimmed signal, and a second end is connected to a signal to be trimmed, wherein the trimming network comprises a plurality of trimming units connected in series, and each of the trimming units comprises a trimming adjustment point;

[0007] A single-line communication circuit, wherein the input end of the single-line communication circuit is connected to the clock signal output end, and includes a plurality of output ends, each of which is connected to a trimming adjustment point;

[0008] The single-line communication circuit is used to generate a bit address according to an input clock signal, and to perform programming according to the bit address to change the access state of the trimming unit.

[0009] Optionally, each of the trimming units comprises a trimming device and a transistor connected in parallel with each other;

[0010] The gate of the transistor is connected to an output end of the single-line communication circuit as a trimming adjustment point of the trimming unit.

[0011] Optionally, the transistor is a PMOS transistor;

[0012] A first parallel connection point between the source of the transistor and the first end of the trimming device is connected to a previous trimming unit, and a second parallel connection point between the drain of the transistor and the second end of the trimming device is connected to a subsequent trimming unit;

[0013] The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

[0014] Optionally, the transistor is an NMOS transistor;

[0015] A first parallel connection point between the drain of the transistor and the first end of the trimming device is connected to a previous trimming unit, and a second parallel connection point between the source of the transistor and the second end of the trimming device is connected to a subsequent trimming unit;

[0016] The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

[0017] Optionally, the trimming circuit includes two or more trimming networks, and the second end of each trimming network is connected to a different signal to be trimmed.

[0018] Optionally, the single-line communication circuit includes:

[0019] Delay circuit, timing circuit, data storage and output circuit, storage circuit;

[0020] The input end of the delay circuit, the input end of the timing circuit and the first input end of the data storage and output circuit are respectively connected to the clock signal output end;

[0021] The output end of the delay circuit is connected to the second input end of the data storage and output circuit;

[0022] The output terminal of the timing circuit is connected to the enable / reset terminal of the data storage and output circuit;

[0023] The output end of the data storage and output circuit is connected to the input end of the storage circuit;

[0024] The storage circuit includes a plurality of output terminals, each of which is connected to a trimming point of a trimming unit;

[0025] The timing circuit is used to receive a clock signal, and enable the data storage and output circuit according to the rising edge of the clock signal, and reset the data storage and output circuit when the rising edge is not received within a preset time; the delay circuit is used to receive a clock signal, generate adjustment information according to the pulse width length of the clock signal, and send the adjustment information to the data storage and output circuit; the data storage and output circuit is used to receive and store the adjustment information according to the rising edge of the clock signal when enabled, convert the adjustment information into a bit address, and send the bit address to the storage circuit; the storage circuit is used to burn according to the bit address to change the access status of the adjustment unit.

[0026] Optionally, the data storage and output circuit further includes:

[0027] Counter circuits, shift registers, decoder circuits;

[0028] The first input terminals of the counter circuit and the shift register are respectively connected to the clock signal output terminal, and the enable / reset terminals are respectively connected to the output terminal of the timing circuit;

[0029] The output end of the counter circuit is connected to the enable end of the decoder circuit;

[0030] The second input terminal of the shift register is connected to the output terminal of the delay circuit, and the output terminal is connected to the input terminal of the decoder circuit;

[0031] The output end of the decoder circuit is connected to the input end of the storage circuit;

[0032] The counter circuit is used to receive the clock signal and count the number of pulses, and to generate an enable signal for the decoder circuit when the number of pulses is greater than or equal to a preset number threshold;

[0033] The shift register is used to collect the adjustment information output by the delay circuit according to the clock signal, and send the adjustment information to the decoder circuit;

[0034] The decoder circuit is used to receive the enable signal, and perform decoding processing on the trimming information under the action of the enable signal to obtain a bit address, and send the bit address to the storage circuit.

[0035] A battery protection circuit comprises a reference circuit and a voltage detection circuit, the battery protection circuit further comprising at least one comparator and the adjustment circuit as described above;

[0036] The output end of the comparator is used as the clock signal output end of the trimming circuit and is connected to the input end of the single-line communication circuit of the trimming circuit;

[0037] The trimming circuit comprises at least one trimming network, a second end of the trimming network is connected to a reference voltage or a battery voltage, and a first end is connected to a reference circuit or a voltage detection circuit of the battery protection circuit;

[0038] The comparator is used to generate a pulse signal required by the single-wire communication circuit.

[0039] Optionally, the comparator is a voltage over-discharge comparator, a voltage over-charge comparator, a short-circuit comparator or an over-current comparator in a battery protection circuit.

[0040] A battery protection circuit comprises a reference circuit and a voltage detection circuit, the battery protection circuit further comprising at least one comparator and the adjustment circuit as described above;

[0041] The output end of the comparator is used as the clock signal output end of the trimming circuit and is connected to the input end of the single-line communication circuit of the trimming circuit;

[0042] The trimming circuit includes at least two trimming networks; a second end of one of the trimming networks is connected to a reference voltage, and a first end is connected to a reference circuit of the battery protection circuit; a second end of another trimming network is connected to a battery voltage, and a first end is connected to a voltage detection circuit of the battery protection circuit;

[0043] The comparator is used to generate a pulse signal required by the single-wire communication circuit.

[0044] The trimming circuit provided by the present invention includes a trimming network, wherein the first end of the trimming network serves as the output end of the trimmed signal, and the second end is connected to the signal to be trimmed, wherein the trimming network includes a plurality of trimming units connected in series, and each of the trimming units includes a trimming set point; a single-line communication circuit, wherein the input end of the single-line communication circuit is connected to the clock signal output end, and includes a plurality of output ends, and each output end is respectively connected to a trimming set point; wherein the single-line communication circuit is used to generate a bit address according to the input clock signal, and to burn according to the bit address to change the access state of the trimming unit. Through the trimming circuit provided by the present invention, the signal to be trimmed can be trimmed after the chip is packaged, and the accuracy deviation caused by factors such as packaging stress can be effectively corrected, which greatly improves the trimming accuracy; and the signal to be trimmed can be adjusted to be larger or smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0046] Figure 1 is a schematic diagram of a trimming circuit provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic diagram of a trimming network in a trimming circuit provided in an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of a trimming network in a trimming circuit provided by another embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of a trimming network in a trimming circuit provided by another embodiment of the present invention;

[0050] Figure 5 is a schematic diagram of a single-line communication circuit provided by an embodiment of the present invention;

[0051] Figure 6 is a schematic diagram of a single-line communication circuit provided by another embodiment of the present invention;

[0052] Figure 7 A schematic diagram of the timing of output signals in a single-line communication circuit provided in an embodiment of the present invention;

[0053] Figure 8 A schematic diagram of a battery protection circuit provided by an embodiment of the present invention;

[0054] Fig. 9 A schematic diagram of a battery protection circuit provided according to another embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0056] The present invention provides a trimming circuit, including a trimming network, wherein the first end of the trimming network serves as the trimmed signal output end, and the second end is connected to the signal to be trimmed, wherein the trimming network includes a plurality of trimming units connected in series, and each of the trimming units includes a trimming set point; a single-line communication circuit, wherein the input end of the single-line communication circuit is connected to the clock signal output end, and includes a plurality of output ends, and each output end is respectively connected to a trimming set point; wherein the single-line communication circuit is used to generate a bit address according to the input clock signal, and to burn according to the bit address to change the access state of the trimming unit. Through the trimming circuit provided by the present invention, the signal to be trimmed can be trimmed after the chip is packaged, and the accuracy deviation caused by factors such as packaging stress can be effectively corrected, which greatly improves the trimming accuracy; and the signal to be trimmed can be adjusted to be larger or smaller.

[0057] Figure 1 Schematic diagram of a trimming circuit provided by an embodiment of the present invention. Figure 1 As shown, the trimming circuit comprises:

[0058] A trimming network 10, wherein a first end of the trimming network 10 is used as a trimmed signal output end, and a second end is connected to a signal to be trimmed, wherein the trimming network 10 comprises a plurality of trimming units 101 connected in series, and each of the trimming units 101 comprises a trimming adjustment point;

[0059] A single-line communication circuit 30, wherein the input end of the single-line communication circuit 30 is connected to the clock signal output end, and includes a plurality of output ends, each of which is connected to a trimming adjustment point;

[0060] The single-line communication circuit 30 is used to generate a bit address according to an input clock signal, and to perform programming according to the bit address to change the access state of the trimming unit.

[0061] Different from the prior art method of using laser to trim metal sheets, the embodiment of the present invention extends a trimming adjustment point outward from the trimming unit 101, and controls the trimming unit 101 through the trimming adjustment point, so that the trimming unit 101 is connected to the trimming network 10 to adjust the signal to be trimmed downward, or the trimming unit 101 is short-circuited to adjust the signal to be trimmed upward. Specifically, by inputting a clock signal into the single-line communication circuit 30, the clock signal is a pulse signal, and the single-line communication circuit 30 generates a bit address according to the input clock signal, and burns according to the bit address to control the on and off of the trimming adjustment point to change the access state of the trimming unit 101. The number of trimming units 101 in the trimming network 10 is determined by the trimming bits required for the signal to be trimmed.

[0062] The trimming circuit provided in the embodiment of the present invention is applied to a circuit that needs to be trimmed, such as a battery protection chip. The chip packaging can be completed first, and then after the packaging is completed, the adjustment of the signal to be trimmed in the circuit can be completed by inputting a clock signal to the single-line communication circuit 30. This can effectively correct the accuracy deviation caused by factors such as packaging stress, and greatly improve the trimming accuracy.

[0063] Optionally, as a preferred example of the present invention, each of the trimming units 101 includes a trimming device R and a transistor T connected in parallel with each other;

[0064] The gate of the transistor T is connected to an output terminal of the single-wire communication circuit 30 as a trimming adjustment point of the trimming unit 101 .

[0065] The transistor T may be an NMOS transistor or a PMOS transistor.

[0066] In one embodiment of the present invention, when the transistor T is a PMOS tube, a first parallel connection point between the source of the transistor T and the first end of the trimming device R is connected to a previous trimming unit, and a second parallel connection point between the drain of the transistor T and the second end of the trimming device R is connected to a subsequent trimming unit;

[0067] The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

[0068] Alternatively, for ease of understanding, Figure 2 FIG. 1 is a schematic diagram of a trimming network provided by an embodiment of the present invention. Figure 2In the embodiment, the trimming network includes three trimming units, which are respectively denoted as the first trimming unit 101, the second trimming unit 102, and the third trimming unit 103. The trimming device used in each trimming unit is a resistor. The first trimming unit 101 includes a trimming device R0 and a PMOS tube T0 connected in parallel, the second trimming unit 102 includes a trimming device R1 and a PMOS tube T1 connected in parallel, and the third trimming unit 103 includes a trimming device R2 and a PMOS tube T2 connected in parallel. The gate of the transistor T0 is connected to the first output end of the single-line communication circuit 30 as the trimming adjustment point of the first trimming unit 101, the gate of the transistor T1 is connected to the second output end of the single-line communication circuit 30 as the trimming adjustment point of the second trimming unit 102, and the gate of the transistor T2 is connected to the third output end of the single-line communication circuit 30 as the trimming adjustment point of the second trimming unit 103. The first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 serves as the first end of the trimming network; the third trimming unit 103 serves as the last trimming unit, and its second parallel connection point connects the second end of the trimming network to the signal to be trimmed. Exemplarily, if the trimming circuit is applied to a battery protection circuit, such as trimming a reference voltage in the battery protection circuit, the second parallel connection point of the third trimming unit 103 is connected to the reference voltage output end of the battery protection circuit, and the first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 is used as the output end of the trimmed reference voltage, and is connected to a voltage-dividing resistor string corresponding to the reference voltage in the battery protection circuit; or when applied to trimming a battery voltage in the battery protection circuit, the second parallel connection point of the third trimming unit 103 is connected to a battery voltage sampling point of the battery protection circuit, and the first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 is used as the output end of the trimmed battery voltage, and is connected to a voltage-dividing resistor string corresponding to the battery voltage in the battery protection circuit.

[0069] It should be understood that the above Figure 2 This is only a schematic diagram of a trimming network provided for an embodiment of the present invention, and is not intended to limit the number of trimming units of the present invention. In practical applications, other numbers of trimming units may also be included.

[0070] In another embodiment of the present invention, when the transistor T is an NMOS tube, a first parallel connection point between the drain of the transistor T and the first end of the trimming device R is connected to a previous trimming unit, and a second parallel connection point between the source of the transistor T and the second end of the trimming device R is connected to a subsequent trimming unit;

[0071] The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

[0072] Alternatively, for ease of understanding, Figure 3 FIG. 1 is a schematic diagram of a trimming network provided by another embodiment of the present invention. Figure 3 In the embodiment, the trimming network includes three trimming units, which are respectively denoted as the first trimming unit 101, the second trimming unit 102, and the third trimming unit 103. The trimming device used in each trimming unit is a resistor. The first trimming unit 101 includes a trimming device R0 and an NMOS transistor T0 connected in parallel, the second trimming unit 102 includes a trimming device R1 and an NMOS transistor T1 connected in parallel, and the third trimming unit 103 includes a trimming device R2 and an NMOS transistor T2 connected in parallel. The gate of the transistor T0 is connected to the first output terminal of the single-line communication circuit 30 as the trimming adjustment point of the first trimming unit 101, the gate of the transistor T1 is connected to the second output terminal of the single-line communication circuit 30 as the trimming adjustment point of the second trimming unit 102, and the gate of the transistor T2 is connected to the third output terminal of the single-line communication circuit 30 as the trimming adjustment point of the second trimming unit 103. The first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 serves as the first end of the trimming network; the third trimming unit 103 serves as the last trimming unit, and its second parallel connection point serves as the second end of the trimming network to connect the signal to be trimmed. Exemplarily, if the trimming circuit is applied to a battery protection circuit, such as trimming a reference voltage in the battery protection circuit, the second parallel connection point of the third trimming unit 103 is connected to the reference voltage output end of the battery protection circuit, and the first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 is used as the output end of the trimmed reference voltage, and is connected to a voltage-dividing resistor string corresponding to the reference voltage in the battery protection circuit; or when applied to trimming a battery voltage in the battery protection circuit, the second parallel connection point of the third trimming unit 103 is connected to a battery voltage sampling point of the battery protection circuit, and the first parallel connection point of the first trimming unit 101 or the second trimming unit 102 or the third trimming unit 103 is used as the output end of the trimmed battery voltage, and is connected to a voltage-dividing resistor string corresponding to the battery voltage in the battery protection circuit.

[0073] It should be understood that the above Figure 3 This is only a schematic diagram of a trimming network provided for an embodiment of the present invention, and is not intended to limit the number of trimming units of the present invention. In practical applications, other numbers of trimming units may also be included.

[0074] Different from the conventional method of connecting a metal sheet in parallel with the trimming resistor, the embodiment of the present invention connects a transistor T in parallel with the trimming device R, so that the trimming device R can be connected to the trimming network or short-circuited by turning off or on the transistor T, thereby increasing the adjustment resistance or decreasing the signal to be trimmed, thereby realizing bidirectional adjustment of the signal to be trimmed.

[0075] Optionally, in one embodiment of the present invention, the trimming circuit may further include two or more trimming networks, each trimming network includes a plurality of trimming units, and a trimming point of each trimming unit is connected to an output end of the single-line communication circuit 30 .

[0076] For ease of understanding, Figure 4 Schematic diagrams of two adjustment networks provided in the embodiments of the present invention. The structure of the adjustment network is specifically shown in the above Figure 2 or Figure 3 The description of the corresponding embodiment is not repeated here. The second end of each trimming network is connected to different signals to be trimmed, so that one trimming circuit can trim multiple signals to be trimmed.

[0077] As mentioned above, in order to realize trimming after the chip packaging is completed, the embodiment of the present invention introduces a single-line communication circuit, inputs a clock signal to the single-line communication circuit 30, and the single-line communication circuit 30 generates a bit address according to the input clock signal, and then burns according to the bit address to change the access status of each trimming unit 101, so that the trimming unit 101 is connected to the trimming network or is short-circuited. Figure 5 Schematic diagram of a single-line communication circuit provided by an embodiment of the present invention. Figure 5 As shown, the single-line communication circuit 30 includes:

[0078] Delay circuit 31, timing circuit 32, data storage and output circuit 33, storage circuit 34;

[0079] The input end of the delay circuit 31, the input end of the timing circuit 32 and the first input end of the data storage and output circuit 33 are connected to the clock signal output end respectively;

[0080] The output end of the delay circuit 31 is connected to the second input end of the data storage and output circuit 33;

[0081] The output end of the timing circuit 32 is connected to the enable / reset end of the data storage and output circuit 33;

[0082] The output end of the data storage and output circuit 33 is connected to the input end of the storage circuit 34;

[0083] The storage circuit 34 includes a plurality of output terminals, each of which is connected to a trimming point of the trimming unit 101;

[0084] The timing circuit 32 is used to receive a clock signal, and enable the data storage and output circuit according to the rising edge of the clock signal, and reset the data storage and output circuit 33 when no rising edge is received within a preset time; the delay circuit 31 is used to receive a clock signal, generate adjustment information according to the pulse width length of the clock signal, and send the adjustment information to the data storage and output circuit 33; the data storage and output circuit 33 is used to receive and store the adjustment information according to the rising edge of the clock signal when enabled, convert the adjustment information into a bit address, and send the bit address to the storage circuit 34; the storage circuit 34 is used to burn according to the bit address to change the access status of the adjustment unit.

[0085] In an embodiment of the present invention, the data storage and output circuit 33 is enabled and reset by the timing circuit 32. The timing circuit 32 receives a clock signal. When the data storage and output circuit 33 is in a reset state, if the timing circuit 32 receives the rising edge of the clock signal, an enable signal is generated to the data storage and output circuit 33, such as a high level output, to enable the data storage and output circuit 33. When the data storage and output circuit 33 is in an enabled state, if the timing circuit 32 receives the rising edge of the clock signal within a preset time, the enable signal is kept output; otherwise, if the timing circuit 32 does not receive the rising edge of the clock signal within the preset time, a reset signal is output to the data storage and output circuit 33, such as a low level output, to reset the data storage and output circuit 33. Here, the embodiment of the present invention enables and resets the data storage and output circuit 33 through the timing circuit 32, thereby realizing the enabling control of the single-line communication circuit 30, and avoiding mistaken entry into the single-line communication circuit without adjustment. Optionally, the preset time is set according to actual application requirements, and is not limited here.

[0086] The delay circuit 31 is used to receive the clock signal and generate adjustment information according to the pulse width length of the clock signal. Specifically, when and only when the pulse width length of the clock signal is greater than or equal to the preset pulse width threshold, the delay circuit 31 outputs a pulse, and when the rising edge of the next clock signal arrives, the pulse output by the delay circuit 31 is collected through the data storage and output circuit 33, and after the data storage and output circuit 33 completes the collection, it is delayed for a certain time and then cleared; otherwise, a low level is output.

[0087] The data storage and output circuit 33 is used to receive and store the adjustment information according to the rising edge of the clock signal when enabled. Specifically, when the rising edge of the clock signal arrives, the data storage and output circuit 33 collects the signal output by the delay circuit 31. If the delay circuit 31 outputs a pulse at this time, data 1 is collected correspondingly. If the delay circuit 31 outputs a low level at this time, data 0 is collected correspondingly, and the adjustment information is finally obtained. The adjustment information is converted into a bit address, and the bit address is sent to the storage circuit 34.

[0088] After receiving the bit address, the storage circuit 34 burns the corresponding bit address to change the output state of the storage circuit output terminal. Here, regardless of whether there is a burning communication, the output of the storage circuit 34 is used to control the adjustment unit 101, but through burning, the output state of the storage circuit 34 will change, thereby changing the access state of the adjustment unit 101.

[0089] Optionally, as a preferred example of the present invention, in order to avoid mistakenly entering the single-line communication mode when no adjustment is required and mistakenly triggering the adjustment mode, the data storage and output circuit 33 in the embodiment of the present invention also controls the start of the adjustment mode through a counter circuit. Figure 6 As shown, the data storage and output circuit 33 also includes:

[0090] Counter circuit 331, shift register 332, decoder circuit 333;

[0091] The first input terminals of the counter circuit 331 and the shift register 332 are respectively connected to the clock signal output terminal, and the enable / reset terminals are respectively connected to the output terminal of the timing circuit 32;

[0092] The output end of the counter circuit 331 is connected to the enable end of the decoder circuit 333;

[0093] The second input terminal of the shift register 332 is connected to the output terminal of the delay circuit 31, and the output terminal is connected to the input terminal of the decoder circuit 333;

[0094] The output end of the decoder circuit 333 is connected to the input end of the storage circuit 34;

[0095] The counter circuit 331 is used to receive the clock signal and count the number of pulses, and generate an enable signal for the decoder circuit 333 when the number of pulses is greater than or equal to a preset number threshold;

[0096] The shift register 332 is used to collect the adjustment information output by the delay circuit 31 according to the clock signal, and send the adjustment information to the decoder circuit 333;

[0097] The decoder circuit 333 is used to receive the enable signal, and perform decoding processing on the adjustment information under the action of the enable signal to obtain a bit address, and send the bit address to the storage circuit 34.

[0098] Here, the embodiment of the present invention receives the clock signal and calculates the number of pulses through the counter circuit 331, and generates an enable signal for the decoder circuit 333 when and only when the number of pulses reaches a preset number threshold, so as to enable the decoder circuit 333 and enter the trimming mode; otherwise, when the number of pulses does not meet the preset number threshold, the decoder circuit 333 is not enabled, so that the trimming circuit does not enter the trimming mode, effectively avoiding further erroneous triggering of the trimming mode after mistakenly entering the single-line communication circuit 30 when no trimming is required, and realizing double protection against erroneous start of trimming. Optionally, the preset number threshold is set according to actual application requirements and is not limited here.

[0099] The shift register 332 enters the enabled state when receiving the enable signal output by the timing circuit 32, and collects the adjustment information output by the delay circuit 31 according to the clock signal in the enabled state. Specifically, when the rising edge of the clock signal arrives, the shift register 332 collects the output signal of the delay circuit 31. If the delay circuit 31 outputs a pulse at this time, the corresponding data 1 is collected. If the delay circuit 31 outputs a low level at this time, the corresponding data 0 is collected. The collected data is combined to obtain the adjustment information. Then the adjustment information is sent to the decoder circuit 333.

[0100] The decoder circuit 333 enters the enabled state when receiving the enable signal output by the counter circuit 331. Specifically, the decoder circuit 333 receives the trimming information, performs decoding processing on the trimming information to obtain the bit address, and sends the bit address to the storage circuit 34. When the decoder circuit 333 does not receive the enable signal, the decoder circuit 333 is not allowed to decode the output of the register 332.

[0101] The storage circuit 34 receives the bit address sent by the decoder circuit 333. When the storage circuit 34 is connected to a power supply voltage, such as a 7V voltage, the storage circuit 34 will program the trimming unit 101 connected to the output end according to the bit address, and control the transistor T connected in parallel with the trimming device R to be connected to the trimming network or short-circuited.

[0102] Optionally, for ease of understanding, Figure 7A timing diagram of each output signal in a single-line communication circuit provided in an embodiment of the present invention. Here, a 3-bit trimming bit, a bit address of 110, and a preset number threshold of 6 clks are taken as an example. When the first rising edge of the clock signal arrives, the timing circuit 32 outputs an enable signal to enable the counter circuit 331 and the shift register 332; when the sixth rising edge of the clock signal arrives, the counter circuit 331 enables the decoder circuit 333 because the preset number threshold is reached. Among them, in order to obtain the bit address 110, the first, second, third, and sixth pulses of the clock signal are set to narrow pulses, and the fourth and fifth pulses are set to wide pulses and the pulse width length is greater than the preset pulse width threshold. Then, the delay circuit 31 outputs a low level at the third pulse of the clock signal, and the shift register 332 collects the output signal of the delay circuit 31 when the fourth pulse arrives, obtains 0, and writes the trimming data data <0> The delay circuit 31 outputs a high level at the fourth pulse of the clock signal, and the shift register collects the output signal of the delay circuit 31 when the fifth rising edge of the clock signal arrives, and obtains 1, and writes the trimmed data data <1> The delay circuit 31 outputs a high level at the fifth pulse of the clock signal, and the shift register collects the output signal of the delay circuit 31 when the sixth rising edge of the clock signal arrives, and obtains 1, and writes the trimmed data data <2> Finally, the shift register combines the collected data to obtain the trimming data 110. After being decoded by the decoder circuit 333 to obtain the bit address, it is transmitted to the storage circuit 34. After the storage circuit 34 is connected to the power supply voltage 7V, the trimming device of the trimming network is connected or short-circuited according to the bit address.

[0103] Optionally, Figure 8 A schematic diagram of a battery protection circuit provided by an embodiment of the present invention. Figure 8 As shown, the battery protection circuit includes a reference circuit and a voltage detection circuit, and also includes the adjustment circuit 1 as described above, and at least one comparator 2;

[0104] The output end of the comparator 2 is used as the clock signal output end of the trimming circuit 1 and is connected to the input end of the single-line communication circuit 30 of the trimming circuit 1;

[0105] The trimming circuit 1 comprises at least one trimming network 10, wherein the second end of the trimming network 10 is connected to a reference voltage or a battery voltage, and the first end of the trimming network 10 is connected to a reference circuit or a voltage detection circuit of the battery protection circuit;

[0106] The comparator 2 is used to generate a pulse signal required by the single-wire communication circuit 30 .

[0107] Optionally, when the battery protection circuit includes one of a voltage overcharge comparator, a voltage overdischarge comparator, a short-circuit comparator, and an overcurrent comparator, or any combination thereof, the comparator 2 may adopt the voltage overcharge comparator, the voltage overdischarge comparator, the short-circuit comparator, or the overcurrent comparator. The adjustment circuit 1 is connected to the output end of the voltage overcharge comparator, the voltage overdischarge comparator, the short-circuit comparator, or the overcurrent comparator. In another embodiment, the comparator 2 may also adopt an independent comparator instead of the voltage overcharge comparator, the voltage overdischarge comparator, the short-circuit comparator, or the overcurrent comparator, which is not limited here.

[0108] In the case where adjustment is required, the comparator outputs a pulse signal by providing a preset signal threshold to the inverting input terminal of the comparator and providing an input signal higher or lower than the preset signal threshold to the non-inverting input terminal. For example, when the preset signal threshold is 4V, when the input signal provided to the non-inverting input terminal varies between 3V and 5V, if the input signal is <4V, the comparator output is low, and when the input signal is >4V, the comparator output is high, thereby realizing pulse signal output.

[0109] The structure and function of the adjustment network 10, the function of the storage circuit 34, and the structure and function of the single-line communication circuit 30 are the same as those of the above embodiment. Please refer to the description of the above embodiment for details, and they will not be repeated here.

[0110] Fig. 9 A schematic diagram of a battery protection circuit provided by another embodiment of the present invention. Fig. 9 As shown, the battery protection circuit includes a reference circuit and a voltage detection circuit, and also includes the adjustment circuit 1 as described above, and at least one comparator 2;

[0111] The output end of the comparator 2 is used as the clock signal output end of the trimming circuit 1 and is connected to the input end of the single-line communication circuit 30 of the trimming circuit 1;

[0112] The trimming circuit 1 includes at least two trimming networks 10; the second end of one of the trimming networks 10 is connected to the reference voltage, and the first end is connected to the reference circuit of the battery protection circuit; the second end of the other trimming network 10 is connected to the battery voltage, and the first end is connected to the voltage detection circuit of the battery protection circuit;

[0113] The comparator 2 is used to generate a pulse signal required by the single-wire communication circuit 30 .

[0114] The principle of the comparator 2 is described in detail in Figure 8The description of the corresponding embodiment is not repeated here. In this embodiment, the storage circuit 34 of the trimming circuit 1 can control two trimming networks 10 at the same time, wherein the second end of one trimming network 10 is connected to the reference voltage Vref to trim the reference circuit in the battery protection circuit; the second end of the other trimming network 10 is connected to the battery voltage VDD to trim the voltage detection circuit in the battery protection circuit.

[0115] The structure and function of the adjustment network 10, the function of the storage circuit 34, and the structure and function of the single-line communication circuit 30 are the same as those of the above embodiment. Please refer to the description of the above embodiment for details, and they will not be repeated here.

[0116] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A trimming circuit, characterized in that: include: A trimming network, wherein a first end of the trimming network serves as an output end of a trimmed signal, and a second end is connected to a signal to be trimmed, wherein the trimming network comprises a plurality of trimming units connected in series, and each of the trimming units comprises a trimming adjustment point; A single-line communication circuit, wherein the input end of the single-line communication circuit is connected to the clock signal output end, and includes a plurality of output ends, each of which is connected to a trimming adjustment point; The single-line communication circuit is used to generate a bit address according to an input clock signal, and to perform programming according to the bit address to change the access state of the trimming unit; Each of the trimming units includes a trimming device and a transistor connected in parallel; The gate of the transistor is connected to an output end of the single-line communication circuit as a trimming adjustment point of the trimming unit; The single-line communication circuit comprises: Delay circuit, timing circuit, data storage and output circuit, storage circuit; The input end of the delay circuit, the input end of the timing circuit and the first input end of the data storage and output circuit are respectively connected to the clock signal output end; The output end of the delay circuit is connected to the second input end of the data storage and output circuit; The output terminal of the timing circuit is connected to the enable / reset terminal of the data storage and output circuit; The output end of the data storage and output circuit is connected to the input end of the storage circuit; The storage circuit includes a plurality of output terminals, each of which is connected to a trimming point of a trimming unit; The timing circuit is used to receive a clock signal, and enable the data storage and output circuit according to the rising edge of the clock signal, and reset the data storage and output circuit when the rising edge is not received within a preset time; the delay circuit is used to receive a clock signal, generate adjustment information according to the pulse width length of the clock signal, and send the adjustment information to the data storage and output circuit; the data storage and output circuit is used to receive and store the adjustment information according to the rising edge of the clock signal when enabled, convert the adjustment information into a bit address, and send the bit address to the storage circuit; the storage circuit is used to burn according to the bit address to change the access status of the adjustment unit.

2. The trimming circuit according to claim 1, characterized in that: The transistor is a PMOS tube; A first parallel connection point between the source of the transistor and the first end of the trimming device is connected to a previous trimming unit, and a second parallel connection point between the drain of the transistor and the second end of the trimming device is connected to a subsequent trimming unit; The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

3. The trimming circuit according to claim 1, wherein: The transistor is an NMOS tube; A first parallel connection point between the drain of the transistor and the first end of the trimming device is connected to a previous trimming unit, and a second parallel connection point between the source of the transistor and the second end of the trimming device is connected to a subsequent trimming unit; The first parallel connection point of any trimming unit serves as the first end of the trimming network; the second parallel connection point of the last trimming unit serves as the second end of the trimming network to connect the signal to be trimmed.

4. The trimming circuit according to any one of claims 1 to 3, characterized in that: The trimming circuit includes two or more trimming networks, and the second end of each trimming network is connected to different signals to be trimmed.

5. The trimming circuit according to claim 1, wherein: The data storage and output circuit further includes: Counter circuits, shift registers, decoder circuits; The first input terminals of the counter circuit and the shift register are respectively connected to the clock signal output terminal, and the enable / reset terminals are respectively connected to the output terminal of the timing circuit; The output end of the counter circuit is connected to the enable end of the decoder circuit; The second input terminal of the shift register is connected to the output terminal of the delay circuit, and the output terminal is connected to the input terminal of the decoder circuit; The output end of the decoder circuit is connected to the input end of the storage circuit; The counter circuit is used to receive the clock signal and count the number of pulses, and to generate an enable signal for the decoder circuit when the number of pulses is greater than or equal to a preset number threshold; The shift register is used to collect the adjustment information output by the delay circuit according to the clock signal, and send the adjustment information to the decoder circuit; The decoder circuit is used to receive the enable signal, and perform decoding processing on the trimming information under the action of the enable signal to obtain a bit address, and send the bit address to the storage circuit.

6. A battery protection circuit, comprising a reference circuit and a voltage detection circuit, characterized in that: The battery protection circuit further comprises at least one comparator and a trimming circuit as claimed in any one of claims 1 to 5; The output end of the comparator is used as the clock signal output end of the trimming circuit and is connected to the input end of the single-line communication circuit of the trimming circuit; The trimming circuit comprises at least one trimming network, a second end of the trimming network is connected to a reference voltage or a battery voltage, and a first end is connected to a reference circuit or a voltage detection circuit of the battery protection circuit; The comparator is used to generate a pulse signal required by the single-wire communication circuit.

7. The battery protection circuit according to claim 6, characterized in that: The comparator is a voltage over-discharge comparator, a voltage over-charge comparator, a short-circuit comparator or an over-current comparator in a battery protection circuit.

8. A battery protection circuit, comprising a reference circuit and a voltage detection circuit, characterized in that: The battery protection circuit further comprises at least one comparator and a trimming circuit as claimed in any one of claims 1 to 5; The output end of the comparator is used as the clock signal output end of the trimming circuit and is connected to the input end of the single-line communication circuit of the trimming circuit; The trimming circuit includes at least two trimming networks; a second end of one of the trimming networks is connected to a reference voltage, and a first end is connected to a reference circuit of the battery protection circuit; a second end of another trimming network is connected to a battery voltage, and a first end is connected to a voltage detection circuit of the battery protection circuit; The comparator is used to generate a pulse signal required by the single-wire communication circuit.

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