Image sensor and method of operating the same

Abstract

An image sensor and an operating method of the image sensor are disclosed. The image sensor includes a pixel array and a row driver. The pixel array includes a first pixel and a second pixel. Each of the first pixel and the second pixel includes at least one photosensitive element and a switch element configured to transfer charge generated by the at least one photosensitive element to a floating diffusion node. The first pixel and the second pixel are connected to the same column line. The row driver is configured to provide a clamp control signal to the switch element in the first pixel. During a read cycle of the second pixel, the clamp control signal is changed from a first level to a second level less than the first level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0119775 filed on September 27, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an image sensor and an operating method thereof, and more particularly, to an image sensor that generates a pixel signal based on a plurality of pixels and an operating method thereof. Background Art

[0004] An image sensor is a device that detects and communicates information used to generate an image of an object. Some image sensors are capable of generating two-dimensional or three-dimensional images of an object. An image sensor can generate an image of an object using a photosensitive element that reacts according to the intensity of light reflected from the object. A complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photosensitive pixels. The charge from each pixel is converted into a voltage that represents the image of the object. Summary of the invention

[0005] At least one embodiment of the inventive concept provides an image sensor for preventing a pixel signal output from a pixel from being excessively reduced and a method of operating the same.

[0006] According to an exemplary embodiment of the present invention, an image sensor including a pixel array and a row driver is provided. The pixel array includes a first pixel and a second pixel. Each of the first pixel and the second pixel includes at least one photosensitive element and a switch element configured to transfer the charge generated by the at least one photosensitive element to a floating diffusion node. The first pixel and the second pixel are connected to the same column line. The row driver is configured to provide a clamp control signal to the switch element in the first pixel. During a read cycle of the second pixel, the clamp control signal is changed from a first level to a second level less than the first level.

[0007] According to an exemplary embodiment of the present invention, an image sensor is provided, which includes a pixel array, a row driver, a voltage generating circuit, a ramp signal generator, an analog-to-digital converter (ADC) and a timing generator. The pixel array includes a first pixel and a second pixel connected to the same column line. The row driver is configured to provide a control signal to the pixel array. The voltage generating circuit is configured to provide a driving voltage for driving the first and second pixels to the row driver. The ramp signal generator is configured to generate a ramp signal. The analog-to-digital converter (ADC) is configured to convert the pixel voltage received from the column line into a pixel data value based on the ramp signal. The timing generator is configured to control the row driver, the ramp signal generator and the ADC. The row driver sequentially applies a clamping control signal of a first level and a second level less than the first level to a switching element in the first pixel.

[0008] According to an exemplary embodiment of the inventive concept, there is provided an operating method of an image sensor including a pixel array including first and second pixels arranged in different rows and connected to the same column line. The operating method includes: resetting the pixel array; applying a clamp control signal reduced from a first level to a second level to the first pixel during a reset count period when performing a read operation on the second pixel; and applying a transmission control signal of an activation level to the second pixel during a signal transmission period after the reset count period. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 is a circuit diagram of a pixel array and an analog-to-digital converter (ADC) according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 is a graph showing a read operation performed on a pixel;

[0013] Figure 4 is a circuit diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept;

[0014] Figure 5A and Figure 5B is a timing diagram of signals for a pixel array in a read operation of an image sensor according to an exemplary embodiment of the inventive concept;

[0015] Figure 6 is the circuit diagram of a winner-takes-all circuit;

[0016] Fig. 7A , Figure 7B and Figure 7C is a block diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept;

[0017] Fig. 8A shows a pixel array according to an exemplary embodiment of the inventive concept;

[0018] Figure 8B is a block diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept;

[0019] Fig. 9 is a circuit diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept;

[0020] Fig. 10A shows a clamping level according to an exemplary embodiment of the inventive concept;

[0021] Fig. 10B is a circuit diagram of one example of a current source according to an exemplary embodiment of the inventive concept;

[0022] Fig.11 is a circuit diagram of an image sensor according to an exemplary embodiment of the inventive concept, and illustrates a read operation of the image sensor;

[0023] Fig.12 is Fig.11 A timing diagram of signals for a pixel array in a read operation of an image sensor;

[0024] Fig.13 is a flowchart of an operating method of an image sensor according to an exemplary embodiment of the inventive concept; and

[0025] Fig.14 is a block diagram of an image processing system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0026] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of an image sensor 100 according to an exemplary embodiment of the inventive concept.

[0028] The image sensor 100 may be included in an electronic device having an image or photo sensing function. For example, the image sensor 100 may be installed on an electronic device such as a camera, a smart phone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation machine, a drone, or an advanced driver assistance system (ADAS). In addition, the image sensor 100 may be installed on an electronic device included as a component in a vehicle, furniture, a manufacturing facility, a door, or various types of metering instruments.

[0029] Reference Figure 1 , the image sensor 100 includes a pixel array 110, a row driver 120 (e.g., a driver circuit), an analog-to-digital converter (ADC) 130 (e.g., an ADC converter circuit), a ramp signal generator 160, a timing generator 170 (e.g., a signal generator), and a buffer 180 (e.g., a buffer circuit). The ADC 130 includes a comparison block 140 (e.g., a comparison circuit) and a counter block 150 (e.g., a counter circuit).

[0030] The pixel array 110 includes a plurality of row lines ROW, a plurality of column lines COL, and a plurality of pixels 111 arranged in a matrix, and each pixel 111 is connected to the plurality of row lines ROW and column lines COL. Figure 1 The pixel array 110 is shown to include 16 pixels 111 arranged in 4 rows×4 columns, but this is for convenience of description, and the pixel array 110 may include a greater number of pixels.

[0031] Each of the plurality of row lines ROW extends in the row direction and may be connected to pixels arranged in the same row. For example, three row lines ROW may be connected to pixels 111 arranged in the same row, and the three row lines ROW may transmit control signals output from the row driver 120 to the pixels 111 and 112 of the same row, respectively. Figure 2 Each of the plurality of column lines COL extends in a column direction and may be connected to the pixels 111 arranged in the same column. Each of the plurality of column lines COL may output a pixel signal PXS to the ADC 130.

[0032] Each of the plurality of pixels 111 includes a photosensitive element (or a photoelectric conversion element). For example, the photosensitive element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode. Each of the plurality of pixels 111 may include at least one photosensitive element, and according to an embodiment of the inventive concept, each of the plurality of pixels 111 includes a plurality of photosensitive elements. The plurality of photosensitive elements may be arranged on the same layer or stacked in a vertical direction.

[0033] A microlens for gathering light may be arranged above each of the plurality of pixels 111 or above each of the plurality of pixel groups including adjacent pixels 111. Each of the plurality of pixels 111 may sense light of a specific spectral band from the light received through the microlens. For example, the pixel array 110 may include a red pixel configured to convert light of a red spectral band into an electrical signal, a green pixel configured to convert light of a green spectral band into an electrical signal, and a blue pixel configured to convert light of a blue spectral band into an electrical signal. A color filter for transmitting light of a specific spectral band may be arranged above each of the plurality of pixels 111. However, the pixel array 110 is not limited thereto, and the pixel array 110 may include pixels configured to convert light of different spectral bands other than red, green, and blue into electrical signals.

[0034] According to an exemplary embodiment of the inventive concept, the plurality of pixels 111 have a multilayer structure. The multilayer structured pixel 111 may include stacked photosensitive elements configured to convert light of different spectral bands into electrical signals corresponding to different colors, respectively. In other words, one pixel 111 may output electrical signals corresponding to a plurality of colors.

[0035] The plurality of pixels 111 may sense light by using a photosensitive element and convert the sensed light into a pixel signal PXS (e.g., a pixel voltage) as an electrical signal. For example, when bright light is applied, the plurality of pixels 111 may emit a large amount of electrons (photocharges). The brighter the light, the smaller the voltage value output from the photosensitive element. When the output voltage value is too low, various types of noise including band noise may occur.

[0036] The row driver 120 may select at least one row line ROW of the pixel array 110 according to a control signal (e.g., a row address signal) received from the timing generator 170. The pixel 111 connected to the selected at least one row line ROW may output a pixel signal PXS. For example, the pixel signal PXS may have any one of a voltage corresponding to a reset state, a voltage corresponding to a photocharge, and a clamp voltage.

[0037] The row driver 120 can drive the pixel array 110 in units of rows and control the read operation of the pixel 111. Hereinafter, the read operation may indicate an operation of resetting a pixel and outputting a pixel signal PXS with an amplitude corresponding to the amount of photocharge from the pixel. The row driver 120 can control the read operation of the pixel array 110 by outputting a control signal to a plurality of pixels 111 via a plurality of row lines ROW. The selected row for performing the read operation is referred to as a read row, and the other rows are referred to as unread rows. The pixel for performing the read operation is referred to as a read pixel, and the other pixels are referred to as unread pixels.

[0038] According to an exemplary embodiment of the present embodiment, when a read operation is performed on the pixels 111 of the read row, the row driver 120 controls the pixels 111 of the adjacent unread row to operate as a clamp circuit. The clamp circuit prevents the voltage of the column line COL (i.e., the level of the pixel signal PXS (e.g., pixel voltage)) from being less than a specific level. For example, when a read operation is performed on the pixels 111 of the third row among the first to fourth rows in the pixel array 111, the row driver 120 controls the pixels 111 of the adjacent unread row (e.g., the second row) to operate as a clamp circuit. According to an exemplary embodiment of the inventive concept, the pixels 111 of the row or dummy row to which the read operation has ended within one frame period are operated as a clamp circuit. Hereinafter, in at least one embodiment of the inventive concept, the pixels operating as a clamp circuit are referred to as clamp pixels, and the rows including the clamp pixels are referred to as clamp rows.

[0039] According to an embodiment of the inventive concept, the row driver 120 provides a clamp control signal to the pixels 111 of the unread row. The row driver 120 may provide the clamp control signal through the row line ROW connected to the pixels 111 of the unread row. In an exemplary embodiment, the clamp control signal is changed from a first level to another second level at a time point when a read operation is performed on the pixels 111 of the read row. In an exemplary embodiment, the second level is less than the first level, and the clamp control signal is changed from the first level to the second level during a reset count period or before a charge transfer period among a plurality of sub-periods in a read period.

[0040] When a read operation is performed on the pixels 111 of the read row, the row driver 120 provides a transfer control signal to each of the pixels 111 of the read row through the row line ROW connected to the pixels 111 of the read row, and provides a clamping control signal to each of the pixels 111 of the adjacent unread row through the row line ROW connected to the pixels 111 of the unread row.

[0041] According to an exemplary embodiment of the inventive concept, a transfer control signal and a clamp control signal are input to a driving terminal (e.g., a gate terminal of a transfer transistor) of a charge transfer element included in each pixel 111. For example, a transfer control signal may be input to a gate terminal of a transfer transistor included in a pixel 111 of a read row, and a clamp control signal may be input to a gate terminal of a transfer transistor included in a pixel 111 of at least one unread row adjacent to the read row.

[0042] In an exemplary embodiment, the ramp signal generator 160 generates a ramp signal RAMP. The ramp signal RAMP may be a signal having a voltage that increases according to a constant slope or gradient. The ramp signal generator 160 may operate based on a ramp control signal provided from the timing generator 170. The ramp control signal may include at least one of a ramp enable signal and a mode signal. When the ramp enable signal is activated, the ramp signal generator 160 may generate a ramp signal having a gradient set based on the mode signal.

[0043] The ADC 130 converts the pixel signal PXS (i.e., analog signal) received from the pixel array 110 into a digital signal. For example, the ADC 130 may generate a comparison result by comparing the pixel signal PXS with the ramp signal RAMP so as to effectively detect the difference between the reset signal and the image signal. The ADC 130 may count the signal output as the comparison result to convert the pixel signal PXS into a digital signal.

[0044] The comparison block 140 may include a plurality of comparison circuits (COMP) 141 , and each of the plurality of comparison circuits 141 may compare the ramp signal RAMP with the pixel signal PXS received through the corresponding column line COL to output a comparison result.

[0045] The comparison circuit 141 may generate a comparison result signal to which a correlated double sampling scheme is applied, and may be referred to as a correlated double sampling circuit. The pixel signal PXS output from the plurality of pixels 111 may have a deviation caused by a unique characteristic of each pixel (e.g., fixed pattern noise (FPN) etc.) and / or a deviation caused by a characteristic difference in the logic used to output the pixel signal PXS from the pixel 111. Obtaining the reset component (or reset signal) and the image component (or image signal) of each pixel signal and extracting the difference therebetween as an effective signal component to compensate for these deviations between the pixel signals PXS is referred to as correlated double sampling. The comparison circuit 141 may output a comparison result signal to which a correlated double sampling scheme is applied.

[0046] The counter block 150 may include a plurality of counters (CNT) 151 (e.g., counting circuits). The plurality of counters 151 may be connected to the output terminals of the comparison circuit 141 to count based on the outputs of the comparison circuit 141, respectively. The counter control signal received from the timing generator 170 may include at least one of a counter clock signal, a counter reset signal for controlling a reset operation of the plurality of counters 151, and an inversion signal for inverting an internal bit of each of the plurality of counters 151. The counter block 150 may output a digital signal by counting the comparison result signal according to the counter clock signal.

[0047] The buffer 180 may include a column memory block 181 and a sense amplifier 182, and the column memory block 181 may include a plurality of memories 183. The plurality of memories 183 may respectively temporarily store digital signals (e.g., pixel data) output from the plurality of counters 151 and then output the stored digital signals to the sense amplifier 182. The sense amplifier 182 may sense and amplify the digital signals output from the plurality of memories 183. The sense amplifier 182 may output the amplified digital signals as image data IDTA.

[0048] The timing generator 170 may generally control the image sensor 100. For example, the timing generator 170 may control the operation or timing of the row driver 120 and the ADC 130 by transmitting a control signal or a clock signal to each of the row driver 120 and the ADC 130.

[0049] When too much light is applied to the pixel array 110, so that the output value of the pixel 111 (i.e., the level of the pixel signal PXS) is too low, the current source that draws current from the column line COL to which the pixel 111 is connected is turned off. When multiple current sources in the same row are turned off, changes in current consumption and the resulting changes in the power supply voltage may occur, resulting in band noise. However, as described above, in the image sensor 100 according to an exemplary embodiment of the present invention, the row driver 120 operates the pixels of the unread row as a clamp circuit to prevent the level of the pixel signal PXS from being too low. Therefore, the image sensor 100 according to an exemplary embodiment of the present invention can suppress the occurrence of band noise.

[0050] In addition, since the row driver 120 may use pixels of at least one unread row as clamp pixels when performing a read operation on read pixels without additional wiring or circuits on the pixel array 10, no additional circuit area or power consumption is required.

[0051] Figure 2 is a circuit diagram of a pixel array 110 and an ADC 130 according to an exemplary embodiment of the inventive concept.

[0052] Reference Figure 2 , the pixel array 110 includes a first pixel PX1 and a second pixel PX2 connected to the same column line COL. The first pixel PX1 and the second pixel PX2 are located in different rows. For example, the first pixel PX1 and the second pixel PX2 may be located in adjacent rows. However, the first pixel PX1 and the second pixel PX2 are not limited thereto, and at least one other pixel may be located between the first pixel PX1 and the second pixel PX2. Although for the convenience of description, Figure 2 Each row is shown to include only one pixel, but Figure 1As shown, each row may include a plurality of other pixels. The pixel array 110 operates in units of rows, and thus, the operations of the plurality of other pixels may be similar to the operations of the first pixel PX1 and the second pixel PX2.

[0053] Reference Figure 2 , the first pixel PX1 and the second pixel PX2 include reset transistors RX1 and RX2, transfer transistors TX1 and TX2, drive transistors DX1 and DX2, selection transistors SX1 and SX2, and photodiodes PD1 and PD2, respectively. The reset transistors RX1 and RX2, the transfer transistors TX1 and TX2, and the selection transistors SX1 and SX2 can be turned on or off in response to the received control signal, and thus can be operated as switching elements. The photodiodes PD1 and PD2 can be replaced by other photosensitive elements. The control signal can be transmitted through a plurality of row lines ( Figure 1 ROW) is transmitted to the reset transistors RX1 and RX2, the transfer transistors TX1 and TX2, and the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2, and in this case, the plurality of row lines ROW may extend in the row direction on the pixel array 110 and may be connected to the pixels arranged in the same row.

[0054] The operation of the first pixel PX1 and the second pixel PX2 is described based on the first pixel PX1 as an example. When the read operation of the first pixel PX1 is performed, the photodiode PD1 variably generates photocharge according to the intensity of incident light. The transfer transistor TX1 generates photocharge according to the intensity of the incident light from the row driver ( Figure 1 The transmission control signal TG1 output by the row driver 120 transmits the photocharge to the floating diffusion node FD1. For example, the transmission control signal TG1 is applied to the gate terminal of the transmission transistor TX1. According to the potential of the photocharge accumulated in the floating diffusion node FD1, the driving transistor DX1 can amplify the photocharge and transmit the amplified photocharge to the selection transistor SX1. For example, the gate terminal of the driving transistor DX1 can receive a signal having a voltage corresponding to the potential from the diffusion node FD1. When the drain terminal of the selection transistor SX1 is connected to the source terminal of the driving transistor DX1 and the selection transistor SX1 is turned on in response to the selection signal SEL1 output from the row driver 120, the output signal Vout corresponding to the voltage level of the floating diffusion node FD1 can be output to the column line COL connected to the first pixel PX1. For example, the selection signal SEL1 can be output to the gate terminal of the selection transistor SX1. The reset transistor RX1 can reset the floating diffusion node FD1 based on the power supply voltage VDD according to the reset signal RS1 provided from the row driver 120. For example, the reset signal RS1 may be applied to the gate terminal of the reset transistor RX1 to apply the power supply voltage VDD to the floating diffusion node FD1 .

[0055] When the row where the second pixel PX2 is disposed is a read row, the row where the first pixel PX1 is disposed is an unread row, and the first pixel PX1 operates as a clamp pixel of the second pixel PX2, the clamp control signal ( Figure 4 The clamp control signal CG) is applied to the transfer transistor TX1, and the voltage level of the floating diffusion node FD1 in the first pixel PX1 may change in response to the clamp control signal CG. For example, the clamp control signal may be applied to the gate terminal of the transfer transistor TX1. In this case, the voltage level of the floating diffusion node FD1 is independent of the photocharge generated by the photodiode PD1 and may be determined based on the change in the level (voltage level) of the clamp control signal CG. The selection transistor SX1 may output an output signal Vout having a level corresponding to the voltage level of the floating diffusion node FD1 in response to the selection signal SEL1.

[0056] The current source PL is connected to one end of the column line COL, and the current source PL can draw a load current I from the column line COL. L The current source PL may be referred to as a pixel load. In an exemplary embodiment, the current source PL is implemented by an electronic circuit that sinks current independently of the voltage across the current source.

[0057] The pixel signal PXS output from the first pixel PX1 or the second pixel PX2 may be provided to the ADC 130 through the column line COL. The ADC 130 includes a comparison circuit 141 (eg, an operational amplifier) ​​and a counter 151 (eg, a counting circuit). Although for convenience of description, Figure 2 A comparison circuit 141 and a counter 151 are shown connected to one column line COL, but as shown in FIG. Figure 1 As described above, the ADC 130 may include a plurality of comparison circuits 141 and a plurality of counters 151 connected to the plurality of column lines COL.

[0058] The comparison circuit 141 may be implemented using at least one comparator. For example, the comparator may include a differential amplifier, an operational transconductance amplifier (OTA), or a source follower. According to an embodiment of the inventive concept, a capacitor is connected to two input terminals of the comparison circuit 141. The comparison circuit 141 may compare the received pixel signal PXS with the ramp signal RAMP to generate a comparison result and output the comparison result. The counter 151 may count the output Vcomp of the comparison circuit 141 based on the counting clock signal CCLK and the inverting signal CONV to generate a counting result, and output the counting result as the pixel data PXD. The pixel data PXD may have an image component with a reset component removed from the pixel signal PXS, that is, a digital value corresponding to the image signal.

[0059] Figure 3 is a graph showing a read operation performed on a pixel.

[0060] Figure 3 The selection signal SEL, reset signal RS, and transfer control signal TG shown are control signals applied to the pixel on which the read operation is performed. Figure 2 The read operation is performed on the first pixel PX1.

[0061] Reference Figure 2 and Figure 3 , before the time point t0, a high level reset signal RS is applied to the reset transistor RX1, and the floating diffusion node FD1 is reset based on the power supply voltage VDD. For example, the voltage level of the floating diffusion node FD1 may be the same as that of the power supply voltage VDD.

[0062] The read operation is performed from time point t0 to time point t10. When the read operation is performed, the selection signal SEL maintains a high level to turn on the selection transistor SX1, and the reset signal RS maintains a low level to turn off the reset transistor RX1.

[0063] The period between the time point t0 and the time point t1 may be referred to as an auto-zero period, and the period between the time point t1 and the time point t10 may be referred to as a comparison operation period. The auto-zero signal AZS is activated from the time point t0 to the time point t1, and the comparison circuit 141 may be initialized in response to the auto-zero signal AZS. For example, the input terminal and / or the output terminal of the comparator included in the comparison circuit 141 may have the same level. In order to reset the count (for example, to count the reset signal of the pixel PX1), an offset may be applied to the ramp signal RAMP at the time point t2, and then the ramp signal RAMP may be reduced from the time point t3. From the time point t3 to the time point t4 when the polarity of the output Vcomp of the comparison circuit 141 changes, the counter 151 may count the output Vcomp based on the count clock signal CCLK. From the time point t3 to the time point t4, the count value CV may increase.

[0064] When the reset count ends, for signal counting (e.g., counting the image signal of the pixel PX1), an offset may be applied to the ramp signal RAMP again at time point t5, and then at time point t6, the bit of the count value CV may be inverted in response to the inversion signal CONV. At time point t7, the transfer control signal TG may be turned into a high level, and the transfer transistor TX1 may be turned on in response to the transfer control signal TG to transfer the photocharge accumulated in the photodiode PD1 to the floating diffusion node FD1. Therefore, the pixel signal PXS indicating the voltage level of the floating diffusion node FD1 may decrease.

[0065] From time point t8, the ramp signal RAMP decreases. Since the voltage level of the ramp signal RAMP is the same as the voltage level of the pixel signal PXS, from time point t8 to time point t9 when the polarity of the output Vcomp of the comparison circuit 141 changes, the counter 151 can count the output Vcomp based on the count clock signal CCLK. The count value CV can be output as the pixel data PXD. When the signal counting ends, the ADC 130 can be initialized.

[0066] Although an example in which a digital correlated double sampling scheme is applied to the ADC 130 is described in the present inventive concept, the present inventive concept is not limited thereto, and an analog correlated double sampling scheme may be applied to the ADC 130 .

[0067] Figure 4 is a circuit diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept. Figure 5A and Figure 5B is a timing diagram of signals for a pixel array in a read operation of an image sensor according to an exemplary embodiment of the inventive concept.

[0068] Reference Figure 4 , the first pixel PX1 and the second pixel PX2 may be arranged in different rows and connected to the same column COL. A read operation on the second pixel PX2 may be performed, and in this case, as described above with reference to Figure 1 As described, the first pixel PX1 in the row adjacent to the row in which the second pixel PX2 is arranged operates as a clamp pixel. In this case, the first pixel PX1 may be a pixel whose reading operation has ended or a dummy pixel.

[0069] The row driver 120 may provide control signals to the first pixel PX1 and the second pixel PX2 through a plurality of row lines. For example, the row driver 120 may provide selection signals SEL1 and SEL2 and reset signals RS1 and RS2 to each of the first pixel PX1 and the second pixel PX2. Herein, the same selection signal SEL and the same reset signal RS may be provided to the first pixel PX1 and the second pixel PX2. The row driver 120 may provide a transmission control signal TG to the second pixel PX2 and a clamp control signal CG to the first pixel PX1.

[0070] The row driver 120 may include a first transmission driver TXD1 and a second transmission driver TXD2. The first transmission driver TXD1 and the second transmission driver TXD2 may be implemented using an amplifier, a buffer, or an inverter.

[0071] The first transmission driver TXD1 generates a clamp control signal CG and transmits the clamp control signal CG to the first pixel PX1. The first transmission driver TXD1 can generate a clamp control signal CG by clamping the reference signal SCLP The clamp control signal CG is generated by buffering or level conversion.

[0072] The second transmission driver TXD2 generates a transmission control signal TG and transmits the transmission control signal TG to the second pixel PX2. TX The transmission control signal TG is generated by buffering or level conversion.

[0073] Although for the sake of convenience, Figure 4 The row driver 120 is shown to include a first transmission driver TXD1 and a second transmission driver TXD2 , but the row driver 120 is not limited thereto and may further include other transmission drivers for transmitting the selection signal SEL and the reset signal RS to the first pixel PX1 and the second pixel PX2 .

[0074] Reference Figure 5A and Figure 5B The read cycle HP of one row may include an auto-zero cycle, a reset count cycle, a signal transmission cycle, and a signal count cycle.

[0075] In the initial stage of the read cycle HP, the reset transistors RX1 and RX2 are turned on in response to the reset signal RS of the activation level (e.g., high level), so that the power supply voltage VDD is applied to the floating diffusion nodes FD1 and FD2 of the first pixel PX1 and the second pixel PX2. Therefore, the voltages VFD1 and VFD2 of the floating diffusion nodes FD1 and FD2 (hereinafter, referred to as floating diffusion node voltages) may be the same as the power supply voltage VDD. Thereafter, the reset signal RS is changed to a deactivation level (e.g., low level), and the selection signal SEL is changed to an activation level (e.g., high level). In this case, the clamp control signal CG has a high level (e.g., a first voltage level V1), and then the clamp control signal CG is changed to a low level (e.g., a second voltage level V2).

[0076] A parasitic capacitor C may be formed at the floating diffusion node FD1 in the first pixel PX1. FD , and a coupling capacitor C may be formed between the floating diffusion node FD1 and the gate terminal of the transfer transistor TX1 C When the clamp control signal CG applied to the gate terminal of the transmission transistor TX1 changes from a high level to a low level, the floating diffusion node voltage VFD1 may be increased due to the coupling capacitor C CIn this case, the floating diffusion node voltage VFD1 may be determined based on the voltage change of the clamp control signal CG. The voltage change ΔVFD1 of the floating diffusion node voltage VFD1 may be proportional to the voltage change ΔVCLP of the clamp control signal CG (e.g., the difference between the first voltage level V1 and the second voltage level V2), and may be determined by the parasitic capacitance C FD and coupling capacitor C C The voltage change △VFD1 of the floating diffusion node voltage VFD1 can be expressed by mathematical formula 1.

[0077]

[0078] Therefore, the larger the voltage change ΔVCLP of the clamp control signal CG is, the smaller the floating diffusion node voltage VFD1 is.

[0079] In the signal transmission period, the transmission control signal TG has an activation level (e.g., a high level), and the transmission transistor TX2 of the second pixel PX2 is turned on in response to the transmission control signal TG to transmit the photocharge generated by the photodiode PD2 to the floating diffusion node FD2. Therefore, the floating diffusion node voltage VFD2 of the second pixel PX2 can be reduced. Since both the selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2 are turned on, the floating diffusion node voltages VFD1 and VFD2 of the first pixel PX1 and the second pixel PX2 can be output through the column line COL. In this case, the output voltage Vout of the column line COL can be determined based on the higher voltage between the floating diffusion node voltages VFD1 and VFD2, that is, the pixel signal ( Figure 2 This refers to Figure 6 to describe.

[0080] Figure 6 It is the circuit diagram of the winner-takes-all circuit.

[0081] Reference Figure 6 , the two transistors shown (e.g., the first transistor TR1 and the second transistor TR2) may correspond to the driving transistor DX included in the pixel according to an embodiment of the inventive concept. For example, the first transistor TR1 and the second transistor TR2 may correspond to the first driving transistor DX1 included in the first pixel PX1 and the second driving transistor DX2 included in the second pixel PX2, respectively. Hereinafter, for convenience of description, it is assumed that the first transistor TR and the second transistor TR2 are implemented using negative channel metal oxide semiconductor (NMOS) transistors.

[0082] When the first gate voltage VG1 is greater than the second gate voltage VG2, the voltage applied to the common node CN is the same as the value obtained by subtracting the gate-source voltage Vgs from the first gate voltage VG1. That is, VG1-Vgs=VCN. In addition, when the first gate voltage VG1 is greater than the second gate voltage VG2, the bias current Io can be a value based on the first current I1 and has nothing to do with the second current I2. Therefore, only transistors with a larger gate voltage level can operate, while transistors with a lower gate voltage level do not operate. A circuit that operates in this manner may be referred to as a winner-takes-all circuit. For example, referring to Figure 6 and Figure 4 ,right Figure 6 The principle of applying voltage to the common node CN in Figure 4 The principle of applying voltage to the column line COL in is similar. In this case, Figure 6 The first gate voltage VG1 and the second gate voltage VG2 may correspond to Figure 4 Therefore, a higher voltage between the floating diffusion node voltages VFD1 and VFD2 may be output through the column line COL. The output voltage Vout of the column line COL may correspond to a higher voltage between the floating diffusion node voltages VFD1 and VFD2.

[0083] Reference Figure 5A and Figure 5B Before the signal transmission period, since the floating diffusion node voltage VFD1 of the first pixel PX1 is less than or equal to the floating diffusion node voltage VFD2 of the second pixel PX2, the floating diffusion node voltage VFD2 of the second pixel PX2 may be output as the output voltage Vout.

[0084] Afterwards, if Figure 5A As shown, when the floating diffusion node voltage VFD1 of the first pixel PX1 is greater than the floating diffusion node voltage VFD2 of the second pixel PX2 in the signal counting period due to the excessive decrease (e.g., close to 0V) of the floating diffusion node voltage VFD2 of the second pixel PX2 in the signal transmission period, the floating diffusion node voltage VFD1 of the first pixel PX1 may be output as the output voltage Vout. Therefore, the output voltage Vout may be prevented from being excessively decreased.

[0085] On the contrary, Figure 5B As shown, when the floating diffusion node voltage VFD2 of the second pixel PX2 is greater than the floating diffusion node voltage VFD1 of the first pixel PX1 in the signal counting period, the floating diffusion node voltage VFD2 of the second pixel PX2 may be output as the output voltage Vout.

[0086] The floating diffusion node voltage VFD1 of the first pixel PX1 may be smaller than the comparison circuit ( Figure 2 Therefore, when the floating diffusion node voltage VFD2 of the second pixel PX2 is in the comparison circuit ( Figure 2 141) within the input range (for example, Figure 5B ), the floating diffusion node voltage VFD2 of the second pixel PX2 can be provided to the comparison circuit ( Figure 2 141), so that the pixel data value of the second pixel PX2 can be read.

[0087] When the floating diffusion node voltage VFD2 of the second pixel PX2 is excessively reduced and the comparison circuit ( Figure 2 When the current source ( Figure 2 When the floating diffusion node voltage VFD2 of the second pixel PX2 cannot operate normally due to the floating diffusion node voltage VFD2 of the second pixel PX2, band noise may occur. However, as described above, even when the floating diffusion node voltage VFD2 of the second pixel PX2 is excessively reduced, the first pixel PX1 operates as a clamp circuit (for example, Figure 5A ), thus, the output voltage Vout can be prevented from being excessively reduced. Therefore, the occurrence of noise can be prevented. The lower limit value of the output voltage Vout may be referred to as a clamping level, and the clamping level may be determined by the floating diffusion node voltage VFD1 of the first pixel PX1.

[0088] As described above, the image sensor according to the exemplary embodiment of the inventive concept provides a clamp control signal to each pixel in an adjacent unread row, specifically, to the gate terminal of a transfer transistor included in each pixel in the unread row, when performing a read operation on a read pixel in a read row, thereby using the pixels in the unread row as a clamp circuit. Therefore, by using the pixels in the adjacent unread row as a clamp circuit without additional wiring or circuit, the occurrence of noise can be suppressed without requiring an additional circuit area or increasing power consumption.

[0089] Fig. 7A , Figure 7B and Figure 7C is a block diagram illustrating a reading operation of an image sensor according to an exemplary embodiment of the inventive concept. Fig. 7A , Figure 7B and Figure 7C It is assumed that the nth row Rn is the read row. Although Fig. 7A , Figure 7B and Figure 7C It is shown that one pixel is arranged in each of the rows Rn-2 to Rn+2, but this is for convenience of description. Figure 1As shown, a plurality of pixels may be arranged in each of the rows Rn-2 to Rn+2, and the same control signal may be applied to the plurality of pixels arranged in the same row.

[0090] Reference Fig. 7A , Figure 7B and Figure 7C When a read operation is performed on pixels of a read row (i.e., the nth row Rn), pixels connected to the same column line COL as the line to which the read pixels are connected and arranged in an unread row operate as clamped pixels. According to an exemplary embodiment of the inventive concept, the clamped row may be a row for which the read operation has ended.

[0091] Reference Fig. 7A , the unread row that is most adjacent to the read row can be operated as the clamp row. For example, when the nth row Rn is the read row, the n-1th row Rn-1 for which the read operation has been completed among the unread rows that are most adjacent to the nth row Rn can be operated as the clamp row.

[0092] The nth transmission driver TXDn included in the row driver 120 may transmit the transmission control signal TG to the pixels PX in the nth row Rn, and the n-1th transmission driver TXDn-1 may transmit the clamp control signal CG to the pixels PX in the n-1th row Rn-1. Figure 5A and Figure 5B As described, the clamp control signal CG may transition from a high level to a low level before the signal transmission period, and the transmission control signal TG may have a high level in the signal transmission period of the read period HP and have a low level in the remaining period of the read period HP.

[0093] Reference Figure 7B , at least one of the unread rows adjacent to the read row can be operated as a clamp row. According to an embodiment of the present invention, Figure 7B As shown, the unread row is arranged between the read row and the clamp row. For example, when the nth row Rn is the read row, the n-2th row Rn-2 can be operated as the clamp row.

[0094] The nth transmission driver TXDn included in the row driver 120 may transmit the transmission control signal TG to the pixels PX in the nth row Rn, and the n-2th transmission driver TXDn-2 may transmit the clamp control signal CG to the pixels PX in the n-2th row Rn-2.

[0095] Reference Figure 7C , a plurality of unread rows are operated as clamp rows. For example, the n-2th row Rn-2 and the n-1th row Rn-1 before the nth row Rn as the read row are operated as clamp rows. However, the present embodiment is not limited thereto, and three or more rows may be operated as clamp rows.

[0096] The nth transmission driver TXDn included in the row driver 120 may transmit the transmission control signal TG to the pixels PX in the nth row Rn, and the n-2th transmission driver TXDn-2 and the n-1th transmission driver TXDn-1 may transmit the clamping control signal CG to the pixels PX in the n-2th row Rn-2 and the n-1th row Rn-1, respectively.

[0097] Fig. 8A 1 shows a pixel array 110a according to an exemplary embodiment of the inventive concept. Figure 8B is a block diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept.

[0098] Reference Fig. 8A , the pixel array 110a includes a valid pixel area VPA and an invalid pixel area NVPA. Each of the valid pixel area VPA and the invalid pixel area NVPA may include a plurality of rows. Fig. 8A The invalid pixel area NVPA is shown to be located at the top and bottom of the pixel array 110a, but the invalid pixel area NVPA is not limited thereto, and the invalid pixel area NVPA may be arranged at the top or bottom of the pixel array 110a or between a plurality of valid pixel areas VPA.

[0099] The image sensor may generate image data based on pixel signals output from pixels in the effective pixel area VPA. Pixel signals output from pixels in the invalid pixel area NVPA may be used for various purposes such as characteristic analysis, noise elimination, and data correction.

[0100] Reference Figure 8B , a row (e.g., a dummy row Rdm) in the invalid pixel area NVPA may be used as a clamping row. When a read operation is performed on the pixels PX in the nth row, the dummy row Rdm may be used as a clamping row. In addition, when a read operation is performed on each of the other rows (e.g., the n-1th row, the n+1th row, and the n+2th row) in the valid pixel area VPA, at least one dummy row Rdm may be used as a clamping row.

[0101] According to an exemplary embodiment of the present inventive concept, Fig. 8A As shown, the invalid pixel area NVPA may be located at the top and bottom of the pixel array 110a, and when a read operation of a row in the valid pixel area VPA is performed, a dummy row Rdm most adjacent to the read row among a plurality of dummy rows Rdm included in the invalid pixel area NVPA at the top and bottom of the pixel array 110a may be operated as a clamp row. The dummy row Rdm includes a dummy pixel PXdm. In an exemplary embodiment, the dummy pixel PXdm does not output a PXS signal.

[0102] Fig. 9 is a circuit diagram illustrating a read operation of an image sensor according to an exemplary embodiment of the inventive concept.

[0103] Reference Fig. 9 , when performing a read operation on the second pixel PX2, the first pixel PX1 operates as a clamp circuit. The first transmission driver TXD1 included in the row driver 120 may transmit the clamp control signal CG to the first pixel PX1. In this case, the first transmission driver TXD1 may be based on the first clamp voltage VH CLP and the second clamping voltage VL CLP The first clamping voltage VH CLP Greater than the second clamping voltage VL CLP The first transmission driver TXD1 can be configured to provide a first clamp voltage VH based on the first clamp voltage VH. CLP Or the second clamping voltage VL CLP Amplify (buffer or level shift) the clamped reference signal S CLP Therefore, the high level of the clamp control signal CG can be connected to the first clamp voltage VH CLP The voltage level of the clamping control signal CG may be the same as or similar to the voltage level of the second clamping voltage VL. CLP The voltage levels are the same or similar.

[0104] The second transmission driver TXD2 may be configured based on the first transmission voltage VH TX and the second transmission voltage VL TX The first transmission voltage VH TX Greater than the second transmission voltage VL TX The second transmission driver TXD2 can be driven by a first transmission voltage VH TX or the second transmission voltage VL TX To amplify (buffer or level shift) the transmission reference signal S TX Therefore, the high level of the transmission control signal TG can be consistent with the first transmission voltage VH TX The voltage level of the transmission control signal TG may be the same as or similar to the voltage level of the second transmission voltage VL. TX The voltage levels are the same or similar.

[0105] When performing a read operation on the first pixel PX1, the first transmission driver TXD1 generates a signal based on the first transmission voltage VH TX and the second transmission voltage VL TX To generate a transmission control signal TG and transmit the transmission control signal TG to the first pixel PX1. In addition, when the second pixel PX2 operates as a clamping pixel, the second transmission driver TXD2 generates a transmission control signal TG based on the first clamping voltage VH. CLPand the second clamping voltage VL CLP To generate a clamp control signal CG and transmit the clamp control signal CG to the second pixel PX2.

[0106] According to an embodiment of the inventive concept, the image sensor includes the voltage generator 190, and the voltage generator 190 generates the first clamping voltage VH CLP , the second clamping voltage VL CLP , the first transmission voltage VH TX and the second transmission voltage VL TX The first clamping voltage VH CLP , the second clamping voltage VL CLP , the first transmission voltage VH TX and the second transmission voltage VL TX Provided to the row driver 120. The voltage generator 190 can generate the first clamping voltage VH at a preset level based on the received voltage control signal CLP , the second clamping voltage VL CLP , the first transmission voltage VH TX and the second transmission voltage VL TX Or the first clamping voltage VH can be variably changed CLP , the second clamping voltage VL CLP , the first transmission voltage VH TX and the second transmission voltage VL TX voltage level.

[0107] According to an embodiment of the inventive concept, the first clamping voltage VH CLP The first transmission voltage VH TX The same, and the second clamping voltage VL CLP and the second transmission voltage VL TX For example, the first clamping voltage VH CLP and the first transmission voltage VH TX It can be the analog power supply voltage of the image sensor, the second clamping voltage VL CLP and the second transmission voltage VL TX It can be ground voltage.

[0108] According to another embodiment of the inventive concept, the first clamping voltage VH CLP Different from the first transmission voltage VH TX , and the second clamping voltage VL CLP Different from the second transmission voltage VL TX .

[0109] The first clamping voltage VH CLP and the second clamping voltage VL CLPThe voltage difference between VFD1 and VFD2 may correspond to the voltage change ΔVCLP of the clamp control signal CG, and as described with reference to Mathematical Formula 1, the voltage change ΔVFD1 of the floating diffusion node voltage VFD1 of the first pixel PX1 may be proportional to the voltage change ΔVCLP of the clamp control signal CG, and the clamp level may be determined based on the voltage change ΔVFD1 of the floating diffusion node voltage VFD1 of the first pixel PX1. Therefore, as the voltage change ΔVCLP of the clamp control signal CG increases, the clamp level may decrease, and as the voltage change ΔVCLP of the clamp control signal CG decreases, the clamp level may increase. The voltage generator 190 may adjust the first clamp voltage VH based on the received voltage control signal. CLP and the second clamping voltage VL CLP The voltage level of the output pin is set to generate the target clamping level.

[0110] Fig. 10A A clamping level according to an exemplary embodiment of the inventive concept is shown. Fig. 10B is a circuit diagram of one example of a current source according to an exemplary embodiment of the inventive concept.

[0111] Reference Fig. 10A The minimum value of the column line COL (ie, the clamping level V CLP ). The input range of the comparison circuit 141 may be between the first input voltage VinH and the second input voltage VinL. In this case, when the clamping level V CLP When the voltage is set to be smaller than the input range of the comparison circuit 141 , the comparison circuit 141 receives the pixel signal PXS from the read pixel.

[0112] The current source PL can be implemented using a bias transistor TRb and an enable transistor TRen connected in series. When the enable transistor TRen is turned on in response to the enable signal Ven, the bias transistor TRb sinks current based on the bias voltage Vb. For example, the enable signal Ven is applied to the gate terminal of the enable transistor TRen, and the bias voltage Vb is applied to the gate terminal of the bias transistor TRb. In this case, when the voltage of the column line COL is less than the minimum operating voltage of the current source PL (i.e., the voltage required for the normal operation of the current source PL), the current source PL cannot operate normally. The minimum operating voltage of the current source PL may be the drain-source voltage Vds of the bias transistor TRb. In this case, the drain-source voltage of the enable transistor TRen may be almost 0V. Therefore, the clamping level V as the minimum voltage level of the column line COL is 0V. CLP Can be set greater than Vds.

[0113] According to an embodiment of the present invention, Fig. 10BAs shown, the current source PLa can be implemented using at least two bias transistors TRb1 and TRb2 connected in series and an enable transistor TRen. The minimum operating voltage of the current source PLa can be 2×Vds′ (the sum of the drain-source voltage Vds′ of the two bias transistors TRb1 and TRb2). Therefore, the clamping level V as the minimum voltage level of the column line COL is CLP Can be set to be greater than 2×Vds'.

[0114] As reference Fig. 10A and Fig. 10B As described, in an exemplary embodiment, the clamping level V CLP is set to be smaller than the input range of the comparison circuit 141 and larger than the operating voltage of the current source PL.

[0115] Fig.11 is a circuit diagram of an image sensor 100 c according to an exemplary embodiment of the inventive concept and illustrates a read operation of the image sensor 100 c. Fig.12 is Fig.11 FIG. 1 is a timing diagram of signals for the pixel array 110 c in a read operation of the image sensor 100 c.

[0116] Reference Fig.11 , the image sensor 100c includes a pixel array 110c, a row driver 120c (e.g., a driving circuit), and a signal generator 171. According to an exemplary embodiment of the inventive concept, the signal generator 171 is included in the timing generator 170. However, the signal generator 171 is not limited thereto and may be implemented as a circuit separate from the timing generator 170. The image sensor 100c may further include a reference Figure 1 Other components described.

[0117] A pixel 111c (e.g., a first pixel PX1) included in the pixel array 110c may include a plurality of photosensitive elements PD11, PD12, PD13, and PD14, a plurality of transfer transistors (e.g., first to fourth transfer transistors TX11, TX12, TX13, and TX14), a reset transistor RX1, a drive transistor DX1, and a selection transistor SX1. The plurality of transfer transistors TX11, TX12, TX13, and TX14 may be connected to the plurality of photosensitive elements PD11, PD12, PD13, and PD14, respectively, and may also be commonly connected to the drive transistor DX1. Therefore, a structure in which a plurality of photosensitive elements PD11, PD12, PD13, and PD14 are connected to one drive transistor may be referred to as a multi-sharing structure.

[0118] although Fig.11One pixel 111 c is shown to include four photosensitive elements PD11 , PD12 , PD13 , and PD14 and four transfer transistors TX11 , TX12 , TX13 , and TX14 , but the pixel 111 c is not limited thereto, and the number of photosensitive elements and the number of transfer transistors may be variably changed.

[0119] When a read operation is performed on the second pixel PX2, the first pixel PX1 operates as a clamp circuit. A reset signal RS may be applied to respective reset transistors RX1 and RX2 of the first pixel PX1 and the second pixel PX2, and a selection signal SEL may be applied to respective selection transistors SX1 and SX2 of the first pixel PX1 and the second pixel PX2. A transmission control signal TG may be applied to a plurality of transmission transistors TX21, TX22, TX23, and TX24 in the second pixel PX2. According to an embodiment of the inventive concept, the transmission control signal TG may be applied to some of the plurality of transmission transistors TX21, TX22, TX23, and TX24 in the second pixel PX2.

[0120] In an exemplary embodiment, the clamp control signal CG is applied to at least one of the plurality of transfer transistors TX11, TX12, TX13, and TX14 in the first pixel PX1, and the blocking control signal OFF is applied to the remaining transfer transistors. Fig.11 As an example, the clamp control signal CG is applied to the first transfer transistor TX11 and the second transfer transistor TX12 in the first pixel PX1, and the blocking control signal OFF is applied to the third transfer transistor TX13 and the fourth transfer transistor TX14 therein, but the embodiments of the present disclosure are not limited thereto, and the clamp control signal CG may be applied to at least one transfer transistor. For example, the clamp control signal CG may be applied to all of the plurality of transfer transistors TX11, TX12, TX13, and TX14. During the read operation of the first pixel PX1, the blocking control signal OFF may have a specific level. According to an exemplary embodiment of the inventive concept, the level of the blocking control signal OFF is the same as the low level of the clamp control signal CG.

[0121] The plurality of transfer transistors TX11, TX12, TX13, and TX14 share the floating diffusion node FD1. Therefore, when the first pixel PX1 is used as a clamping pixel, the voltage variation of the floating diffusion node voltage VFD1 can be variably changed based on the number of transfer transistors to which the clamping control signal CG is applied among the plurality of transfer transistors TX11, TX12, TX13, and TX14. In other words, the low level of the floating diffusion node voltage VFD1 can be variably changed.

[0122] Reference Fig.12In an exemplary embodiment, the voltage variation of the floating diffusion node voltage VFD1 is proportional to the number of transfer transistors to which the clamp control signal CG is applied. For example, when the clamp control signal CG is applied to one transfer transistor and the blocking control signal OFF is applied to the other transfer transistors, that is, when one transfer transistor is used for clamping, the voltage variation of the floating diffusion node voltage VFD1 is △VFD11. When two transfer transistors are used for clamping, the voltage variation of the floating diffusion node voltage VFD1 is 2×△VFD11, and when three transfer transistors are used for clamping, the voltage variation of the floating diffusion node voltage VFD1 is 3×△VFD11. When four transfer transistors are used for clamping, the voltage variation of the floating diffusion node voltage VFD1 is 4×△VFD11. In other words, the more the number of transfer transistors used for clamping in the clamping pixel (e.g., the first pixel PX1), the greater the voltage variation of the floating diffusion node voltage VFD1. Therefore, as the number of pass transistors used for clamping increases, the lower limit value (eg, the clamping level) of the output voltage Vout may decrease.

[0123] Return to reference Fig.11 , the row driver 120c may include: a first driver 121 (e.g., a driving circuit) and a second driver 122, the first driver 121 is configured to drive the row where the first pixel PX1 is located (i.e., the clamping row), and the second driver 122 is configured to drive the row where the second pixel PX2 is located (i.e., the reading row). The first driver 121 may include first to fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 configured to drive the first to fourth transmission transistors TX11, TX12, TX13, and TX14, respectively. For example, each of the first to fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 may be implemented using an operational amplifier. The first to fourth transmission drivers TXD11, TXD12, TXD13, and TXD14 may be implemented by a clamping reference signal S provided from the signal generator 171. CLP and blocking reference signal S OFF Buffering or level conversion is performed to generate the clamp control signal CG and the blocking control signal OFF.

[0124] The signal generator 171 may generate an input signal (eg, a clamp reference signal S 171 ) to be provided to the first to fourth transmission drivers TXD11 , TXD12 , TXD13 , and TXD14 . CLP and blocking reference signal S OFF ) and adjust the clamp reference signal S CLP Therefore, the number of transfer transistors to be used for clamping in a clamping pixel (eg, the first pixel PX1) can be adjusted.

[0125] According to an exemplary embodiment of the inventive concept, when a pixel has a multi-sharing structure, the image sensor 100c adjusts the clamping level by adjusting the number of transfer transistors to be used for clamping. Fig. 9 The method described above of adjusting the clamping level by adjusting the first level and the second level of the clamping control signal CG may be combined with an embodiment having a multi-sharing structure.

[0126] Fig.13 is a flowchart of an operating method of an image sensor according to an exemplary embodiment of the inventive concept. Fig.13 The operation method of the image sensor in Figure 1 or Fig.12 The image sensor 100 or 100c is performed, and therefore, the above-mentioned operation method of the image sensor can be applied to the present embodiment.

[0127] Fig.13 A method performed by an image sensor including a first pixel and a second pixel connected to the same column line is shown. When a read operation is performed on the second pixel, the first pixel serves as a clamp circuit. In this case, the first pixel and the second pixel may be arranged in different rows, and according to an exemplary embodiment of the inventive concept, the first pixel may be a pixel for which the read operation has ended, and may be a pixel adjacent to the second pixel or a dummy pixel.

[0128] Reference Fig.13 In operation S110, a plurality of pixels in a pixel array of the image sensor are reset in response to a reset signal. Thereafter, a read operation may be performed in units of rows of the pixel array.

[0129] In the reset count cycle, in operation S120, a clamp control signal that is reduced from a first level to a second level is applied to the first pixel through the first row line. The clamp control signal may be applied to the gate terminal of the transfer transistor in the first pixel. Due to the parasitic capacitance between the gate terminal of the transfer transistor and the floating diffusion node, the voltage level of the floating diffusion node of the first pixel may be reduced. The voltage variation of the floating diffusion node voltage may be variably changed based on the difference between the first level and the second level. For example, the greater the difference between the first level and the second level, the greater the voltage variation of the floating diffusion node voltage, and therefore, the floating diffusion node voltage may be further reduced. In an exemplary embodiment, the floating diffusion node voltage of the first pixel is less than the comparison circuit ( Figure 2 141) input range and is greater than the current source connected to the column line ( Figure 2 A voltage for normal operation (eg, the sum of source-drain voltages of transistors included in the current source) of PL.

[0130] Thereafter, in the signal transmission period, in operation S130, a transmission control signal of an activation level is applied to the second pixel through the second row line, and the transmission transistor in the second pixel is turned on in response to the transmission control signal. In this case, the activation level of the transmission control signal may be the same as or different from the first level of the clamp control signal.

[0131] In operation S140, a higher voltage between the output voltage of the first pixel and the output voltage of the second pixel is output as a pixel signal through a column line. The output voltage of the pixel may indicate the floating diffusion node voltage of the pixel. Therefore, the pixel signal may be determined based on the higher voltage between the floating diffusion node voltage of the first pixel and the floating diffusion node voltage of the second pixel. Before the signal transmission period, the floating diffusion node voltage of the second pixel may be higher than or equal to the floating diffusion node voltage of the first pixel. Therefore, the floating diffusion node voltage of the second pixel may be output as a pixel signal. Thereafter, in the signal transmission period, in response to the light charge generated by the photosensitive element flowing into the floating diffusion node in the second pixel, the floating diffusion node voltage of the second pixel may be reduced. When the floating diffusion node voltage of the second pixel is excessively reduced and is less than the floating diffusion node voltage of the first pixel, the floating diffusion node voltage of the first pixel may be output as a pixel signal, thereby preventing the occurrence of band noise when the pixel signal is excessively reduced.

[0132] Fig.14 is a block diagram of an image processing system 400 according to an exemplary embodiment of the inventive concept.

[0133] Reference Fig.14 , an image processing system 400 according to an exemplary embodiment of the inventive concept includes an image sensor 100 , an image processor 200 , a display unit 500 (eg, a display device), and a lens 320 .

[0134] Image sensor 100 includes pixel array 110 , row driver 120 , ramp signal generator 160 , timing generator 170 , control register block 195 , and buffer 180 .

[0135] The image sensor 100 may sense the object 310 photographed through the lens 320 under the control of the image processor 200, and the image processor 200 may output the image sensed and output by the image sensor 100 to the display unit 500. In this case, the display unit 500 includes all components capable of outputting or presenting an image. For example, the display unit 500 may include a computer, a cellular phone, and other image output terminals.

[0136] The image processor 200 includes a camera controller 201 (e.g., a control circuit), an image signal processor 202, and a personal computer interface (PC I / F) 203. The camera controller 201 can control the control register block 195. For example, the camera controller 201 can control the image sensor 100 (i.e., the control register block 195) by using an inter-integrated circuit (I2C). However, the present embodiment is not limited thereto, and various interfaces can be applied between the camera controller 201 and the control register block 195.

[0137] The image signal processor 202 receives the image data IDTA as an output signal of the buffer 180, processes the image data IDTA into a processed image that can be viewed as an image by a user, and outputs the processed image to the display unit 500. Alternatively, the image signal processor 202 may receive a control signal from an external host through the PC I / F 203 and provide the processed image to the external host.

[0138] The image sensor 100 may be referred to as Figure 1 and Fig.12 The control register block 195 may output a control signal to each of the ramp signal generator 160, the timing generator 170, the buffer 180, and the voltage generator 190 to control the operation thereof. In this case, the control register block 195 may operate based on the control of the camera controller 201.

[0139] The pixel array 110, the row driver 120, the ADC 130, the timing generator 170, the buffer 180, the ramp signal generator 160, and the voltage generator 190 are described in detail above with reference to the accompanying drawings, and therefore, a repeated description thereof is omitted here. When a read operation is performed in the pixel array 110, the pixels in the unread row adjacent to the read row may be used as clamped pixels (i.e., clamped circuits). In addition, before the signal transmission period, a clamped signal reduced from a first level to a second level may be applied to the gate terminal of the transfer transistor of the clamped pixel, and in response to the reduction of the clamped signal due to the parasitic capacitance between the gate terminal of the transfer transistor and the floating diffusion node, the floating diffusion node voltage may be reduced. The voltage level of the floating diffusion node voltage may be used as a clamping level. When the floating diffusion node voltage of the read pixel is excessively reduced, the floating diffusion node voltage of the clamped pixel may be output as a pixel signal. Therefore, the pixel signal may be prevented from being excessively reduced, thereby suppressing the occurrence of band noise.

[0140] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. An image sensor, comprising: a pixel array, comprising a first pixel and a second pixel, each of the first pixel and the second pixel comprising at least one photosensitive element and a switch element, the switch element of the first pixel being configured to transfer charges generated by the at least one photosensitive element of the first pixel to a first floating diffusion node of the first pixel, and the switch element of the second pixel being configured to transfer charges generated by the at least one photosensitive element of the second pixel to a second floating diffusion node of the second pixel, wherein the first pixel and the second pixel are connected to the same column line and are arranged in different rows; and a row driver circuit configured to supply a clamp control signal to a switch element in the first pixel in which a read operation is not performed, the clamp control signal transitioning from a first level to a second level less than the first level during a reset count period of a read cycle of the second pixel, and The row driver circuit is configured to provide a transmission control signal of a third level to the switch element of the second pixel during a signal transmission period after the reset count period in the read period.

2. The image sensor according to claim 1, wherein: A pixel voltage output from the column line is determined based on a relatively higher voltage between a voltage of a first floating diffusion node in the first pixel and a voltage of a second floating diffusion node in the second pixel.

3. The image sensor according to claim 1, wherein: The row driver circuit is further configured to provide the transfer control signal to a switch element in the second pixel, and After the clamp control signal changes to the second level, the switch element in the second pixel is turned on in response to the transfer control signal of the third level, so that the charge generated by at least one photosensitive element of the second pixel is transferred to the second floating diffusion node in the second pixel.

4. The image sensor according to claim 3, wherein: The first level is the same as the third level.

5. The image sensor according to claim 3, wherein: The row driver circuit comprises: a first transmission driver circuit configured to generate the clamp control signal based on the first voltage of the first level and the second voltage of the second level, and output the clamp control signal to a first row line connected to the first pixel; and a second transmission driver circuit configured to generate the transmission control signal based on a third voltage of the third level and a fourth voltage of a fourth level smaller than the third level, and output the transmission control signal to a second row line connected to the second pixel, The first level is different from the third level.

6. The image sensor according to claim 1, wherein: A voltage of a first floating diffusion node in the first pixel decreases based on a difference between a first level and a second level of the clamp control signal.

7. The image sensor according to claim 1, wherein: The first pixel includes a plurality of photosensitive elements and a plurality of switch elements configured to transfer charges generated by the plurality of photosensitive elements of the first pixel to first floating diffusion nodes of the first pixel, respectively. The second pixel includes a plurality of photosensitive elements and a plurality of switch elements configured to transfer charges generated by the plurality of photosensitive elements of the second pixel to second floating diffusion nodes of the second pixel, respectively, and The row driver circuit is further configured to provide the clamp control signal to at least one switching element among the plurality of switching elements in the first pixel.

8. The image sensor according to claim 7, wherein: The row driver circuit is further configured to transmit a blocking control signal of a specific level to at least one other switching element among the plurality of switching elements in the first pixel.

9. The image sensor according to claim 1, wherein: The first pixel and the second pixel are arranged in different rows, and the first pixel is arranged in a row most adjacent to a row in which the second pixel is arranged.

10. The image sensor according to claim 1, wherein: The first pixel is a dummy pixel arranged in an invalid pixel area of ​​the pixel array.

11. The image sensor according to claim 1, wherein: The pixel array further includes a third pixel connected to the same column line as the column line to which the first pixel and the second pixel are connected, and The row driver circuit is further configured to provide the clamp control signal to each of the switching element in the first pixel and the switching element in the third pixel during a read cycle of the second pixel.

12. The image sensor according to claim 1, further comprising: a current source connected to the column line and configured to draw a load current from the column line; as well as a comparator configured to compare the pixel voltage output from the column line with the ramp signal to generate a comparison result, The voltage of the first floating diffusion node in the first pixel decreases to a clamping level in response to the clamping control signal, and the clamping level is less than a lower limit of an input range of the comparator and greater than an operating voltage of the current source.

13. An image sensor, comprising: a pixel array including first pixels and second pixels arranged in different rows and connected to the same column line; a row driver circuit configured to provide control signals to the pixel array; a voltage generating circuit configured to provide a driving voltage for driving the first pixel and the second pixel to the row driver circuit; a ramp signal generator configured to generate a ramp signal; an analog-to-digital converter configured to convert a pixel voltage received from the column line into a pixel data value based on the ramp signal; as well as a timing signal generator configured to control the row driver circuit, the ramp signal generator and the analog-to-digital converter, wherein, when a read operation is performed on the second pixel, the row driver circuit sequentially applies a clamp control signal of a first level and a second level less than the first level to a switch element in the first pixel where the read operation is not performed, and Wherein, before the charge transfer signal of the third level is applied to the signal transfer period of the switch element in the second pixel, the clamp control signal is reduced from the first level to the second level.

14. The image sensor according to claim 13, wherein The switching element of the first pixel includes a charge transfer transistor connected to a photosensitive element in the first pixel and a gate terminal of a driving transistor, and The clamp control signal is applied to a gate terminal of the charge transfer transistor.

15. The image sensor according to claim 13, wherein: The first pixel comprises: a photosensitive element configured to generate photocharges corresponding to a received optical signal; a first transistor configured to reset a floating diffusion node of the first pixel; a second transistor configured to transfer photocharge generated by the photosensitive element of the first pixel to a floating diffusion node of the first pixel; a third transistor configured to output a voltage corresponding to a voltage of a floating diffusion node of the first pixel; and a fourth transistor configured to output the output of the third transistor of the first pixel to a column line in response to a selection signal, wherein the second transistor of the first pixel is used as a switching element of the first pixel, and The second pixel comprises: a photosensitive element configured to generate photocharges corresponding to a received optical signal; a first transistor configured to reset a floating diffusion node of the second pixel; a second transistor configured to transfer photocharge generated by the photosensitive element of the second pixel to a floating diffusion node of the second pixel; a third transistor configured to output a voltage corresponding to a voltage of a floating diffusion node of the second pixel; and a fourth transistor configured to output the output of the third transistor of the second pixel to a column line in response to a selection signal, The second transistor of the second pixel is used as a switching element of the second pixel.

16. The image sensor according to claim 13, wherein: The row driver circuit is further configured to receive a first voltage of the first level, a second voltage of the second level, a third voltage of the third level, and a fourth voltage of a fourth level, generate the clamp control signal based on the first voltage and the second voltage, and generate the charge transfer signal based on the third voltage and the fourth voltage, wherein the third level is greater than the fourth level, The first level is different from the third level.

17. The image sensor according to claim 13, wherein: A minimum value of the pixel voltage is determined based on the first level and the second level.

18. The image sensor according to claim 15, wherein: The first pixel includes a plurality of photosensitive elements and a plurality of switch elements configured to transfer photocharges generated by the plurality of photosensitive elements of the first pixel to floating diffusion nodes of the first pixel, respectively. The second pixel includes a plurality of photosensitive elements and a plurality of switch elements configured to transfer photocharges generated by the plurality of photosensitive elements of the second pixel to floating diffusion nodes of the second pixel, respectively, and The row driver circuit is further configured to provide the clamp control signal to at least one switching element among the plurality of switching elements in the first pixel.

19. A method for operating an image sensor comprising a pixel array, the pixel array comprising first pixels and second pixels arranged in different rows and connected to the same column line, the method comprising: resetting the pixel array; When a read operation is performed on the second pixel, a clamp control signal is applied to the first pixel on which the read operation is not performed during a reset count period, and during the reset count period, the clamp control signal is reduced from a first level to a second level; as well as During a signal transmission period after the reset count period, a transmission control signal of an active level is applied to the second pixel.

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