Method for preparing mask data for producing integrated circuit

Abstract

An embodiment of the present invention provides a mask data preparation method for producing an integrated circuit. According to some embodiments of the present invention, a method for producing an integrated circuit includes: receiving a first IC design layout by a processor; replacing a specific region in the first IC design layout with a first difference region by the processor; performing a reverse lithography process on a junction region between the first difference region and the first IC design layout by the processor to generate mask data; and causing the IC to be manufactured according to the mask data.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for preparing mask data for producing an integrated circuit. Background Art

[0002] In semiconductor manufacturing technology, the layout of a circuit design or structure is typically designed and stored in one or more data files. The data files are then provided to a writer, which is used to convert the data files into an image on a substrate (e.g., a mask or semiconductor wafer). In advanced technology nodes, the layout becomes increasingly complex. This can be a result of various factors including reduced critical dimensions (CDs) of the images, larger image sizes, and more complex patterns. This results in longer data preparation cycles as the node size decreases and the size of the corresponding data file(s) increases. Therefore, there is a need to provide a method for reducing the cycle time of data preparation during an integrated circuit (IC) manufacturing process. Summary of the invention

[0003] An embodiment of the present invention discloses a method for producing an integrated circuit (IC), comprising: receiving a first IC design layout by a processor; replacing a specific region in the first IC design layout with a first difference region by the processor; performing an inverse lithography technology (ILT) process on a junction region between the first difference region and the first IC design layout by the processor to generate mask data; and causing the IC to be manufactured according to the mask data.

[0004] An embodiment of the present invention discloses a method for producing an integrated circuit (IC), which includes: receiving a first IC design layout by a processor; comparing the first IC design layout with a second IC design layout by the processor to identify a difference area; performing an OPC process on the difference area by the processor to form an OPC-processed difference area; merging the OPC-processed difference area with the OPC-processed IC design layout by the processor; performing an inverse lithography technology (ILT) process on a first line of the OPC-processed difference area and a second line of the OPC-processed IC design layout by the processor to generate mask data; and causing the IC to be manufactured according to the mask data.

[0005] An embodiment of the present invention discloses a non-transitory computer-readable medium having instructions embodied thereon, the instructions being executable by a processor to perform a method comprising: receiving a first IC design layout; replacing a specific region in the first IC design layout with a first difference region; and performing an inverse lithography technology (ILT) process on a junction region between the first difference region and the first IC design layout to generate mask data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present invention are best understood from the following detailed description read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a simplified block diagram illustrating an embodiment of an integrated circuit manufacturing system 100 and an IC manufacturing flow associated with the IC manufacturing system.

[0008] Figure 2 is a flow chart illustrating a method of producing an IC according to some embodiments.

[0009] Figure 3 is a diagram illustrating a revised IC design layout and an initial IC design layout according to some embodiments.

[0010] Figure 4A is a diagram illustrating a difference area and an OPC processed difference area according to some embodiments.

[0011] Figure 4B is a diagram illustrating an original mask of a major component and an OPC-processed mask of a major component according to some embodiments.

[0012] Figure 5 is a diagram illustrating an OPC processed IC design layout according to some embodiments.

[0013] Figure 6 is a diagram illustrating a singulated IC design layout subjected to OPC processing according to some embodiments.

[0014] Figure 7 is a diagram illustrating a revised IC design layout subjected to OPC processing according to some embodiments.

[0015] Figure 8 is a diagram illustrating a portion on a junction region in a revised IC design layout that is OPC processed according to some embodiments.

[0016] Fig. 9 is a diagram illustrating Manhattan optimization according to some embodiments.

[0017] Fig.10 is a method for implementing Figure 2 A diagram of a computer system that implements the method of operation. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and arrangements will be described below to simplify embodiments of the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member above or on a second member may include embodiments in which a first member and a second member in direct contact are formed, and may also include embodiments in which an additional member may be formed between the first member and the second member so that the first member and the second member may not be in direct contact. In addition, embodiments of the present invention may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to describe the relationship of one element or component to another element or components, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] Figure 1 1 is a simplified block diagram illustrating an embodiment of an integrated circuit (IC) manufacturing system 100 and an IC manufacturing flow associated with the IC manufacturing system 100. The IC manufacturing system 100 includes multiple entities (e.g., a design studio 110, a mask fabrication plant 120, and an IC manufacturer 130) that interact with each other in terms of design, development, and manufacturing cycles and / or services related to manufacturing an IC device 140. The multiple entities may be connected by a communication network, which may be a single network or a variety of different networks (e.g., an intranet and the Internet) and may include wired and / or wireless communication channels. Each entity may interact with the other entities and may provide services to the other entities and / or receive services from the other entities. The design studio 110, the mask fabrication plant 120, and the IC manufacturer 130 may be a single entity or separate entities.

[0021] For example, when manufacturing an IC, a tape-out process is performed. The tape-out process may include a floorplanning process, in which the various structures that make up the IC are provided in a design layout. The process may include generating an electronic file of the design layout in a GDS format. The design layout GDS file is checked by a design rule check (DRC) tool to ensure that the design layout complies with various design rules, such as minimum density rules. It should be understood that other types of file formats may also be used in this example. The process continues with an assembly process. The circuit design may be divided into various blocks, each of which performs a specific function. Therefore, the various blocks are assembled together and the entire design layout is ready for photomask (or mask) processing.

[0022] During the design phase, the design studio 110 generates an IC design layout 112. The IC design layout 112 includes various geometric patterns designed for the IC product based on the specifications of the IC product to be manufactured. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 140 to be manufactured. Various layers are combined to form various IC components. For example, a portion of the IC design layout 112 may include various IC components (such as active areas, gate electrodes, source and drain, metal lines or paths for interlayer interconnection, and openings for bonding pads), which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 110 implements an appropriate design process to form the IC design layout 112. The design process may include logical design, physical design and / or placement and routing. The IC design layout 112 is presented in one or more data files with information of the geometric patterns. For example, the IC design layout 112 can be represented in a GDSII file format.

[0023] During electron beam operation (EBO), mask fabrication plant 120 uses IC design layout 112 to manufacture one or more photomasks (or masks) for manufacturing various layers of IC products according to IC design layout 112. Mask fabrication plant 120 performs: mask data preparation 122, in which IC design layout 112 is converted into a form that can be physically written by a mask writer; and mask tooling 124, in which the design layout prepared by mask data preparation 122 is modified to conform to a specific mask writer and / or mask manufacturer. In the present embodiment, mask data preparation 122 and mask tooling 124 are described as separate elements, however, mask data preparation 122 and mask tooling 124 may be collectively referred to as mask data preparation, which may further include mask manufacturing. A large number of mask images may be generated based on completing the design layout. The number of mask images will vary depending on the complexity of the design layout. The process is now in the off-line stage, which represents the time when the design layout (or database) is ready for chip manufacturing.

[0024] The mask data preparation 122 includes a logic operation (LOP) 150 , a retargeting process (RET) 160 , an optical proximity correction (OPC) 170 , and a fracture process (FRAC) 180 .

[0025] LOP 150 is performed on IC design layout 112 to modify IC design layout 112 according to manufacturing rules. For example, the conversion process can be implemented by software in LOP 150. Various manufacturer modules convert manufacturing constraints into a set of rules that IC design layout 112 must comply with. If IC design layout 112 does not comply with this set of rules, then IC design layout 112 will be modified accordingly until the modified IC design layout complies with these rules. This modification is implemented by logic operation 150.

[0026] RET 160 and OPC 170 are resolution enhancement techniques. RET 160 (or rule-based OPC) can modify IC design layout 112 to compensate for limitations of the lithography process used to manufacture IC products according to IC design layout 112. OPC 170 (or model-based OPC) is a lithography enhancement technique used to compensate for image errors (such as image errors caused by diffraction, interference, or other process effects). RET 160 and OPC 170 features (such as scatter bars, serifs, and / or hammerheads) are added to IC design layout 112 according to an optical model or rule. Mask data preparation 122 may include further resolution enhancement techniques, such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, or combinations thereof.

[0027] OPC 170 accounts for distortions in the pattern transfer process by modifying the design shape to print the desired image on the wafer. OPC 170 may include general modifications to limitations in the lithography process, and in one specific example, accounts for the case of optical lithography. OPC 170 may include modifications to the design image to account for optical limitations as well as mask manufacturing limitations and photoresist limitations. Modifications to the design image may also account for subsequent process steps such as dry etching or implantation. It may also account for spot and pattern density variations in the optical system. Another application of proximity correction is to compensate for aberration effects in the optical system used to print the mask image onto the wafer.

[0028] FRAC 180 performs a fracturing process on the RET processed and OPC processed IC design layout (which may also be referred to as a modified IC design layout) to convert to a writer format (e.g., an e-beam format). The fracturing process is performed on the data file to "fracture" the design features into polygons or other structures suitable for mask generation. In one embodiment, the fracturing process generates temporary files, which are individual files generated by individual machines connected to the host in batches for merging. The process may further include merging the temporary files into a single file and converting the single file to a flat polygon format. The flat polygon format is generated by electronic design and analysis (EDA) tools (e.g., In mask tooling 124, a "write file" process converts the data from the fracture process (in a planar polygon format) into a unique file format used by different writers, such as Toshiba's vsb12 format.

[0029] The data preparation may further include other processes, including, but not limited to, various pre-OPC and post-OPC processes. In one example, the post-OPC process includes, but is not limited to, a lithography process check (LPC) and various quality assurance processes (e.g., differential area alignment quality assurance and LPC check of boundary areas, XOR, CRC) that simulate the process to be implemented by the IC manufacturer 130 to manufacture the IC device 140. The LPC may simulate this process based on the modified IC design layout to produce a simulated manufacturing device, such as the IC device 140. The simulated manufacturing device may be all or part of the IC design layout. In the present embodiment, the LPC may simulate the process of the modified IC design layout that has been subjected to LOP 150, RET 160, OPC 170, and FRAC 180.

[0030] The LPC may determine whether the simulated fabricated device violates any of a plurality of hotspot rules. If the simulated fabricated device satisfies the hotspot rules, mask data preparation may be completed and the IC design layout 112 (more specifically, the modified IC design layout) undergoes further processing in mask tooling 124. Alternatively, the modified IC design layout undergoes further model-based testing, rule-based testing, and / or is otherwise modified or tested to further improve the design and / or layout of the device prior to the fabrication stage.

[0031] After mask data preparation 122 and mask tooling 124, a mask or mask group is manufactured based on the modified IC design layout. For example, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (photomask or master mask) based on the modified IC design layout. The mask can be formed using various techniques. In one embodiment, a binary technique is used to form the mask. In this embodiment, the mask pattern includes an opaque area and a transparent area. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, the binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, a phase shift technique is used to form the mask. In a phase shift mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shift mask may be an attenuated PSM or an alternating PSM as known in the art.

[0032] During the manufacturing phase, IC manufacturer 130 (e.g., semiconductor foundry) uses masks manufactured by mask fabrication plant 120 to manufacture IC device 140. IC manufacturer 130 may be an IC manufacturing enterprise, which may include a large number of manufacturing facilities for manufacturing a variety of different IC products. For example, there may be a manufacturing facility for front-end manufacturing (i.e., front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (i.e., back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services of the foundry business. In the present embodiment, a mask (or several masks) is used to manufacture semiconductor wafers to form IC device 140.

[0033] The semiconductor wafer may include a silicon substrate or other suitable substrate with a material layer formed on a silicon substrate. Other suitable substrate materials include: another suitable element semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The semiconductor wafer may further include various doped regions, dielectric components, and multilayer interconnects (formed in subsequent manufacturing steps). Masks can be used in various processes. For example, the mask can be used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etched regions in the semiconductor wafer, in a deposition process (such as chemical vapor deposition (CVD) or physical vapor deposition (PVD)) to form thin films in various regions on the semiconductor wafer, and / or for other suitable processes.

[0034] Figure 2 2 is a flow chart illustrating a method 200 of producing an IC according to some embodiments. When the mask manufacturing plant 120 receives a revised IC design layout, operations 202 to 222 in the method 200 may reduce the cycle time of IC mask data preparation in the mask manufacturing plant 120. The revised IC design layout may be a revised version of an initial IC design layout, whose mask is pre-fabricated by the mask manufacturing plant 120. Therefore, the mask data and related data files of the initial IC design layout may be stored in the mask manufacturing plant 120. According to some embodiments, operations 202 to 218 of the method 200 may be implemented by a processor or computer system in the mask manufacturing plant 120. However, this is not a limitation of the present embodiment.

[0035] In operation 202 and Figure 3 , which is a diagram illustrating a revised IC design layout 302 and an initial IC design layout 304 according to some embodiments, a revised IC design layout 302 is received by mask fabrication house 120 from design studio 110. Revised IC design layout 302 is a re-spin layout of a previous layout (eg, initial IC design layout 304).

[0036] In operation 204 and Figure 3 In the embodiment, the initial IC design layout 304, which may be stored in a storage device in the mask fabrication facility 120, is retrieved or read out from a computer system in the mask fabrication facility 120. According to some embodiments, the revised IC design layout 302 is different from the initial IC design layout 304 because the partial region 316 in the initial IC design layout 304 has been revised to the difference region 306 in the revised IC design layout 302.

[0037] When the revised IC design layout 302 is different from the initial IC design layout 304, the environment in which the OPC process is performed in the revised IC design layout 302 may be different from the environment in which the OPC process is performed in the initial IC design layout 304. For the instance of the layout block 308 near the boundary of the difference area 306 in the revised IC design layout 302, the layout block 308 is not revised. Therefore, the layout block 308 is the same as the corresponding layout block 310 in the initial IC design layout 304, that is, the layout structure, size, and position of the layout block 308 are the same as the layout structure, size, and position of the layout block 310, respectively. Although the layout block 308 and the layout block 310 are the same layout block, the OPC environment of the layout block 308 (that is, the area surrounded by the range 312) may be different from the OPC environment of the layout block 310 (that is, the area surrounded by the range 314). This is because the OPC environment of the layout block 308 includes a portion of the revised difference area 306, while the OPC environment of the layout block 310 does not include the portion of the revised difference area 306.

[0038] According to some embodiments, the OPC process is used to compensate for layout distortions on the silicon wafer that occur during lithography. Due to proximity effects, these layout distortions may consist of increased fillets, shortened line ends, and line width changes when located in an isolated or dense environment. For example, the proximity effect may cause an isolated layout structure to be larger than a densely packed layout structure. Therefore, the OPC environment of the layout block is an area that affects the proximity effect of the layout block during the OPC process. Therefore, the size of the layout block 308 may be different from the size of the layout block 310 after performing the OPC process. The different sizes between the layout block 308 and the layout block 310 may cause a mask size (DOM) conflict on the boundary of the difference area 306, as will be explained in more detail in a later paragraph.

[0039] In operation 206 and Figure 4A, which is a diagram illustrating a difference area 306 and an OPC-processed difference area 402 according to some embodiments, the revised IC design layout 302 is compared to the initial IC design layout 304 to identify the difference area 306 or a revised area in the revised IC design layout 302 that is different from the initial IC design layout 304. According to some embodiments, the difference area 306 is identified by performing an XOR operation on the revised IC design layout 302 and the initial IC design layout 304. In addition, the difference area 306 of the revised IC design layout 302 may include a boundary patch 404 that includes a portion of the initial IC design layout 304 to avoid gaps when merging the OPC-processed difference area (i.e., 402). In other words, the difference area 306 may be larger than the difference determined by the boundary patch 404 surrounding the difference through the XOR operation.

[0040] In operation 208 and Figure 4A , the difference region 306 is segmented from the revised IC design layout 302 .

[0041] In operation 210 and Figure 4A , an optical proximity correction (OPC) process is performed on the difference area 306 to produce an OPC-processed difference area 402. The OPC process can be applied to the difference area 306 using a rule-based approach or a model-based approach. For the rule-based approach (rule-based OPC), the displacement of the line segments in the difference area 306 will be set by a list of rules that depend on, for example, the size of the feature and its environment. For the model-based approach (model-based OPC), a model of the pattern transfer process will be used to simulate the printed image on the wafer. The correction will be set so that the simulated image matches the desired wafer image. A combination of rule-based OPC and model-based OPC, sometimes referred to as hybrid OPC, can also be used.

[0042] In one example, image quality can be improved by adding printed or non-printed auxiliary features along the edges of the primary features. These auxiliary features modify the diffraction spectrum of the pattern in a way that improves the printing of the primary features. The actual implementation of the auxiliary features is enhanced by correcting any optical printing artifacts as well as photoresist and etch artifacts using the proximity effect correction described above. Figure 4B 4 is a diagram illustrating an original mask 406 of a main feature and an OPC-processed mask 408 of the main feature according to some embodiments. By adding printed assist features (e.g., 410) and non-printed assist features (e.g., 412) on the mask 408, a final pattern 414 on the wafer is improved with improved resolution and accuracy over the pattern 416 of the original mask 406.

[0043] In operation 212 and Figure 5, which is a diagram illustrating an OPC processed IC design layout 500 according to some embodiments, retrieves an OPC processed IC design layout 500 corresponding to the initial IC design layout 304. More specifically, the OPC processed IC design layout 500 is an OPC processed layout of the initial IC design layout 304. Since the initial IC design layout 304 was previously fabricated by the mask fabrication facility 120, the OPC process may be performed on the initial IC design layout 304 in the mask fabrication facility 120. Therefore, before the revised IC design layout 302 is received by the mask fabrication facility 120, the OPC processed IC design layout 500 corresponding to the initial IC design layout 304 may be stored in a storage device of the mask fabrication facility 120. Therefore, rather than performing the OPC process again on the entire revised IC design layout 302, the OPC processed IC design layout 500 may be reused in this operation to save processing time for the OPC process.

[0044] In operation 212, the specific OPC-processed area 506 in the OPC-processed IC design layout 500 is replaced with the OPC-processed difference area 402 to generate the OPC-processed layout of the revised IC design layout 302. More specifically, the specific OPC-processed area 402 is the OPC-processed layout of the difference area 306 in the revised IC design layout 302, and the specific OPC-processed area 506 is the OPC-processed layout of the partial area 316 in the initial IC design layout 304, wherein the specific OPC-processed area 402 is formed in operation 210, and the specific OPC-processed area 506 is pre-formed by the mask fabrication factory 120 during the OPC processing of the initial IC design layout 304. According to some embodiments, the location of the specific OPC-processed area 506 on the OPC-processed IC design layout 500 is the same as the location of the difference area 306 on the revised IC design layout 302. For example, the coordinates of the specific OPC processed area 506 on the OPC processed IC design layout 500 may be the same as the coordinates of the difference area 306 on the revised IC design layout 302. Therefore, the location of the specific OPC processed area 506 on the OPC processed IC design layout 500 may be identified by using the location of the difference area 306 on the revised IC design layout 302 determined in operation 206.

[0045] For brevity, Figure 5 Also shown in FIG. 5 is an OPC processed layout block 502 corresponding to the layout block 310 in the initial IC design layout 304 and a corresponding OPC range 504 .

[0046] In operation 214 and Figure 6, which is a diagram illustrating an OPC processed singulated IC design layout 600 according to some embodiments, a specific OPC processed area 506 in the OPC processed IC design layout 500 is removed to form a blank area 602 in the OPC processed singulated IC design layout 600 .

[0047] In operation 216 and Figure 7 (which is a diagram illustrating a revised IC design layout 700 processed by OPC according to some embodiments), the OPC processed difference area 402 is placed or merged on the blank area 602 of the cut IC design layout 600 processed by OPC to form the revised IC design layout 700 processed by OPC. As mentioned in operation 206, the difference area 306 can be larger than the difference determined by the boundary patch 404 around the difference through the XOR operation, and therefore, the size of the OPC processed difference area 402 can also be larger than the size of the blank area 602, so that the peripheral portion of the OPC processed difference area 402 can cover the portion of the OPC processed IC design layout 500 near the blank area 602 (i.e., Figure 7 The junction area 702 in FIG. 5 may include the OPC processed layout block 502. Please refer again to Figure 3 and Figure 5 , the OPC processed layout block 502 is obtained by performing an OPC process on the layout block 310 within the range 314 on the initial IC design layout 304, wherein the range 314 covers a portion of the partial area 316 in the initial IC design layout 304. When the partial area 316 is replaced with the difference area 306, the conditions or environment in which the OPC processed layout block 502 is formed are also changed. Therefore, when the peripheral portion of the OPC processed difference area 402 covers the OPC processed layout block 502, the layout block in the peripheral portion of the OPC processed difference area 402 may not completely overlap with the original layout block (e.g., the OPC processed layout block 502) in the junction area 702. When the layout size on the peripheral portion of the OPC processed difference area 402 is different from the layout size on the portion of the OPC processed IC design layout 500 near the blank area 602, a DOM conflict may occur on the junction area 702.

[0048] Figure 8is a diagram illustrating a portion 802 on a junction region 702 in a revised IC design layout 700 processed by OPC according to some embodiments. For simplicity, the junction region 702 includes a portion of the OPC processed difference region 402 and a portion of the OPC processed IC design layout 500. In the junction region 702, the portion 802 includes a first metal line layout 804 and a second metal line layout 806. The first metal line layout 804 is connected to the second metal line layout 806. However, a width w1 of the first metal line layout 804 is different from a width w2 of the second metal line layout 806. When the width w1 of the first metal line layout 804 is different from the width w2 of the second metal line layout 806, a DOM conflict may occur on the portion 802.

[0049] Specifically, two metal line layouts 808 and 810 are combined into portion 802, such as Figure 8 . Metal line layout 808 is a layout portion of the OPC processed IC design layout 500. Metal line layout 810 is a layout portion of the OPC processed difference area 402. Because metal line layout 808 and metal line layout 810 are processed under different OPC environments, metal line layout 808 and metal line layout 810 may have different line widths (i.e., w1 and w2) on boundary 704. For metal line layout 808, layout portion 812 on the left side of boundary 704 and specific OPC processed area 506 are removed together, and layout portion 814 on the right side of boundary 704 is retained. For metal line layout 810, layout portion 816 on the left side of boundary 704 is retained, and layout portion 818 on the right side of boundary 704 is removed. Then, when metal line layout 810 and metal line layout 808 are merged, a step 820 may be formed on the interface between layout portion 816 and layout portion 814 due to the different widths w1 and w2. The step 820 may cause a DOM violation during the mask making process.

[0050] In operation 218, an inverse photolithography technology (ILT) process is performed on the junction region 702 of the OPC processed revised IC design layout 700. The ILT process is applied to obtain a mask for smoothing the steps 820 on the junction region 702 so that the profile of the conductive line matches the target profile after manufacturing. Specifically, the ILT process is a process of mathematically deriving an optimized photomask shape corresponding to a specific light source and circuit pattern shape used to produce the desired features on the wafer.

[0051] According to some embodiments, the ILT process is performed only on the junction region 702 of the OPC processed revised IC design layout 700 and not on the OPC processed difference region 402 and the OPC processed IC design layout 500 to save computer execution time.

[0052] ILT is a technique that uses curved features for mask lithography. However, due to unmanageable mask writing time, it may not be possible to write an ideal mask shape. To manage the mask writing time, a process called Manhattan optimization can be applied to "Manhattanize" the mask to produce a mask pattern that can be written using only rectangular variable shaped beam emission. According to some embodiments, in operation 218, to prepare the mask pattern for the junction region 702, Manhattan optimization is also performed on the junction region 702 in operation 218. In Manhattan optimization, the update mask is based on the gradient calculated from the cost function definition. The movement of each edge in the junction region 702 follows the direction suggested by the average gradient on the circuit pattern shape. In addition, Manhattan optimization does not generate additional edges on the updated mask.

[0053] Fig. 9 is a diagram illustrating Manhattan optimization according to some embodiments. Manhattan optimization is performed on a circuit pattern. For simplicity, Fig. 9 , where the initial mask 902 is the mask before Manhattan optimization, the gradient field 904 shows the gradient change of the initial mask 902, and the updated mask 906 is the mask after Manhattan optimization is performed. During Manhattan optimization, the vector V1 of the line segment / edge (i.e., [c0, c1, ..., c n ]), the vector V2 of gradient samples on each line segment / edge (i.e., [g0, g1, ..., g n ]) and the step size δ of the circuit pattern. Then, the product of vector V2 and step size δ is subtracted from vector V1 to obtain vector V3 with the updated / new mask of the moved line segment / edge (i.e., [c 0new ,c 1new ,...,c nnew ]). For example, Fig. 9 As shown in portion 908 of , edge 912 is modified to edge 910 after Manhattan optimization.

[0054] After operation 218 , mask data of the OPC-processed revised IC design layout 700 is obtained in the mask fabrication facility 120 .

[0055] In operation 220 , a photomask corresponding to the OPC processed revised IC design layout 700 is fabricated in the mask tooling 124 of the mask fabrication facility 120 based on the mask data.

[0056] In operation 222 , an IC device corresponding to the revised IC design layout 302 may be fabricated by the IC manufacturer 130 based on the photomask.

[0057] Fig.102 is a diagram illustrating a computer system 1000 for implementing operations 202-218 of method 200 according to some embodiments. According to some embodiments, computer system 1000 (e.g., a data preparation computer and / or a mask tool) includes a bus 1002 or other communication mechanism for communicating information that interconnects subsystems and components such as: a processing component 1004 (e.g., a processor, a microcontroller, a digital signal processor (DSP), etc.), a system memory component 1006 (e.g., a RAM), a static storage component 1008 (e.g., a ROM), a disk drive component 1010 (e.g., a magnetic or optical), a network interface component 1012 (e.g., a modem or an Ethernet card), a display component 1014 (e.g., a CRT or LCD), an input component 1016 (e.g., a keyboard, a touch screen), and a cursor control component 1018 (e.g., a mouse or a trackball). In one implementation, disk drive component 1010 may include a database having one or more disk drive components.

[0058] According to some embodiments, the computer system 1000 performs specific operations (e.g., operations 202 to 218) by the processor 1004 executing one or more sequences of one or more instructions contained in the system memory component 1006. Such instructions may be read into the system memory component 1006 from another non-transitory computer-readable medium (e.g., static storage component 1008 or disk drive component 1010). In other embodiments, hard-wired circuits may be used instead of or in combination with software instructions to implement embodiments of the present invention. In one example, the processor 1004 is configured to receive and access initial IC design layout data, receive and access revised IC design layout data, identify difference areas between the initial IC design layout data and the revised IC design layout data, perform OPC on the difference areas, merge OPC-processed difference areas, perform a fracture process, perform an ILT process, and / or perform Manhattan optimization. The processor 1004 is further configured to receive instructions from other components of the computer system 1000 (e.g., even from a network through the network interface component 1012).

[0059] Logic may be encoded in a computer readable medium, which may refer to any medium that participates in providing instructions to processor 1004 for execution. Such media may be in many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. In various implementations, non-volatile media include optical or magnetic disks (such as disk drive component 1010), volatile media include dynamic memory (such as system memory component 1006), and transmission media include coaxial cables, copper wire, and optical fiber, including the wires that make up bus 1002. In one example, transmission media may be in the form of acoustic or light waves, such as those generated during radio and infrared data communications.

[0060] Some common forms of computer-readable media include, for example, a floppy disk, a floppy disk, a hard disk, magnetic tape, any other magnetic media, a CD-ROM, any other optical media, punch cards, paper tape, any other physical media with a pattern of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, a carrier wave, or any other media from which a computer is adapted to read.

[0061] In various embodiments of the present invention, the execution of instruction sequences may be performed by computer system 1000 to practice embodiments of the present invention. In various other embodiments of the present invention, multiple computer systems 1000 coupled by communication link 1020 (e.g., communication network, such as LAN, WLAN, PTSN and / or various other wired or wireless networks, including telecommunications, mobile and cellular telephone networks) may cooperate with each other to execute instruction sequences to practice embodiments of the present invention.

[0062] Computer system 1000 may transmit and receive messages, data, information, and instructions, including one or more programs (i.e., application code), through communication link 1020 and communication interface 1012. Received program code may be executed by processor 1004 when received and / or stored in disk drive component 1010 or some other non-volatile storage component for execution.

[0063] Where appropriate, hardware, software, or a combination of hardware and software may be used to implement the various embodiments provided by the embodiments of the present invention. In addition, where appropriate, the various hardware components and / or software components described herein may be combined into composite components comprising software, hardware, and / or both without departing from the spirit of the embodiments of the present invention. Where appropriate, the various hardware components and / or software components described herein may be separated into subcomponents comprising software, hardware, or both without departing from the scope of the embodiments of the present invention. In addition, where appropriate, it may be considered that software components are implemented as hardware components, and vice versa.

[0064] According to embodiments of the present invention, software (e.g., program code and / or data) may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more general or special-purpose computers and / or computer systems connected over a network and / or in other ways. Where appropriate, the order of the various steps described herein may be changed, combined into composite steps, and / or separated into sub-steps to provide the features described herein.

[0065] In brief, to reduce the time required to perform data preparation associated with mask design, the OPC process is performed on the corrected area rather than the entire layout or chip area. When the DOM of the OPC process is more complex in advanced technology nodes, an ILT process is applied to perform on the junction area between the corrected area and the initial area to repair the DOM conflict, so that the time-saving OPC process can be applied to the advanced technology nodes.

[0066] In some embodiments, an embodiment of the present invention provides a method for producing an integrated circuit (IC). The method includes: receiving a first IC design layout by a processor; replacing a specific region in the first IC design layout with a first difference region by the processor; performing an inverse lithography technology (ILT) process on a junction region between the first difference region and the first IC design layout by the processor to generate mask data; and causing the IC to be manufactured according to the mask data.

[0067] In some embodiments, an embodiment of the present invention provides a method for producing an IC. The method includes: receiving a first IC design layout by a processor; comparing the first IC design layout with a second IC design layout by the processor to identify a difference area; performing an OPC process on the difference area by the processor to form an OPC-processed difference area; merging the OPC-processed difference area with the OPC-processed IC design layout by the processor; performing an ILT process on a first line of the OPC-processed difference area and a second line of the OPC-processed IC design layout by the processor to generate mask data; and causing the IC to be manufactured according to the mask data.

[0068] In some embodiments, embodiments of the present invention provide a non-transitory computer-readable medium having instructions embodied thereon, the instructions being executable by a processor to perform a method, the method comprising: receiving a first IC design layout; replacing a specific region in the first IC design layout with a first difference region; and performing an ILT process on a junction region between the first difference region and the first IC design layout to generate mask data.

[0069] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions should not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions, and modifications to this document without departing from the spirit and scope of the embodiments of the present invention.

[0070] Explanation of symbols

[0071] 100 Integrated Circuit (IC) Manufacturing System

[0072] 110 Design Studio

[0073] 112 IC Design Layout

[0074] 120 Mask Manufacturing Plant

[0075] 122 Mask Data Preparation

[0076] 124 Mask tool processing

[0077] 130 IC Manufacturers

[0078] 140 IC devices

[0079] 150 Logical Operations (LOP)

[0080] 160 Retargeting Process (RET)

[0081] 170 Optical Proximity Correction (OPC)

[0082] 180 Fracture Process (FRAC)

[0083] 200 Methods

[0084] 202 Operation

[0085] 204 Operation

[0086] 206 Operation

[0087] 208 Operation

[0088] 210 Operation

[0089] 212 Operation

[0090] 214 Operation

[0091] 216 Operation

[0092] 218 Operation

[0093] 220 Operation

[0094] 222 Operation

[0095] 302 Revised IC Design Layout

[0096] 304 Initial IC Design Layout

[0097] 306 Difference Area

[0098] 308 Layout Block

[0099] 310 Layout Block

[0100] 312 Range

[0101] 314 Range

[0102] 316 Partial area

[0103] 402 OPC processed difference area

[0104] 404 Border Patch

[0105] 406 Original Mask

[0106] 408 OPC processed mask

[0107] 410 Print auxiliary features

[0108] 412 Non-printing auxiliary features

[0109] 414 Final Pattern

[0110] 416 Pattern

[0111] 500 IC design layout processed by OPC

[0112] 502 Layout block processed by OPC

[0113] 504 OPC Range

[0114] 506 Specific OPC treated areas

[0115] 600 Cut IC design layout processed by OPC

[0116] 602 blank area

[0117] 700 Revised IC design layout after OPC processing

[0118] 702 Knot Region

[0119] 704 Boundary

[0120] 802 Part

[0121] 804 First Metal Line Layout

[0122] 806 Second Metal Line Layout

[0123] 808 Metal Line Layout

[0124] 810 Metal Line Layout

[0125] 812 Layout section

[0126] 814 Layout section

[0127] 816 Layout section

[0128] 818 Layout section

[0129] 820 stairs

[0130] 902 Initial Mask

[0131] 904 Gradient Field

[0132] 906 Update Mask

[0133] 908 parts

[0134] 910 Edge

[0135] 912 Edge

[0136] 1000 Computer Systems

[0137] 1002 Bus

[0138] 1004 Processing Components / Processors

[0139] 1006 System Memory Components

[0140] 1008 Static Storage Component

[0141] 1010 Disk Drive Assembly

[0142] 1012 Network Interface Components

[0143] 1014 Display Components

[0144] 1016 Input Components

[0145] 1018 Cursor Control Component

[0146] 1020 Communication Link

[0147] V1 Vector

[0148] V2 Vector

[0149] V3 Vector

[0150] w1 width

[0151] w2 width

Claims

1. A method for producing an integrated circuit IC, the method comprising: Receiving, by a processor, a first IC design layout and a second IC design layout; comparing, by the processor, the first IC design layout and a second IC design layout to identify a first difference region of the first IC design layout that is different from the second IC design layout; segmenting, by the processor, the first difference region from the first IC design layout; and performing, by the processor, an optical proximity correction (OPC) process on the first difference area to generate a second difference area; replacing, by the processor, a specific region in a third IC design layout with the second difference region; performing, by the processor, an inverse lithography technology (ILT) process on a junction region between the second difference region and the third IC design layout to generate mask data; and The IC is caused to be manufactured according to the mask data. 2 . The method of claim 1 , wherein the third IC design layout is an OPC-processed IC design layout of the second IC design layout.

3. The method according to claim 1, wherein replacing the specific area in the third IC design layout with the second difference area comprises: identifying, by the processor, a first position of the specific region in the third IC design layout according to a second position of the first difference region in the first IC design layout; removing, by the processor, the specific region in the third IC design layout to generate a blank region in the first position of the third IC design layout; and The second difference region is placed, by the processor, into the blank region of the third IC design layout. 4 . The method according to claim 3 , wherein the first position of the specific region on the third IC design layout is the same as the second position of the first difference region on the first IC design layout.

5. The method of claim 1 , wherein performing an ILT process on the junction region between the second difference region and the third IC design layout to generate the mask data comprises: identifying, by the processor, a first line of the second difference region in the junction region and a second line of the third IC design layout; Determining, by the processor, whether a mask size DOM conflict occurs by comparing, by the processor, a first width on the first line with a second width on the second line; The ILT process is performed by the processor on the first line and the second line (806) to generate the mask data for the junction region. The method of claim 5 , wherein the mask size conflict occurs when the first width is different from the second width. 7 . The method of claim 5 , wherein the first line of the second difference region is connected with the second line of the third IC design layout in the junction region.

8. A method for producing an integrated circuit IC, the method comprising: receiving, by a processor, a first IC design layout; comparing, by the processor, the first IC design layout and the second IC design layout to identify areas of difference; performing, by the processor, an OPC process on the difference area to form an OPC-processed difference area; merging, by the processor, the OPC processed difference region with the OPC processed IC design layout; performing, by the processor, an inverse lithography technology (ILT) process on the first line of the OPC processed difference area and the second line of the OPC processed IC design layout to generate mask data; and The IC is caused to be manufactured according to the mask data.

9. The method of claim 8, wherein performing the inverse lithography technology (ILT) process on the first line of the OPC processed difference area and the second line of the OPC processed IC design layout to generate the mask data comprises: Determining, by the processor, whether a mask size DOM conflict occurs by comparing, by the processor, a first width on the first line with a second width on the second line; and When the mask size conflict occurs, the processor performs the ILT process on the first line and the second line to generate the mask data. 10 . The method of claim 9 , wherein a mask size conflict occurs when the first width is different from the second width.

11. The method of claim 9, wherein the first line of the OPC processed difference area is connected to the second line of the OPC processed IC design layout.

12. A non-transitory computer-readable medium having instructions embodied thereon, the instructions executable by a processor to perform a method comprising: receiving a first IC design layout and a second IC design layout; comparing, by the processor, the first IC design layout and a second IC design layout to identify a first difference region of the first IC design layout that is different from the second IC design layout; segmenting, by the processor, the first difference region from the first IC design layout; and performing, by the processor, an optical proximity correction (OPC) process on the first difference area to generate a second difference area; replacing a specific region in the third IC design layout with the second difference region; and An inverse lithography technology (ILT) process is performed on a junction region between the second difference region and the third IC design layout to generate mask data.

13. The non-transitory computer-readable medium of claim 12, wherein the third IC design layout is an OPC-processed IC design layout of the second IC design layout.

14. The non-transitory computer-readable medium of claim 12, wherein replacing the specific region in the third IC design layout with the second difference region comprises: identifying a first position of the specific region in the third IC design layout according to a second position of the first difference region in the first IC design layout; removing the specific area in the third IC design layout to generate a blank area in the first position of the third IC design layout; and The second difference region is placed into the blank region of the third IC design layout. 15 . The non-transitory computer-readable medium of claim 14 , wherein the first position of the specific region on the third IC design layout is the same as the second position of the first difference region on the first IC design layout.

16. The non-transitory computer-readable medium of claim 12, wherein performing an ILT process on the junction region between the second difference region and the third IC design layout to generate the mask data comprises: identifying a first line of the second difference region in the junction region and a second line of the third IC design layout; determining whether a mask size DOM conflict occurs by comparing a first width on the first line with a second width on the second line; and When the mask size conflict occurs, the ILT process is performed on the first line and the second line to generate the mask data.

17. The non-transitory computer-readable medium of claim 16, wherein the mask size conflict occurs when the first width is different from the second width. 18 . The non-transitory computer readable medium of claim 16 , wherein the first line of the second difference region is connected with the second line of the third IC design layout in the junction region.

Images