storage device

Abstract

The present invention provides a storage device comprising: a plurality of bit lines extending in a first direction; a plurality of lower storage cells below and connected to the plurality of bit lines; and a plurality of upper storage cells above and connected to the plurality of bit lines. The storage device includes a plurality of cell array regions and a plurality of bit line contact regions alternately stacked in the first direction, wherein the plurality of upper storage cells and the plurality of lower storage cells are located in the cell array regions, and at least one of the plurality of upper storage cells or at least one of the plurality of lower storage cells is arranged in at least one of the bit line contact regions.

Description

Technical Field

[0001] Various exemplary embodiments of the present invention relate to storage devices. Background Technology

[0002] Storage devices can provide the functions of recording (e.g., writing), erasing, and / or retrieving recorded data. Recently, there has been active research into storage devices that utilize resistance changes to write or erase data. Storage devices using resistors include phase-change random access memory (PRAM), resistive RAM (ReRAM), and magnetic RAM (MRAM). Summary of the Invention

[0003] One aspect of at least one exemplary embodiment of the present invention provides a storage device including storage cells above a region, wherein bit lines and circuit regions are connected in the region.

[0004] In at least one example embodiment, a storage device includes: a plurality of bit lines extending in a first direction; a plurality of lower storage cells below the plurality of bit lines, the plurality of lower storage cells being connected to the plurality of bit lines; a plurality of upper storage cells above the plurality of bit lines, the plurality of upper storage cells being connected to the plurality of bit lines; a plurality of cell array regions and a plurality of bit line contact regions alternately arranged in the first direction, the plurality of cell array regions including the plurality of upper storage cells and the plurality of lower storage cells, and at least one of the plurality of upper storage cells or at least one of the plurality of lower storage cells being arranged in at least one of the plurality of bit line contact regions.

[0005] In at least one example embodiment, a storage device includes: a plurality of bit lines located at different heights from an upper surface of a substrate, the plurality of bit lines extending parallel to the upper surface of the substrate in a first direction; a plurality of word lines located at different heights from the plurality of bit lines in a direction perpendicular to the upper surface of the substrate, the plurality of word lines extending in a second direction intersecting the first direction; and a plurality of storage layers, each storage layer including a plurality of storage cells disposed between the plurality of bit lines and the plurality of word lines adjacent to each other in a direction perpendicular to the upper surface of the substrate, the uppermost storage layer of the plurality of storage layers including a greater number of storage cells than the number of storage cells included in each of the remaining storage layers of the plurality of storage layers.

[0006] In at least one example embodiment, a memory device includes: a substrate comprising a plurality of unit regions; a plurality of bit lines extending in a first direction parallel to an upper surface of the substrate; a plurality of lower word lines between the plurality of bit lines and the upper surface of the substrate, the plurality of lower word lines extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a plurality of upper word lines extending in the second direction above the plurality of bit lines; a plurality of word line contact regions including a plurality of upper word line contacts connected to the plurality of upper word lines, the plurality of word line contact regions being between the plurality of unit regions; and a plurality of memory cells between the plurality of bit lines and the plurality of lower word lines and between the plurality of bit lines and the plurality of upper word lines, the number of the plurality of upper word lines being greater than the number of the plurality of lower word lines. Attached Figure Description

[0007] The above and other aspects, features, and advantages of exemplary embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 and Figure 2 This is a schematic diagram illustrating a storage device according to at least one exemplary embodiment;

[0009] Figure 3 This is a block diagram schematically illustrating a storage device according to at least one example embodiment;

[0010] Figures 4 to 7 It is a diagram illustrating the arrangement of storage cells in a storage device according to at least one exemplary embodiment;

[0011] Figure 8 This is a view showing the stacked structure of a storage device according to at least one example embodiment;

[0012] Figure 9 This is a diagram illustrating a comparative example of the planar structure of a storage device according to at least one exemplary embodiment;

[0013] Figure 10 This is a diagram schematically illustrating the planar structure of a storage device according to at least one exemplary embodiment;

[0014] Figure 11 It is based on at least one example implementation. Figure 10 An enlarged perspective view of area A1;

[0015] Figure 12 It is based on at least one example implementation along Figure 11 A cross-sectional view taken from line I-I';

[0016] Figure 13It is based on at least one example implementation. Figure 10 An enlarged perspective view of area B1;

[0017] Figure 14 It is based on at least one example implementation along Figure 13 A cross-sectional view taken from line II-II';

[0018] Figure 15 It is based on at least one example implementation. Figure 10 An enlarged perspective view of region C1;

[0019] Figure 16 It is based on at least one example implementation along Figure 15 A cross-sectional view taken from line III-III';

[0020] Figure 17 This is a diagram schematically illustrating the planar structure of a storage device according to at least one exemplary embodiment;

[0021] Figure 18 It is based on at least one example implementation. Figure 17 An enlarged perspective view of region C2;

[0022] Figure 19 It is based on at least one example implementation along Figure 18 A cross-sectional view taken from line IV-IV';

[0023] Figure 20 and Figure 21 This is a schematic diagram illustrating the planar structure of a storage device according to some example embodiments;

[0024] Figure 22 and Figure 23 This is a diagram illustrating the operation of a storage device according to some example embodiments;

[0025] Figure 24 This is a diagram schematically illustrating the planar structure of a storage device according to at least one exemplary embodiment;

[0026] Figure 25 It is based on at least one example implementation along Figure 24 A cross-sectional view taken from line V-V';

[0027] Figure 26 It is based on at least one example implementation along Figure 24 A cross-sectional view taken from line VI-VI'; and

[0028] Figure 27 This is a schematic block diagram illustrating an electronic device including a storage device according to at least one example embodiment. Detailed Implementation

[0029] Various exemplary embodiments will be described below with reference to the accompanying drawings. However, these exemplary embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments of the inventive concept to those skilled in the art. In the drawings, the thickness of layers and regions has been enlarged for clarity. The same reference numerals and / or numbers in the drawings denote the same elements, and therefore their description may be omitted.

[0030] For ease of description, spatial relational terms such as “below,” “under,” “down,” “above,” “above,” etc., may be used herein to describe the relationship of one element or feature to other elements(s) or features(s) as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relational terms are also intended to cover other different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will be oriented “above” said other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0031] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate structures) of the example embodiments. Thus, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments should not be construed as limited to the specific shapes of the areas shown herein, but will include, for example, deviations in shape caused by manufacturing processes. For example, an injection area shown as rectangular may have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from an injection area to a non-injection area. Similarly, an embedded area formed by injection may result in some injection in the area between the embedded area and the surface through which the injection occurs. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the example embodiments.

[0032] Although corresponding plan views and / or perspective views of some cross-sectional views may not be shown, the cross-sectional views(s) of the device structures shown herein support multiple device structures extending in two different directions (as will be shown in the plan views) and / or three different directions (as will be shown in the perspective views). The two different directions may be orthogonal to each other or may not be orthogonal to each other. The three different directions may include a third direction orthogonal to the two different directions. The multiple device structures may be integrated into the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in a cross-sectional view, the electronic device may include multiple device structures (e.g., memory cell structures or transistor structures), as will be shown in a plan view of the electronic device. The multiple device structures may be arranged in an array and / or in a two-dimensional pattern.

[0033] Figure 1 and Figure 2 This is a diagram schematically illustrating a storage device according to at least one example embodiment.

[0034] First refer to Figure 1 The storage device 1 according to at least one exemplary embodiment may include a cell region 2, a peripheral circuit region (or peripheral region) 3, and / or a pad region 4, etc., but the exemplary embodiment is not limited thereto. In the cell region 2, storage cells are formed, word lines and / or bit lines connected to the storage cells are formed, and the cell region 2 may include multiple cell regions. The pad region 4 may be a region in which multiple pads for inputting and / or outputting control commands and data are formed, and the peripheral circuit region 3 is a region in which various circuits desired and / or required for the operation of the storage device 1 are formed.

[0035] According to some exemplary embodiments, the memory cells included in cell region 2 may be located in multiple layers, but the exemplary embodiments are not limited to this. For example, at least a portion of the memory cells in different layers may also share word lines and / or bit lines, etc.

[0036] Peripheral circuit region 3 may include decoder circuitry, read / write circuitry, power supply circuitry, and / or control logic circuitry, but the example embodiments are not limited thereto. Control logic circuitry may control decoder circuitry, read / write circuitry, power supply circuitry, etc., but the example embodiments are not limited thereto. For example, decoder circuitry may identify at least one of the memory cells formed in cell region 2 as a selected memory cell, and read / write circuitry may read data from the selected memory cell and / or write data to the selected memory cell. In at least one example embodiment, at least a portion of the circuitry included in peripheral circuit region 3 may also be located below cell region 2, as will be referred to below. Figure 2 It is described, but not limited to.

[0037] refer to Figure 2 According to at least one example embodiment, at least a portion of the peripheral circuitry region 3 may be located below the cell region 2 in the storage device 1, but is not limited thereto. For example, decoder circuitry connected to word lines and / or bit lines, as well as read / write circuitry for reading and / or writing data, may be located below the cell region 2. Because the decoder circuitry connected to the word lines and bit lines included in the cell region 2 is located below the cell region 2, the electrical characteristics of the storage device can be improved.

[0038] In at least one example embodiment, the decoder circuit may include word line decoders connected to word lines and bit line decoders connected to bit lines, etc. As described above, memory cells may be located in multiple layers within cell region 2, and memory cells in different layers may be connected to different word lines and / or different bit lines. Within cell region 2, memory cells, word lines, and bit lines may be connected in a cross-point structure, but the example embodiment is not limited to this.

[0039] For example, an upper memory cell can be connected to an upper word line, and a lower memory cell in a lower layer can be connected to a lower word line, but the example implementation is not limited to this. The upper and lower word lines can share a single word line decoder, or according to some example implementations, they can be connected to different word line decoders, but this is not a limitation. According to some example implementations, different word line decoders can also be connected to a single read / write circuit, but this is not a limitation.

[0040] For example, cell region 2 may include lower word lines, lower memory cells, bit lines, upper memory cells, and / or upper word lines, etc., sequentially stacked on peripheral circuit region 3. Since there are no other word lines, bit lines, and / or memory cells, etc., between the lower word lines and peripheral circuit region 3, the lower word lines can be connected to peripheral circuit region 3 without any restrictions or with very few restrictions.

[0041] On the other hand, it may be necessary to connect the bit lines and upper word lines to the peripheral circuitry region 3 to avoid interference between the memory cells and the lower word lines. For example, the memory cells may not be located in the bit line contact area where the bit lines connect to the peripheral circuitry region 3. In at least one example embodiment, the lower memory cell may be omitted from the bit line contact area, and the upper memory cell may be connected to the bit line contact area, thereby improving the integration of the memory device 1. Furthermore, the reliability of the memory device 1 can be improved by utilizing the upper memory cells in the bit line contact area for redundancy and / or testing.

[0042] Figure 3 This is a block diagram schematically illustrating a storage device according to at least one example embodiment.

[0043] A storage device 10 according to at least one example embodiment may include a storage controller 20 and / or a storage cell array 30, etc. The storage controller 20 may include decoder circuits 21 and 22, read / write circuitry 23, control logic circuitry 24, etc. The storage cell array 30 may include a plurality of storage cells. The decoder circuits 21 and 22 may include a word line decoder 21 connected to the plurality of storage cells via word lines WL, and a bit line decoder 22 connected to the plurality of storage cells via bit lines BL, etc. The operation of the word line decoder 21, the bit line decoder 22, and the read / write circuitry 23 may be controlled by the control logic circuitry 24. The control logic circuitry 24 may include: hardware containing logic circuitry; a hardware / software combination executing software, such as at least one processor; or a combination thereof. For example, the control logic circuitry 24 may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. In at least one example implementation, the read / write circuit 23 may include program circuitry for writing data to at least one selected memory cell specified by the word line decoder 21 and the bit line decoder 22, and readout circuitry for reading data from the selected memory cell.

[0044] As described above, the word line decoder 21 and the bit line decoder 22 can be located below the memory cell array 30, but are not limited thereto. Therefore, the wiring connecting the word line WL and the word line decoder 21 and / or connecting the bit line BL and the bit line decoder 22 can be further simplified. According to some example embodiments, the read / write circuitry 23 can also be located below the memory cell array 30 together with the word line decoder 21 and the bit line decoder 22.

[0045] Figures 4 to 7 This is a diagram illustrating the arrangement of storage cells in a storage device according to some example embodiments. Figures 4 to 7 It can be a schematic diagram showing the memory cells, word lines, and bit lines included in a memory device.

[0046] Figure 4 and Figure 5 This may be a view illustrating comparative examples of storage devices according to some example embodiments. (Refer to...) Figure 4 and Figure 5The memory cell array 40 may include bit lines BL1 to BLn extending in a first direction (e.g., the Y-axis direction) and word lines LWL1, LWL2, ..., LWLi-1, LWLi, LWLi+1, LWLi+2, ..., LWLm-1 and LWLm, and UWL1, UWL2, ..., UWLi-1, UWLi, UWLi+1, UWLi+2, ..., UWLm-1 and UWLm extending in a direction different from the bit lines BL1 to BLn, such as a second direction (e.g., the X-axis direction). However, the example implementation is not limited to this. The first direction and the second direction are directions that intersect each other and may, for example, be perpendicular to each other, but are not limited to this.

[0047] The lower memory cell (LMC) can be located between bit lines BL1 to BLn and lower word lines LWL1 to LWLm, while the upper memory cell (UMC) can be located between bit lines BL1 to BLn and upper word lines UWL1 to UWLm. The lower memory cell (LMC) and the upper memory cell (UMC) can have the same structure, but are not limited to this.

[0048] For example, each of the lower memory cell LMC and the upper memory cell UMC may include a switching element SW and / or a memory element ME, etc. In at least one example embodiment, the switching element SW may include at least one of a PN junction diode, a Schottky diode, and / or a bidirectional threshold switch (OTS), or any combination thereof. In at least one example embodiment, the memory element ME may be formed using a phase change material including, but not limited to, chalcogenide materials and / or superlattices. For example, the memory element ME may include a phase change material capable of undergoing a phase transition between an amorphous phase and a crystalline phase based on heating time and temperature. The memory element ME and the switching element SW may be connected in series with each other, but are not limited to this. The order in which the memory element ME and the switching element SW are connected is not limited and can be changed. For example, the memory element ME and the switching element SW may be sequentially connected between word lines LWL1 to LWLm and UWL1 to UWLm and bit lines BL1 to BLn, etc.

[0049] Reference Figure 4 and Figure 5 The lower word lines LWL1 to LWLm, the upper word lines UWL1 to UWLm, and the memory cells LMC and UMC may not be in at least some of these regions. Therefore, as Figure 4 and Figure 5 As shown, a relatively large space can be ensured between the portion of the lower word lines LWL1 to LWLm and the portion of the upper word lines UWL1 to UWLm, but it is not limited to this. This space can be a bit line contact area, in which bit lines BL1 to BLm are connected to the bit line decoder 41 via bit line contacts BC, etc.

[0050] Figure 6 and Figure 7 This is a schematic diagram of a storage cell array 50 included in a storage device according to some example embodiments. (Refer to...) Figure 6 and Figure 7 The memory cell array 50 includes bit lines BL1 to BLn extending in a first direction (e.g., the Y-axis direction) and word lines LWL1 to LWLm and UWL1 to UWLm extending in a direction different from the bit lines BL1 to BLn, such as a second direction (e.g., the X-axis direction), but is not limited thereto. The lower memory cell LMC can be located between the bit lines BL1 to BLn and the lower word lines LWL1 to LWLm, and the upper memory cell UMC can be located between the bit lines BL1 to BLn and the upper word lines UWL1 to UWLm. The lower memory cell LMC and the upper memory cell UMC can have the same structure, but are not limited thereto. Each of the memory cells LMC and UMC can include a memory element ME and a switching element SW. As described above, the connection order of the memory element ME and the switching element SW is not limited and can be changed. Furthermore, the connection order of the memory element ME and the switching element SW in the lower memory cell LMC and the upper memory cell UMC can be different from each other.

[0051] Reference Figure 6 and Figure 7 In some example implementations, the upper word lines UWLm+1 and UWLm+2 and the upper memory unit UMC may be further located in the bit line contact region of the bit line decoder 51, where the bit lines BL1 to BLn are connected to the bit line decoder 51 via the bit line contact BC. For example, only the upper word lines UWLm+1 and UWLm+2 and the upper memory unit UMC may be in the bit line contact region, but the example implementation is not limited to this. According to some other example implementations, the lower word lines LWL1 to LWLm and the lower memory unit LMC may be in the bit line contact region. Therefore, with Figure 4 and Figure 5 Compared to the example implementation shown, the integration of the storage device can be improved.

[0052] Additionally, the reliability of the memory device can be improved by using upper memory cells (UMCs) in the bit line contact area for redundancy. Since the upper memory cells (UMCs) in the bit line contact area are connected to the added upper word lines UWLm+1 and UWLm+2, the upper word lines UWLm+1 and UWLm+2 in the bit line contact area can be used for word line redundancy. For example, if a word line is found to be defective (e.g., defective, non-functional, etc.) among the lower word lines LWL1 to LWLm and the upper word lines UWL1 to UWLm, that word line can be replaced by the upper word lines UWLm+1 and UWLm+2 added to the bit line contact area.

[0053] In at least one example embodiment, the upper memory cell (UMC) in the bit line contact region can be used to test the memory device. During the testing process after the memory device is manufactured, the upper memory cell (UMC) in the bit line contact region can be tested instead of the normal memory cell, thereby significantly reducing stress on the normal memory cell and thus improving the reliability of the memory device.

[0054] Figure 8 This is a view showing the stacked structure of a storage device according to at least one example embodiment.

[0055] Reference Figure 8 The storage device 100 according to at least one example embodiment may include, but is not limited to, multiple layers 110 to 150, etc. The multiple layers (e.g., layers 110 to 150, etc.) may include a lower storage layer 110, an upper storage layer 120, a bit line layer 130, a lower word line layer 140, an upper word line layer 150, etc. The bit line layer 130 includes multiple bit lines BL, the lower word line layer 140 includes multiple lower word lines LWL, and the upper word line layer 150 includes multiple upper word lines UWL.

[0056] The lower storage layer 110 may include a plurality of lower storage cells, and the lower storage layer 110 may be located between the bit line layer 130 and the lower word line layer 140, but is not limited thereto. The lower storage cells may be connected to at least one of the bit lines BL and at least one of the lower word lines LWL, respectively. The upper storage layer 120 may include a plurality of upper storage cells, and the upper storage layer 120 may be located between the bit line layer 130 and the upper word line layer 150, but is not limited thereto. The upper storage cells may be connected to at least one of the bit lines BL and at least one of the upper word lines UWL, respectively. According to at least one example embodiment, the upper storage cells and the lower storage cells may share the bit line BL, but are not limited thereto. For example, the upper storage cells may be connected to the upper surface (or top surface) of the bit line BL, and the lower storage cells may be connected to the lower surface (or bottom surface) of the bit line BL, respectively.

[0057] According to some example implementations, only one of the top and bottom surfaces of the bit line BL can be connected to a memory cell, or in other words, a single surface of the bit line BL can be connected to a memory cell, etc. For example, the upper memory cell above the bit line BL and the lower memory cell below the bit line BL may not share the bit line BL. In this case, the lower memory cell in the lower memory layer 110 and the upper memory cell in the upper memory layer 120 can be connected to different bit lines BL.

[0058] The storage device 100 may include a plurality of unit regions UA. The unit region UA ​​may be a region extending in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction), but the example implementation is not limited thereto. In each unit region UA, the bit line BL may extend in the first direction, and the upper word line UWL and the lower word line LWL may extend in a direction different from the bit line BL, such as the second direction, but the example implementation is not limited thereto.

[0059] In each unit region UA, the number of bit lines BL may be different from or the same as the number of upper word lines UWL and / or lower word lines LWL. For example, according to at least one example embodiment, the number of upper word lines UWL may be greater than the number of bit lines BL, and the number of lower word lines LWL may also be greater than the number of bit lines BL. For example, the number of upper word lines UWL and / or the number of lower word lines LWL may be equal to twice the number of bit lines BL, but is not limited thereto. Additionally, in at least one example embodiment, the length of each unit region UA ​​in the first direction may be greater than its length in the second direction, for example, it may be twice or more its length in the second direction, but is not limited thereto.

[0060] Furthermore, in the upper word line (UWL) and lower word line (LWL), the number of word lines connected to the storage cells storing data can be greater than, or the same as, the number of bit lines connected to the storage cells storing data, or they can be the same, etc. Specifically, aside from storage cells used for redundancy and / or testing purposes of the storage device, according to at least one example embodiment, the number of word lines connected to the storage cells storing data can be greater than the number of bit lines connected to the storage cells storing data, but is not limited thereto. For example, the number of word lines connected to the storage cells storing data can be twice or more the number of bit lines connected to the storage cells storing data, but is not limited thereto.

[0061] The lower memory layer 110 may include multiple cell array regions (such as cell array regions 111 and 112) and / or multiple bit line contact regions (such as bit line contact regions 113 to 115). Cell array regions 111 and 112 and bit line contact regions 113 to 115 may be arranged alternately in a first direction (e.g., stacked, layered, etc.). The multiple bit line contact regions may have a physical area smaller than the physical area of ​​the multiple cell array regions. For example, the lower memory cell may be located only in cell array regions 111 and 112 and may not be located in bit line contact regions 113 to 115. Therefore, the lower word line (LWL) may also be located only in cell array regions 111 and 112.

[0062] Bit line contact regions 113 to 115 may be regions where the bit line BL is connected to a bit line contact extending in a third direction (e.g., the Z-axis direction), but are not limited thereto. The bit line contact connected to the bit line BL may be connected to circuitry below the lower word line layer 140 and the lower memory layer 110. Therefore, the lower memory cell LMC and the lower word line LWL may not be located on the bit line contact regions 113 to 115 to ensure space for connecting the bit line BL and the bit line contact.

[0063] The lower storage layer 110 can be divided into multiple lower unit regions (LUA). Lower word lines (LWL) can be separated between the multiple lower unit regions (LUA). Furthermore, word line contact regions 116 and 117 can be located between the multiple lower unit regions (LUA).

[0064] Bitline layer 130 can be divided into multiple unit regions UA. Each unit region UA ​​of bitline layer 130 can correspond to a lower unit region LUA. For example, the space between unit regions UA can correspond to word line contact regions 116 and 117 between lower unit regions LUA.

[0065] The upper storage layer 120 may include cell array regions 121 and 122 and bit line contact regions 123 arranged alternately (e.g., stacked, layered, etc.) in a first direction. The upper storage cells and upper word lines (UWL) may be located only in the cell array regions 121 and 122 and may not be located in the bit line contact region 123. However, the bit line contact connected to the bit line BL may not be located in the bit line contact region 123 of the upper storage layer 120. In this case, the upper storage cells and upper word lines (UWL) may also be located in the bit line contact region 123, but are not limited thereto.

[0066] The upper storage layer 120 may include multiple upper unit regions UUA, and the upper unit regions UUA and lower unit regions LUA may be arranged in a second direction, for example, in a zigzag pattern, but the example implementation is not limited to this. For example, the space between the upper unit regions UUA may be located in the center of the lower unit regions LUA, etc.

[0067] The word line contact areas 126 and 127 included in each upper unit region UUA can correspond to the word line contact areas 116 and 117 between the lower unit regions LUA. Additionally, the bit line BL may not be located below the word line contact areas 126 and 127 included in each upper unit region UUA; in other words, the bit line BL may not be in physical contact with the word line contact areas 126 and 127. Therefore, the word line contacts connected to the upper word line UWL can be connected to the circuitry below the lower word line layer 140 via the word line contact areas 126 and 127 of the upper memory layer 120 and the word line contact areas 116 and 117 of the lower memory layer 110.

[0068] exist Figure 8 In at least one example embodiment shown, the upper storage layer 120 may be the uppermost layer among the storage layers included in the storage device 100, and the storage layer may further lie below the lower storage layer 110, but is not limited thereto. In at least one example embodiment, since space for the connection of bit line contacts and bit lines BL should be ensured in the storage layers other than the uppermost storage layer, the storage cells may not be located in the bit line contact regions 113 to 115. On the other hand, due to the connection of the bit lines BL and bit line contacts, the storage cells in the uppermost storage layer can be positioned without any restrictions or with very few restrictions.

[0069] According to some example embodiments, the memory cells may be further located above the upper word line layer 150 and / or below the lower word line layer 110. In at least one example embodiment, the memory cells on the upper word line layer 150 may also share the upper word line UWL with the upper memory cells included in the upper memory layer 120, but are not limited thereto. Additionally, additional word lines may be further formed on the upper word line layer 150, and the memory cells may also be connected to the additionally formed word lines. Similarly, memory cells located below the lower word line layer 140 may share the lower word line LWL with the lower memory cells included in the lower memory layer 110 or may not share the lower word line LWL.

[0070] Figure 9 This is a diagram illustrating a comparative example of the planar structure of a storage device according to at least one exemplary embodiment.

[0071] Figure 9 This could be a plan view showing a portion of the peripheral circuitry area beneath the memory cells in storage device 200. (See reference) Figure 9 The peripheral circuit region can be divided into unit regions UA. The unit region UA ​​can be at least two-dimensional, for example, arranged in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction), but the example implementation is not limited thereto. Memory cells, bit lines and / or word lines, etc., can be located on the peripheral circuit region in a third direction (e.g., the Z-axis direction), but are not limited thereto.

[0072] The peripheral circuit region may include a bit line decoder region 201, multiple word line decoder regions 202 and 203, a circuit region 204, a word line contact region 205, a bit line contact region 206, etc. The word line contact regions 205 may be between unit regions UA, and each unit region UA ​​may include at least a first sub-unit region and a second sub-unit region separated by the bit line contact regions 206 in a first direction.

[0073] A bitline decoder connected to a bitline via a bitline contact can be located in bitline decoder region 201. In at least one example embodiment, the bitline may be positioned above the peripheral circuitry region in a third-direction orientation and may extend in a first direction. The bitline decoder may include a switching device connected to the bitline contact and may select at least one bitline based on the on / off operation of the switching device, but the example embodiments are not limited thereto.

[0074] Word line decoder regions 202 and 203 may include, but are not limited to, lower word line decoder region 202 and / or upper word line decoder region 203, etc. The lower word line decoder in the lower word line decoder region 202 can be connected to the lower word line through a first set of word line contacts, and the upper word line decoder in the upper word line decoder region 203 can be connected to the upper word line through a second set of word line contacts (e.g., other word line contacts).

[0075] The lower word line and the upper word line may extend in a second direction, with the lower word line extending in a third direction between the peripheral circuit region and the bit line, and the upper word line extending in a third direction on the bit line, but the example implementation is not limited thereto. The lower word line decoder and the upper word line decoder may include a switching device connected to the word line contact, and at least one of the lower word line and the upper word line may be selected according to the on / off state of the switching device, but the example implementation is not limited thereto.

[0076] Bit line contacts connected to bit line 207 can be formed in bit line contact region 206. Additionally, circuit lines 208 connected to components in bit line decoder region 201 can extend into bit line contact region 206. (See reference...) Figure 9 The width W1 of each bit line 207 may, for example, be smaller than the width W2 of each circuit line 208, but is not limited thereto. There are limitations to reducing the width W2 of each circuit line 208, and all bit line contacts connected to the bit lines BL included in each unit region UA ​​may not be connected to the circuit lines 208 in a bit line contact region 206.

[0077] In at least one exemplary embodiment of the present invention, bit line contacts and circuit lines can be connected to multiple bit line contact regions in each unit region UA. Furthermore, in at least one of the bit line contact regions, a memory cell can be located above a bit line. Therefore, the reduction in the integration density of the memory device due to the increased number of bit line contact regions can be reduced and / or prevented, thereby improving the performance, efficiency, and / or lifespan of the memory device.

[0078] Figure 10 This is a diagram schematically illustrating the planar structure of a storage device according to at least one example embodiment.

[0079] Figure 10This could be a plan view showing a portion of the peripheral circuitry area beneath the memory cells in storage device 300. (Refer to...) Figure 10 The peripheral circuit region may include multiple unit regions UA arranged in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction), but the example implementation is not limited thereto. Memory cells, bit lines, and / or word lines may be located above the peripheral circuit region in a third direction (e.g., the Z-axis direction).

[0080] The peripheral circuit region may include a bit line decoder region 301, multiple word line decoder regions 302 and 303, circuit region 304, word line contact region 305, bit line contact region 306, etc., but the example implementation is not limited thereto. The word line contact region 305 may exist between unit regions UA, and each unit region UA ​​may include a first sub-unit region and / or a second sub-unit region separated in a first direction by the bit line contact region 306, etc. In each unit region UA, the bit line decoder region 301, word line decoder regions 302 and 303, circuit region 304, word line contact region 305, and bit line contact region 306, etc., may have a rotationally symmetrical structure relative to the center of the first bit line contact region 306A, or in other words, Figure 10 The upper left quadrant of the storage device 300 (e.g., a semiconductor device) can be symmetrical to the lower right quadrant of the storage device 300 across the origin of the quadrants of the storage device 300. Similarly, the upper right quadrant of the storage device 300 can be symmetrical to the lower left quadrant of the storage device 300 across the origin of the quadrants of the storage device 300, and so on.

[0081] The bitline decoder can be located in bitline decoder region 301, and the lower word line decoder and upper word line decoder can be located in the plurality of word line decoder regions 302 and 303. Circuitry connected to at least one of the bitline decoder, lower word line decoder, and upper word line decoder can be located in circuit region 304. For example, a precharge circuit, a sense amplifier, etc., can be located in circuit region 304, but the exemplary embodiment is not limited thereto.

[0082] Reference Figure 10The upper word line decoder can be closer to the word line contact area 305 than the lower word line decoder, but the example implementation is not limited to this. The lower word line decoder can be connected to the lower word line between the peripheral circuit area and the bit line via the lower word line contact. Therefore, the location of the lower word line decoder in the memory device can be unrestricted and / or have very few restrictions. On the other hand, the upper word line contact connected to the upper word line decoder may need to extend in a third direction without interfering with the bit line, lower word line, and lower memory cell. Therefore, the upper word line contact is located in the word line contact area 305 between unit areas UA, and the upper word line decoder can be close to the word line contact area 305 to significantly improve resistance characteristics, etc. In a third direction, the lower word line contact can be shorter than the upper word line contact, but the example implementation is not limited to this.

[0083] As referenced above Figure 8 As described, the lower word line can be arranged along a second direction within a unit region UA, but is not limited thereto, and can be arranged along other directions. On the other hand, the upper word line can cross, for example, the boundary between a pair of unit regions UA adjacent to each other in the second direction, and can be separated, for example, in the second direction, in a region adjacent to the center of each unit region UA. In one example, for example, upper word lines at the same position in the first direction can be separated from each other in another direction (e.g., the second direction) at the boundary between the lower word line decoder region 302 and the circuit region 304, etc.

[0084] In at least one example implementation, by appropriately arranging the lower word line decoder and the upper word line decoder within a storage device and / or semiconductor device, the skew between memory cells can be significantly reduced. For example, the lower word line decoder may be located near the center (and / or approximately at the center, etc.) of each unit region UA, but is not limited thereto; the upper word line decoder may be located near the boundary (and / or approximately at the boundary, etc.) between unit regions UA. For example, the lower word line decoder may be relatively closer to the center of each unit region UA, and the upper word line decoder may be relatively closer to the boundary between unit regions UA, but the example implementation is not limited thereto.

[0085] The lower word line decoder can be connected to the lower word line via a lower word line contact, and the lower word line contact can be in or around the lower word line decoder region 302. Similarly, the upper word line decoder can be connected to the upper word line via an upper word line contact, and the upper word line contact can be in the word line contact region 305 between unit regions UA. Therefore, the distance between the lower word line decoder and the lower word line contact, and the distance between the upper word line decoder and the upper word line contact, can be reduced, thereby improving the performance of the storage device and / or reducing the physical size of the storage device, etc.

[0086] The arrangement of the lower word line decoders allows the lower word line contact to be close to the center of the lower word line, and the arrangement of the upper word line decoders allows the upper word line contact to be close to the center of the upper word line. Therefore, the skew between lower memory cells and the skew between upper memory cells can be significantly reduced.

[0087] Reference Figure 10 The lower word line decoder region 302 may, for example, be closer to the center of each unit region UA ​​than the boundary between unit regions UA in the second direction, but is not limited thereto. Similarly, the upper word line decoder region 303 may be closer to the boundary between unit regions UA than to the center of each unit region UA ​​in the second direction, but is not limited thereto. Therefore, the distance between the upper word line decoder region 303 and the word line contact region 305 in which the upper word line contact is connected to the upper word line can be reduced, thus improving the performance of the storage device and / or reducing the physical size of the storage device. Lower word line contacts connected to the lower word lines may be formed in or around the lower word line decoder region 302, etc.

[0088] exist Figure 10 In the example embodiment shown, a plurality of bit line contact regions 306 may be located within each unit region UA. The bit line contact regions 306 may be formed within the unit region UA ​​and may not deviate from each unit region UA ​​(separated from each unit region UA), for example, in a second direction. For example, in the second direction, the length of each bit line contact region 306 may be less than or equal to the length of each unit region UA, etc.

[0089] The cell array region (where the storage cells are located) and the bit line contact region 306 may be arranged alternately in each unit region UA ​​in, for example, a first direction (e.g., stacked, layered, etc.), but are not limited thereto. The bit line contact region 306 may include a first bit line contact region 306A (which divides each unit region UA ​​into a first sub-unit region and a second sub-unit region) and a second bit line contact region 306B. The second bit line contact region 306B may extend in a different direction (e.g., a second direction) and may overlap with at least a portion of the bit line decoder region 301 in the first direction. For example, in the second direction, the length of the bit line decoder region 301 may be greater than the length of each bit line contact region 306.

[0090] At least one of the bit line contact regions 306 may be located between word line contact regions 305 in a second direction, for example. For example, the second bit line contact region 306B may be located between word line contact regions 305 in a second direction. On the other hand, the first bit line contact region 306A may not contact the word line contact region 305 in the direction (e.g., the second direction) in which the second bit line contact region 306B contacts the word line contact region 305. For example, see reference... Figure 10The word line contact area 305 may not extend to the first word line contact area 306A in, for example, the first direction.

[0091] Figure 11 yes Figure 10 A magnified perspective view of area A1. Figure 12 It is based on at least one example implementation along Figure 11 The cross-sectional view taken from line I-I'.

[0092] Reference Figure 11 and Figure 12 The storage device 300 may include: a peripheral circuit region P, including a plurality of circuit devices 311A ​​formed on a semiconductor substrate 310; and a cell region C, including a plurality of storage cells 330 and 350. The cell region C includes a plurality of bit lines 340 extending in a first direction (e.g., the Y-axis direction) and a plurality of word lines 320 and 360 extending in a direction different from the plurality of bit lines 340, such as a second direction (e.g., the X-axis direction), but the example embodiments are not limited thereto.

[0093] For example, cell region C may include a lower word line 320 below bit line 340 and an upper word line 360 ​​above bit line 340 in a third direction (e.g., the Z-axis direction). Lower memory cell 330 may be located between bit line 340 and lower word line 320, and upper memory cell 350 may be located between bit line 340 and upper word line 360.

[0094] The circuit device 311A ​​may be adjacent to the device isolation layer 312A in at least one direction (such as the first direction and / or the second direction) and may be connected to the circuit line 314A via the device contact 313A. The circuit device 311A ​​may be covered by the interlayer insulation layer 315, but is not limited thereto. Figure 11 It can be Figure 10 An enlarged perspective view of region A1, and circuit device 311A ​​can provide a lower word line decoder connected to lower word line 320.

[0095] The lower letter 320 can be connected to the heating electrode layer 321, etc. Figure 11 In at least one example embodiment shown, the heating electrode layer 321 is shown connected to a pair of adjacent lower memory cells 330 in a second direction; however, this example embodiment is provided by way of illustration only and is not a limitation. For example, each lower memory cell 330 may be connected to a heating electrode layer 321, etc. On the other hand, a recess 317 may be formed in the process of forming the heating electrode layer 321 and the lower word line 320.

[0096] The heating electrode layer 321 can be separated from each other by the lower insulating pattern 322. The insulating spacer 323 and the inner insulating layers 324 and 325 can be included in the heating electrode layer 321. The lower insulating pattern 322, the insulating spacer 323, and the inner insulating layers 324 and 325 can be formed of silicon oxide, silicon nitride, etc.

[0097] Each lower memory cell 330 may include a variable resistance layer 331 that contacts the heating electrode layer 321, a first electrode layer 332 and / or a selection device layer 334, etc., sequentially stacked on the variable resistance layer 331, a second electrode layer 336, etc. According to some example embodiments, a first interface layer 333 and a second interface layer 335, etc., may be located between the selection device layer 334 and the first electrode layer 332, and between the selection device layer 334 and the second electrode layer 336, respectively.

[0098] The variable resistance layer 331 can be formed of a material in which a phase change can occur through heat transferred from the heating electrode layer 321 and / or based on the heat transferred from the heating electrode layer 321. For example, the variable resistance layer 331 may include Ge-Sb-Te (GST) (which is a chalcogenide material), but the example embodiments are not limited thereto. Alternatively, the variable resistance layer 331 may be formed of a chalcogenide material, which includes at least two elements selected from silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), etc., or any combination thereof.

[0099] The selector layer 334 may include a material in which the resistance varies according to the magnitude of the voltage applied across the selector layer 334, and may include, for example, a bidirectional threshold switch (OTS) material, but is not limited thereto. The OTS material may include chalcogenide switching materials, etc. In at least one example embodiment, the selector layer 334 may include Si, Te, As, Ge, In, or any combination of these elements, or may further include nitrogen, etc. The material of the selector layer 334 is not limited to those described above, and the selector layer 334 may include various material layers capable of selecting devices.

[0100] The upper memory cell 350, the heating electrode layer 361, and the upper word line 360 ​​can be located on the bit line 340. (See reference) Figure 11 and Figure 12 The heating electrode layer 361 can be connected to the upper letter line 360, and the heating electrode layer 361 can be separated from each other by the upper insulating pattern 362. The insulating spacer 363 and the inner insulating layers 364 and 365 can be included in the heating electrode layer 361.

[0101] The upper memory cell 350 may have the same structure as the lower memory cell 330, but is not limited thereto. For example, each upper memory cell 350 may include a variable resistance layer 351 in contact with the heating electrode layer 361, a first electrode layer 352 and / or a selection device layer 354 arranged sequentially (e.g., stacked, layered, etc.) below the variable resistance layer 351, and a second electrode layer 356, etc. Similar to the case of the lower memory cell 330, a first interface layer 353 and a second interface layer 355 may be located between the selection device layer 354 and the first electrode layer 352, and between the selection device layer 354 and the second electrode layer 356, respectively.

[0102] Figure 13 yes Figure 10 A magnified perspective view of area B1. Figure 14 It is based on some example implementations along Figure 13 The cross-sectional view taken from line II-II'.

[0103] Region B1 may be an area overlapping with word line contact region 305, but is not limited thereto. Word line contact region 305 may be an area where word line contact WC connects to the upper word line 360 ​​and extends upwards, for example, to a third line. See above for reference. Figure 8 and Figure 10 As described, the lower character line 320 and the upper character line 360 ​​may be arranged in a zigzag pattern, for example, in a second direction, but the exemplary implementation is not limited thereto. For example, the lower character line 320 may be separated in the character line contact area 305 in the second direction, and the upper character line 360 ​​may extend continuously in the character line contact area 305 and may be connected to the character line contact WC.

[0104] Reference Figure 13 and Figure 14 Bit line 340, lower word line 320, and memory cells 330 and 350 may not be included in word line contact region 305. Therefore, the word line contact WC connected to the upper word line 360 ​​in word line contact region 305 can extend to peripheral circuit region P. According to some example embodiments, the word line contact WC can be divided into multiple layers, for example, in a third direction.

[0105] The circuit device 311B connected to the word line contact WC can provide an upper word line decoder for selecting at least one of the upper word lines 360. The upper word line decoder can be included in an upper word line decoder region 303 adjacent to the word line contact region 305 in, for example, a second direction, but is not limited thereto. Therefore, the design of the metal wire 314B and the device contact 313B used to connect the circuit device 311B and the word line contact WC can be simplified. The circuit device 311B can be separated from each other by a device isolation layer 312B.

[0106] Figure 15yes Figure 10 A magnified perspective view of region C1. Figure 16 It is based on some example implementations along Figure 15 The cross-sectional view taken from line III-III'.

[0107] Region C1 may be a region overlapping with bit line contact region 306. Bit line contact regions 306A and 306B (e.g., bit line contact region 306) may be respective regions extending in, for example, a second direction, and may be the region in which bit line contact BC connects to bit line 340. To simplify the connection structure between bit line contact BC and a bit line decoder that selects at least one bit line 340, bit line contact region 306 may be adjacent to bit line decoder region 301 in different directions, such as the first direction.

[0108] According to at least one example embodiment, the upper storage cell 350 may be further included in at least one of the bit line contact regions 306. (See also...) Figure 15 and Figure 16 The lower storage cell 330 is not formed in the bit line contact region 306 to ensure space for arranging the bit line contact BC, while the upper storage cell 350 can be connected to the upper part of the bit line 340. Therefore, the integration density of the storage device 300 can be improved.

[0109] The upper storage cell 350 in each bit line contact region 306 can be used for various purposes. For example, the upper storage cell 350 in the first bit line contact region 306A can be a dummy storage cell. On the other hand, the upper storage cell 350 in the second bit line contact region 306B can operate like a normal storage cell, or it can be used for redundancy and / or testing purposes, etc. However, in some example embodiments, the upper storage cell 350 in the first bit line contact region 306A can also operate like a normal storage cell, or it can also be used for redundancy and / or testing purposes, etc.

[0110] Bit line contact BC connects bit line 340 to circuit device 311C. Circuit devices 311C can be separated from each other by device isolation layer 312C and can provide a bit line decoder. As described above, by arranging bit line contact region 306 adjacent to bit line decoder region 301, the design difficulty and / or complexity of circuit line 314C and device contact 313C connecting bit line contact BC and circuit device 311C can be reduced, thus improving manufacturing yield and / or reducing manufacturing cost.

[0111] Figure 17 This is a diagram schematically illustrating the planar structure of a storage device according to at least one example embodiment.

[0112] Figure 17This could be a plan view showing a portion of the peripheral circuitry area beneath the memory cells in storage device 400. (Refer to...) Figure 17 The peripheral circuit region may include unit regions UA arranged in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction). Memory cells, bit lines, and word lines may be located on the peripheral circuit region in a third direction (e.g., the Z-axis direction), but are not limited thereto.

[0113] The peripheral circuit area may include, but is not limited to, bit line decoder area 401, word line decoder areas 402 and 403, circuit area 404, word line contact area 405, and bit line contact areas 406A to 406C (e.g., bit line contact area 406). The arrangement and configuration of bit line decoder area 401, word line decoder areas 402 and 403, circuit area 404, and word line contact area 405 can be similar to those described in the reference. Figure 10 The described layout and configuration are, but not limited to, those described.

[0114] exist Figure 17 In at least one example embodiment shown, a plurality of bit line contact regions 406 may be included in each unit region UA. Therefore, the cell array region (in which the memory cells are located) and the bit line contact regions 406 may be alternately arranged, stacked, or layered in each unit region UA, for example, in a first direction.

[0115] Bit line contact region 406 may include a first bit line contact region 406A (which divides each unit region UA ​​into a first sub-unit region and a sub-second unit region), a second bit line contact region 406B, and / or a third bit line contact region 406C, etc. The bit line contact regions 406 may extend in different directions, such as a second direction. According to some example embodiments, the third bit line contact region 406C may extend along the boundary of the bit line decoder region 401, for example, in a second direction.

[0116] In at least one example embodiment, the first to third bit line contact regions of each bit line contact region 406 may have different widths, but are not limited thereto. For example, the width T2 of the second bit line contact region 406B may be greater than the width T3 of the third bit line contact region 406C, but is not limited thereto. The width T1 of the first bit line contact region 406A may be greater than or equal to the width of the second bit line contact region 406B. The first bit line contact region 406A is closer to the center of the plurality of bit lines in the first direction, such as the Y direction, or the center of the unit region UA ​​in the first direction, such as the Y direction, than the second bit line contact region 406B and the third bit line contact region 406C. For example, the width T3 of the third bit line contact region 406C, which is closest to the boundary between a pair of adjacent unit regions UA in the first direction, may be the smallest, but is not limited thereto. The respective widths of the first to third bit line contact regions of each bit line contact region 406 may be determined based on and / or depending on the number of bit line contacts in each bit line contact region 406.

[0117] As referenced above Figure 9 Described, the width of each bit line BL may be smaller than the width of the circuit line connected to the element in the bit line decoder region 401. This width may be a width defined in a second direction, but is not limited thereto. In at least one example embodiment, the width of each bit line BL may be, for example, half the width of each circuit line or less, etc. Therefore, the plurality of bit line contact regions 406 may include circuit lines connecting the respective bit lines BL to the element in the bit line decoder region 401.

[0118] For example, a case could be provided where 8N bit lines (where N is a natural number) extend in the first direction and are arranged in the second direction within each unit region UA. In this case, the left side (relative to...) Figure 17 The 4N bit lines of the second sub-unit region can be connected to the bit line decoder included in the bit line decoder region 401. Additionally, the right side (relative to...) Figure 17 The 4N bit lines can be connected to the bit line decoder included in the bit line decoder region 401 of the first sub-unit region.

[0119] First, N bit lines out of the 4N bit lines on the left side of each unit region UA ​​can be connected to the N bit line contacts included in the third bit line contact region 406C. Additionally, N bit lines out of the remaining 3N bit lines can be connected to the N bit line contacts included in the first bit line contact region 406A. Finally, the remaining 2N bit lines can be connected to the 2N bit line contacts included in the second bit line contact region 406B.

[0120] Similarly, 2N of the 4N bit lines on the right side of each unit region UA ​​can be connected to the 2N bit line contacts in the second bit line contact region 406B. N of the remaining 2N bit lines can be connected to the N bit line contacts in the first bit line contact region 406A. Additionally, the remaining N bit lines can be connected to the N bit lines in the third bit line contact region 406C.

[0121] In at least one example embodiment, the number of bit line contact regions 406 can be determined by Equation 1 below. In Equation 1, W1 can be the width of the bit line or the spacing between bit lines, and W2 can be the width of the circuit line connected to the bit line or the spacing between circuit lines. In Equation 1, M can be the desired and / or minimum number of second bit line contact regions 406B and third bit line contact regions 406C in each unit region UA. For example, the number of second bit line contact regions 406B and third bit line contact regions 406C in each unit region UA ​​can be M or more.

[0122] [Equation 1]

[0123] (M-1)*W1<W2<W*W1

[0124] For example, a case where W1 is 30 μm and W2 is 100 μm can be provided as an example, in which case M can be 4, but is not limited to this. Therefore, as Figure 17 As shown, the number of second bit line contact areas 406B and third bit line contact areas 406C in each unit area UA can be four or more, but is not limited to this.

[0125] according to Figure 17 In at least one example embodiment shown, the number of bit line contacts in the third bit line contact region 406C in each unit region UA ​​can be less than the number of bit line contacts in each of the first bit line contact region 406A and the second bit line contact region 406B. Therefore, the width T3 of the third bit line contact region 406C can be relatively small. In at least one example embodiment, the width T3 of the third bit line contact region 406C can be equal to or less than half the width of the second bit line contact region 406B, but is not limited thereto.

[0126] On the other hand, each bit line contact region 406 may be adjacent to the bit line decoder region 401 and / or may have a region overlapping with the bit line decoder region 401. Therefore, the wiring design for connecting the elements of the bit line contacts and the bit line decoder region 401 can be simplified, the performance of the storage device can be improved, and / or the size of the storage device can be reduced, etc.

[0127] Figure 18 yes Figure 17 A magnified perspective view of region C2. Figure 19 It is based on at least one example implementation along Figure 18 The cross-sectional view taken from line IV-IV'.

[0128] refer to Figure 18 and Figure 19 The storage device 400 may include: a peripheral circuit region P having a plurality of circuit devices 411C formed on a semiconductor substrate 410; and a cell region C having a plurality of storage cells 430 and 450, etc. The cell region C may include a plurality of bit lines 440 extending in a first direction (e.g., the Y-axis direction) and a plurality of word lines 420 and 460 extending in different directions, such as a second direction (e.g., the X-axis direction). The word lines (420 and 460) may include a lower word line 420 below the bit line 440 and an upper word line 460 above the bit line 440.

[0129] The configuration of the unit region C and the peripheral circuit region P can be similar to, but not limited to, the other example embodiments described above. For example, the circuit device 411C can be adjacent to the device isolation layer 412C in at least one of the first and second directions, and can be connected to the circuit line 414C via the device contact 413C. The circuit device 411C can be covered by the interlayer insulating layer 415.

[0130] The lower memory cell 430 and the upper memory cell 450 can share the bit line 440. The lower memory cell 430 can be connected to the lower word line 420 via the heating electrode layer 421. (Refer to...) Figure 18 and Figure 19 In the example embodiment, the heating electrode layer 421 is shown connected to a pair of adjacent lower memory cells 430 in a second direction, but the example embodiment is not limited thereto. For example, each lower memory cell 430 may also be connected to a single heating electrode layer 421. In the process of forming the heating electrode layer 421 and the lower word line 420, a recess 417 may be formed.

[0131] Heating electrode layers 421 can be separated from each other by a lower insulating pattern 422, and insulating spacers 423 and inner insulating layers 424 and 425 can be included in heating electrode layers 421. Each lower memory cell 430 may include a variable resistance layer 431 in contact with the heating electrode layer 421, a first electrode layer 432 and a selection device layer 434 sequentially stacked (e.g., arranged and / or layered) on the variable resistance layer 431, a second electrode layer 436, etc. According to some exemplary embodiments, a first interface layer 433 and a second interface layer 435 may be located between the selection device layer 434 and the first electrode layer 432, and between the selection device layer 434 and the second electrode layer 436, respectively. The materials included in the variable resistance layer 431 and the selection device layer 434 may be similar to those referenced. Figure 11-12 The materials described above.

[0132] The variable resistance layer 431 can be formed of a material capable of inducing a phase transition based on and / or through heat transferred from the heating electrode layer 421. For example, the variable resistance layer 431 may include Ge-Sb-Te (GST) (which is a chalcogenide material), but is not limited thereto. Alternatively, the variable resistance layer 431 may be formed of a chalcogenide material comprising at least two elements selected from Si, Ge, Sb, Te, Bi, In, Sn, Se, etc., or any combination thereof.

[0133] Upper memory cell 450, heating electrode layer 461, and upper word line 460 may be on bit line 440. Upper word line 460 may be connected to upper memory cell 450 via heating electrode layer 461, which may be separated from each other via upper insulating pattern 462, but is not limited thereto. Insulating spacer 463 and internal insulating layers 464 and 465 may be included within heating electrode layer 461. Upper memory cell 450 may have the same structure as lower memory cell 430, but is not limited thereto. For example, each upper memory cell 450 may include a variable resistor layer 451 in contact with heating electrode layer 461, a first electrode layer 452 and a select device layer 454, a second electrode layer 456, etc., sequentially stacked (e.g., arranged and / or layered) below the variable resistor layer 451. Similar to the case of the lower memory cell 430, the first interface layer 453 and the second interface layer 455 can be located between the select device layer 454 and the first electrode layer 452, and between the select device layer 454 and the second electrode layer 456, respectively.

[0134] Reference Figure 18 and Figure 19 The bit line contact BC can be included in the second bit line contact area 406B and the third bit line contact area 406C. (See above reference.) Figure 17 As described, the second bit line contact area 406B and the third bit line contact area 406C may have different widths, but are not limited thereto.

[0135] The lower storage unit 430 may not be included in each of the second bit line contact areas 406B and the third bit line contact area 406C, and only the upper storage unit 450 may be included in each of the second bit line contact areas 406B and the third bit line contact area 406C. The upper storage unit 450 included in the second bit line contact area 406B and the third bit line contact area 406C can operate as a normal storage unit for storing data, and / or can be used for redundancy or testing purposes, etc.

[0136] For example, when the second bit line contact area 406B and the third bit line contact area 406C have different widths, the number of upper memory cells 450 in the second bit line contact area 406B and the third bit line contact area 406C can be different. For example, the number of upper memory cells 450 in the second bit line contact area 406B can be greater than the number of upper memory cells 450 in the third bit line contact area 406C, but it is not limited to this. In addition, the number of upper word lines 460 in the second bit line contact area 406B can be greater than the number of upper word lines 460 in the third bit line contact area 406C, but it is not limited to this.

[0137] Despite Figure 18 and Figure 19 Although not shown, the upper storage cell 450 may also be included in the first line contact area 406A. The upper storage cell 450 in the first line contact area 406A may operate as a normal storage cell, be used for redundancy and / or testing purposes, and / or be assigned to a dummy storage cell, etc.

[0138] Figure 20 and Figure 21 This is a schematic diagram illustrating the planar structure of a storage device according to some example embodiments.

[0139] Figure 20 and Figure 21 This could be a plan view showing a portion of the peripheral circuitry area beneath the memory cells in each of the memory devices 500 and 600. (See reference...) Figure 20 and Figure 21 The peripheral circuit region may include unit regions UA arranged in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction). Memory cells, bit lines, and word lines may be located on the peripheral circuit region in a third direction (e.g., the Z-axis direction). The peripheral circuit region may include bit line decoder regions 501 and 601, word line decoder regions 502, 503, 602, and 603, bit line contact regions 504 and 604, word line contact regions 505 and 605, circuit regions 506 and 606, etc.

[0140] The bitline decoder can be included in bitline decoder regions 501 and 601, and the lower word line decoder and upper word line decoder can be included in word line decoder regions 502, 503, 602, and 603, respectively. Circuitry connected to at least one of the bitline decoder, lower word line decoder, and upper word line decoder can be included in circuit region 506 or 606. For example, a precharge circuit, a sense amplifier, etc., can be included in circuit region 506 or 606.

[0141] exist Figure 20 and Figure 21In some example implementations shown, the lower word line decoder region 502 or 602 may be included in the center (or approximately the center) of each unit region UA ​​in a second direction. The upper word line decoder region 503 or 603 may be adjacent to the boundary of each unit region UA. Bit lines and memory cells may not be located in the region connecting the upper word line and the upper word line decoder. Therefore, the upper word line decoder may be adjacent to the boundary between the bit lines and the unit region UA ​​(where memory cells are not located).

[0142] exist Figure 20 and Figure 21 In some example implementations shown, the lower word line may be separated in a second direction at the boundary between unit regions UA, and the upper word line may be separated in a second direction at the center within the unit region UA, etc. In one example, the upper word line may be separated in a second direction on the lower word line decoder region 502 or 602. Therefore, the lower word line contact may be adjacent to the central connection of the lower word line, and the upper word line contact may also be adjacent to the central connection of the upper word line, and the skew between memory cells can be significantly reduced, thus improving the performance of the memory cells.

[0143] According to Figure 20 In the storage device 500 of at least one example embodiment shown, each unit region UA ​​may include a plurality of bit line contact regions 504A to 504B. The first bit line contact region 504A may be a region overlapping the upper portion of a bit line decoder region 501 in which a bit line decoder is formed, but is not limited thereto. The second bit line contact region 504B may be a region separated from the bit line decoder region 501 in a first direction, but may be within a desired and / or predetermined range from the bit line decoder region 501 to simplify circuit wiring design and thus reduce the complexity of the storage device, increase the manufacturing yield of the storage device, and / or reduce the manufacturing cost of the storage device, etc.

[0144] According to Figure 21 In the memory device 600 of at least one example embodiment shown, each unit region UA ​​may include a plurality of bit line contact regions 604A to 604C. The first bit line contact region 604A may be a region overlapping the upper portion of a bit line decoder region 601 in which a bit line decoder is formed, but is not limited thereto. The second bit line contact region 604B and the third bit line contact region 604C may be regions separated from the bit line decoder region 601 in a first direction, but may be within a desired and / or predetermined range from the bit line decoder region 601 to simplify circuit wiring design, thereby reducing the complexity of the memory device, increasing the manufacturing yield of the memory device, and / or reducing the manufacturing cost of the memory device, etc.

[0145] exist Figure 21In at least one example embodiment shown, the width (or physical area) of the bit line contact region 604 may vary, but is not limited thereto. For example, the width T3 of the third bit line contact region 604C, which is furthest from the bit line decoder region 601 in the first direction, may be smaller than the width T1 or T2 of each of the other bit line contact regions 604A and 604B. The respective widths of the bit line contact regions 604 can be determined based on the number of bit line contacts in each bit line contact region 604.

[0146] Figure 22 and Figure 23 This is a diagram illustrating the operation of a storage device according to some example embodiments.

[0147] First, refer to Figure 22 The storage device 700 according to at least one example embodiment may include multiple storage layers, such as storage layers 701 and 702, etc., said multiple storage layers (701 and 702) may include a first storage layer 701 and a second storage layer 702, etc. The lower storage cell LMC included in the first storage layer 701 may be connected to the lower word line LWL (including lower word lines LWL1, ..., LWLm-1 and LWLm), and the upper storage cell UMC included in the second storage layer 702 may be connected to the upper word line UWL (including upper word lines UWL1, ..., UWLm and UWLm+1).

[0148] The upper storage unit UMC and the lower storage unit LMC can share bit lines BL (including bit lines BL1, BL2, BL3, ..., BLn-1 and BLn). For example, the upper storage unit UMC can be connected to the upper part of bit lines BL (e.g., the first subset), and the lower storage unit LMC can be connected to the lower part of bit lines BL (e.g., the second subset). Regardless of how bit lines BL are shared, the upper storage unit UMC and the lower storage unit LMC can be controlled independently and / or together. For example, when the bit line decoder 730 selects the first bit line BL1 and the upper word line decoder 720 selects the first upper word line UWL1, the lower word line decoder 710 may not select the first lower word line LWL1. Therefore, the upper storage unit UMC connected between the first bit line BL1 and the first upper word line UWL1 can be controlled.

[0149] exist Figure 22 In at least one example implementation shown, the number of upper word lines (UWL) can be greater than the number of lower word lines (LWL), therefore, the number of upper memory cells (UMC) can be greater than the number of lower memory cells (LMC). See also... Figure 22The number of lower word lines (LWL) can be m, while the number of upper word lines (UWL) can be greater than the number of lower word lines (m). For example, an additional upper word line (UWLm+1) connected to the second memory layer 702 can be included in the bit line contact region where the bit line BL and bit line contacts are connected. For example, only the upper memory cell (UMC) can be included in the bit line contact region, but the example implementation is not limited to this.

[0150] Next reference Figure 23 The storage device 800 according to at least one example embodiment may include a plurality of storage layers 801 to 804. The plurality of storage layers (such as storage layers 801 to 804) may include a first storage layer 801, a second storage layer 802, a third storage layer 803, and / or a fourth storage layer 804, etc., that are stacked sequentially (e.g., arranged, layered, etc.). In at least one example embodiment, the odd-numbered layer storage cells OMC included in the first storage layer 801 and the third storage layer 803 can be connected to the odd-numbered layer word line decoder 810 via odd-numbered layer word lines OWL (including word lines OWL1, OWL2, ..., and OWLm). The even-numbered layer storage cells EMC included in the second storage layer 802 and the fourth storage layer 804 can be connected to the even-numbered layer word line decoder 820 via even-numbered layer word lines EWL (including word lines EWL1, EWL2, ..., EWLm and EWLm+1). On the other hand, in some example embodiments, storage layers 801 to 804 may also be connected to different word line decoders respectively.

[0151] exist Figure 23 In at least one example embodiment shown, bit lines BL can be shared by odd-layer memory cells OMC and even-layer memory cells EMC. Bit lines BL can include lower bit lines (including OBL1, OBL2, ..., and OBLn) between the first memory layer 801 and the second memory layer 802, and upper bit lines (including EBL1, EBL2, ..., and EBLn) between the third memory layer 803 and the fourth memory layer 804, etc. For example, lower and upper bit lines at the same location on a plane perpendicular to the stacking direction of memory layers 801 to 804 can be electrically connected to each other. Therefore, when one of the bit lines BL is selected by the bit line decoder 830, the lower and upper bit lines can be selected simultaneously. However, according to some example embodiments, lower and upper bit lines can be electrically separated from each other and can be selected individually by different bit line decoders.

[0152] exist Figure 23 In at least one example embodiment shown, the fourth storage layer 804, located at the topmost layer, may be connected to a greater number of word lines than the other storage layers 801 to 803 are connected to, but is not limited thereto. See also... Figure 23Each of the first to third memory layers 801 to 803 is connected to m word lines, while the fourth memory layer 804 may be connected to a larger number of word lines, but is not limited thereto. For example, an additional word line EWLm+1 connected to the fourth memory layer 804 may be included in the bit line contact region where the bit line BL and bit line contacts are connected. For example, in the bit line contact region, memory cells and at least one word line connected to the memory cells may be added to the uppermost layer, but is not limited thereto.

[0153] Figure 24 This is a schematic cross-sectional view illustrating the planar structure of a storage device according to at least one exemplary embodiment. Figure 25 It is along Figure 24 A cross-sectional view taken from line V-V'. Figure 26 It is based on some example implementations along Figure 24 The cross-sectional view taken from line VI-VI'.

[0154] First, refer to Figure 24 , Figure 24 This may be a plan view showing a portion of the peripheral circuitry region beneath the memory cells in the memory device 900. The peripheral circuitry region may include unit regions UA arranged in a first direction (e.g., the Y-axis direction) and a second direction (e.g., the X-axis direction). The peripheral circuitry region may include, but is not limited to, bit line decoder region 901, word line decoder region 902, circuitry region 906, word line contact region 905, bit line contact regions 904A to 904C (e.g., bit line contact region 904), etc. The arrangement and configuration of the regions may be similar to the above reference. Figure 17 The described layout and configuration are, but not limited to, those described.

[0155] The storage device 900 may include storage cells and bit lines, as well as word lines, etc., located above the peripheral circuit region in a third direction (e.g., the Z-axis direction). The peripheral circuit region P and the cell region C on the peripheral circuit region P are shown together with the reference diagram. Figure 25 and Figure 26 The storage device 900 may include multiple storage layers stacked upwards on a third party, such as storage layers 941 to 944.

[0156] refer to Figure 25 and Figure 26 Multiple circuit devices 911 can be formed in the peripheral circuit region P. The circuit devices 911 formed on the semiconductor substrate 910 can be separated from each other by a device isolation layer 912. The circuit devices 911 can be connected to the circuit lines 914 by device contacts 913. The circuit devices 911, device contacts 913 and circuit lines 914 can be covered by multiple interlayer insulating layers such as interlayer insulating layers 915, 916 and 917.

[0157] Cell region C includes multiple storage layers stacked upwards on a third side, such as first to fourth storage layers 941 to 944, each of which includes multiple storage cells. The storage cells may be arranged in a first direction and a second direction in each of the storage layers (e.g., storage layers 941 to 944).

[0158] Word lines 921 to 924 and bit lines 931 and 932 can be located between memory layers 941 to 944. For example, first-layer word line 921 can be located between the first memory layer 941 and the peripheral circuit region P, but is not limited thereto. Lower-layer bit line 931 can be located between the first memory layer 941 and the second memory layer 942. Therefore, memory cells in each of the memory layers 941 to 944 can be connected to the corresponding word lines in word lines 921 to 924 and the corresponding bit lines in bit lines 931 and 932, etc.

[0159] Reference Figure 25 The second word line 922 on the second storage layer 942 can be connected to the circuit device 911 via the word line contact 950 in the word line contact area 905. As an example, the circuit device 911 connected to the word line contact 950 can be included in a word line decoder for selecting at least one memory cell in the second storage layer 942.

[0160] Reference Figure 26 The storage device 900 may include a plurality of bit line contact regions, such as bit line contact regions 904A to 904C, and the bit line contact regions 904A to 904C may be separated from each other in a first direction. Each of bit lines 931 and 932 may be connected to a bit line contact 960 in at least one of the bit line contact regions 904A to 904C. Figure 26 In at least one example embodiment shown, bit line contact 960 may be commonly connected to lower bit line 931 and upper bit line 932 at the same location in the second direction, but is not limited thereto.

[0161] like Figure 24 As shown, bit line contact regions 904A to 904C can be adjacent to bit line decoder region 901 in the first direction, or can be located within bit line decoder region 901 in the first direction. Therefore, in Figure 26 In the example embodiment shown, the circuit device 911 connected to bit lines 931 and 932 via bit line contact 960 can be an element included in the bit line decoder.

[0162] The bit line contact areas 904A to 904C may have different widths and / or the same width in the first direction, etc. (See reference) Figure 24 and Figure 26The third bit line contact region 904C, adjacent to the boundary of the bit line decoder region 901, may have a width smaller than, but is not limited to, the width of the first bit line contact region 904A and the second bit line contact region 904B. Therefore, a relatively small number of bit line contacts 960 can be included in the third bit line contact region 904C. For example, the width of the third bit line contact region 904C may be less than or equal to half the width of each of the first bit line contact region 904A and the second bit line contact region 904B, but is not limited to this.

[0163] Reference Figure 26 In the bit line contact regions 904A to 904C, memory cells may be located only in the fourth memory layer 944, which is the topmost layer in the third direction, but are not limited thereto. For example, in the bit line contact regions 904A to 904C, memory cells may not be included in the corresponding first to third memory layers 941 to 943, but may be included in the fourth memory layer 944. Therefore, the fourth memory layer 944, located at the topmost layer, may include more memory cells than each of the first to third memory layers 941 to 943 and may be connected to more word lines than each of the first to third memory layers 941 to 943 is connected to, but is not limited thereto.

[0164] Figure 27 This is a schematic block diagram illustrating an electronic device including a storage device according to at least one example embodiment.

[0165] according to Figure 27 The electronic device 1000, illustrated in at least one example embodiment, may include a display 1010, at least one sensor 1020, a memory 1030, at least one communication transceiver 1040, processing circuitry including, for example, at least one processor 1050, a port 1060, etc., but is not limited thereto. Additionally, the electronic device 1000 may further include a power supply, input / output devices, etc. Figure 27 Among the components shown, port 1060 may be a device that enables electronic device 1000 to communicate with video cards, sound cards, memory cards, USB devices, etc. Electronic device 1000 may include not only general-purpose desktop or laptop computers, but also smartphones, tablets, smart wearable devices, Internet of Things (IoT) devices, autonomous vehicles, robotic devices, virtual reality and / or augmented reality devices, gaming devices, etc.

[0166] Processor 1050 can execute specific operations, instructions, tasks, etc. Processor 1050 may include: hardware including logic circuitry; hardware / software combinations, such as at least one processor executing software; or combinations thereof. For example, processor 1050 may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processor 1050 can communicate via bus 1070 with other devices connected to port 1060, as well as displays 1010, sensors 1020, memory 1030, and communication transceivers 1040, etc.

[0167] Memory 1030 may be a non-transitory computer-readable storage medium for storing data and / or multimedia data used in the operation of electronic device 1000. Memory 1030 may include volatile memory such as random access memory (RAM) or non-volatile memory such as flash memory. Memory 1030 may also include at least one of solid-state drives (SSDs), hard disk drives (HDDs), and optical disk drives (ODDs) as storage devices. Figure 27 In at least one example embodiment shown, the memory 1030 may include components according to the above references. Figures 1 to 26 Storage devices for various example implementations described.

[0168] As described above, according to at least one example embodiment, the storage device includes bit lines extending in a first direction and word lines extending in a second direction intersecting the first direction, and storage cells may be located between the bit lines and word lines. The bit lines can be connected to circuit devices via bit line contacts in bit line contact regions, and the storage cells may further be located above the bit lines in the bit line contact regions. Therefore, the integration density of the storage device can be increased, the physical size of the storage device can be reduced, and the complexity of the storage device can be reduced, thereby improving the manufacturing yield of the storage device and / or reducing manufacturing costs, and / or additionally, the storage cells can be used for redundancy and / or testing purposes, thereby improving the reliability of the storage device, etc.

[0169] Although various exemplary embodiments have been illustrated and described above, it will be apparent to those skilled in the art that various modifications and variations may be made without departing from the scope of the exemplary embodiments of the inventive concept as defined by the appended claims.

[0170] This application claims priority to Korean Patent Application No. 10-2019-0121568, filed with the Korean Intellectual Property Office on October 1, 2019, the entire disclosure of which is incorporated herein by reference for all purposes.

Claims

1. A storage device, comprising: Multiple bit lines extending in the first direction; Multiple lower memory cells below the multiple bit lines, the multiple lower memory cells being connected to the multiple bit lines; Multiple upper storage cells above the multiple bit lines, the multiple upper storage cells being connected to the multiple bit lines; as well as Multiple cell array regions and multiple bit line contact regions are alternately arranged in the first direction. The plurality of cell array regions include the plurality of upper storage cells and the plurality of lower storage cells, and Only the upper storage cell is arranged in at least one of the plurality of bit line contact regions.

2. The storage device according to claim 1, wherein, The plurality of bit lines are connected to a plurality of bit line contacts included in the plurality of bit line contact regions; and The plurality of bit line contacts are connected to a plurality of circuit devices, which are arranged below the lower memory cells in the plurality of cell array regions.

3. The storage device according to claim 1, wherein, The plurality of bit line contact regions have a physical area smaller than the physical area of ​​the cell array region.

4. The storage device according to claim 3, wherein, At least two of the plurality of bit line contact regions have different physical areas from each other.

5. The storage device according to claim 3, wherein, The plurality of bit line contact areas include a first bit line contact area and a second bit line contact area arranged at different positions in the first direction. as well as The first bit line contact area and the second bit line contact area have different widths in the first direction.

6. The storage device according to claim 5, wherein, The first bit line contact area is closer to the center of the plurality of bit lines in the first direction than the second bit line contact area; as well as The second bit line contact area has a width smaller than that of the first bit line contact area in the first direction.

7. The storage device according to claim 1, wherein, The plurality of upper storage cells included in the plurality of bit line contact regions are test storage cells or redundant storage cells.

8. The storage device according to claim 1, wherein, The number of the plurality of upper storage units is greater than the number of the plurality of lower storage units.

9. The storage device according to claim 1, further comprising: Multiple lower word lines extending in a second direction, the second direction intersecting the first direction, the multiple lower word lines being below the multiple lower memory cells and configured to connect to the multiple lower memory cells; Multiple upper word lines extending in the second direction and above the plurality of upper memory cells, the plurality of upper word lines being configured to connect to the plurality of upper memory cells; as well as Multiple word line contact areas arranged in the second direction, The plurality of lower character lines are connected to a plurality of lower character line contacts below the plurality of unit array regions, and the plurality of upper character lines are connected to a plurality of upper character line contacts included in the plurality of character line contact regions.

10. The storage device according to claim 9, wherein, The plurality of upper character lines are connected to the upper character line decoder area; and The upper word line decoder region is adjacent to one of the word line contact regions in the second direction.

11. The storage device according to claim 10, wherein, The plurality of lower word line contacts are connected to the lower word line decoder area; as well as The upper word line decoder region is arranged in the second direction between one of the word line contact regions and the lower word line decoder region.

12. The storage device according to claim 11, further comprising: Multiple bit line contacts connected to the bit line decoder region; as well as At least one boundary of the bitline decoder region is adjacent to one of the plurality of bitline contact regions in the first direction.

13. A storage device, comprising: Multiple bit lines located at different heights from the upper surface of the substrate, the multiple bit lines extending parallel to the upper surface of the substrate in a first direction; Multiple word lines are located at a height different from the height of the multiple bit lines in a direction perpendicular to the upper surface of the substrate, and the multiple word lines extend in a second direction that intersects the first direction; as well as Multiple memory layers, each memory layer including multiple memory cells disposed between multiple bit lines and multiple word lines adjacent to each other in a direction perpendicular to the upper surface of the substrate, and The topmost storage layer of the plurality of storage layers includes a larger number of storage cells than the number of storage cells included in each of the remaining storage layers. The plurality of bit lines are connected to a plurality of bit line contacts included in a plurality of bit line contact regions, the plurality of bit line contact regions being located between the memory cells in the first direction, and Among them, a pair of bit lines are located at different heights in the direction perpendicular to the upper surface of the substrate, at the same position in the second direction, and are jointly connected to one of the plurality of bit line contacts.

14. A storage device, comprising: Substrates comprising multiple unit regions; Multiple bit lines extending in a first direction, which is parallel to the upper surface of the substrate; Multiple lower word lines are located between the multiple bit lines and the upper surface of the substrate, and the multiple lower word lines extend in a second direction that is parallel to the upper surface of the substrate and intersects the first direction. Multiple upper character lines extending in the second direction, the multiple upper character lines being above the multiple position lines; Multiple character line contact areas, including multiple upper character line contacts connected to the multiple upper character lines, the multiple character line contact areas being between the multiple unit areas; Multiple memory cells between the multiple bit lines and the multiple lower word lines and between the multiple bit lines and the multiple upper word lines; as well as The number of the multiple upper character lines is greater than the number of the multiple lower character lines. Each of the aforementioned unit regions includes: Multiple bit line contact regions extending in the second direction, Multiple bit line contacts connected to the multiple bit lines are located in the multiple bit line contact areas. At least one of the plurality of upper character lines is arranged in the plurality of bit line contact areas.

15. The storage device according to claim 14, wherein, The plurality of word line contact areas extend in the first direction, and the plurality of word line contact areas are located between a pair of unit areas that are adjacent to each other in the second direction among the plurality of unit areas.

16. The storage device according to claim 14, wherein, The plurality of bit line contacts are located between the plurality of memory cells in the first direction.

17. The storage device according to claim 14, wherein, The plurality of bit line contact regions includes a first bit line contact region that is closest to the boundary between two unit regions adjacent to each other in the first direction, and the first bit line contact region has a width smaller than the width of each of the other bit line contact regions in the plurality of bit line contact regions.

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