Resistive memory devices and methods of operating resistive memory devices

Abstract

A resistive memory device includes a memory cell array of resistive memory cells connected to a word line and a bit line, each memory block of the memory cell array including K memory patches; a write / read circuit connected to the memory cell array through a row decoder and a column decoder, the write / read circuit configured to perform a write operation in a target memory patch of the memory cell array, the write / read circuit including a write driver corresponding to the memory block; a control voltage generator configured to generate a first control voltage and a second control voltage based on a reference current; and a control circuit configured to control the write / read circuit and the control voltage generator. A first write driver corresponding to a first memory block of the memory blocks is configured to provide a write current to the target memory patch corresponding to a physical location of a selected memory cell of the target memory patch in the memory cell array.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0121358, filed on October 1, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus and methods consistent with the example embodiments relate to storage devices, and more specifically, to resistive storage devices and / or methods of operating resistive storage devices. Background Technology

[0004] Volatile memory is a computer storage device that retains data while the device is powered on. Non-volatile memory is a computer storage device that can retrieve stored information even after being cycled through power-on (e.g., after a power outage). In response to the demand for high-capacity and low-power storage devices, research is underway on next-generation storage devices that are non-volatile and do not require refresh operations. Next-generation storage devices typically require / include the high integration of Dynamic Random Access Memory (DRAM), the non-volatile nature of Flash Memory, and the high-speed characteristics of Static RAM (SRAM). Examples of next-generation storage devices include Phase-Change RAM (PRAM), Nanoscale Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), and / or Resistive RAM (RRAM). Summary of the Invention

[0005] One or more example embodiments provide a resistive storage device with improved performance.

[0006] One or more example embodiments provide a method of operating a resistive storage device with improved performance.

[0007] According to some example embodiments, a resistive memory device includes: a memory cell array comprising a plurality of resistive memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cell array being divided into a plurality of memory bays, each memory bay comprising K memory tiles, where K is a natural number greater than 1; a write / read circuit connected to the memory cell array via a row decoder and via a column decoder, the write / read circuit being configured to perform a write operation in a target memory tile of the memory cell array, the write / read circuit including a plurality of write drivers corresponding to the plurality of memory bays; a control voltage generator configured to generate a first control voltage and a second control voltage based on a reference current, and to provide the first control voltage and the second control voltage to the write / read circuit; and a control circuit configured to control the write / read circuit and the control voltage generator. A first write driver, corresponding to a first memory bay among the plurality of memory bays, is configured to provide a write current to the target memory tile corresponding to the physical location of a selected memory cell in the target memory tile of the memory cell array.

[0008] According to some example embodiments, a resistive memory device includes: a memory cell array comprising a plurality of resistive memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cell array being divided into a plurality of memory blocks, each memory block comprising K memory chips, where K is a natural number greater than 1; a row decoder connected to the memory cell array via the plurality of word lines, the row decoder comprising a plurality of row selection switches; a column decoder connected to the memory cell array via the plurality of bit lines, the column decoder comprising a plurality of column selection switches; a write / read circuit connected to the memory cell array via the row decoder and the column decoder, the write / read circuit being configured to perform a write operation in a target memory chip of the memory cell array, the write / read circuit comprising a plurality of write drivers corresponding to the plurality of memory blocks; a control voltage generator configured to generate a first control voltage and a second control voltage based on a reference current, and to provide the first control voltage and the second control voltage to the write / read circuit; and a control circuit configured to control the write / read circuit and the control voltage generator based on commands and addresses. The first write driver, which corresponds to the first memory block among the plurality of memory blocks, is configured to provide the target memory chip with a write current corresponding to the physical location of a selected memory cell in the memory cell array.

[0009] According to some example embodiments, a method for operating a resistive memory device is provided, the resistive memory device including a memory cell array, the memory cell array including a plurality of resistive memory cells connected to a plurality of word lines and a plurality of bit lines, wherein the memory cell array is divided into a plurality of memory blocks, each of the plurality of memory blocks including K memory chips, where K is a natural number greater than 1, the method comprising: identifying a selected memory cell among the plurality of resistive memory cells disposed in a target memory chip based on a row address and a column address indicated in a write command; and providing a write current corresponding to the physical location of the selected memory cell in the target memory chip in the memory cell array by a first write driver in the write driver based on the write command. Attached Figure Description

[0010] The above and other aspects and features will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments;

[0012] Figure 2 This illustrates some example embodiments. Figure 1 A block diagram of the memory controller in the memory;

[0013] Figure 3 This illustrates some example embodiments. Figure 1 A block diagram of a resistive storage device in a computer.

[0014] Figure 4 This is a circuit diagram illustrating a memory cell array according to some example embodiments;

[0015] Figure 5A , Figure 5B and Figure 5C These are circuit diagrams of memory cells according to some example embodiments;

[0016] Figure 6 This is a diagram illustrating a memory cell array according to some example embodiments;

[0017] Figure 7A The resistance distribution of a single-level memory cell is shown;

[0018] Figure 7B The resistance distribution of a multi-level memory cell is shown;

[0019] Figure 8A It shows Figure 4 The current and voltage characteristic curves of the memory cells in the image;

[0020] Figure 8B It shows Figure 4 The current and voltage characteristic curves of the memory cells in the image;

[0021] Figure 9 This illustrates some example embodiments. Figure 3 A block diagram of the control circuit in a resistive storage device;

[0022] Figure 10 The following are illustrated according to some example embodiments. Figure 3 The memory cell array, write circuit, and control voltage generator in resistive memory devices;

[0023] Figure 11 The following are illustrated according to some example embodiments. Figure 10 A first memory block, a control voltage generator, and a first write driver corresponding to the first memory block in a resistive memory device;

[0024] Figure 12 Other example embodiments are shown. Figure 10 A first memory block, a control voltage generator, and a first write driver corresponding to the first memory block in a resistive memory device;

[0025] Figure 13 It is shown Figure 11 and Figure 12 A graph showing the resistance along the path from the selected memory block to the data sensing node and the voltage drop across the shielding transistor in the write driver.

[0026] Figure 14 The following are illustrated according to some example embodiments. Figure 3 Part of the resistive storage device;

[0027] Figure 15 It shows in detail Figure 14 Resistive storage devices;

[0028] Figure 16 The levels of the selection signals applied to the row selection switch and column selection switch are shown;

[0029] Figure 17 It shows when in Figure 15 The selected bit line, selected word line, and programming current level when performing programming operations in a resistive memory device;

[0030] Figure 18 This is an equivalent circuit diagram of a memory cell array according to some example embodiments;

[0031] Figure 19 This is a perspective view of a storage device according to some example embodiments, and Figure 20 It is along Figure 19The cross-sectional views taken by lines A-A' and B-B';

[0032] Figure 21 This is a flowchart illustrating a method of operating a resistive storage device according to some example embodiments;

[0033] Figure 22 This is a diagram illustrating a non-volatile memory module according to some example embodiments; and

[0034] Figure 23 This is a block diagram illustrating a mobile system according to some example embodiments. Detailed Implementation

[0035] Example embodiments will be described more fully below with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments.

[0037] A memory device that includes resistive memory cells can be referred to as a resistive memory device. Alternatively or additionally, a memory device may include various types of memory cells. For example, a memory device may include a heterogeneous collection of memory cells. Because memory cells can be located at the intersection of multiple first signal lines and multiple second signal lines, a memory device may be referred to as a cross-point memory device.

[0038] refer to Figure 1 The memory system 10 includes a memory controller 100 and a resistive memory device 200. The resistive memory device 200 includes a memory cell array (MCA) 210, control circuitry 300, and write / read circuitry 400. When the memory cell array 210 includes multiple resistive memory cells, the memory system 10 may be referred to as a resistive (resistive type) memory system.

[0039] In response to a write / read request from the host, the memory controller 100 reads data stored in the resistive memory device 200 and / or controls the resistive memory device 200 to write data to the resistive memory device 200. In some example embodiments, the memory controller 100 provides the resistive memory device 200 with an address (signal) ADDR, a command (signal) CMD, and a control signal CTRL to control programming (or write) operations and / or read operations for the resistive memory device 200.

[0040] Additionally, write target data DTA and read data DTA can be exchanged between the memory controller 100 and the resistive storage device 200. For example, write target data DTA can be written to the resistive storage device 200 in response to a write command, and read data DTA can be read from the resistive storage device 200 in response to a read command.

[0041] Additionally, the memory controller 100 may include a read retry controller 110 (e.g., control circuitry) and / or an error correction code (ECC) engine 120 (e.g., ECC circuitry). The read retry controller 110 may control the memory controller 100 to operate in read retry mode to perform read retry operations. The ECC engine 120 may perform error detection and correction on data provided from the resistive storage device 200. For example, the ECC engine 120 may detect whether the data contains errors and potentially correct them.

[0042] The storage cell array 210 may include a plurality of storage cells respectively disposed in the region where the first signal line and the second signal line intersect. Furthermore, each storage cell may be a single-level cell (SLC) storing one bit of data, or a multi-level cell (MLC) storing at least two bits of data.

[0043] Alternatively, the storage cell array 210 may include both SLC and MLC.

[0044] In some example embodiments, the storage cell array 210 includes storage cells with a two-dimensional horizontal structure. Alternatively or additionally, the storage cell array 210 includes storage cells with a three-dimensional vertical structure.

[0045] The memory cell array 210 may include resistive (resistive-type) memory cells, which include variable resistor elements. For example, when the resistance of a variable resistor element formed of a phase change material (e.g., Ge-Sb-Te) changes with temperature, the resistive memory device is a phase change RAM (PRAM). As another example, when the variable resistor device is formed of a composite metal oxide including an upper electrode, a lower electrode, and a transition metal oxide therebetween, the resistive memory device is a resistive RAM (RRAM). As another example, when the variable resistor device is formed of an upper electrode of magnetic material, a lower electrode of magnetic material, and a dielectric therebetween, the resistive memory device is a magnetic RAM (MRAM). The memory cell array 210 may include a heterogeneous collection of resistive memory cells; for example, the memory cell array 210 may include PRAM cells, RRAM cells, and MRAM cells; however, the example embodiments are not limited thereto.

[0046] The write / read circuit 400 performs write and read operations on the memory cell. In some example embodiments, the write / read circuit 400 is connected to the memory cell via a bit line and includes a write driver (e.g., a drive circuit) for writing data to the memory cell and a sense amplifier for a resistive component that senses the memory cell.

[0047] In some example embodiments, control circuitry 300 controls the operation of resistive memory device 200 and controls write / read circuitry 400 to perform memory operations such as write or read operations. For write and read operations of resistive memory device 200, control circuitry 300 may provide pulse signals, such as write pulses or read pulses, to write / read circuitry 400. For example, write / read circuitry 400 may provide write current (or write voltage) to memory cell array 210 in response to a write pulse and read current (or read voltage) to memory cell array 210 in response to a read pulse. The read current / write current or read voltage / write voltage may be the same as or different from each other.

[0048] During a write operation to the resistive storage device 200, the resistance value of the variable resistor of the storage cell in the storage cell array 210 can be increased or decreased according to the write data associated with the write operation. For example, each storage cell in the storage cell array 210 may have a resistance value based on the data currently stored therein, and this resistance value can be increased or decreased according to the data to be written to each storage cell.

[0049] In some example embodiments, the write operation is divided into a reset write operation and a set write operation. In the set state, the resistive memory cell can have a relatively low resistance value, while in the reset state, the resistive memory cell can have a relatively high resistance value. A reset write operation may involve performing a write operation to increase the resistance value of the variable resistor in the resistive memory cell, while a set write operation may involve performing a write operation to decrease the resistance value of the variable resistor in the resistive memory cell.

[0050] In some example embodiments, when a detected error in the data read by the resistive storage device 200 is uncorrectable, the memory controller 100 controls the resistive storage device 200 to operate in a read retry mode to perform a read retry operation. For example, the ECC engine 120 can determine whether the read data has an error and whether the error is correctable. During the read retry operation, while the storage device 200 changes the reference used to determine data "0" and data "1" (e.g., the read reference), the storage device 200 reads (or rereads) the data, analyzes the valleys in the resistance level distribution of the memory cells by performing a data determination operation on the read data, and, based on the analysis results, executes a recovery algorithm that selects the read reference to minimize or reduce the occurrence of data errors. The read retry operation can be controlled by the read retry controller 110.

[0051] Figure 2 This illustrates some example embodiments. Figure 1 A block diagram of the memory controller in the memory.

[0052] refer to Figure 2 The memory controller 100 includes a read retry controller 110, an ECC engine 120, a central processing unit (CPU) 130, a host interface (I / F) 140, and a memory interface (I / F) 150. The read retry controller 110, ECC engine 120, CPU 130, host interface 140, and memory interface 150 can communicate with each other via the system bus 105.

[0053] CPU 130 controls the operation of memory controller 100. For example, CPU 130 can control various function blocks related to memory operations on resistive memory device 200. Host interface 140 interfaces with a host. For example, host interface 140 can receive requests for memory operations from the host. For example, host interface 140 receives requests from the host for reading and / or writing data, and in response to such requests, host interface 140 generates internal signals for memory operations on memory device 200.

[0054] In some example embodiments, ECC engine 120 performs ECC encoding on written data and ECC decoding on read data. For example, ECC engine 120 can perform error detection on data read from resistive storage device 200, and can perform error correction on the read data when the result of the error detection indicates the presence of an error. Read retry controller 110 can provide various types of information for controlling the operation of storage device 200 during read retry mode, as described above. Memory interface 150 interfaces with resistive storage device 200 to exchange various signals (e.g., commands, addresses, mode signals, reference information, data, etc.) between memory controller 100 and resistive storage device 200.

[0055] Figure 3 This illustrates some example embodiments. Figure 1 A block diagram of a resistive storage device.

[0056] refer to Figure 3The resistive memory device 200 includes a memory cell array 210, a control circuit 300, a control voltage generator 260, and a write / read circuit 400. Additionally, the resistive memory device 200 may also include a row decoder 220, a column decoder 230, a voltage generator 240, and a reference signal generator 250. The memory cell array 210, the write / read circuit 400, the row decoder 220, and the column decoder 230 may be formed in a core region 202 of the semiconductor substrate in which the resistive memory device 200 is formed. The control voltage generator 260, the voltage generator 240, and the reference signal generator 250 may be formed in a peripheral region 201 of the semiconductor substrate. The write / read circuit 400 may include a write circuit (WC) 410, a read amplifier (SA) 420 including a read circuit, a write buffer (WB) 430, a page buffer (PB) 440, and a verification circuit 450. The write circuit 410 may include multiple write drivers.

[0057] The memory cells arranged in the memory cell array 210 are connected to the word line WL and the bit line BL. Because various voltage or current signals are provided through the bit line BL and the word line WL, data can be written to or read from the selected memory cell, and data can be prevented from being written to or read from the remaining unselected memory cells, or the probability of such occurrence can be reduced.

[0058] The address (or access address) ADDR used to indicate access to the target memory cell, along with the command CMD, can be received by the control circuitry 300. In some example embodiments, the address ADDR includes a row address R_ADDR of the memory cell array 210 for selecting word lines WL and a column address C_ADDR of the memory cell array 210 for selecting bit lines BL. The row decoder 220 performs a word line selection operation in response to the row address R_ADDR, and the column decoder 230 performs a bit line selection operation in response to the column address C_ADDR.

[0059] The write / read circuit 400 can be connected to the bit line BL, so that data can be written to or read from the memory cell. The write / read circuit 400 can be connected to the row decoder 220 and the column decoder 230.

[0060] For example, a set voltage VST or a reset voltage VRST can be provided from voltage generator 240 to the selected memory cell, inhibit voltages Vinhx and Vinhy can be provided from voltage generator 240 to the unselected word line and unselected bit line, and a read voltage VRD can be provided from voltage generator 240 to the selected memory cell during a read operation. Write / read circuitry 400 can provide write voltage or write current to memory cell array 210 based on the data via column decoder 230. Alternatively or additionally, to determine the data during a read operation, write / read circuitry 400 can include a comparator connected to a node (e.g., a data sensing node) of bit line BL, and the data value can be read by performing a comparison operation on the sensed voltage or sensed current of the sensed node. Reference voltage VREF and / or reference current IREF can be provided to write / read circuitry 400 and can therefore be used for data determination operations. Reference signal generator 250 can generate reference voltage VREF and / or reference current IREF. Reference signal generator 250 can provide reference current IREF to control voltage generator 260, and voltage generator 240 can provide bias voltage Vb to control voltage generator 260 and / or write / read circuit 400.

[0061] Alternatively or additionally, the write / read circuit 400 may provide a pass / fail signal P / F to the control circuit 300 based on the read result of the read data. The control circuit 300 may refer to the pass / fail signal P / F and thus control the write and read operations of the memory cell array 210.

[0062] In some example embodiments, the control circuit 300 generates multiple control signals CTL1 to CTL6 based on the command CMD, address ADDR, control signal CTRL, and pass / fail signal P / F. In some example embodiments, the control circuit 300 provides the first control signal CTL1 to the voltage generator 240, the second control signal CTL2 to the reference signal generator 250, the third control signal CTL3 to the write / read circuit 400, the fourth control signal CTL4 to the row decoder 220, the fifth control signal CTL5 to the column decoder 230, and the sixth control signal CTL6 to the control voltage generator 260.

[0063] The control circuit 300 can control at least one of the row decoder 220, column decoder 230, control voltage generator 260, and write / read circuit 400 based on the row address R_ADDR and / or column address C_ADDR (e.g., address ADDR).

[0064] Figure 4 This illustrates some example embodiments. Figure 3The circuit diagram of the memory cell array.

[0065] The storage cell array 210a includes multiple cells. Figure 4 An array of cells with cell blocks is shown, wherein a cell block comprises multiple cells.

[0066] refer to Figure 4 The memory cell array 210a includes multiple word lines WL1 to WLn, multiple bit lines BL1 to BLm, and multiple memory cells 214. Although Figure 4 Five word lines WL are shown, but the example embodiment is not limited to this, as there may be fewer or more than five word lines WL. For example, the number n of word lines WL may be the same as or different from the number m of bit lines BL. A memory cell MC connected to one word line can be defined as page cell 213.

[0067] In some example embodiments, each memory cell MC includes a variable resistor R and a selection device D. Here, the variable resistor R may be referred to as a variable resistor element and / or variable resistor material, and the selection device D may be referred to as a switching element. The variable resistor R is connected between one of the bit lines BL1 to BLm and the selection device D, and the selection device D is connected between the variable resistor device R and one of the word lines WL1 to WLn.

[0068] The resistance value of a variable resistor R can be changed to one of several resistance states. For example, the resistance value can change in response to an electrical pulse being applied to the corresponding variable resistor R.

[0069] In some example embodiments, the phase change material has an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. The phase of the phase change material can be changed according to the Joule heating generated by the electric current. Using the phase change, data can be written to the corresponding cells.

[0070] The selector D is connected between one of the word lines WL1 to WLn and the variable resistor R, and controls the current supplied to the variable resistor R based on the voltages applied to the connected word lines and bit lines. In some example embodiments, the selector D is a PN junction diode or a PIN junction diode. The anode of the diode can be connected to the variable resistor R, and the cathode of the diode can be connected to one of the word lines WL1 to WLn. Here, the diode conducts when the voltage difference between the anode and cathode of the diode is greater than the diode's threshold voltage (e.g., greater than 0.7 volts), thereby supplying current to the variable resistor R.

[0071] Figure 5A , Figure 5B and Figure 5C This is a circuit diagram of a memory cell according to an example embodiment. For example, Figure 5A , Figure 5B and Figure 5C The storage unit in is Figure 4 An example of a storage unit in the example.

[0072] refer to Figure 5A According to an example embodiment, memory cell 214a includes a variable resistor Ra connected (e.g., directly connected) between bit line BL and word line WL. Memory cell 214a stores data by applying voltages to bit line BL and word line WL, respectively.

[0073] refer to Figure 5B The memory cell 214b according to the example embodiment includes a variable resistor Rb and a bidirectional diode Db. The variable resistor Rb includes a resistive material for storing data. The bidirectional diode Db is connected (e.g., directly connected) between the variable resistor Rb and the word line WL, and the variable resistor Rb is connected (e.g., directly connected) between the bit line BL and the bidirectional diode Db. Alternatively, the positions of the bidirectional diode Db and the variable resistor Rb can be changed. By using the bidirectional diode Db, leakage current that may flow through unselected resistor cells can be eliminated or reduced. The variable resistor Rb may include a phase change material such as GeSbTe (GST), and the bidirectional diode Db may include a bidirectional threshold switch (OTS).

[0074] refer to Figure 5C The memory cell 214c according to the example embodiment includes a variable resistor Rc and a transistor TR. The transistor TR is a selection device (e.g., a switching device) that connects the variable resistor Rc to the source line SL according to the voltage of the word line WL. For example, current can be selectively supplied to the variable resistor Rc according to the voltage of the word line WL. Figure 5C As shown, in addition to the word line WL, a source line SL is additionally arranged to adjust the voltage level across the variable resistor Rc. A transistor TR is connected between the variable resistor Rc and the source line SL, and the variable resistor Rc is connected (e.g., directly to) the bit line BL and the transistor TR. Alternatively, the positions of the transistor TR and the variable resistor Rc can be changed relative to each other. Memory cell 214c is selected or not selected based on the on or off state of the transistor TR driven by the word line WL.

[0075] Figure 6 This is a diagram illustrating a storage cell array according to an example embodiment.

[0076] refer to Figure 6 The memory cell array 210b is implemented using a three-dimensional stacked structure. An exemplary three-dimensional stacked structure includes multiple vertically stacked memory cell layers 211_1 to 211_8. However, the example embodiment is not limited thereto, and the memory cell array may include different numbers of memory cell layers.

[0077] Each storage cell layer in storage cell layers 211_1 to 211_8 may include a normal cell array and a redundant cell array. When the storage cell array 210b has a three-dimensional stacked structure, each storage cell layer in storage cell layers 211_1 to 211_8 has Figure 4 The intersection structure shown.

[0078] Figure 7A The resistance distribution of a single-stage unit is shown.

[0079] refer to Figure 7A The horizontal axis represents resistance, and the vertical axis represents the cell number. For example, if a cell (e.g., cell 214) is a single-level cell programmed with 1 bit, then the cell may have a low-resistance state LRS. The example embodiment is not limited to this, and a cell may be a cell programmed with 1 bit while simultaneously having a high-resistance state HRS. A set operation (e.g., a set-write operation) refers to the operation of switching cell 214 from the high-resistance state HRS to the low-resistance state LRS by applying a write pulse to the cell. Similarly, a reset operation (e.g., a reset-write operation) refers to the operation of switching the cell from the low-resistance state LRS to the high-resistance state HRS by applying a write pulse to the cell.

[0080] The threshold resistance Rth can be set as the resistance between the distribution of the low-resistance state LRS and the distribution of the high-resistance state HRS. During a read operation performed on a memory cell, when the read result is greater than or equal to the threshold resistance Rth, the read result can be determined as the high-resistance state HRS, and when the read result is less than the threshold resistance Rth, the read result can be determined as the low-resistance state LRS. In some example embodiments, information about the read reference REF corresponding to the threshold resistance Rth is received from the memory controller 100. For example, this information can be used to determine the threshold resistance Rth of the memory cell. Cells with a resistance value less than Rth can correspond to cells with a logic value of "0", while cells with a resistance value greater than or equal to Rth can correspond to cells with a logic value of "1". However, the example embodiments are not limited to this.

[0081] Figure 7B The resistance distribution of a multi-level memory cell is shown.

[0082] refer to Figure 7BThe horizontal axis represents resistance, and the vertical axis represents the memory cell number. For example, if a memory cell is a multi-level cell programmed with 2 bits, then the memory cell can have one of a first resistance state RS1, a second resistance state RS2, a third resistance state RS3, and a fourth resistance state RS4. In an example embodiment, the first resistance state RS1 and the second resistance state RS2 can be referred to as low resistance states, while the third resistance state RS3 and the fourth resistance state RS4 can be referred to as high resistance states.

[0083] The resistance between the distribution of the first resistance state RS1 and the distribution of the second resistance state RS2 can be set as a first threshold resistance Rth1; the resistance between the distribution of the second resistance state RS2 and the distribution of the third resistance state RS3 can be set as a second threshold resistance Rth2; and the resistance between the distribution of the third resistance state RS3 and the distribution of the fourth resistance state RS4 can be set as a third threshold resistance Rth3. In a read operation performed on memory cell 214, when the read result is equal to or greater than the first threshold resistance Rth1, the read result can be determined as one of the second to fourth resistance states RS2, RS3, and RS4; and when the read result is less than the first threshold resistance Rth1, the read result can be determined as the first resistance state RS1. In an example embodiment, information about read references REFa, REFb, and REFc corresponding to the first threshold resistance Rth1, the second threshold resistance Rth2, and the third threshold resistance Rth3, respectively, is received from the memory controller 100. Mapping may exist between the logic value of a cell and the resistance value of a cell that is less than Rth1, between Rth1 and Rth2, between Rth2 and Rth3, and between cells that are greater than Rth3. For example, a cell with a resistance value less than Rth1 can be a cell with a logic value corresponding to "00", a cell with a resistance value between Rth1 and Rth2 can be a cell with a logic value corresponding to "01", a cell with a resistance value between Rth2 and Rth3 can be a cell with a logic value corresponding to "11", and a cell with a resistance value greater than Rth3 can be a cell with a logic value corresponding to "10"; however, the example embodiment is not limited to this, and other such mappings may exist.

[0084] Figure 8A It shows Figure 4 The current and voltage characteristic curves of the memory cells in the image.

[0085] refer to Figure 8AThe horizontal axis represents voltage, and the vertical axis represents current. Solid lines indicate the low resistance state (LRS). Dashed lines indicate the high resistance state (HRS). As the voltage increases, memory cell 214 exhibits a switching behavior from HRS to LRS for set write states. As the voltage decreases, memory cell 214 exhibits a switching behavior from LRS to HRS for reset write states. Memory cell 214 can determine the low resistance state or the high resistance state by detecting the write current IR at a specific voltage.

[0086] Figure 8B It shows Figure 4 The current and voltage characteristic curves of the memory cells in the image.

[0087] refer to Figure 8B The first part of the curve, 171, shows the minimum current flowing through... Figure 4 The voltage-current relationship under the selected device D condition is shown. Device D can be used as the threshold voltage V. T This is a switching device with a first voltage level of 173. When both voltage and current are 0 and the voltage gradually increases, almost no current flows through the selection device D until the voltage reaches the threshold voltage V. T For example, the first voltage level is 173. However, once the voltage exceeds the threshold voltage V... T The current flowing through the selector D will increase rapidly, and the voltage applied to the selector D can be reduced to the saturation voltage Vs, for example, the second voltage level 174.

[0088] The second part of the curve, 172, illustrates the voltage-current relationship in the state when current flows through the selector D. As the current flowing through the selector D increases to a level greater than the first current level 176, the voltage applied to the selector D can increase to a level slightly greater than the second voltage level 174. For example, although the current flowing through the selector D increases significantly from the first current level 176 to the second current level 177, the voltage applied to the selector D may only increase slightly from the second voltage level 174. For example, once current begins to flow through the selector D, the voltage applied to the selector D can be maintained almost at the saturation voltage Vs. When the current decreases below the holding current level (e.g., the first current level 176), the selector D can switch back to a resistive state, thus effectively blocking the current until the voltage increases to the threshold voltage Vs. T .

[0089] Figure 9 This illustrates some example embodiments. Figure 3 A block diagram of the control circuit in a resistive storage device.

[0090] refer to Figure 9The control circuit 300 includes a command decoder 310, an address buffer 320, a position information generator 330, and a control signal generator 340.

[0091] Command decoder 310 decodes command CMD to generate decoded command D_CMD, and provides decoded command D_CMD to control signal generator 340.

[0092] Address buffer 320 receives address ADDR, provides row address R_ADDR to row decoder 220 and position information generator 330, and provides column address C_ADDR to column decoder 230 and position information generator 330.

[0093] Location information generator 330 receives row address R_ADDR and column address C_ADDR, generates location information PSI1 and PSI2 indicating the selected memory cell specified by row address R_ADDR and column address C_ADDR, and provides location information PSI1 and PSI2 to control signal generator 340. Location information PSI1 may include location information associated with the memory block (bay) containing the selected memory cell.

[0094] The control signal generator 340 receives the decoded command D_CMD and position information PSI1 and PSI2, and generates the first control signal to the sixth control signal CTL1 to CTL6 based on the operation specified by the decoded command D_CMD and the position of the selected memory cell.

[0095] The control signal generator 340 provides the first control signal CTL1 to the voltage generator 240, the second control signal CTL2 to the reference signal generator 250, the third control signal CTL3 to the write / read circuit 400, the fourth control signal CTL4 to the row decoder 220, the fifth control signal CTL5 to the column decoder 230, and the sixth control signal CTL6 to the control voltage generator 260.

[0096] Figure 10 The following are illustrated according to some example embodiments. Figure 3 The memory cell array, write circuit, and control voltage generator in resistive memory devices.

[0097] refer to Figure 10 The memory cell array 210 and the write circuit 410 are disposed in the core region 202 of the semiconductor substrate, and the control voltage generator 260 is disposed in the peripheral region 201 of the semiconductor substrate.

[0098] The storage cell array 210 may include a plurality of storage cells BK1 to BKN (N is a natural number greater than 2) extending along a first (row) direction D1 and arranged along a second (column) direction D2, and each of the plurality of storage cells BK1 to BKN is divided into a plurality of storage blocks (bay) arranged along the first direction D1. For example, storage cell BK1 may include a plurality of storage blocks Bay11 to Bay1M (M is a natural number greater than 2), storage cell BK2 may include a plurality of storage blocks Bay21 to Bay2M, and storage cell BKN may include a plurality of storage blocks BayN1 to BayNM.

[0099] The write circuit 410 may include a plurality of write drivers (WD) 411 to 41N corresponding to memory banks arranged along the column direction.

[0100] The control voltage generator 260 can generate a first control voltage VCTL1 and a second control voltage VCTL2 based on a reference current IEF, and can provide the first control voltage VCTL1 and the second control voltage VCTL2 to a plurality of write drivers 411 to 41N corresponding to a memory bank and memory block including a selected memory cell. The control voltage generator 260 can receive a bias voltage Vb.

[0101] Figure 11 The following are illustrated according to some example embodiments. Figure 10 The resistive memory device includes a first memory block, a control voltage generator, and a first write driver corresponding to the first memory block.

[0102] refer to Figure 11 The storage block Bay1M included in storage block BK1 may include K (here, K is 4) storage tiles TL1 to TL4. Each other storage block Bay12 to Bay1M may include K storage tiles.

[0103] The control voltage generator 260a may include current sources CS1 and CS2 coupled to the supply voltage VCC, switches SW1 and SW2, a first control voltage generation circuit CVG11, a second control voltage generation circuit CVG12, and buffers 267 and 268. In an example embodiment, the control voltage generator 260a may receive a reference current IREF without including current sources CS1 and CS2.

[0104] The first control voltage generation circuit CVG11 may include n-channel metal-oxide-semiconductor (NMOS) transistors 261, 262, and 263 connected in series between a first node N11 and a negative voltage VNEG. The first node N11 is connected to a switch SW1. NMOS transistors 261, 262, and 263 may be referred to as a first active element, a second active element, and a fifth active element, respectively. NMOS transistor 261 is connected to the first node N11, NMOS transistor 262 is connected between NMOS transistors 261 and 263, and NMOS transistor 263 is connected to the negative voltage VNEG. The gate of NMOS transistor 262 is connected to the first node N11, and the first control voltage generation circuit CVG11 provides the voltage of the first node N11 based on the reference current IREF as the first control voltage VCTL1 to the write driver 411a via a buffer 267 and a signal line SL1.

[0105] The second control voltage generation circuit CVG12 may include NMOS transistors 264, 265, and 266 connected in series between the second node N12 and the negative voltage VNEG. The second node N12 is connected to switch SW2. NMOS transistors 264, 265, and 266 may be referred to as the third active element, the fourth active element, and the sixth active element, respectively. NMOS transistor 264 is connected to the second node N12, NMOS transistor 265 is connected between NMOS transistors 264 and 266, and NMOS transistor 266 is connected to the negative voltage VNEG. The gates of NMOS transistors 264 and 265 are both connected to the second node N12, and the second control voltage generation circuit CVG12 provides the voltage of the second node N12 based on the reference current IREF as the second control voltage VCTL2 to the write driver 411a through buffer 268 and signal line SL2.

[0106] In response to the first switch control signal SCS1, switch SW1 provides a reference current IREF from current source CS1 to the first node N11, and switch SW2 in response to the first switch control signal SCS1 provides a reference current IREF from current source CS2 to the second node N12.

[0107] (First) The write driver 411a includes a shielded transistor TR2, a bias transistor TR1, and a degradation element TR3 connected in series between the data sensing node SDL and the negative voltage VNEG. The bias transistor TR1 is connected between nodes N21 and N22, its gate receives a first control voltage VCTL1, and generates a write current IPGM based on the first control voltage VCTL1. The shielded transistor TR2 is connected between the data sensing node SDL and node N21, its gate receives a second control voltage VCTL2, and represents a voltage drop depending on the resistance on the path to the selected memory cell based on the second control voltage VCTL2. The degradation element TR3 is connected between the bias transistor TR1 and the negative voltage VNEG.

[0108] Because NMOS transistors 263 and 266 and the degradation element TR3 operate in the linear region in response to the bias voltage Vb, and are used as degradation resistors for each of the NMOS transistors 262 and 265 and the bias transistor TR1, which operate as current mirrors, the changed current can be minimized (reduced) through the first control voltage generation circuit CVG11, the second control voltage generation circuit CVG12, and the write driver 411a.

[0109] Memory chips TL1, TL2, TL3, and TL4 in the Bay1M memory block can be coupled to the data sensing node SDL via traces WR21–WR24, traces WR11–WR13, and switch SW3. Switch SW3 closes / opens in response to the second switch control signal SCS2. Traces WR21–WR24 and WR11–WR13 can be internal traces connected to the line decoder 220 of the Bay1M memory block. Traces WR21–WR24 can be represented as resistors RT21–RT24, and traces WR11–WR13 can be represented as resistors RT11–RT13. The resistance along the path from the selected memory chip to the data sensing node SDL can vary depending on the location of the selected memory chip among TL1, TL2, TL3, and TL4 in the Bay1M memory block.

[0110] The voltage drop across the shielding transistor TR2 can depend on the resistance along the path from the selected memory chip to the data sensing node SDL. The voltage drop across TR2 can be inversely proportional to the resistance along the path from the selected memory chip to the data sensing node SDL. If memory chip TL1 is selected from among TL1, TL2, TL3, and TL4 in memory block Bay1M, the total resistance along the path from the selected TL1 to the data sensing node SDL corresponds to RT21 + RT11 + RT12 + RT13. Therefore, the voltage drop across the shielding transistor TR2 can be reduced because the resistance along the path from the selected TL1 to the data sensing node SDL is large. If memory chip TL4 is selected from among TL1, TL2, TL3, and TL4 in memory block Bay1M, the total resistance along the path from the selected TL4 to the data sensing node SDL corresponds to RT24. Therefore, the voltage drop across the shielding transistor TR2 can be increased because the resistance along the path from the selected TL4 to the data sensing node SDL is small. The shielding transistor TR2 modulates (attenuates) the change in drain-source voltage of the bias transistor TR1 inversely proportional to the resistance on the path, and the bias transistor TR1 can generate a write current IPGM with a normal level.

[0111] If the write driver 411a does not include the shielding transistor TR2, the level of the write current IPGM generated by the bias transistor TR1 depends on the drain voltage of the bias transistor TR1, and the drain voltage of the bias transistor TR1 is determined based on the resistance on the path from the selected memory block to the data sensing node SDL. Therefore, the write current IPGM can have a certain distribution.

[0112] Figure 12 Other example embodiments are shown. Figure 10 The resistive memory device includes a first memory block, a control voltage generator, and a first write driver corresponding to the first memory block.

[0113] Figure 12 and Figure 11 The differences are as follows: the first control voltage generation circuit CVG21 includes a degradation resistor R2 instead of an NMOS transistor 263, the second control voltage generation circuit CVG22 includes a degradation resistor R1 instead of an NMOS transistor 266, the write driver 411b includes a degradation resistor R3 instead of a degradation element TR3, and the bias voltage Vb is not applied to the control voltage generator 260b and the write driver 411b. Therefore, details regarding... Figure 12 A detailed description is provided. Degraded resistors R1, R2, and R3 can have essentially the same resistance relative to each other.

[0114] Figure 13 It is shown Figure 11 and Figure 12 The graph shows the resistance along the path from the selected memory block to the data sensing node and the voltage drop across the shielding transistor in the write driver.

[0115] refer to Figures 11 to 13 In write drivers 411a or 411b, the resistance 181 on the path is proportional to the distance from the selected memory block to the data sensing node SDL. The voltage drop 183 across the shielded transistor TR2 is inversely proportional to the distance from the selected memory block to the data sensing node SDL.

[0116] Figure 14 The following are illustrated according to some example embodiments. Figure 3 It is a part of the resistive storage device.

[0117] refer to Figure 14 The resistive storage device 200 includes a first storage chip TL1, a row decoder 220, a column decoder 230, a write driver 411a, a control voltage generator 260, and a read circuit 420.

[0118] Figure 14 A first memory chip TL1 is shown comprising memory cells MC1, MC2, MC3, and MC4 connected to (e.g., coupled to and / or directly connected to) word lines WL1 and WL2 and bit lines BL1 and BL2. Memory cell MC1 is a selected memory cell SMC, and each of memory cells MC2, MC3, and MC4 is an unselected memory cell UMC. Each memory cell MC1, MC2, MC3, and MC4 includes a phase change element GST and a selection element OTS, which are connected in series, coupled to, and / or directly in series.

[0119] The inhibit voltage Vinhx is applied to word line WL2, which is coupled to the unselected memory cell UMC. The inhibit voltage Vinhy is applied to bit line BL2, which is connected, coupled to, and / or directly connected to the unselected memory cell UMC.

[0120] The row decoder 220 may include a pre-decoder 221, row selection switches LX1 and LX2, and a global selection switch GX1. The pre-decoder 221 decodes the row address R_ADDR and the fourth control signal CTL4 to apply the row selection signal RSEL and the global selection signal GRSEL to the row selection switches LX1 and LX2 and the global selection switch GX1, respectively. The row selection switches LX1 and LX2 are connected in parallel with the global selection switch GX1 at node N1.

[0121] The pre-decoder 221 applies a high-level row select signal RSEL1 to turn on the row select switch LX1 and applies a low-level row select signal RSEL2 to turn off the row select switch LX2, thereby selecting word line WL1. The pre-decoder 221 applies a high-level global select signal GRSEL1 to connect the write driver 411a to the selected word line WL1.

[0122] The write driver 411a can be connected between the global selection switch GX1 and the negative voltage VNEG, and can receive the first control voltage VCTL1, the second control voltage VCTL2 and the bias voltage Vb.

[0123] The control voltage generator 260 can be connected between the power supply voltage VCC and the negative voltage VNEG, and can provide the first control voltage VCTL1 and the second control voltage VCTL2 to the write driver 411a in response to the sixth control signal CTL6. The sixth control signal CTL6 may include the first switch control signal SCS1.

[0124] The column decoder 230 may include a pre-decoder 231, column selection switches LY1 and LY2, and a global selection switch GY1. The pre-decoder 231 decodes the column address C_ADDR and the fifth control signal CTL5 to apply the column selection signal CSEL and the global selection signal GCSEL to the column selection switches LY1 and LY2 and the global selection switch GY1, respectively. The column selection switches LY1 and LY2 are connected / coupled in parallel with the global selection switch GY1 at node N2.

[0125] The pre-decoder 231 applies a high-level column select signal CSEL1 to turn on column select switch LY1 and applies a low-level column select signal CSEL2 to turn off column select switch LY2, thereby selecting bit line BL1. It also applies a high-level global select signal GCSEL1 to connect the read circuit 420 to the selected bit line BL1. The read circuit 420 can receive a control signal CTL31, and the control signal CTL31 can be included in a third control signal CTL3.

[0126] The effects of set-write current or set-write voltage on the selected memory cell SMC can vary depending on the distance from at least one of the first access point AP1 or the second access point AP2 to the selected memory cell SMC. The first access point AP1 corresponds to the row selection switch LX1 leading to the selected word line WL1 connected / coupled to the selected memory cell SMC, and the second access point AP2 corresponds to the column selection switch LY1 leading to the selected bit line BL1 connected / coupled to the selected memory cell SMC.

[0127] Figure 15 It shows in detail Figure 14 Resistive storage devices.

[0128] exist Figure 15 middle, Figure 14 The read circuit 420 includes a pre-charge circuit 421 and a clamping circuit 425. Additionally, it employs... Figure 11 The write drive 411a in the middle.

[0129] refer to Figure 15 The precharge circuit 421 includes a first p-channel metal-oxide-semiconductor (PMOS) transistor 422 connected / coupled between the power supply voltage VPP and the precharge node PCN. The gate of the first PMOS transistor 422 receives the precharge control signal PCS.

[0130] The clamping circuit 425 is connected / coupled in parallel with the precharge circuit 421 to the precharge node PCN, and includes a second PMOS transistor 426 and a first NMOS transistor 427.

[0131] The second PMOS transistor 426 and the first NMOS transistor 427 are connected in series / coupled between the power supply voltage VPP and the precharge node PCN. The gates of the second PMOS transistor 426 and the first NMOS transistor 427 receive clamp control signals CCS1 and CCS2, respectively.

[0132] The precharge control signal PCS and the clamp control signals CCS1 and CCS2 can be included in the control signal CTL31.

[0133] The selected word line WLj (SEL) coupled to the selected memory cell SMC is connected / coupled to the write driver 411a via the row selection switch LXj and the global selection switch GX1, which are turned on based on the row selection signal RSELj and the global selection signal GRSEL1, respectively. The selected bit line BLi (SEL) coupled to the selected memory cell SMC is connected / coupled to the precharge circuit 421 and the clamping circuit 425 via the column selection switch LYi and the global selection switch GY1, which are turned on based on the column selection signal CSELi and the global selection signal GCSEL1, respectively.

[0134] The current IPGM from the selected memory cell SMC flows into the data sensing node SDL coupled to the write driver 411a.

[0135] Figure 16 It shows Figure 15 In resistive storage devices, the levels of selection signals, such as voltage levels, applied to row selection switches and column selection switches are determined according to the distance from the access point to the selected memory cell.

[0136] refer to Figure 15 and Figure 16 During the first interval INT1 corresponding to the standby interval, the column selection signal CSELi with ground voltage VSS and the global selection signal GCSEL1 are applied to the column selection switch LYi and the global selection switch GY1, respectively. The row selection signal RSELj with power supply voltage VDD and the global selection signal GRSEL1 are applied to the row selection switch LXj and the global selection switch GX1, respectively. The first clamping control signal CCS1 with ground voltage VSS is applied to the gate of the PMOS transistor 426, and the second clamping control signal CCS2 with power supply voltage VPP is applied to the gate of the NMOS transistor 427. Therefore, no programming current is applied to the selected memory cell SMC.

[0137] During the second interval INT2 corresponding to the programming interval, the column selection signal CSELi with level VP and the global selection signal GCSEL1 are applied to the column selection switch LYi and the global selection switch GY1, respectively. The row selection signal RSELj with level VN and the global selection signal GRSEL1 are applied to the row selection switch LXj and the global selection switch GX1, respectively. Additionally, a first clamp control signal CCS1 with power supply voltage VPP is applied to the gate of PMOS transistor 426, and a second clamp control signal CCS2 with ground voltage VSS is applied to the gate of NMOS transistor 427. Therefore, the programming current IPGM is applied to the selected memory cell SMC.

[0138] Here, the voltage level VP is equal to or greater than the ground voltage VSS and less than the supply voltage VPP. Additionally, the voltage level VN is greater than the negative voltage VNEG and equal to or less than the supply voltage VDD.

[0139] When the programming operation is completed, the column selection signal CSELi and the global selection signal GCSEL1 with power supply voltage VPP are applied to the column selection switch LYi and the global selection switch GY1, respectively, and the row selection signal RSELj and the global selection signal GRSEL1 with negative voltage VNEG are applied to the row selection switch LXj and the global selection switch GX1, respectively.

[0140] Figure 17 Showing when in Figure 15 The selected bit line, selected word line, and programming current level when performing programming operations in a resistive memory device.

[0141] refer to Figure 15 and Figure 17By activating the clamping control signal CCS2 with a high level before activating the precharge control signal PCS, and by partially overlapping the activation intervals of the clamping control signal CCS2 and the precharge control signal PCS, the control circuit 300 precharges the selected bit line BLi with the first power supply voltage VPP during the first interval INT21, and precharges the selected bit line BLi with the second power supply voltage 2VPP during the second interval INT22.

[0142] Before the first interval INT21, the voltage level of the selected word line WLj is reduced to a level below ground and above the negative voltage VNEG, and during the second interval INT22, it is reduced to a level corresponding to the negative voltage VNEG.

[0143] Before the first interval INT21, the write current IPGM is zero because no current flows into the selected memory cell SMC before the first interval INT21; during the first interval INT21, the write current IPGM has a level greater than zero because current begins to flow into the selected memory cell SMC during the first interval INT21; and during the second interval INT22, due to the operation of the bias transistor TR1, the write current IPGM with a constant (normal) level RVL is provided to the selected memory cell SMC.

[0144] Figure 18 This is an equivalent circuit diagram illustrating a memory cell array according to some example embodiments.

[0145] refer to Figure 18 The memory cell array 210c includes lower word lines WL11 and WL12 extending along a first direction X and spaced apart from each other along a second direction Y perpendicular to the first direction X, and upper word lines WL21 and WL22 extending along the first direction X and spaced apart from each other along the second direction Y. The upper word lines WL21 and WL22 are spaced apart from the lower word lines WL11 and WL12 along a third direction Z perpendicular to the first direction X and the second direction Y. Additionally, the memory cell array 210c includes common bit lines BL1, BL2, BL3, and BL4, which are spaced apart from each other along the first direction X and spaced apart from the upper word lines WL21 and WL22 and the lower word lines WL11 and WL12 along the third direction Z, and extend along the second direction Y.

[0146] The first memory cell MC1 and the second memory cell MC2 are respectively disposed between common bit lines BL1, BL2, BL3, and BL4 and lower word lines WL11 and WL12, and between common bit lines BL1, BL2, BL3, and BL4 and upper word lines WL21 and WL22. For example, the first memory cell MC1 can be arranged at the corresponding intersections of common bit lines BL1, BL2, BL3, and BL4 with lower word lines WL11 and WL12, and each first memory cell MC1 can include a variable resistor pattern ME for storing data and a selection device SW for selecting the variable resistor pattern ME. The second memory cell MC2 can be arranged at the corresponding intersections of common bit lines BL1, BL2, BL3, and BL4 with upper word lines WL21 and WL22, and each second memory cell MC2 can also include a variable resistor pattern ME for storing data and a selection device SW for selecting the variable resistor pattern ME.

[0147] The first memory cell MC1 and the second memory cell MC2 can have substantially the same structure and can be arranged along a third direction Z. For example, in the first memory cell MC1 arranged between the lower word line WL11 and the common bit line BL1, the select device SW can be electrically connected to the lower word line WL11, the variable resistor pattern ME can be electrically connected (e.g., directly electrically connected or coupled) to the common bit line BL1, and the variable resistor pattern ME and the select device SW can be connected in series with each other. Similarly, in the second memory cell MC2 arranged between the upper word line WL21 and the common bit line BL1, the variable resistor pattern ME can be electrically connected (e.g., directly electrically connected or coupled) to the upper word line WL21, the select device SW can be electrically connected to the common bit line BL1, and the variable resistor pattern ME and the select device SW can be connected in series with each other.

[0148] When the storage cell array 210 includes Figure 18 When the memory cell array 210c is in use, the write driver 411a or 411b can (automatically) compensate for the resistance distribution based on the physical location of the memory chip including the selected memory cell, and can provide a write current with a normal level to the selected memory cell.

[0149] Figure 19 These are perspective views of storage devices according to some example embodiments. Figure 20 It is along Figure 19 The cross-sectional view taken by lines A-A' and B-B'.

[0150] To reduce the complexity of the accompanying figures and provide a better understanding, from... Figure 20 Insulation layers 560a, 560b, 560c, 560d, and 560e are omitted.

[0151] refer to Figure 19 and Figure 20 The memory device 500 includes a substrate 501, a first electrode line layer 510L, a second electrode line layer 520L, a third electrode line layer 530L, a first memory cell layer MCL1, a second memory cell layer MCL2, a first spacer 550-1, and a second spacer 550-2.

[0152] like Figure 19 and Figure 20 As shown, an interlayer insulating layer 505 is disposed on a substrate 501. The interlayer insulating layer 505 may be formed of an oxide material (e.g., silicon oxide) and / or a nitride material (e.g., silicon nitride) and may be used to electrically isolate the first electrode line layer 510L from the substrate 501. Although the interlayer insulating layer 505 is shown as disposed on the substrate 501, this is merely an example, and the example embodiments are not limited thereto. For example, in a memory device 500 according to some example embodiments, an integrated circuit layer may be disposed on the substrate 501, and memory cells may be disposed on the integrated circuit layer. The integrated circuit layer may include, for example, peripheral circuitry for operating the memory cells and / or core circuitry for computation. Here, the structure of disposing of an integrated circuit layer including peripheral circuitry and / or core circuitry on a substrate and disposing of memory cells on the integrated circuit layer may be referred to as a co-occurrence peripheral (COP) structure.

[0153] The first electrode line layer 510L may include a plurality of first electrode lines 510, which extend along a first direction X and are arranged parallel to each other, and are spaced apart from each other along a second direction Y. The second electrode line layer 520L may include a plurality of second electrode lines 520, which extend along the second direction Y and are arranged parallel to each other, and are spaced apart from each other along the first direction X. Furthermore, the third electrode line layer 530L may include a plurality of third electrode lines 530, which extend along the first direction X and are arranged parallel to each other, and are spaced apart from each other along the second direction Y.

[0154] In terms of operation of the memory device, the first electrode line 510 and the third electrode line 530 can be used as word lines, while the second electrode line 520 can be used as a bit line. When the first electrode line 510 and the third electrode line 530 are used as word lines, the first electrode line 510 can be used as the lower word line, and the third electrode line 530 can be used as the upper word line. Additionally, the second electrode line 520 can be shared by the lower word line and the upper word line. For example, the second electrode line 520 can be used as a common bit line. Each of the first electrode line 510, the second electrode line 520, and the third electrode line 530 can include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The first electrode line 510, the second electrode line 520, and the third electrode line 530 can be formed of the same metal or alternatively, different metals. The thickness of the first electrode line 510, the thickness of the second electrode line 520, and the thickness of the third electrode line 530 can be the same as or different from each other. The sheet resistance and / or resistivity of each of the first electrode line 510, the second electrode line 520 and the third electrode line 530 may be the same as each other, or alternatively may be different from each other.

[0155] The first storage cell layer MCL1 includes a plurality of first storage cells 540-1, which are spaced apart from each other along the first direction X and the second direction Y, and are used as... Figure 18 The first storage cell MC1. The second storage cell layer MCL2 includes a plurality of second storage cells 540-2, which are spaced apart from each other along the first direction X and the second direction Y, and are used as... Figure 18 The second storage unit MC2. For example... Figure 19 As shown, the first electrode line 510 and the second electrode line 520 intersect each other, and the second electrode line 520 and the third electrode line 530 intersect each other. A first storage unit 540-1 is disposed between the first electrode line layer 510L and the second electrode line layer 520L, and at each intersection of the first electrode line 510 and the second electrode line 520, and is connected to the first electrode line 510 and the second electrode line 520. A second storage unit 540-2 is disposed between the second electrode line layer 520L and the third electrode line layer 530L, and at each intersection of the second electrode line 520 and the third electrode line 530, and is connected to the second electrode line 520 and the third electrode line 530.

[0156] In some example embodiments, each of the first memory cell 540-1 and the second memory cell 540-2 has a columnar structure with a rectangular cross-section. Each first memory cell 540-1 and each second memory cell 540-2 includes lower electrodes 541-1 and 541-2, selection devices 543-1 and 543-2, intermediate electrodes 545-1 and 545-2, heating electrodes 547-1 and 547-2, and variable resistor patterns 549-1 and 549-2, respectively. Because the first memory cell 540-1 and the second memory cell 540-2 have substantially the same structure, for ease of discussion, the following description will be given with reference to the first memory cell 540-1.

[0157] A first spacer 550-1 is provided to surround the side surface of the first memory cell 540-1. A second spacer 550-2 is provided to surround the side surface of the second memory cell 540-2. Because the first spacer 550-1 and the second spacer 550-2 are provided to surround the sides of the first memory cell 540-1 and the second memory cell 540-2, the first spacer 550-1 and the second spacer 550-2 can be used to protect the first memory cell 540-1 and the second memory cell 540-2 (especially the variable resistor patterns 549-1 and 549-2 and / or the selection devices 543-1 and 543-2).

[0158] In the storage device 500, a first spacer 550-1 has a first thickness T1, and a second spacer 550-2 has a second thickness T2. In some example embodiments, the first thickness T1 is greater than the second thickness T2. In the storage device 500, by forming a thick first spacer 550-1 for the first storage cell 540-1 and a thinner second spacer 550-2 for the second storage cell 540-2, the resistive characteristics of the first storage cell 540-1 and the second storage cell 540-2 can be modified, for example, enhanced.

[0159] The storage device 500 also includes a first internal spacer 552-1 and a second internal spacer 552-2. The first internal spacer 552-1 is provided to cover the lower electrode 541-1 and select device 543-1 of the first storage cell 540-1, and the second internal spacer 552-2 is provided to cover the lower electrode 541-2 and select device 543-2 of the second storage cell 540-2. The first internal spacer 552-1 and the second internal spacer 552-2 can be formed using a process separate from the process used to form the first spacer 550-1 and the second internal spacer 550-2, in order to more effectively protect the select devices 543-1 and 543-2. ​​However, in some example embodiments, the first internal spacer 552-1 and the second internal spacer 552-2 are omitted.

[0160] like Figure 19 As shown, a first insulating layer 560a is disposed between the first electrode lines 510, and a second insulating layer 560b is disposed between the first memory cells 540-1 of the first memory cell layer MCL1. Additionally, a third insulating layer 560c is disposed between the second electrode lines 520, a fourth insulating layer 560d is disposed between the second memory cells 540-2 of the second memory cell layer MCL2, and a fifth insulating layer 560e is disposed between the third electrode lines 530.

[0161] Figure 21 This is a flowchart illustrating a method of operating a resistive storage device according to some example embodiments.

[0162] refer to Figures 3 to 21 In the method of operating resistive memory device 200, resistive memory device 200 includes memory cell array 210, memory cell array 210 includes multiple resistive memory cells connected / coupled to multiple word lines and multiple bit lines, and includes multiple memory blocks and multiple write drivers corresponding to the multiple memory blocks, each memory block includes K memory chips, row decoder 220 and column decoder 230 determine one of the resistive memory cells as the selected memory cell based on address ADDR including row address and column address (S710).

[0163] The first write driver, which corresponds to the first memory block including the selected memory cell, automatically compensates for the resistance distribution based on the physical location of the first memory block including the selected memory cell and provides a write current with a normal level to the selected memory cell (S730).

[0164] Figure 22 This is a diagram illustrating a non-volatile memory module according to some example embodiments.

[0165] refer to Figure 22 The non-volatile memory module 700 may include multiple non-volatile memory chips (NVM) 710 and a module controller (NVM CTRL) 720.

[0166] like Figure 22 As shown, multiple non-volatile memory chips 710 can be disposed on a printed circuit board (PCB) 705, and a module controller 720 can be disposed on the PCB 705 among the multiple non-volatile memory chips 710. In some example embodiments, the multiple non-volatile memory chips 710 and the module controller 720 can be disposed on the PCB 705 according to the Non-Volatile Dual In-line Memory Module (NVDIMM) standard.

[0167] In some example embodiments, each of the plurality of non-volatile memory chips 710 may employ Figure 3 The resistive memory device 200. Each non-volatile memory chip 710 may include a phase-change memory cell. In some example embodiments, at least one of the plurality of non-volatile memory chips 710 may include a NAND flash memory device, and the remainder of the plurality of non-volatile memory chips 710 may employ Figure 3 200 resistive storage device.

[0168] The module controller 720 can receive command signals, address signals, and data from the memory controller 100, and can control the operation of the plurality of non-volatile memory chips 710 by providing command signals, address signals, and / or data to at least one of the plurality of non-volatile memory chips 710.

[0169] Figure 23 This is a block diagram illustrating a mobile system according to some example embodiments.

[0170] refer to Figure 23 The mobile system 800 includes an application processor (AP) 810, connectivity circuitry 820, volatile storage device (VM) 830, non-volatile storage device (NVM) 840, user interface 850, and power supply 860, all connected via a system bus 870. Any or all components of the mobile system 800, such as AP 810, connectivity circuitry 820, VM 830, NVM 840, user interface 850, or power supply 860, may include processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof.

[0171] The application processor 810 can execute at least one application such as a web browser, a game application, a video player, etc. The connection circuit 820 can perform wired and / or wireless communication with external devices.

[0172] The volatile storage device 830 may store data processed by the application processor 810 or may operate as working memory. For example, the volatile storage device 830 may be or include DRAM, such as at least one of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power DDR (LPDDR) SDRAM, Graphics DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), etc.

[0173] The non-volatile storage device 840 can store a boot image and other data for booting the mobile system 800. The non-volatile storage device 840 can be or includes phase change random access memory (PRAM) using phase change materials, resistive random access memory (RRAM) using variable resistive materials such as composite metal oxides, and / or magnetoresistive random access memory (MRAM) using magnetic materials.

[0174] User interface 850 may include at least one input device (e.g., a keypad, a touchscreen, etc.) and at least one output device (e.g., a speaker, a display device, etc.). Power supply 860 may supply power voltage to mobile system 800.

[0175] The non-volatile storage device 840 can (automatically) compensate for resistance distribution based on the physical location of the first storage block including the selected storage cell, and provide a write current with a normal level to the selected storage cell, as shown in the reference. Figures 1 to 21 As described.

[0176] The example embodiments can be applied to resistive memory devices and systems that include resistive memory devices.

[0177] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that many variations and modifications can be made to the described exemplary embodiments without departing substantially from the principles of this disclosure as defined by the appended claims.

Claims

1. A resistive storage device, comprising: A memory cell array includes multiple resistive memory cells connected to multiple word lines and multiple bit lines. The memory cell array is divided into multiple memory blocks, each memory block including K memory chips, where K is a natural number greater than 1. A write / read circuit is connected to the memory cell array via a row decoder and a column decoder. The write / read circuit is configured to perform write operations in target memory chips of the memory cell array. The write / read circuit includes a plurality of write drivers corresponding to the plurality of memory blocks. A control voltage generator is configured to generate a first control voltage and a second control voltage based on a reference current, and to provide the first control voltage and the second control voltage to the write / read circuit. as well as The control circuit is configured to control the write / read circuit and the control voltage generator. The first write driver, which corresponds to the first memory block among the plurality of memory blocks, is configured to provide a write current to the target memory chip corresponding to the physical location of a selected memory cell in the memory cell array.

2. The resistive storage device according to claim 1, wherein, The control voltage generator is disposed in the peripheral region of the semiconductor substrate on which the resistive memory device is located, and The plurality of write drivers are disposed in a core region of the semiconductor substrate that is separated from the peripheral region.

3. The resistive storage device according to claim 1, wherein, The control voltage generator includes: A first control voltage generation circuit is configured to generate the first control voltage based on the reference current, the first control voltage generation circuit including a first active element and a second active element; and A second control voltage generation circuit is configured to generate the second control voltage based on the reference current, the second control voltage generation circuit including a third active element and a fourth active element.

4. The resistive storage device according to claim 3, wherein, The first control voltage generation circuit includes a first active element, a second active element, and a fifth active element connected in series between a first node receiving the reference current and a negative voltage. The second control voltage generation circuit includes a third active element, a fourth active element, and a sixth active element connected in series between the second node receiving the reference current and the negative voltage. Each of the first active element, the second active element, the third active element, the fourth active element, the fifth active element, and the sixth active element comprises an n-channel metal-oxide-semiconductor (NMOS) transistor.

5. The resistive storage device according to claim 4, wherein, The gate of the second active element is connected to the first node. The first control voltage generation circuit is configured to provide the first control voltage to the first node. The gates of the third active element and the fourth active element are connected to the second node, and The second control voltage generation circuit is configured to provide the second control voltage to the second node.

6. The resistive storage device according to claim 3, wherein, The first control voltage generation circuit includes a first active element, a second active element, and a first resistor connected in series between the first node receiving the reference current and the negative voltage. The second control voltage generation circuit includes a third active element, a fourth active element, and a second resistor connected in series between the second node receiving the reference current and the negative voltage. Each of the first active element, the second active element, the third active element, and the fourth active element comprises an n-channel metal-oxide-semiconductor (NMOS) transistor.

7. The resistive storage device according to claim 3, wherein, The control voltage generator also includes: A first buffer is configured to buffer the first control voltage; and The second buffer is configured to buffer the second control voltage.

8. The resistive storage device according to claim 1, wherein, The first write drive includes: A bias transistor is configured to generate the write current based on the first control voltage; A shielding transistor, connected between the bias transistor and the data sensing node, is configured to provide a voltage drop corresponding to the resistance between the data sensing node and the selected memory cell based on the second control voltage; and A degradation element is connected between the bias transistor and the negative voltage.

9. The resistive storage device according to claim 8, wherein, The voltage drop is inversely proportional to the resistance between the data sensing node and the selected storage unit.

10. The resistive storage device according to claim 8, wherein, The bias transistor includes a first n-channel metal-oxide-semiconductor (NMOS) transistor, the gate of which is configured to receive the first control voltage. The shielding transistor includes a second NMOS transistor, the gate of which is configured to receive the second control voltage. The degradation element includes a third NMOS transistor, the gate of which is configured to receive a bias voltage, and the third NMOS transistor is connected between the first NMOS transistor and the negative voltage.

11. The resistive storage device according to claim 8, wherein, The bias transistor includes a first n-channel metal-oxide-semiconductor (NMOS) transistor, the gate of which receives the first control voltage. The shielding transistor includes a second NMOS transistor, the gate of which receives the second control voltage. The degradation element includes a degradation resistor connected between the first NMOS transistor and the negative voltage.

12. The resistive storage device according to claim 8, wherein, The shielding transistor is configured to adjust the drain-source voltage of the bias transistor inversely proportional to the resistance between the data sensing node and the selected memory cell.

13. The resistive storage device according to claim 8, wherein, The bias transistor is configured to generate the write current regardless of the physical location of the target memory chip.

14. The resistive storage device according to claim 1, wherein, The write / read circuit includes: The read circuitry is connected via a column selection switch to a selected bit line connected to the selected memory cell, the selected bit line being one of the plurality of bit lines; and The write circuitry includes a first write driver connected via a row selection switch to a selected word line connected to a selected memory cell, the selected word line being one of the plurality of word lines.

15. The resistive storage device according to claim 1, wherein, Each of the plurality of resistive memory cells includes a variable resistor element and a selection element connected in series between a corresponding word line in the plurality of word lines and a corresponding bit line in the plurality of bit lines. The variable resistance element comprises a phase change material whose resistance changes with temperature, and The resistive storage device includes a phase-change random access memory (PRAM) device.

16. The resistive storage device according to claim 1, wherein, The control circuit includes: The command decoder is configured to decode commands from the external memory controller and output the decoded commands. An address buffer is configured to receive access addresses from the external memory controller and output row and column addresses based on the access addresses; A location information generator is configured to generate location information indicating the location of the selected storage unit based on the row address and the column address; and A control signal generator is configured to generate control signals based on the decoded commands and the position information to control the row decoder, the column decoder, the control voltage generator, and the write / read circuitry.

17. The resistive storage device according to claim 1, wherein, The control circuit and the write / read circuit are arranged on an integrated circuit layer, which is arranged on a substrate, and the memory cell array is arranged on the integrated circuit layer. The memory cell array includes: a first memory cell layer comprising first memory cells; and a second memory cell layer comprising second memory cells, wherein the first memory cells and the second memory cells share the plurality of bit lines, and The plurality of word lines include a lower word line connected to the first memory cell and an upper word line connected to the second memory cell.

18. A resistive storage device, comprising: A memory cell array includes multiple resistive memory cells connected to multiple word lines and multiple bit lines. The memory cell array is divided into multiple memory blocks, each memory block including K memory chips, where K is a natural number greater than 1. A row decoder is connected to the storage cell array via the multiple word lines, and the row decoder includes multiple row selection switches; A column decoder is connected to the memory cell array via the multiple bit lines, and the column decoder includes multiple column selection switches; A write / read circuit is connected to the memory cell array via the row decoder and the column decoder. The write / read circuit is configured to perform write operations in target memory chips of the memory cell array. The write / read circuit includes a plurality of write drivers corresponding to the plurality of memory blocks. A control voltage generator is configured to generate a first control voltage and a second control voltage based on a reference current, and to provide the first control voltage and the second control voltage to the write / read circuit. as well as The control circuitry is configured to control the write / read circuitry and the control voltage generator based on commands and addresses. The first write driver, which corresponds to the first memory block among the plurality of memory blocks, is configured to provide a write current to the target memory chip corresponding to the physical location of a selected memory cell in the memory cell array.

19. The resistive storage device according to claim 18, wherein, The control voltage generator is disposed in the peripheral region of the semiconductor substrate on which the resistive memory device is located, and The first write drive includes: A bias transistor is configured to generate the write current based on the first control voltage; A shielding transistor, connected between the bias transistor and the data sensing node, is configured to provide a voltage drop corresponding to the resistance between the data sensing node and the selected memory cell based on the second control voltage; and A degradation element is connected between the bias transistor and the negative voltage.

20. A method of operating a resistive memory device, the resistive memory device comprising a memory cell array, the memory cell array including a plurality of resistive memory cells connected to a plurality of word lines and a plurality of bit lines, wherein the memory cell array is divided into a plurality of memory blocks, each of the plurality of memory blocks including K memory chips, K being a natural number greater than 1, the method comprising: Based on the row address and column address indicated in the write command, identify the selected memory cell among the plurality of resistive memory cells located in the target memory chip; as well as The first write driver among a plurality of write drivers corresponding to the plurality of memory blocks provides a write current corresponding to the physical location of the selected memory cell in the target memory chip in the memory cell array, based on the write command.

Images