Semiconductor device with buried gate structure and method for manufacturing the same

Abstract

The present application provides a semiconductor device with a buried gate structure and a method for manufacturing the same. A method for manufacturing a semiconductor device includes: forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate partially filling the trench above the gate dielectric layer, forming a low work function layer above the lower gate, forming a spacer above the low work function layer, etching the low work function layer to self-align with the spacer to form a vertical gate on two upper edges of the lower gate, and forming an upper gate above the lower gate between inner sidewalls of the vertical gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0114010, filed on September 17, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor device, and more particularly, to a semiconductor device having a buried gate structure and a method of manufacturing the semiconductor device. Background Art

[0004] In order to achieve high performance of transistors, metal gate electrodes are applied. In particular, buried gate type transistors require control of threshold voltage to achieve high performance operation. In addition, gate induced drain leakage current (GIDL) characteristics have a great influence on the performance of buried gate type transistors. Summary of the invention

[0005] Various embodiments of the present invention are directed to a semiconductor device that can improve gate induced drain leakage (GIDL), and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a trench in a substrate; forming a gate dielectric layer above the surface of the trench; forming a lower gate above the gate dielectric layer, the lower gate partially filling the trench; forming a low work function layer above the lower gate; forming a spacer on the low work function layer; etching the low work function layer to self-align with the spacer so as to form a vertical gate on two upper edges of the lower gate; and forming an upper gate above the lower gate between the inner side walls of the vertical gate.

[0007] According to an embodiment, a semiconductor device may include: a gate dielectric layer conformally covering a trench of a substrate; a lower gate formed above the gate dielectric layer and partially filling a lower portion of the trench; a vertical gate formed on two upper edges of the lower gate; an upper gate filling an inner space of the vertical gate; a covering layer formed above the upper gate; and a spacer formed between the gate dielectric layer and the covering layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2A is a diagram showing the semiconductor device along Figure 1 A cross-sectional view taken along line AA′ is shown in FIG.

[0010] Figure 2B is a diagram showing the semiconductor device along Figure 1 A cross-sectional view taken along line BB′ is shown in FIG.

[0011] FIG. 3A to FIG. 3K is a cross-sectional view illustrating an example of a method of forming a semiconductor device according to an embodiment of the present invention.

[0012] Figure 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0013] FIG. 5A to FIG. 5C It is shown Figure 4 A cross-sectional view of an example of a method of forming a semiconductor device shown in FIG.

[0014] Fig. 6A and Figure 6B is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0015] FIG. 7A to FIG. 7G is a cross-sectional view illustrating an example of a method of forming a semiconductor device according to an embodiment of the present invention.

[0016] FIG. 8A to FIG. 8C It is shown Figure 6B A cross-sectional view of an example of a method of forming a semiconductor device shown in FIG.

[0017] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0018] FIG. 12A to FIG. 12F It is shown Fig. 9A A cross-sectional view of an example of a method of forming a semiconductor device shown in FIG.

[0019] Fig.13 is a cross-sectional view showing a memory cell. DETAILED DESCRIPTION

[0020] The various embodiments described herein may be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices according to specific embodiments of the present invention. It should be noted that the structures in the accompanying drawings may be modified by manufacturing techniques and / or tolerances. The present invention is not limited to the described embodiments and the specific structures shown in the accompanying drawings, but may include other embodiments, or modifications to the described embodiments, including any modifications to the structures according to the requirements of the manufacturing process. Accordingly, the areas shown in the accompanying drawings have schematic properties, and the shapes of the areas shown in the accompanying drawings are intended to illustrate the specific structures of the areas of the elements, rather than to limit the scope of the present invention.

[0021] Here, in an embodiment of the present invention, the threshold voltage Vt may depend on the flat band voltage VFB, and the flat band voltage VFB may depend on the work function. The work function may be adjusted by various methods. For example, the work function may be adjusted by the material used for the gate electrode, or by the material used between the gate electrode and the channel of the memory cell. Adjusting the work function may cause the flat band voltage to shift. Generally speaking, a high work function may shift the flat band voltage in a positive direction, while a low work function may shift the flat band voltage in a negative direction. In this way, the threshold voltage may be adjusted by shifting the flat band voltage. In various embodiments, the threshold voltage may be adjusted by shifting the flat band voltage even when the channel doping concentration is reduced or the channel doping is omitted. In particular, the flat band voltage may be reduced by using a material with a low work function, thereby improving the gate induced drain leakage current (GIDL).

[0022] Here, in various embodiments of the semiconductor device of the present invention, a buried gate structure may be provided in the trench. The buried gate structure may include a stack of a gate dielectric layer, a gate electrode, and a capping layer. The gate dielectric layer may cover the surface of the trench, and the gate electrode may be formed on the gate dielectric layer. The gate electrode may be in direct contact with the gate dielectric layer. The gate electrode may partially fill the trench, and the capping layer may fill the remaining portion of the trench not covered by the gate electrode. The gate electrode may be referred to as a "buried gate electrode".

[0023] The gate electrode according to the present invention may be a dual gate electrode. Unlike a single gate electrode generally formed of a single material of polysilicon or metal, a dual gate may include a double layer stack of different gate electrodes. The dual gate electrode may include a same metal dual gate formed by stacking two layers made of the same metal, a different metal dual gate formed by stacking two layers made of different metals, or a different material dual gate formed by stacking a layer made of metal and a layer made of polysilicon.

[0024] The dual gate may include an upper gate and a lower gate. The lower gate may include a barrier layer and a low-resistivity material, the barrier layer separating the low-resistivity material from a gate dielectric layer lining a trench in which a gate electrode is formed. The barrier layer may be used to block impurities that diffuse from the low-resistivity material to the gate dielectric layer, or to prevent mutual diffusion and reaction between the two different materials. The low-resistivity material may be used to reduce the sheet resistance of the gate electrode.

[0025] The gate electrode may include a material having an engineered work function. Engineering of the work function may refer to a material or method that can adjust the work function to have a reduced work function (ie, a low work function) or an increased work function (ie, a high work function).

[0026] The lower gate may fill the lower portion of the trench, while the upper gate may fill the middle portion of the trench. The upper gate may be formed on the lower gate and in direct contact with the lower gate. The gate electrode may be referred to as a double gate, wherein the upper gate is located on the lower gate. The lower gate may overlap the channel vertically and laterally. The upper gate may overlap the first doped region and the second doped region (i.e., the source region and the drain region) laterally. The overlap of the upper gate with the first doped region and the second doped region may only partially overlap, which means that the upper gate does not extend together with the first doped region and the second doped region in the vertical direction.

[0027] Figure 1 is a plan view illustrating a semiconductor device 100 according to an embodiment of the present invention. Figure 2A The semiconductor device 100 is shown along Figure 1 A cross-sectional view taken along line AA′ is shown in FIG. Figure 2B The semiconductor device 100 is shown along Figure 1 A cross-sectional view taken along line BB′ is shown in FIG.

[0028] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor device 100 may include a substrate 101 and a buried gate structure 100G embedded in the substrate 101. The semiconductor device 100 may be a part of a memory cell. For example, the semiconductor device 100 may be a part of a memory cell of a DRAM.

[0029] The substrate 101 may be a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a silicon-containing material. The substrate 101 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 101 may include another semiconductor material, such as germanium. The substrate 101 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0030] An isolation layer 102 and an active region 104 may be formed in a substrate 101. The active region 104 may be defined by the isolation layer 102. The isolation layer 102 may be a shallow trench isolation (STI) region formed by trench etching. The isolation layer 102 may be formed by filling a shallow trench (e.g., isolation trench 103) with a dielectric material. The isolation layer 102 may be made of or include silicon oxide, silicon nitride, or a combination thereof.

[0031] A trench 105 may be formed in the substrate 101. Figure 1 , the groove 105 may have a linear shape extending in any direction. The groove 105 may have a linear shape that crosses the active area 104 and the isolation layer 102. The groove 105 may have a depth shallower than the isolation groove 103. The groove 105 is a space in which the buried gate structure 100G is formed, and may also be referred to as a "gate groove". In one embodiment, the groove 105 may have a bottom with a curvature (also referred to as a bottom surface in this article), and an upper portion having a first sidewall and a second sidewall opposite to each other. The sidewalls of the groove 105 may be slightly curved at the edge portion where it is connected to the bottom of the groove 105. The sidewalls of the groove 105 may be perpendicular to or substantially perpendicular to the top surface of the substrate. In some other embodiments, the groove 105 may have a bottom that is substantially flat and parallel to the top surface of the substrate 101 (also referred to as a bottom surface in this article). The edge of the bottom of the groove 105 may be curved to provide a smooth transition between the vertical sidewall and the flat bottom. The sidewall of the trench may be slightly curved at an edge portion thereof connecting with the bottom of the trench 105 .

[0032] The first doping region 107 and the second doping region 108 may be formed in the active region 104. The first doping region 107 and the second doping region 108 may be doped with conductive dopants. For example, the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb) or boron (B). The first doping region 107 and the second doping region 108 may be doped with the same conductive dopant. The first doping region 107 and the second doping region 108 may be located in the active region 104 on both sides of the trench 105. The bottom surfaces of the first doping region 107 and the second doping region 108 may be located at a predetermined depth from the top surface of the active region 104. The first doping region 107 and the second doping region 108 may contact the sidewalls of the trench 105. The bottom surfaces of the first doping region 107 and the second doping region 108 may be higher than the bottom surface of the trench 105. The first doping region 107 may be referred to as a "first source / drain region", and the second doping region 108 may be referred to as a "second source / drain region". A channel 106 may be defined between the first doping region 107 and the second doping region 108 by the buried gate structure 100G. The channel 106 may be defined along the contour of the trench 105.

[0033] The trench 105 may include a first trench T1 and a second trench T2. The first trench T1 may be formed in the active area 104. The second trench T2 may be formed in the isolation layer 102. The trench 105 may have a shape extending continuously from the first trench T1 to the second trench T2. In the trench 105, the bottom surfaces of the first trench T1 and the second trench T2 may be located at different levels. For example, the bottom surface of the first trench T1 may be located at a level higher than the bottom surface of the second trench T2. Since the isolation layer 102 is recessed, a height difference may be formed between the first trench T1 and the second trench T2. Therefore, the second trench T2 may include a recessed region R having a bottom surface lower than the first trench T1. Due to the step change in depth between the first trench T1 and the second trench T2, a fin region 104F may be formed in the active area 104. Therefore, the active area 104 may include a fin region 104F.

[0034] Therefore, the fin region 104F may be formed below the first trench T1, and the sidewall of the fin region 104F is exposed through the recessed isolation layer 102F. The fin region 104F is a region that may form a portion of the channel CH. The fin region 104F is also referred to as a "saddle fin". The fin region 104F may increase the channel width and improve electrical characteristics.

[0035] In one embodiment, the fin region 104F may be omitted.

[0036] The buried gate structure 100G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105. The buried gate structure 100G may also include a gate electrode 120 and a capping layer 130, which are sequentially stacked in the vertical direction within the trench to fill the trench 105. The gate electrode 120 and the capping layer 130 may be directly formed on the gate dielectric layer 110. The gate electrode 120 may be composed of or include a lower gate 121, an upper gate 122, and a vertical gate 123. The lower gate 121 may fill the lower portion of the trench 105 on the gate dielectric layer 110. The upper gate 122 and the vertical gate 123 may be directly formed on the lower gate 121 to fill the middle portion of the trench 105. The vertical gate 123 may be formed on both upper edges of the lower gate 121 and directly contact a portion of the gate dielectric layer 110 covering the sidewalls of the trench 105. The upper gate 122 may be formed to fill the space formed between the inner sidewalls of the vertical gate 123. The outer sidewalls of the vertical gate 123 are in direct contact with the corresponding portions of the gate dielectric layer 110 covering the sidewalls of the trench 105. The capping layer 130 may fill the upper portion of the trench 105 covering the upper gate 122 and the vertical gate 123. The lower, middle, and upper portions of the trench 105 are for convenience of description, and their heights or depths may be the same or different. In a top view, the ends of the vertical gate 123 may be connected to each other and surround the sidewalls of the upper gate 122.

[0037] The gate dielectric layer 110 may be made of silicon oxide, silicon nitride, silicon oxynitride, high-K material or a combination thereof, or include silicon oxide, silicon nitride, silicon oxynitride, high-K material or a combination thereof. The high-K material may be or include a material having a higher dielectric constant than silicon oxide. For example, the high-K material may be or include any suitable material having a dielectric constant higher than 3.9. In one embodiment, the high-K material may be or include any suitable material having a dielectric constant higher than 10. In one embodiment, the high-K material may be or include any suitable material having a dielectric constant in the range of 10 to 30. The high-K material may be or include at least one metal element. The high-K material may be or include a hafnium-containing material. The hafnium-containing material may be or include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride or a combination thereof. In one embodiment, the high-K material may be or include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide or a combination thereof. As the high-K material, other well-known high-K materials may also be selectively used. The gate dielectric layer 110 may be or include a metal oxide.

[0038] The gate electrode 120 may be located inside the trench 105 so that the top layer of the gate electrode 120 may be located at a level lower than the top surface of the active area 104. The lower gate 121 may have a shape that fills the lower portion of the trench 105. The lower gate 121 may be or include a low resistivity material so as to reduce the gate sheet resistance. The lower gate 121 may be or include a metal-based material. The lower gate 121 may be or include a metal, a metal nitride, or a combination thereof. The lower gate 121 may be or include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. In one embodiment, the lower gate 121 may be formed only of titanium nitride. In another embodiment, the lower gate 121 may be formed by a stack of titanium nitride (TiN) and tungsten (W), referred to as a TiN / W stack.

[0039] In one embodiment, the lower gate 121 may have a high work function, i.e., a work function higher than the mid-bandgap work function of silicon. A low work function refers to a work function lower than the mid-bandgap work function of silicon. Specifically, the high work function may be higher than 4.5 eV, while the low work function may be lower than 4.5 eV. The lower gate 121 may be made of or include P-type polysilicon or nitrogen-rich titanium nitride (TiN).

[0040] In one embodiment, the lower gate 121 may have an increased high work function. The lower gate 121 may be made of or include metal silicon nitride. The metal silicon nitride may be a metal nitride doped with silicon. The lower gate 121 may be made of or include metal silicon nitride with an adjusted silicon atomic percentage. For example, the lower gate 121 may be made of or include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function and contain silicon to further increase its work function. Titanium silicon nitride may have an adjusted silicon atomic percentage, thereby having an increased high work function. In order to have an increased high work function, the atomic percentage (at%) of silicon in titanium silicon nitride may be equal to or less than 21at%. As a comparative example, in order to have a low work function, the atomic percentage (at%) of silicon in titanium silicon nitride may be equal to or greater than 30at%.

[0041] The upper gate 122 may be formed directly on the lower gate 121 to fill the space of the middle portion of the trench 105 defined by the vertical gate 123. Therefore, the upper gate 122 may have a shape that partially fills the middle portion of the trench 105. The top surface of the upper gate 122 may be located at a level lower than the top surface of the active region 104. The upper gate 122 and the lower gate 121 may be made of the same material or different materials. In one embodiment, the upper gate 122 and the lower gate 121 may be made of the same material. In another embodiment, the upper gate 122 and the lower gate 121 may be made of different materials.

[0042] The upper gate 122 may be made of a low resistivity material to reduce the gate sheet resistance. The upper gate 122 may be made of or include a metal-based material. The upper gate 122 may be made of or include a metal, a metal nitride, or a combination thereof. The upper gate 122 may be made of tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof, or include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. In one embodiment, the upper gate 122 may be formed only of titanium nitride. In another embodiment, the upper gate 122 may be formed by a stack of titanium nitride (TiN) and tungsten (W) (i.e., a TiN / W stack). In one embodiment, each of the lower gate 121 and the upper gate 122 may be formed only of titanium nitride. In another embodiment, each of the lower gate 121 and the upper gate 122 may be formed of a stack of titanium nitride (TiN) and tungsten (W) (i.e., a TiN / W stack). The upper gate 122 may have a smaller height than the lower gate 121, so the volume of the trench 105 occupied by the lower gate 121 may be larger. The upper gate 122 may be formed to have a smaller width than the lower gate 121, and the vertical gate 123 fills the space between the gate dielectric layer 110 and the sidewall of the upper gate 122. Therefore, the upper gate 122 may not directly contact the gate dielectric layer 110.

[0043] The vertical gate 123 may cover both sidewalls of the upper gate 122. The vertical gate 123 may be located between the upper gate 122 and the gate dielectric layer 110. The vertical gate 123 may extend vertically from both upper edge surfaces of the lower gate 121. The vertical gate 123 may have a lower work function than the lower gate 121. The vertical gate 123 may be made of or include a low work function metal or N-type polysilicon.

[0044] In the present embodiment, the lower gate 121 and the upper gate 122 may be made of or include a low-resistivity metal-based material, and the vertical gate 123 may be made of or include a low-work function material.

[0045] The capping layer 130 may be used to protect the upper gate 122 and the vertical gate 123. The capping layer 130 may fill the upper portion of the trench 105 and may be formed directly on the upper gate 122 and the vertical gate 123. The top surface of the capping layer 130 may be located at the same level as the top surfaces of the first doping region 107 and the second doping region 108. The capping layer 130 may be made of a dielectric material or include a dielectric material. The capping layer 130 may be made of silicon nitride, silicon oxynitride, or a combination thereof or include silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the capping layer 130 may be made of a combination of silicon nitride and silicon oxide or include a combination of silicon nitride and silicon oxide. The capping layer 130 may be made of a silicon nitride liner and a spin-on dielectric (SOD) material or include a silicon nitride liner and a spin-on dielectric (SOD) material.

[0046] A hard mask layer 109 may be formed on both sides of the cap layer 130. The hard mask layer 109 may be directly formed on both sides of the cap layer 130. The hard mask layer 109 may be made of or include a dielectric material. The hard mask layer 109 may be formed on the substrate 101 and cover the active area 104 and the isolation layer 102. The hard mask layer 109 may be in direct contact with the active area 104 and the isolation layer 102.

[0047] As described above, the gate electrode 120 may include the lower gate 121, the upper gate 122, and the vertical gate 123. This structure may be advantageous because gate induced drain leakage (GIDL) may be significantly improved by the vertical gate 123.

[0048] FIG. 3A to FIG. 3K is a cross-sectional view illustrating an example of a method of forming a semiconductor device according to an embodiment of the present invention. FIG. 3A to FIG. 3K The diagram shows Figure 2A An example of a method of forming the semiconductor device 100 is provided.

[0049] like Figure 3A As shown, an isolation layer 12 can be formed in the substrate 11 to define an active area 14. The isolation layer 12 can be formed using a shallow trench isolation (STI) process. For example, an isolation trench 13 can be formed by etching the substrate 11, and filled with a dielectric material to form the isolation layer 12. The isolation layer 12 can be made of silicon oxide, silicon nitride, or a combination thereof or include silicon oxide, silicon nitride, or a combination thereof. The isolation trench 13 can be filled with a dielectric material using a deposition process such as a chemical vapor deposition (CVD) process. In addition, a planarization process such as chemical-mechanical polishing (CMP) can also be used to remove any excess deposited material above the isolation trench 13.

[0050] A trench 15 may be formed in the substrate 11. The trench 15 may have a linear shape that crosses the active region 14 and the isolation layer 12. The trench 15 may be formed by etching the substrate 11 using a hard mask layer 16 as an etching mask. The hard mask layer 16 may be formed on the substrate 11 and the isolation layer 12, and may have a linear opening. The hard mask layer 16 may be formed of a material having an etching selectivity relative to the material of the substrate 11. For example, the hard mask layer 16 may be silicon oxide, such as tetraethyl orthosilicate (TEOS). The trench 15 may be formed to be shallower than the isolation trench 13. The trench 15 may be deep enough and wide enough to allow the formation of a sufficiently large gate electrode having a large average cross-sectional area to be formed subsequently. In this way, the resistance of the gate electrode may be reduced. In one embodiment, the bottom edge of the trench 15 may have an arc.

[0051] Subsequently, the fin region 14F may be formed. The fin region 14F may be formed by selectively recessing the isolation layer 12 below the trench 15. For the structure of the fin region 14F, refer to Figure 2B Fin region 104F.

[0052] like Figure 3B As shown, a gate dielectric layer 17 may be formed directly on the surface of the trench 15 to cover the entire surface (bottom and sidewalls) of the trench 15. Before forming the gate dielectric layer 17, the surface of the trench 15 damaged by the etching process may be restored. For example, a sacrificial oxide may be formed by a thermal oxidation process, and then the sacrificial oxide may be removed. The gate dielectric layer 17 may be formed by a thermal oxidation process. The gate dielectric layer 17 may be made of or include silicon oxide. In one embodiment, the gate dielectric layer 17 may be formed by a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The gate dielectric layer 17 formed by the deposition process may be made of a high-K material, an oxide, a nitride, an oxynitride, or a combination thereof, or may include a high-K material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-K material may be or include a hafnium-containing material. The hafnium-containing material may be or include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In one embodiment, the high-K material may be or include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide, or a combination thereof. As the high-K material, other well-known high-K materials may also be selectively used. The gate dielectric layer 17 may include a stack of silicon oxide and a high-K material, and the high-K material may be or include a material having a higher surface density of oxygen atoms than silicon oxide.

[0053] like Figure 3CAs shown, a lower gate layer 18' may be formed on the gate dielectric layer 17 and the hard mask layer 16. The lower gate layer 18' may be directly formed on the gate dielectric layer 17 and the hard mask layer 16. The lower gate layer 18' may fill the trench 15 and directly contact the gate dielectric layer 17 covering the bottom and sidewalls of the trench 15. The lower gate layer 18' may be made of or include a low-resistivity metal material. The lower gate layer 18' may be made of or include tungsten. The lower gate layer 18' may be formed by deposition including, for example, CVD or ALD.

[0054] In one embodiment, the lower gate layer 18' may be made of or include a high work function material. The lower gate layer 18' may be made of or include a high work function metal-based material or a high work function polysilicon. The high work function polysilicon may be or include P-type polysilicon. The high work function metal may be or include nitrogen-rich titanium nitride (TiN).

[0055] like Figure 3D As shown, a lower gate 18 can be formed in the trench 15. In order to form the lower gate 18, a recessing process can be performed. The recessing process can be or include a dry etching process, such as an etch-back process. The etch-back process can be performed using plasma. The lower gate 18 can be formed by performing an etch-back process on the lower gate layer 18'. In one embodiment, a planarization process can be performed first to expose the top surface of the hard mask layer 16, and then an etch-back process of the recessing process can be performed on the lower gate layer 18'. The top surface of the lower gate 18 can be recessed to a level lower than the top surface of the active area 14. After the lower gate 18 is formed, a portion of the surface of the gate dielectric layer 17 can be exposed.

[0056] like Figure 3E As shown, a work function layer 19B may be formed on the lower gate 18. The work function layer 19B may be in direct contact with the lower gate 18. In order to form the work function layer 19B, a work function material 19A may be deposited to fill the trench 15 on the lower gate 18, and then a recess process may be performed on the work function material 19A. The work function material 19A may be formed by a deposition including, for example, CVD or ALD. The recess process on the work function material 19A may include a dry etching process such as an etch-back process. The work function layer 19B may be formed by performing an etch-back process on the work function material 19A. In one embodiment, a planarization process may be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of a recess process may be performed on the work function material 19A. The top surface of the work function layer 19B may be located at a level lower than the top surface of the active area 14.

[0057] The work function layer 19B may have a work function lower than that of the lower gate 18. The work function layer 19B may have a work function layer 19B lower than the mid-bandgap work function of silicon. The work function layer 19B may be referred to as a low work function layer. The work function layer 19B may be made of or include a low work function metal-based material or a low work function polysilicon. The low work function polysilicon may be made of or include N-type polysilicon. The low work function metal may be made of or include titanium-rich titanium nitride (TiN). In the present embodiment, the work function layer 19B may be polysilicon doped with N-type impurities.

[0058] After forming the work function layer 19B, a portion of the surface of the gate dielectric layer 17 may be exposed. The work function layer 19B may have a shape that partially fills the trench 15 on the lower gate 18.

[0059] like Figure 3F As shown, a spacer layer 20′ may be formed. The spacer layer 20′ may be made of or include a material that is selective to the etching process on the work function layer 19B. The etching process may be a dry etching process. The spacer layer 20′ may be made of or include an oxide. The spacer layer 20′ may be made of or include silicon oxide. The spacer layer 20′ may include a conformal film deposition (CFD) oxide or an ultra low temperature oxide (ULTO). The spacer layer 20′ may cover the top surface of the work function layer 19B, the exposed portion of the gate dielectric layer 17, and the surface of the hard mask layer 16.

[0060] like Figure 3G As shown, a spacer 20 may be formed. To form the spacer 20, the spacer layer 20′ may be etched by an etch-back process. The spacer 20 may cover the exposed portion of the gate dielectric layer 17, and the bottom surface of the spacer 20 may contact the edge side top surface of the work function layer 19B. Most of the top surface of the work function layer 19B may be exposed by the spacer 20. A portion of the spacer 20 may cover the exposed portion of the gate dielectric layer 17 and the surface of the hard mask layer 16.

[0061] Subsequently, a vertical gate 19 may be formed. The vertical gate 19 may be formed by etching the work function layer 19B that is not protected by the spacer 20. The vertical gate 19 may be formed by performing a self-aligned etching process on the work function layer 19B using the spacer 20 as an etching mask. The vertical gate 19 may partially cover the exposed portion of the gate dielectric layer 17. The vertical gate 19 may be located above both edges of the lower gate 18.

[0062] As described above, since the vertical gate 19 is formed by the self-aligned etching process using the spacer 20 , the width and height of the vertical gate 19 can be uniformly formed.

[0063] like Figure 3H As shown, the spacer 20 may be removed. After the spacer 20 is removed, a portion of the gate dielectric layer 17 extending at a level higher than the top surface of the vertical gate 19 may be exposed.

[0064] Subsequently, an upper gate layer 21′ may be formed. The upper gate layer 21′ may be formed on the hard mask layer 16 and may fill the trench 15, in particular the space between the inner sidewalls of the vertical gate 19. The upper gate layer 21′ may be made of or include a low resistivity material. The upper gate layer 21′ may be formed of the same material as the lower gate 18. The upper gate layer 21′ and the lower gate 18 may be made of the same material. The upper gate layer 21′ may be made of or include a metal-based material. The upper gate layer 21′ may be made of or include a metal, a metal nitride, or a combination thereof. The upper gate layer 21′ may be made of or include tungsten, tungsten nitride, titanium nitride, or a combination thereof. In one embodiment, the upper gate layer 21′ may be made of or include a low work function metal or a low work function polysilicon.

[0065] like Fig. 3I As shown, a recess process may be performed on the upper gate layer 21′ to form the upper gate 21. The recess process may be a dry etching process, such as an etch-back process. In one embodiment, a planarization process may be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process may be performed on the upper gate layer 21′. The top surface of the upper gate 21 may be located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0066] The lower gate 18, the vertical gate 19 and the upper gate 21 form a gate electrode BG. When the lower gate 18 and the upper gate 21 are each formed of a metal-based material, the volume of the metal-based material occupying the gate electrode BG can be increased. Accordingly, the resistance of the gate electrode BG can be reduced.

[0067] like Figure 3J As shown, a capping layer 22 may be formed on the upper gate 21 to fill the remaining gap of the trench 15. The capping layer 22 may be made of a dielectric material or include a dielectric material. The capping layer 22 may be made of silicon nitride or include silicon nitride. The capping layer 22 may have a multilayer structure, such as an oxide-nitride-oxide (ONO) structure.

[0068] Subsequently, a planarization process may be performed on the capping layer 22 to expose the top surface of the hard mask layer 16. Accordingly, the capping layer 22 filling the trench 15 may remain.

[0069] A bottom surface of the capping layer 22 may contact, for example, directly contact, the upper gate 21 and the vertical gate 19. Both sidewalls of the capping layer 22 may contact, for example, directly contact, the gate dielectric layer 17 and the hard mask layer 16.

[0070] According to the above process, a buried gate structure can be formed. The buried gate structure may include a gate dielectric layer 17, a gate electrode BG, and a capping layer 22. The gate electrode BG may include a lower gate 18, a vertical gate 19, and an upper gate 21. The top surfaces of the upper gate 21 and the vertical gate 19 are located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surfaces of the upper gate 21 and the vertical gate 19 may be located at the same level. The vertical gate 19 may directly contact the upper gate 21, the gate dielectric layer 17, and the lower gate 18.

[0071] like Figure 3K As shown, after forming the capping layer 22, an impurity doping process may be performed by an implantation process or other suitable doping techniques. Accordingly, a first doping region 23 and a second doping region 24 may be formed in the substrate 11. Each of the first doping region 23 and the second doping region 24 may have an effective depth to laterally overlap with the upper gate 21 and the vertical gate 19. The lower gate 18 may not laterally overlap with the first doping region 23 and the second doping region 24. The first doping region 23 and the second doping region 24 may be referred to as a first source region / drain region and a second source region / drain region, respectively.

[0072] As the first doping region 23 and the second doping region 24 are formed, a channel may be defined along the surface of the trench 15 (see Figure 2A denoted by the reference numeral “106”).

[0073] In the present embodiment, the vertical gate 19 may be formed by performing a self-aligned etching process using the spacer 20. The buried gate electrode structure having the vertical gate 19 is advantageous because it can greatly reduce or prevent GIDL.

[0074] Figure 4 is a cross-sectional view showing a semiconductor device 200 according to an embodiment of the present invention. Figure 4 The various features of the semiconductor device 200 shown in FIG. 2 may be similar to those of FIG. Figure 2A The features of the semiconductor device 100 shown in FIG. 1 are shown in FIG. 1 , except for the buried gate structure 200G. Hereinafter, in the present embodiment, detailed descriptions of features overlapping with various features of the semiconductor device 100 may be omitted.

[0075] Reference Figure 4 , the semiconductor device 200 may include a buried gate structure 200G and a first doping region 107 and a second doping region 108. An isolation layer 102 and an active region 104 may be formed in a substrate 101. The first doping region 107 and the second doping region 108 may be formed in the active region 104. A trench 105 may be formed passing through the active region 104 and the isolation layer 102. The buried gate structure 200G may be formed in the trench 105. A channel 106 may be formed between the first doping region 107 and the second doping region 108 along an outline of the trench 105 that is coextensive with an outline of a lower gate 121 of the buried gate structure 200G.

[0076] The buried gate structure 200G may be embedded in the trench 105. The buried gate structure 200G may extend into the isolation layer 102 while being disposed in the active region 104 between the first doping region 107 and the second doping region 108. The fin region 104F may be located in the active region 104 below the buried gate structure 200G.

[0077] The buried gate structure 200G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, a gate electrode 120, and a capping layer 130, which are sequentially stacked to fill the trench 105 on the gate dielectric layer 110. The buried gate structure 200G may further include a spacer 140 between the capping layer 130 and the gate dielectric layer 110.

[0078] The gate electrode 120 may include a lower gate 121, an upper gate 122, and a vertical gate 123. The spacer 140 may directly contact a top surface of the vertical gate 123. The spacer 140 may cover a portion of the gate dielectric layer 110.

[0079] The sidewalls of the spacer 140 and the sidewalls of the vertical gate 123 may be self-aligned. The spacer 140 may be made of a dielectric material or include a dielectric material. The spacer 140 may be made of an oxide or include an oxide. The spacer 140 may include a conformal film deposition (CFD) oxide or an ultra-low temperature oxide (ULTO). In the top view, the two ends of the vertical gate 123 may be connected to each other and surround the sidewalls of the upper gate 122. In the top view, the two ends of the spacer 140 may be connected to each other and surround the sidewalls of the capping layer 130.

[0080] FIG. 5A to FIG. 5C It is shown Figure 4 0 is a cross-sectional view of an example of a method of forming a semiconductor device 200 shown in FIG. FIG. 5A to FIG. 5C The method shown can be similar to FIG. 3A to FIG. 3K The method shown.

[0081] according to Figures 3A to 3G According to the process shown, the spacer 20 and the vertical gate 19 can be formed.

[0082] Then, if Figure 5A As shown, an upper gate layer 21′ may be formed to fill the trench 15 on the lower gate 18 and the spacer 20. The upper gate layer 21′ may be made of or include a low resistivity material. The upper gate layer 21′ may be formed of the same material as the lower gate 18. The upper gate layer 21′ and the lower gate 18 may be made of the same material. The upper gate layer 21′ may be made of or include a metal-based material. The upper gate layer 21′ may be made of or include a metal, a metal nitride, or a combination thereof. The upper gate layer 21′ may be made of or include tungsten, tungsten nitride, titanium nitride, or a combination thereof. In one embodiment, the upper gate layer 21′ may be made of or include a low work function metal or low work function polysilicon.

[0083] like Figure 5B As shown, a recess process may be performed on the upper gate layer 21′ to form the upper gate 21. The recess process on the upper gate layer 21′ may be performed by a dry etching process, such as an etch-back process. In one embodiment, a planarization process may be performed first to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process may be performed on the upper gate layer 21′. The top surface of the upper gate 21 may be located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0084] like Figure 5C As shown, a capping layer 22 may be formed on the upper gate 21. The capping layer 22 may be made of a dielectric material or include a dielectric material. The capping layer 22 may include silicon nitride. The capping layer 22 may have an oxide-nitride-oxide (ONO) structure. The capping layer 22 may be planarized to expose the surface of the hard mask layer 16.

[0085] The bottom surface of the capping layer 22 may contact the upper gate 21 and the vertical gate 19. Both sidewalls of the capping layer 22 may contact the spacer 20. The spacer 20 may be formed between the capping layer 22 and the gate dielectric layer 17. The bottom surface of the spacer 20 may contact the top surface of the vertical gate 19.

[0086] According to the above process, a buried gate structure can be formed. The buried gate structure may include a gate dielectric layer 17, a gate electrode BG, a spacer 20, and a capping layer 22. The gate electrode BG may include a lower gate 18, a vertical gate 19, and an upper gate 21. The top surfaces of the upper gate 21 and the vertical gate 19 are located at a level lower than the top surface of the active region 14.

[0087] After forming the capping layer 22, an impurity doping process may be performed by an implantation process or any other suitable doping technique. Accordingly, a first doping region 23 and a second doping region 24 are formed in the substrate 11. Each of the first doping region 23 and the second doping region 24 may have a depth that laterally overlaps with the upper gate 21 and the vertical gate 19. The lower gate 18 may not laterally overlap with the first doping region 23 and the second doping region 24. The first doping region 23 and the second doping region 24 may be referred to as a first source region / drain region and a second source region / drain region, respectively.

[0088] Fig. 6A and Figure 6B 3 is a cross-sectional view showing semiconductor devices 300 and 301 according to an embodiment of the present invention. Fig. 6A The various features of the semiconductor device 300 shown in FIG. 3 may be similar to those of FIG. Figure 2A , except for the buried gate structure 300G. Figure 6B Various features of the semiconductor device 301 shown may be similar to Figure 4 The various features of the semiconductor device 200 are shown, except for the buried gate structure 301G. Here, in the present embodiment, detailed descriptions of the features that are repeated with respect to the various features of the semiconductor devices 100 and 200 may be omitted.

[0089] Reference Fig. 6A , the semiconductor device 300 may include a buried gate structure 300G and a first doping region 107 and a second doping region 108. An isolation layer 102 and an active region 104 may be formed in a substrate 101. The first doping region 107 and the second doping region 108 may be formed in the active region 104. A trench 105 passing through the active region 104 and the isolation layer 102 may be formed. The buried gate structure 300G may be formed in the trench 105. A channel 106 may be formed between the first doping region 107 and the second doping region 108 by the buried gate structure 300G. The channel 106 may be defined along the contour of the trench 105.

[0090] The buried gate structure 300G may be embedded in the trench 105. The buried gate structure 300G may extend into the isolation layer 102 while being disposed in the active region 104 between the first doping region 107 and the second doping region 108. The fin region 104F may be located in the active region 104 below the buried gate structure 300G.

[0091] The buried gate structure 300G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105 , a gate electrode 320 , and a capping layer 130 , which are sequentially stacked to fill the trench 105 on the gate dielectric layer 110 .

[0092] The gate electrode 320 may be composed of or include a lower gate 321, an upper gate 322, and a vertical gate 323. The upper gate 322 and the vertical gate 323 may correspond to Figure 2A The upper gate 122 and the vertical gate 123 are shown in FIG.

[0093] The lower gate 321 may include a barrier layer 324 and a low-resistivity gate electrode 325. The barrier layer 324 may be conformally formed on the surface of the gate dielectric layer 110. The barrier layer 324 may be in direct contact with the gate dielectric layer 110. The barrier layer 324 may be made of or include a metal-based material. The barrier layer 324 may be made of or include a metal nitride. The barrier layer 324 may be made of or include titanium nitride or tantalum nitride. The low-resistivity gate electrode 325 may be formed on the barrier layer 324 to fill the lower portion of the trench 105. The low-resistivity gate electrode 325 may be made of or include a low-resistivity metal (e.g., tungsten). When the barrier layer 324 includes titanium nitride and the low-resistivity gate electrode 325 includes tungsten, the lower gate 321 may be a TiN / W stack. The upper gate 322 may be made of or include tungsten or titanium nitride. The vertical gate 323 may be made of or include a low work function material (eg, N-type polysilicon).

[0094] refer to Figure 6B , the semiconductor device 301 may include a buried gate structure 301G and a first doping region 107 and a second doping region 108. An isolation layer 102 and an active region 104 may be formed in the substrate 101. The first doping region 107 and the second doping region 108 may be formed in the active region 104. A trench 105 passing through the active region 104 and the isolation layer 102 may be formed. The buried gate structure 301G may be formed in the trench 105. A channel 106 may be formed between the first doping region 107 and the second doping region 108 by the buried gate structure 301G. The channel 106 may be defined along the contour of the trench 105.

[0095] The buried gate structure 301G may be embedded in the trench 105. The buried gate structure 301G may extend into the isolation layer 102 while being disposed in the active region 104 between the first doping region 107 and the second doping region 108. The fin region 104F may be located in the active region 104 below the buried gate structure 301G.

[0096] The buried gate structure 301G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, a gate electrode 320, and a capping layer 130, which are sequentially stacked to fill the trench 105 on the gate dielectric layer 110. The buried gate structure 301G may further include a spacer 140 between the capping layer 130 and the gate dielectric layer 110.

[0097] The gate electrode 320 may be composed of or include a lower gate 321, an upper gate 322, and a vertical gate 323. The spacer 140 may directly contact the top surface of the vertical gate 323. The sidewalls of the spacer 140 and the sidewalls of the vertical gate 323 may be self-aligned. The spacer 140 may be made of or include a dielectric material. The spacer 140 may be made of or include an oxide. The spacer 140 may include a conformal film deposition (CFD) oxide or an ultra low temperature oxide (ULTO).

[0098] The lower gate 321 may include a barrier layer 324 and a low-resistivity gate electrode 325. The barrier layer 324 may be conformally formed on the surface of the gate dielectric layer 110. The barrier layer 324 may be made of or include a metal-based material. The barrier layer 324 may be made of or include a metal nitride. The barrier layer 324 may be made of or include titanium nitride or tantalum nitride. The low-resistivity gate electrode 325 may fill the lower portion of the trench 105 in the barrier layer 324. The low-resistivity gate electrode 325 may be made of or include tungsten. When the barrier layer 324 includes titanium nitride and the low-resistivity gate electrode 325 includes tungsten, the lower gate 321 may be a TiN / W stack. The upper gate 322 may be made of or include tungsten or titanium nitride. The vertical gate 323 may be made of or include a low work function material (eg, N-type polysilicon).

[0099] FIG. 7A to FIG. 7G is a cross-sectional view illustrating an example of a method of forming a semiconductor device according to an embodiment of the present invention. FIG. 7A to FIG. 7G Show Fig. 6A An example of a method of forming a semiconductor device 300 is shown.

[0100] like Fig. 7AAs shown, an isolation layer 12 is formed in a substrate 11. An active area 14 is defined by the isolation layer 12. The isolation layer 12 can be formed by a shallow trench isolation (STI) process. For example, an isolation trench 13 is formed by etching the substrate 11. The isolation trench 13 is filled with a dielectric material to form the isolation layer 12. The isolation layer 12 can be made of silicon oxide, silicon nitride, or a combination thereof or include silicon oxide, silicon nitride, or a combination thereof. The isolation trench 13 can be filled with a dielectric material by CVD or other deposition processes. In addition, a planarization process such as chemical-mechanical polishing (CMP) can also be used.

[0101] A trench 15 may be formed in the substrate 11. The trench 15 may have a linear shape passing through the active region 14 and the isolation layer 12. The trench 15 may be formed by etching the substrate 11 using a hard mask layer 16 as an etching mask. The hard mask layer 16 may be formed on the substrate 11 and have a linear opening. The hard mask layer 16 may be formed of a material having an etching selectivity relative to the substrate 11. The hard mask layer 16 may be or include silicon oxide, such as tetraethyl silicate (TEOS). The trench 15 may be formed to be shallower than the isolation trench 13. The trench 15 may be deep enough to subsequently form a large gate electrode having a large average cross-sectional area. In this way, the resistance of the gate electrode may be reduced. In one embodiment, the bottom edge of the trench 15 may have an arc.

[0102] Subsequently, the fin region 14F may be formed. The fin region 14F may be formed by selectively recessing the isolation layer 12 below the trench 15. For the structure of the fin region 14F, refer to Figure 2B Fin region 104F.

[0103] Subsequently, a gate dielectric layer 17 may be formed on the surface of the trench 15. The surface of the trench 15 damaged by the etching process may be restored before forming the gate dielectric layer 17. For example, a sacrificial oxide may be formed by a thermal oxidation process and then the sacrificial oxide may be removed.

[0104] The gate dielectric layer 17 may be formed by a thermal oxidation process. The gate dielectric layer 17 may be made of or include silicon oxide.

[0105] In one embodiment, the gate dielectric layer 17 can be formed by a deposition process such as CVD or ALD. The gate dielectric layer 17 formed by the deposition process can be made of a high-K material, an oxide, a nitride, an oxynitride, or a combination thereof, or include a high-K material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-K material can be or include a hafnium-containing material. The hafnium-containing material can be or include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In one embodiment, the high-K material can be or include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, silicon zirconium oxynitride, aluminum oxide, or a combination thereof. As a high-K material, other well-known high-K materials can also be selectively used. The gate dielectric layer 17 can be made of a material having a high surface density of oxygen atoms or include a material having a high surface density of oxygen atoms.

[0106] Subsequently, a barrier material 18A′ may be formed on the gate dielectric layer 17 and the hard mask layer 16. The barrier material 18A′ may be conformally formed on the surface of the gate dielectric layer 17. The barrier material 18A′ may be made of or include a metal-based material. The barrier material 18A′ may be made of or include a metal nitride. The barrier material 18A′ may be made of or include titanium nitride or tantalum nitride. The barrier material 18A′ may be formed by ALD or CVD.

[0107] Subsequently, a low-resistivity metal material 18B′ may be formed on the barrier material 18A′. The low-resistivity metal material 18B′ may fill the trench 15 on the barrier material 18A′. The low-resistivity metal material 18B′ may include a low-resistivity metal. The low-resistivity metal material 18B′ may be or include tungsten. The low-resistivity metal material 18B′ may be formed by deposition including, for example, CVD or ALD.

[0108] like Figure 7B As shown, a lower gate 18 may be formed in the trench 15. The lower gate 18 may include a barrier layer 18A and a low-resistivity metal layer 18B. In order to form the barrier layer 18A and the low-resistivity metal layer 18B, a recess process may be performed. The recess process may include a dry etching process such as an etch-back process. The etch-back process may be performed using plasma. The barrier layer 18A may be formed by performing an etch-back process on the barrier material 18A′. The low-resistivity metal layer 18B is formed by performing an etch-back process on the low-resistivity metal material 18B′. In one embodiment, a planarization process may be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of a recess process may be performed on the barrier material 18A′ and the low-resistivity metal material 18B′. The top surface of the barrier layer 18A may be located at the same level as the top surface of the low-resistivity metal material layer 18B.

[0109] The top surfaces of the barrier layer 18A and the low-resistivity metal layer 18B may be recessed to a level lower than the top surface of the active region 14. The barrier layer 18A may correspond to Fig. 6A The barrier layer 324, and the low resistivity metal layer 18B may correspond to Fig. 6A A low resistivity gate electrode 325 is provided.

[0110] like Figure 7C As shown, a work function layer 19B can be formed on the lower gate 18. In order to form the work function layer 19B, a work function material 19A can be deposited to fill the trench 15 on the lower gate 18, and then a recess process can be performed on the work function material 19A. The work function material 19A can be formed by, for example, a deposition including CVD or ALD. The recess process of the work function material 19A can include a dry etching process, such as an etch-back process. The work function layer 19B can be formed by performing an etch-back process on the work function material 19A. In one embodiment, a planarization process can be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process is performed on the work function material 19A. The top surface of the work function layer 19B can be located at a level lower than the top surface of the active area 14.

[0111] The work function layer 19B may have a work function lower than the mid-bandgap work function of silicon. The work function layer 19B may be made of or include a low work function metal or low work function polysilicon. The low work function polysilicon may be made of or include N-type polysilicon. The low work function metal may be made of or include titanium-rich titanium nitride (TiN). In the present embodiment, the work function layer 19B may be polysilicon doped with N-type impurities.

[0112] After forming the work function layer 19B, a portion of the surface of the gate dielectric layer 17 may be exposed. The work function layer 19B may have a shape that partially fills the trench 15 on the lower gate 18.

[0113] like Fig.7D As shown, a spacer 20 may be formed. In order to form the spacer 20, a deposition process and an etch-back process may be performed on the spacer layer 20′. The spacer 20 may cover the exposed portion of the gate dielectric layer 17, and the bottom surface of the spacer layer 20′ may contact the edge side top surface of the work function layer 19B. Most of the top surface of the work function layer 19B may be exposed by the spacer 20. A portion of the spacer 20 may cover the exposed portion of the gate dielectric layer 17 and the surface of the hard mask layer 16.

[0114] Subsequently, a vertical gate 19 may be formed. The vertical gate 19 may be formed by etching the work function layer 19B. The vertical gate 19 may be formed by performing a self-aligned etching process on the work function layer 19B using the spacer 20 as an etching mask. The vertical gate 19 may partially cover the exposed portion of the gate dielectric layer 17. The vertical gate 19 may be located above both edges of the lower gate 18.

[0115] As described above, since the vertical gate 19 is formed by the self-aligned etching process using the spacer 20 , the width and height of the vertical gate 19 may be uniformly formed.

[0116] like Fig. 7E As shown, the spacer 20 can be removed. An upper gate plate layer 21' can be formed on the lower gate 18 and the hard mask layer 16 to fill the space between the inner sidewalls of the vertical gate 19. The upper gate layer 21' can be made of or include a low resistivity material. The upper gate layer 21' can be formed of the same material as the lower gate 18. The upper gate layer 21' and the lower gate 18 can be made of the same material. The upper gate layer 21' can be made of or include a metal-based material. The upper gate layer 21' can be made of or include a metal-based material metal, metal nitride or a combination thereof. The upper gate layer 21' can be made of or include tungsten, tungsten nitride, titanium nitride or a combination thereof. In one embodiment, the upper gate layer 21' can be made of or include a low work function metal or low work function polysilicon.

[0117] like Figure 7F As shown, a recess process may be performed on the upper gate layer 21′ to form the upper gate 21. The recess process on the upper gate layer 21′ may be performed by a dry etching process, such as an etch-back process. In one embodiment, a planarization process may be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process may be performed on the upper gate layer 21′. The top surface of the upper gate 21 may be located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0118] The lower gate 18, the vertical gate 19 and the upper gate 21 form a gate electrode BG. When the lower gate 18 and the upper gate 21 are each formed of a metal-based material, the volume of the metal-based material occupying the gate electrode BG can be increased. Accordingly, the resistance of the gate electrode BG can be reduced.

[0119] like Figure 7GAs shown, a capping layer 22 may be formed on the upper gate 21 and the vertical gate 19. The capping layer 22 may be made of a dielectric material or include a dielectric material. The capping layer 22 may include silicon nitride. The capping layer 22 may have an oxide-nitride-oxide (ONO) structure. The bottom surface of the capping layer 22 may contact the upper gate 21 and the vertical gate 19. Both sidewalls of the capping layer 22 may contact the gate dielectric layer 17 and the hard mask layer 16.

[0120] According to the above process, a buried gate structure can be formed. The buried gate structure may include a gate dielectric layer 17, a gate electrode BG, and a capping layer 22. The gate electrode BG may include a lower gate 18, a vertical gate 19, and an upper gate 21. The top surfaces of the upper gate 21 and the vertical gate 19 are located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surfaces of the upper gate 21 and the vertical gate 19 may be located at the same level.

[0121] After the capping layer 22 may be formed, an impurity doping process is performed by an implantation process or other doping techniques. Accordingly, a first doping region 23 and a second doping region 24 are formed in the substrate 11. Each of the first doping region 23 and the second doping region 23 and 24 may have a depth that laterally overlaps with the upper gate 21 and the vertical gate 19. The lower gate 18 may not laterally overlap with the first doping region 23 and the second doping region 24. The first doping region 23 and the second doping region 24 may be referred to as a first source region / drain region and a second source region / drain region, respectively.

[0122] FIG. 8A to FIG. 8C yes Figure 6B 2 is a cross-sectional view of an example of a method of forming a semiconductor device 301 shown in FIG. FIG. 8A to FIG. 8C The method shown can be similar to FIG. 7A to FIG. 7G The method shown.

[0123] according to Figures 7A to 7D According to the process shown, the spacer 20 and the vertical gate 19 can be formed.

[0124] Then, if Fig. 8AAs shown, an upper gate layer 21′ may be formed on the lower gate 18 and the spacer 20 to fill the trench 15. The upper gate layer 21′ may be made of or include a low resistivity material. The upper gate layer 21′ may be formed of the same material as the lower gate 18. The upper gate layer 21′ and the lower gate 18 may be made of the same material. The upper gate layer 21′ may be made of or include a metal-based material. The upper gate layer 21′ may be made of or include a metal, a metal nitride, or a combination thereof. The upper gate layer 21′ may be made of or include tungsten, tungsten nitride, titanium nitride, or a combination thereof. In one embodiment, the upper gate layer 21′ may be made of or include a low work function metal or low work function polysilicon.

[0125] like Figure 8B As shown, a recess process may be performed on the upper gate layer 21′ to form the upper gate 21. The recess process on the upper gate layer 21′ may be performed by a dry etching process (e.g., an etch-back process). In one embodiment, a planarization process may be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process may be performed on the upper gate layer 21′. The top surface of the upper gate 21 may be located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0126] The lower gate 18 , the vertical gate 19 , and the upper gate 21 form a gate electrode BG.

[0127] like Figure 8C As shown, a capping layer 22 may be formed on the upper gate 21. The capping layer 22 may be made of a dielectric material or include a dielectric material. The capping layer 22 may include silicon nitride. The capping layer 22 may have an oxide-nitride-oxide (ONO) structure. The bottom surface of the capping layer 22 may contact the upper gate 21 and the vertical gate 19. Both sidewalls of the capping layer 22 may contact the spacer layer 20.

[0128] According to the above process, a buried gate structure can be formed. The buried gate structure may include a gate dielectric layer 17, a gate electrode BG, a spacer 20, and a capping layer 22. The gate electrode BG may include a lower gate 18, a vertical gate 19, and an upper gate 21. The top surfaces of the upper gate 21 and the vertical gate 19 are located at a level lower than the top surface of the active region 14.

[0129] After forming the capping layer 22, an impurity doping process may be performed by an implantation process or other doping techniques. Accordingly, a first doping region 23 and a second doping region 24 are formed in the substrate 11. Each of the first doping region 23 and the second doping region 23 and 24 may have a depth that laterally overlaps with the upper gate 21 and the vertical gate 19. The lower gate 18 may not laterally overlap with the first doping region 23 and the second doping region 24. The first doping region 23 and the second doping region 24 may be referred to as a first source region / drain region and a second source region / drain region, respectively.

[0130] Fig. 9A and Fig. 9B 4 is a cross-sectional view showing semiconductor devices 400 and 401 according to an embodiment of the present invention. Fig. 9A and Fig. 9B Various features of the semiconductor devices 400 and 401 shown in FIG. 4 may be similar to those of FIG. Figure 2A The semiconductor device 100 and Fig. 6A 1 and 3. The various features of the semiconductor device 300 shown in FIG. 1 are shown in FIG. 1 , except for the buried gate structures 400G and 401G. Here, in the present embodiment, detailed descriptions of the features that overlap with the various features of the semiconductor devices 100 and 300 may be omitted.

[0131] Reference Fig. 9A , the semiconductor device 400 may include a buried gate structure 400G.

[0132] The buried gate structure 400G may include a gate dielectric layer 110, a gate electrode 420, and a capping layer 130 covering the bottom surface and sidewalls of the trench 105. The gate electrode 420 and the capping layer 130 are sequentially stacked on the gate dielectric layer 110 to fill the trench 105. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422, and a vertical gate 423. The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426 may be formed between the vertical gate 423 and the first barrier layer 424.

[0133] The first barrier layer 424 and the low-resistivity gate electrode 425 may correspond to Fig. 6A The barrier layer 324 and the low resistivity gate electrode 325 of FIG. 4 may be formed of tungsten (W), and the first barrier layer 424 may be formed of titanium nitride (TiN). Accordingly, the lower gate 421 may include a TiN / W stack. The upper gate 422 may be made of or include tungsten, and the vertical gate 423 may be made of or include N-type polysilicon.

[0134] The second barrier layer 426 may be formed on the first barrier layer 424. The second barrier layer 426 may be formed between the first barrier layer 424 and the vertical gate 423, or between the gate dielectric layer 110 and the upper gate 422. The first barrier layer 424 and the second barrier layer 426 may be made of the same material or different materials. The second barrier layer 426 may be made of or include a metal nitride.

[0135] The second barrier layer 426 and the vertical gate 423 may have the same thickness. The thickness of the second barrier layer 426 may be changed in various ways according to the thickness of the vertical gate 423. The vertical gate 423, the first barrier layer 424, and the second barrier layer 426 may have the same thickness.

[0136] As may be described later, the second barrier layer 426 may be formed by plasma nitridation. For example, the second barrier layer 426 may be formed by exposing the top surfaces of the low-resistivity gate electrode 425 and the first barrier layer 424 to plasma nitridation.

[0137] Fig. 9B The various features of the semiconductor device 401 shown may be related to Fig. 9A Various features of the semiconductor device 400 are similar, except for the buried gate structure 401G. Here, in the present embodiment, detailed descriptions of features that overlap with various features of the semiconductor device 400 may be omitted.

[0138] like Fig. 9B As shown, the buried gate structure 401G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, and a gate electrode 420 and a capping layer 130, which are sequentially stacked to fill the trench 105 on the gate dielectric layer 110. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422, and a vertical gate 423. The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426 may be formed between the vertical gate 423 and the first barrier layer 424. The buried gate structure 401G may also include a spacer extending vertically on the vertical gate 423.

[0139] Fig. 10A and Fig. 10B 5 is a cross-sectional view showing semiconductor devices 500 and 501 according to an embodiment of the present invention. Fig. 10A and Fig. 10B Various features of the semiconductor devices 500 and 501 shown in FIG. 5 may be similar to those of FIG. Fig. 9A The semiconductor device 400 and Fig. 9B4. The various features of the semiconductor device 401 shown in FIG. 4 are shown in FIG. 4, except for the buried gate structures 500G and 501G. Here, in the present embodiment, detailed descriptions of the features that overlap with the various features of the semiconductor devices 400 and 401 may be omitted.

[0140] Reference Fig. 10A , the semiconductor device 500 may include a buried gate structure 500G.

[0141] The buried gate structure 500G may include a gate dielectric layer 110, a gate electrode 420, and a capping layer 130 covering the bottom surface and sidewalls of the trench 105. The gate electrode 420 and the capping layer 130 are sequentially stacked on the gate dielectric layer 110 to fill the trench 105. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422, and a vertical gate 423′. The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426′ may be formed between the vertical gate 423′ and the first barrier layer 424. The low-resistivity gate electrode 425 may be formed of tungsten (W), and the first barrier layer 424 may be formed of titanium nitride (TiN). Accordingly, the lower gate 421 may include a TiN / W stack. The upper gate 422 may be made of or include tungsten, and the vertical gate 423 ′ may be made of or include N-type polysilicon.

[0142] The second barrier layer 426' may be formed on the first barrier layer 424. The second barrier layer 426' may be formed between the first barrier layer 424 and the vertical gate 423', and may be formed between the gate dielectric layer 110 and the upper gate 422. The first barrier layer 424 and the second barrier layer 426' may be the same material or different materials. The second barrier layer 426' may be made of or include a metal nitride.

[0143] The second barrier layer 426' and the vertical gate 423' may have the same thickness. The thickness of the second barrier layer 426' may be changed in various ways according to the thickness of the vertical gate 423'. The thickness of the vertical gate 423' and the second barrier layer 426' may be smaller than the thickness of the first barrier layer 424. The upper gate 422 may have a greater width than the low-resistivity gate electrode 425.

[0144] The second barrier layer 426' may be formed by plasma nitridation. For example, the second barrier layer 426' may be formed by exposing the top surfaces of the low-resistivity gate electrode 425 and the first barrier layer 424 to plasma nitridation.

[0145] Fig. 10B The various features of the semiconductor device 501 shown may be related to Fig. 10AVarious features of the semiconductor device 500 are similar, except for the buried gate structure 501G. Here, in the present embodiment, detailed descriptions of features that overlap with various features of the semiconductor device 500 may be omitted.

[0146] like Fig. 10B As shown, the buried gate structure 501G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, and a gate electrode 420 and a capping layer 130, which are sequentially stacked on the gate dielectric layer 110 to fill the trench 105. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422, and a vertical gate 423'. The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426' may be formed between the vertical gate 423' and the first barrier layer 424. The buried gate structure 501G may also include a spacer 140' extending vertically on the vertical gate 423'.

[0147] Fig.11A and Fig. 11B 6 is a cross-sectional view showing semiconductor devices 600 and 601 according to an embodiment of the present invention. Fig.11A and Fig. 11B Various features of the semiconductor devices 600 and 601 shown may be similar to Fig. 9A The semiconductor device 400 and Fig. 9B The various features of the semiconductor device 401 are shown, except for the buried gate structures 600G and 601G. Here, in the present embodiment, detailed descriptions of the features that overlap with the various features of the semiconductor devices 400 and 401 may be omitted.

[0148] Reference Fig.11A , the semiconductor device 600 may include a buried gate structure 600G.

[0149] The buried gate structure 600G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, and a gate electrode 420 and a capping layer 130, which are sequentially stacked on the gate dielectric layer 110 to fill the trench 105. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422, and a vertical gate 423″. The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426″ may be formed between the vertical gate 423″ and the first barrier layer 424. The low-resistivity gate electrode 425 may be formed of tungsten (W), and the first barrier layer 424 may be formed of titanium nitride (TiN). Accordingly, the lower gate 421 may include a TiN / W stack. The upper gate 422 may be made of or include tungsten, and the vertical gate 423″ may be made of or include N-type polysilicon.

[0150] The second barrier layer 426" may be formed on the first barrier layer 424. The second barrier layer 426" may be formed between the first barrier layer 424 and the vertical gate 423". The first barrier layer 424 and the second barrier layer 426" may be the same material or different materials. The second barrier layer 426" may be made of or include a metal nitride.

[0151] The second barrier layer 426″ and the vertical gate 423″ may have the same thickness. The thickness of the second barrier layer 426″ may be changed in various ways according to the thickness of the vertical gate 423″. The vertical gate 423″ and the second barrier layer 426″ may have a greater thickness than the first barrier layer 424. The upper gate 422 may have a smaller width than the low-resistivity gate electrode 425.

[0152] The second barrier layer 426″ may be formed by plasma nitridation. For example, the second barrier layer 426″ may be formed by exposing the top surfaces of the low-resistivity gate electrode 425 and the first barrier layer 424 to plasma nitridation.

[0153] Fig. 11B The various features of the semiconductor device 601 shown may be related to Fig.11A Various features of the semiconductor device 600 are similar, except for the buried gate structure 601G. Here, in the present embodiment, detailed descriptions of features that overlap with various features of the semiconductor device 600 may be omitted.

[0154] like Fig. 11BAs shown, the buried gate structure 601G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, a gate electrode 420 and a capping layer 130, wherein the gate electrode 420 and the capping layer 130 are sequentially stacked on the gate dielectric layer 110 to fill the trench 105. The gate electrode 420 may be composed of or include a lower gate 421, an upper gate 422 and a vertical gate 423". The lower gate 421 may include a first barrier layer 424 and a low-resistivity gate electrode 425. A second barrier layer 426" may be formed between the vertical gate 423" and the first barrier layer 424. The buried gate structure 601G may also include a spacer 140" extending vertically on the vertical gate 423".

[0155] like Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B As shown, second barrier layers 426, 426', and 426" may be formed over the first barrier layer 424. When the first barrier layer 424 includes titanium nitride, the second barrier layers 426, 426', and 426" may include nitrogen-rich titanium nitride.

[0156] refer to Fig. 11B , a portion of the second barrier layer 426" may contact the upper edge of the low-resistivity gate electrode 425. Accordingly, a portion of the second barrier layer 426" may include a portion formed by exposing the top surface of the low-resistivity gate electrode 425 to plasma nitridation. When the low-resistivity gate electrode 425 includes tungsten, a portion of the second barrier layer 426" may be made of or include tungsten nitride. Therefore, the second barrier layer 426" may include a nitrogen-rich compound of titanium nitride and tungsten nitride.

[0157] In one embodiment, the second barrier layers 426, 426' and 426" may be formed by plasma oxidation.

[0158] FIG. 12A to FIG. 12F yes Fig. 9A FIG. 4 is a cross-sectional view of an example of a method of forming a semiconductor device 400 . FIG. 12A to FIG. 12F The method shown can be similar to FIG. 7A to FIG. 7G The method shown.

[0159] pass FIG. 7A to FIG. 7D According to the method shown, the lower gate 18 including the first barrier layer 18A and the low resistivity metal layer 18B can be formed.

[0160] Then, if Fig. 12AAs shown, plasma treatment 31 may be performed. Plasma treatment 31 may be performed in an atmosphere containing nitrogen or oxygen. Plasma treatment 31 may include plasma nitridation or plasma oxidation.

[0161] The top surface 31N of the lower gate 18 may be changed by the plasma treatment 31. For example, the top surface 31N of the lower gate 18 may be nitrided by the plasma nitridation treatment 31.

[0162] like Fig. 12B As shown, after performing the plasma treatment 31, a second barrier layer 32' may be formed. The second barrier layer 32' may be a nitrided top surface of the lower gate 18. The second barrier layer 32' may be a nitrided surface of the lower gate 18. When the low-resistivity metal layer 18B includes tungsten, a portion of the second barrier layer 32' may be made of or include tungsten nitride 32W. When the first barrier layer 18A includes titanium nitride, another portion of the second barrier layer 32' may include nitrogen-rich titanium nitride 32N.

[0163] As described above, the second barrier layer 32 ′ may be selectively formed only on the top surface of the lower gate 18 .

[0164] like Fig. 12C As shown, a work function layer 19B can be formed on the second barrier layer 32'. In order to form the work function layer 19B, a low work function material (not shown) can be deposited to fill the groove 15 on the second barrier layer 32', and then a recess process can be performed on the low work function material. The low work function material can be formed by CVD or ALD. The recess process of the low work function material can be performed by a dry etching process (e.g., an etch-back process). The work function layer 19B can be formed by performing an etch-back process on the low work function material. In one embodiment, a planarization process can be first performed to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process is performed on the low work function material. The top surface of the work function layer 19B can be located at a level lower than the top surface of the active area 14.

[0165] The work function layer 19B may have a work function lower than the mid-bandgap work function of silicon. The work function layer 19B may be made of or include a low work function metal or low work function polysilicon. The low work function polysilicon may be made of or include N-type polysilicon. The low work function metal may be made of or include titanium-rich titanium nitride (TiN). In the present embodiment, the work function layer 19B may be polysilicon doped with N-type impurities.

[0166] After forming the work function layer 19B, a portion of the surface of the gate dielectric layer 17 may be exposed. The work function layer 19B may have a shape partially filling the trench 15 on the second barrier layer 32'. The second barrier layer 32' may prevent interdiffusion between the lower gate 18 and the work function layer 19B.

[0167] A spacer 20 may be formed. A deposition process and an etch-back process may be performed on the spacer layer to form the spacer 20. The spacer 20 may cover the exposed portion of the gate dielectric layer 17, and the bottom surface of the spacer 20 may contact the edge side top surface of the work function layer 19B. Most of the top surface of the work function layer 19B may be exposed by the spacer 20. A portion of the spacer 20 may cover the exposed portion of the gate dielectric layer 17 and the surface of the hard mask layer 16.

[0168] like Fig.12D As shown, a vertical gate 19 may be formed. The vertical gate 19 may be formed by etching the work function layer 19B. The vertical gate 19 may be formed by performing a self-aligned etching process on the work function layer 19B using the spacer 20 as an etching mask. The vertical gate 19 may partially cover the exposed portion of the gate dielectric layer 17. The vertical gate 19 may be located above both edges of the lower gate 18.

[0169] As described above, since the vertical gate 19 is formed by the self-aligned etching process using the spacer 20 , the width and height of the vertical gate 19 may be uniformly formed.

[0170] Subsequently, the second barrier layer 32' may be etched to expose the top surface of the lower gate 18. The second barrier layer 32' may be self-aligned and etched on the sidewalls of the vertical gate 19. The second barrier layer 32 may remain directly below the vertical gate 19. The second barrier layer 32 may be located between the first barrier layer 18A and the vertical gate 19. The first barrier layer 18A, the second barrier layer 32, and the vertical gate 19 may have the same thickness. In one embodiment, the second barrier layer 32 may have a smaller or larger thickness than the first barrier layer 18A. Variation of the thickness of the second barrier layer 32 may be obtained by adjusting the thickness of the spacer 20.

[0171] like Fig.12E As shown, after removing the spacer 20, an upper gate 21 may be formed. In order to form the upper gate 21, a deposition process and a recess process may be performed on an upper gate layer (not shown).

[0172] The top surface of the upper gate 21 may be located at a lower level than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0173] The lower gate 18, the vertical gate 19, and the upper gate 21 form a gate electrode BG. The gate electrode BG may further include a second barrier layer 32. When the lower gate 18 and the upper gate 21 are each formed of a metal-based material, the volume of the metal-based material occupying the gate electrode BG may increase. Accordingly, the resistance of the gate electrode BG may be reduced.

[0174] like Fig.12F As shown, a capping layer 22 may be formed on the upper gate 21. The capping layer 22 may be made of a dielectric material or include a dielectric material. The capping layer 22 may include silicon nitride. The capping layer 22 may have an oxide-nitride-oxide (ONO) structure. Subsequently, the capping layer 22 may be planarized to expose the surface of the hard mask layer 16. The bottom surface of the capping layer 22 may contact the upper gate 21 and the vertical gate 19. Both sidewalls of the capping layer 22 may contact the gate dielectric layer 17 and the hard mask layer 16.

[0175] According to the above process, a buried gate structure can be formed. The buried gate structure may include a gate dielectric layer 17, a gate electrode BG, and a capping layer 22. The gate electrode BG may include a lower gate 18, a vertical gate 19, and an upper gate 21. The top surfaces of the upper gate 21 and the vertical gate 19 are located at a level lower than the top surface of the active region 14. The upper gate 21 may fill the space between the inner sidewalls of the vertical gate 19. The top surface of the upper gate 21 may be located at the same level as the top surface of the vertical gate 19.

[0176] After the capping layer 22 may be formed, an impurity doping process may be performed by an implantation process or any other suitable doping technique. Accordingly, a first doping region 23 and a second doping region 24 are formed in the substrate 11. Each of the first doping region 23 and the second doping region 24 may have a depth that laterally overlaps with the upper gate 21 and the vertical gate 19. The lower gate 18 may not laterally overlap with the first doping region 23 and the second doping region 24. The first doping region 23 and the second doping region 24 may be referred to as a first source region / drain region and a second source region / drain region, respectively.

[0177] In one embodiment, the upper gate 21 may be formed in a subsequent process without removing the spacer 20. Fig. 9B A semiconductor device 401 is shown.

[0178] Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B The semiconductor devices 500, 501, 600 and 601 shown can be FIG. 12A to FIG. 12F For example, semiconductor devices 500, 501, 600 and 601 can be formed by changing Fig. 12CThe spacer 20 may be formed in various ways depending on the thickness of the spacer 20. Fig. 10A and Fig. 10B The semiconductor devices 500 and 501 can be formed by forming the spacer 20 to have a small thickness. In addition, Fig.11A and Fig. 11B The semiconductor devices 600 and 601 may be formed by forming the spacer 20 to have a greater thickness.

[0179] Fig.13 is a cross-sectional view showing the memory cell 100M.

[0180] Reference Fig.13 , the memory cell 100M may include a cell transistor, a bit line BL, and a capacitor CAP. The cell transistor may include Figure 2A The semiconductor device 100 of FIG. 100. Therefore, the cell transistor may include a buried gate structure BWL, a channel 106, and a first doping region 107 and a second doping region 108. The first doping region 107 may be electrically connected to the bit line BL. The second doping region 108 may be electrically connected to the capacitor CAP.

[0181] In the memory cell 100M, the buried gate structure BWL may be referred to as a buried word line structure BWL. The buried word line structure BWL may be embedded in the trench 105. The buried word line structure BWL may include a gate dielectric layer 110, a gate electrode 120, and a capping layer 130. The gate electrode 120 may be made of or include a lower gate 121, an upper gate 122, and a vertical gate 123.

[0182] According to the above-described embodiments, the buried word line structure BWL may be replaced by any one of the buried gate structures 100G, 200G, 300G, 301G, 400G, 401G, 500G, 501G, 600G, and 601G.

[0183] The capacitor CAP may include a storage node, a dielectric layer and a plate node. The storage node may have a cylindrical or columnar shape. The dielectric layer may be formed on the surface of the storage node. The dielectric layer may be or include at least one selected from zirconium oxide, aluminum oxide and hafnium oxide. For example, the dielectric layer may have a ZAZ (ZrO2 / Al2O3 / ZrO2) structure in which a first zirconium oxide, aluminum oxide and a second zirconium oxide are stacked. The plate node is formed on the dielectric layer. The storage node and the plate node may be made of or include a metal-containing material.

[0184] The memory cell 100M may be a part of a dynamic random access memory (DRAM). When the memory cell 100M is applied to a DRAM, the refresh characteristics of the DRAM may be improved. In addition, it is also possible to prevent leakage current, thereby improving retention time.

[0185] According to an embodiment, a vertical gate with a low work function is formed, thereby further reducing GIDL.

[0186] Furthermore, according to the embodiment, since the vertical gate is formed by a self-aligned etching process using a spacer, the width and height of the vertical gate may be uniformly formed.

[0187] Although the present invention has been described with respect to specific embodiments, it should be noted that these embodiments are intended to describe rather than limit the present invention. In addition, it should be noted that the present invention can be implemented in various ways by those skilled in the art by substitution, change and modification without departing from the scope of the present invention defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a trench in a substrate; forming a gate dielectric layer over a surface of the trench; forming a lower gate over the gate dielectric layer, the lower gate partially filling the trench; forming a low work function layer above the lower gate, the low work function layer having a lower work function than the lower gate; forming a spacer over the low work function layer; etching the low work function layer to be self-aligned with the spacer so as to form vertical gates on both upper edges of the lower gate; as well as forming an upper gate over the lower gate between inner sidewalls of the vertical gate, Wherein, the step of forming the spacer on the low work function layer comprises: forming a spacer layer over the low work function layer; and The spacer extending vertically is formed on the upper edge of the low work function layer by etching the spacer layer.

2. The method according to claim 1, wherein: The spacer is formed of a material having an etching selectivity with respect to the low work function layer.

3. The method according to claim 1, wherein: The spacer includes silicon oxide.

4. The method according to claim 1, wherein: The step of forming the low work function layer on the lower gate comprises: forming a low work function material filling the trench on the lower gate; and The low work function material is recessed to form the low work function layer at a level lower than a top surface of the substrate.

5. The method according to claim 1, wherein: The low work function layer includes a low work function material having a work function lower than a mid-bandgap work function of silicon.

6. The method according to claim 1, wherein: The low work function layer includes N-type polysilicon.

7. The method according to claim 1, wherein: The step of forming an upper gate on the lower gate between the inner side walls of the vertical gate comprises: forming an upper gate layer on the substrate to fill the space between the inner sidewalls of the vertical gate; and The upper gate layer is recessed to form the upper gate at a level lower than a top surface of the substrate.

8. The method according to claim 1, wherein: A top surface of the upper gate is located at the same level as a top surface of the vertical gate.

9. The method according to claim 1, wherein: Each of the lower gate and the upper gate includes a metal-based material, and the vertical gate includes N-type polysilicon.

10. The method according to claim 1, further comprising: The spacer is removed before forming the upper gate on the lower gate between the inner sidewalls of the vertical gate.

11. The method according to claim 1, wherein: The forming of the upper gate on the lower gate between the inner side walls of the vertical gate is performed in a state where the spacer remains.

12. The method according to claim 1, further comprising: Before forming the low work function layer, a blocking layer is formed on the lower gate.

13. The method according to claim 12, wherein: The step of forming the barrier layer on the lower gate includes exposing a top surface of the lower gate to plasma treatment to form the barrier layer.

14. The method according to claim 12, wherein: The blocking layer is formed of a surface nitride of the lower gate.

15. The method according to claim 12, wherein: The lower gate includes tungsten, and the barrier layer includes a nitride of the tungsten.

16. The method according to claim 12, wherein: The lower gate includes titanium nitride, and the barrier layer includes nitrogen-rich titanium nitride obtained by nitriding the titanium nitride.

17. The method according to claim 12, further comprising: After forming the vertical gate, etching a portion of the barrier layer to be self-aligned with the vertical gate, The etched barrier layer is located between the upper edge of the lower gate and the vertical gate.

18. The method of claim 1, further comprising: After forming the upper gate, forming a capping layer above the upper gate; forming a first doped region and a second doped region in the substrate that laterally overlap the vertical gate; forming a bit line coupled to the first doped region; as well as A capacitor is formed coupled to the second doped region.

19. A semiconductor device comprising: a gate dielectric layer conformally covering the trench of the substrate; a lower gate formed over the gate dielectric layer and partially filling a lower portion of the trench; A vertical gate formed on two upper edges of the lower gate; an upper gate filled in the inner space of the vertical gate; a capping layer formed over the upper gate; as well as a spacer formed between the gate dielectric layer and the capping layer, a barrier layer between the vertical gate and the lower gate, and The blocking layer includes a material that nitrides the surface of the lower gate.

20. The semiconductor device according to claim 19, wherein The vertical gate is self-aligned with the spacer.

21. The semiconductor device according to claim 19, wherein The spacer is formed of a material having an etching selectivity with respect to the vertical gate.

22. The semiconductor device according to claim 19, wherein The spacer is formed of silicon oxide.

23. The semiconductor device according to claim 19, wherein: The vertical gate is formed of a low work function material having a lower work function than the lower gate.

24. The semiconductor device according to claim 19, wherein The vertical gate is formed of N-type polysilicon, and the lower gate and the upper gate are formed of a metal-based material.

25. The semiconductor device according to claim 19, wherein The lower gate includes titanium nitride, and the barrier layer includes nitrogen-rich titanium nitride.

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