Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device and a method for manufacturing a semiconductor memory device are described herein. A semiconductor memory device includes a stacked structure, the stacked structure including a plurality of conductive layers for local lines stacked to be spaced apart from each other on a semiconductor substrate, the semiconductor substrate being defined by a cell region and a reduced region, wherein the plurality of conductive layers for local lines are stacked in a stepped structure in the reduced region. The semiconductor memory device also includes a plurality of contact plugs, the plurality of contact plugs being formed to penetrate the stacked structure in the reduced region, the plurality of contact plugs corresponding to the plurality of conductive layers for local lines, respectively. Each of the plurality of contact plugs includes a horizontally protruding protruding portion, and the protruding portion is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0121697, filed on October 1, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to semiconductor memory devices and methods of manufacturing the same. Background Art

[0004] Semiconductor devices, especially semiconductor memory devices, are generally classified as volatile memory devices or nonvolatile memory devices.

[0005] A nonvolatile memory device has a relatively slow write and read speed, but retains stored data even when the power supply is interrupted. Therefore, a nonvolatile memory device is used to store data to be retained regardless of whether power is supplied. Examples of volatile memory include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM, magnetic RAM, resistive RAM, ferroelectric RAM, etc. Flash memory is classified into NOR type flash memory or NAND type flash memory.

[0006] Flash memory has the advantages of RAM that data can be freely programmed and erased and ROM that stored data can be saved even when power supply is interrupted. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players.

[0007] Flash memory devices may be classified as two-dimensional semiconductor memory devices in which strings are horizontally formed on a semiconductor substrate or three-dimensional semiconductor memory devices in which strings are vertically formed on a semiconductor substrate.

[0008] A three-dimensional semiconductor memory device is a memory device designed to overcome the integration degree limitation of a two-dimensional memory device, and includes a plurality of channel plugs formed vertically on a semiconductor substrate. These channel plugs may include a drain select transistor, a memory cell, and a source select transistor, which are connected in series between a bit line and a source line. Summary of the invention

[0009] According to an embodiment of the present disclosure, a semiconductor memory device includes a stacked structure, the stacked structure includes a plurality of conductive layers for local lines stacked and spaced apart from each other on a semiconductor substrate, the semiconductor substrate being defined by a cell region and a reduced region, wherein the plurality of conductive layers for local lines are stacked in a stepped structure in the reduced region. The semiconductor memory device also includes a plurality of contact plugs, the plurality of contact plugs being formed to penetrate the stacked structure in the reduced region, the plurality of contact plugs corresponding to the plurality of conductive layers for local lines, respectively. Each of the plurality of contact plugs includes a horizontally protruding protruding portion, and the protruding portion is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.

[0010] According to another embodiment of the present disclosure, a semiconductor memory device includes a peripheral circuit structure formed on a semiconductor substrate and a memory cell array formed above the peripheral circuit structure. The semiconductor memory device also includes a plurality of contact plugs penetrating a reduced area of ​​the memory cell array, and the plurality of contact plugs are connected to a plurality of metal lines of the peripheral circuit structure. The memory cell array includes a plurality of conductive layers for local lines stacked in a stepped structure in the reduced area. In addition, each of the plurality of contact plugs includes a horizontally protruding protruding portion, and the protruding portion is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.

[0011] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: forming a stack structure including a plurality of first material layers and a plurality of second material layers, the first material layers and the second material layers are alternately stacked in a cell region and a reduced region, wherein the first material layers and the second material layers are stacked in a stepped structure, wherein the second material layers are exposed in the reduced region; forming a sacrificial layer along the upper surface of the stack structure in the reduced region; and removing the sacrificial layer formed on the sidewall of the stack structure having the stepped structure so that the sacrificial layer remains only on the upper surface of the stack structure. The method also includes: forming an interlayer insulating layer on the top of the entire structure, and forming a plurality of contact holes penetrating the interlayer insulating layer, the sacrificial layer and the stack structure; forming an insulating layer for a spacer on the sidewall of the second material layer exposed through the sidewall of the contact hole; removing the second material layer, and forming a conductive layer for a local word line in the space where the second material layer is removed; removing the sacrificial layer exposed through the sidewall of the contact hole; and forming contact plugs each having a protruding portion by filling the contact holes each including the space where the sacrificial layer is removed with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the following, example embodiments will be described with reference to the accompanying drawings; however, they may be presented in different forms and should not be construed as limited to the embodiments presented herein. Rather, these embodiments are provided to enable the present disclosure and to convey the scope of the example embodiments to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals throughout the text represent the same elements.

[0014] Figure 1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 2 is a view showing the arrangement between a memory cell array and a peripheral circuit.

[0016] Figure 3 is a view showing a memory cell array including memory blocks formed in a three-dimensional structure.

[0017] Figure 4 is a diagram showing the configuration of a memory block and the connection relationship between the memory block and peripheral circuits.

[0018] Figure 5 is a cross-sectional view of a semiconductor memory device showing a cell region and a reduced region.

[0019] Figures 6 to 15 2 is a view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Fig.16 It is shown Fig.15 3D view of the contact plug shown in FIG.

[0021] Fig.17 It is shown that Figure 1 0014-07-2009 14:02:05 16:02:05 17:02:05 18:02:05 19:02:05 20:02:05 21:02:05 22:02:05 23:02:05 24:02:05 25:02:05 26:02:05 27:02

[0022] Fig.18 It is shown that Figure 1 FIG. 5 is a diagram of another embodiment of a memory system of a semiconductor memory device shown in FIG. DETAILED DESCRIPTION

[0023] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments of the concepts of the present disclosure. Embodiments of the concepts of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily realize the technical spirit of the present disclosure.

[0025] Some embodiments provide a semiconductor memory device capable of improving a process of connecting a local line of a memory block included in the semiconductor memory device to a peripheral circuit, and a method of manufacturing the semiconductor memory device.

[0026] Figure 1 is a diagram illustrating a semiconductor memory device 1100 according to an embodiment of the present disclosure.

[0027] refer to Figure 1 , the semiconductor memory device 1100 may include a memory cell array 100 capable of storing data and a peripheral circuit 110 capable of performing a program, read, or erase operation of the memory cell array 100 .

[0028] The memory cell array 100 may include a plurality of memory blocks including nonvolatile memory cells. A local line LL may be connected to each memory block, and a bit line BL may be commonly connected to the memory blocks.

[0029] The peripheral circuit 110 may include a control logic 111 , a voltage generator 112 , a row decoder 113 , a page buffer group 114 , a column decoder 115 , and an input / output circuit 116 .

[0030] The control logic 111 may control the voltage generator 112, the row decoder 113, the page buffer group 114, the column decoder 115, and the input / output circuit 116 according to the command CMD and the address ADD. For example, the control logic 111 may output the operation signal OPS and the page buffer control signal PBSIG in response to the command CMD, and may output the row address RADD and the column address CADD in response to the address ADD. The control logic 111 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 111 may be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0031] The voltage generator 112 may generate and output an operation voltage Vop required for a program, read or erase operation in response to an operation signal OPS. For example, the voltage generator 112 may generate and output an operation voltage Vop such as a program voltage, a read voltage, an erase voltage and a pass voltage.

[0032] The row decoder 113 may transmit the operating voltage Vop to the selected memory block through the local line LL in response to the row address RADD.

[0033] The page buffer group 114 may include a plurality of page buffers connected to a selected memory block through a bit line BL The page buffer group 114 may temporarily store data in a program or read operation in response to a page buffer control signal PBSIG.

[0034] The column decoder 115 may transfer data between the page buffer group 114 and the input / output circuit 116 in response to the column address CADD.

[0035] The input / output circuit 116 may receive a command CMD and an address ADD from an external device and transmit the command CMD and the address ADD to the control logic 111. The input / output circuit 116 may transmit data DATA received from the external device to the column address 115 in a program operation and transmit output data DATA received from the column address 115 to the external device in a read operation.

[0036] Figure 2 is a view showing the arrangement between the memory cell array 100 and the peripheral circuit 110 .

[0037] refer to Figure 2 , Figure 1 The memory cell array 100 and the peripheral circuit 110 described in the embodiment may be arranged differently. For example, when the substrate is arranged in the XY direction, the memory cell array 100 and the peripheral circuit 110 may also be arranged parallel to each other in the XY direction (210). Alternatively, the memory cell array 100 may be arranged above the peripheral circuit 110 in a direction perpendicular to the substrate (Z direction) (220). That is, the peripheral circuit 110 may be arranged between the substrate and the memory cell array 100.

[0038] Figure 3 is a view showing a memory cell array 100 including memory blocks BLK1 to BLKn formed in a three-dimensional structure.

[0039] refer to Figure 3 , when the memory cell array 100 includes the memory blocks BLK1 to BLKn formed in a three-dimensional structure, the memory blocks BLK1 to BLKn may be arranged in the Y direction. The Y direction may be Figure 1 The direction in which the bit line BL shown in FIG.

[0040] Although Figure 3 1 shows a case where the memory cell array 100 includes one plane, but the memory cell array 100 may include a plurality of planes. The plurality of planes may be arranged in the X direction, and the memory blocks included in each plane may be arranged in the Y direction within the corresponding plane.

[0041] Figure 4110 is a diagram showing the configuration of the memory block BLKn and the connection relationship between the memory block BLKn and the peripheral circuit 110.

[0042] Figure 3 The plurality of memory blocks BLK1 to BLKn described in the above may be configured to be identical to each other. Figure 4 In the embodiment, the memory block BLKn may represent any memory block among the plurality of memory blocks BLK1 to BLKn.

[0043] refer to Figure 4 , the memory block BLKn formed in a three-dimensional structure may include a cell region CR and a reduced region SR, the memory cells are included in the cell region CR, and the reduced region SR is used to electrically connect the peripheral circuit 110 and the cell region CR to each other. For example, a plurality of vertical strings in which memory cells and selection transistors are stacked may be included in the cell region CR, and ends of a plurality of gate lines connected to the memory cells and the selection transistors may be included in the reduced region SR. For example, in the reduced region SR, the gate lines may be stacked in a stepped structure, wherein the gate lines located at a relatively lower portion extend longer than the gate lines located at a relatively higher portion. The gate lines exposed by the stepped structure may be connected to the peripheral circuit 110 through contact plugs.

[0044] When the peripheral circuit 110 and the memory block BLKn are arranged parallel to each other (in the X direction) (210), a plurality of lines ML may be formed to electrically connect the reduction region SR and the peripheral circuit 110. For example, in the structure 210, the plurality of lines ML may be arranged to extend in the X direction and to be spaced apart from each other in the Y direction.

[0045] When the peripheral circuit 110 is disposed under the memory block BLKn (in the Z direction) (220A), a plurality of lines ML for electrically connecting the reduction region SR and the peripheral circuit 110 to each other may be disposed to extend in the Z direction and to be spaced apart from each other in the Y direction. As shown in the figure, the plurality of lines ML extend (in the Z direction) to above the reduction region SR, extend horizontally (in the X direction) to a region outside the reduction region SR, and then extend vertically (in the Z direction) to be connected to the peripheral circuit 110 disposed under the memory block BLKn.

[0046] In another embodiment, when the peripheral circuit 110 is disposed under the memory block BLKn (in the Z direction) (220B), a plurality of lines ML for electrically connecting the reduction region SR and the peripheral circuit 110 to each other penetrate the reduction region SR and are connected to the peripheral circuit 110 disposed under the memory block BLKn.

[0047] In an embodiment of the present disclosure, a semiconductor memory device as shown in a structure 220B will be described in which a plurality of lines ML penetrate the shrinking region SR and are connected to the peripheral circuit 110 disposed under the memory block BLKn.

[0048] Figure 5 is a cross-sectional view of a semiconductor memory device showing a cell region and a reduced region.

[0049] exist Figure 5 In the embodiment, the following case is shown as an example, in which the peripheral circuit 110 is provided under the memory cell array 100 including a plurality of memory cells, and a plurality of lines penetrate the reduced region SR of the memory cell array 100 and are connected to the peripheral circuit 110, as shown in FIG. Figure 4 As shown in the structure 220B described in FIG.

[0050] refer to Figure 5 , the cell region CR and the reduced region SR are disposed adjacent to each other in the XX′ direction.

[0051] The semiconductor memory device according to an embodiment of the present disclosure may have a periphery under cell (PUC) structure. A peripheral circuit 110 may be disposed under a memory cell array 100.

[0052] In one embodiment, the peripheral circuit may include a row decoder 113. Although not shown in the figure, the peripheral circuit 110 may further include Figure 1 At least one of the control logic 111, the voltage generator 112, the page buffer group 114, the column decoder 115, and the input / output circuit 116 shown in FIG.

[0053] The semiconductor substrate 400 may be a single crystal silicon substrate, a polycrystalline silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate, or may include Si, Ge, SiGe, or the like.

[0054] A first interlayer insulating layer 301 covering the peripheral circuit 110 including the row decoder 113 may be disposed on the semiconductor substrate 400. The first interlayer insulating layer 301 may include, for example, an insulating layer such as a silicon oxide layer. Metal lines 401 and 303 connected to the row decoder 113 may be disposed in the first interlayer insulating layer 301.

[0055] The upper substrate 305 is stacked on the first interlayer insulating layer 301, and the second interlayer insulating layer 307 and the conductive layer 311 for the local wiring are alternately stacked on the upper substrate 305. The second interlayer insulating layer 307 is stacked on the uppermost conductive layer 311 for the local wiring.

[0056] The upper substrate 305 may include polysilicon. The upper substrate 305 may be generated using a method of forming a predetermined polysilicon region on the first interlayer insulating layer 301 and growing polysilicon by using the polysilicon region as a seed layer. The upper substrate 305 may be formed to be separated in a region in which a contact plug 333 connected to the row decoder 113 is formed in the reduced region SR.

[0057] The second interlayer insulating layer 307 may include an insulating material such as oxide, and the conductive layer 331 for local wiring may include a conductive material such as polysilicon or tungsten. The conductive layer stacked at the bottom among the conductive layers 331 for local wiring may be a source selection line, the conductive layer stacked at the top among the conductive layers 331 for local wiring may be a drain selection line, and the other conductive layers for local wiring may be word lines.

[0058] The channel plug CP is disposed in the cell region CR of the memory cell array 100. The channel plug CP penetrates the second interlayer insulating layer 307 and the conductive layer 331 for local wiring, and is formed to be perpendicular to the upper substrate 305. The channel plug CP includes a gap filling layer 315, a channel pattern 313 surrounding the gap filling layer 315, and a memory pattern 311 surrounding the channel pattern 313. For example, the memory pattern 311 may include at least one of a charge blocking layer, a data storage layer, and a tunnel insulating layer, and the data storage layer may include a floating gate such as silicon, a charge trap material such as nitride, a phase change material, a nanodot, etc. In addition, the channel pattern 313 may be formed in a completely filled shape in the center region, or in a structure having an open center region. The gap filling layer 315 may be formed in the open center region.

[0059] The conductive layer 331 for the local wiring is disposed to extend from the cell region CR to the reduced region SR. The conductive layer 331 for the local wiring is stacked in the reduced region SR in a stepped shape. For example, the conductive layer 331 for the local wiring may be formed in a stepped structure in which the conductive layer 331 for the local wiring disposed at a relatively lower portion extends longer than the conductive layer disposed at a relatively higher portion.

[0060] Each conductive layer 331 for local wiring is electrically connected to any one of a plurality of contact plugs 333 that vertically penetrate the conductive layer 331 for local wiring and the second interlayer insulating layer 307 and are connected to the lower metal wiring 303. Each of the plurality of contact plugs 333 has a protruding portion that protrudes in the horizontal direction, and the lower surface of the protruding portion contacts the upper surface of the end of any one of the conductive layers 331 for local wiring. For example, each contact plug 333 penetrates the end of the corresponding conductive layer 331 for local wiring and extends in the vertical direction, and includes a protruding portion that is in electrical and physical contact with the upper surface of the end of the corresponding conductive layer 331 for local wiring. In addition, each contact plug 333 may penetrate the conductive layer 331 for local wiring disposed under the corresponding conductive layer 331 for local wiring. The insulating layer 327 for spacers is formed in a region where the contact plug 333 and the conductive layer 331 for local wiring cross each other, that is, formed on the sidewall of the contact plug 333 that penetrates the conductive layer 331 for local wiring. The insulating layer 327 for spacers prevents each contact plug 333 from being electrically connected to other conductive layers 331 for local wirings other than the corresponding conductive layer 331 for local wirings. The insulating layer 327 for spacers may be configured in a shape surrounding the sidewalls of the contact plugs 333 in a region where the contact plugs 333 and the conductive layers 331 for local wirings cross each other. Each contact plug 333 is connected to the conductive layer 331 for local wirings disposed at the uppermost portion among the conductive layers 331 for local wirings penetrated by the contact plug 333 through a protruding portion.

[0061] In addition, a pad layer 321 may be formed on the top of the protruding portion of the contact plug 333 , and a third interlayer insulating layer 323 may be formed in a space between an upper portion of the cell region CR and the contact plug 333 of the reduced region SR.

[0062] Figures 6 to 15 2 is a view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0063] The following will refer to Figures 6 to 15 A method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure is described.

[0064] In an embodiment of the present disclosure, a process after forming the peripheral circuit 110 including the row decoder 113 on a semiconductor substrate and forming the lower metal line 303 connected to the row decoder 113 in the first interlayer insulating layer 301 will be described.

[0065] refer to Figure 6, an upper substrate 305 is formed on the first interlayer insulating layer 301 including the lower metal line 303. The upper substrate 305 may include a source line layer, and the source line layer may be a doped semiconductor layer. For example, the source line layer may be a semiconductor layer doped with n-type impurities. In one embodiment, the source line layer may be formed by injecting impurities into the surface of the upper substrate 305, or by depositing at least one doped silicon layer on the upper substrate 305. In one embodiment, the source line layer may be formed by depositing at least one doped silicon layer on the upper substrate 305. Figure 5 The first interlayer insulating layer 301 is formed on the peripheral circuit 110 shown in FIG. 1 , and then at least one doped silicon layer is deposited on the first interlayer insulating layer 301 .

[0066] In addition, the upper substrate 305 may be formed in a shape in which a region where the lower metal line 303 is formed in the reduced region SR is opened.

[0067] Subsequently, a stack structure ST in which the first material layer 307 and the second material layer 309 are alternately stacked is formed on the cell region CR and the reduced region SR. The second material layer 309 may be a sacrificial layer for forming a conductive layer such as a word line, a selection line, and a pad, and the first material layer 307 may be a second interlayer insulating layer for insulating the stacked conductive layers from each other.

[0068] The first material layer 307 may be formed of a material having a higher etching rate than that of the second material layer 309. For example, the first material layer 307 may include an insulating material such as oxide, and the second material layer 309 may include a sacrificial layer such as nitride.

[0069] refer to Figure 7 , a channel hole in which a channel plug CP is to be formed in the cell region is formed by etching a stacked structure ST formed on the cell region CR. Subsequently, a channel plug CP including a channel pattern 313 and a memory pattern 311 surrounding the channel pattern 313 is formed in the channel hole. For example, the memory pattern 311 is formed on the sidewall of the channel hole. The memory pattern 311 may include at least one of a charge blocking layer, a data storage layer, and a tunnel insulating layer, and the data storage layer may include a floating gate such as silicon, a charge trap material such as nitride, a phase change material, nanodots, etc. Subsequently, the channel plug CP is formed by completely filling the central area of ​​the channel hole with the channel pattern 313. In another embodiment, the channel pattern 313 may be formed in a structure in which the central area of ​​the channel hole is open, and a gap filling layer 315 may be formed in the open central area.

[0070] Subsequently, an etching process is performed so that the stacked structure ST formed on the reduced region SR has a stair shape. For example, in the reduced region SR, the first material layer and the second material layer of the stacked structure ST may be formed in a stair shape, and the step may extend longer as it approaches the bottom. For example, the stacked structure ST may be formed in a stair structure in which the second material layer is exposed upward in the reduced region SR.

[0071] refer to Figure 8 , sacrificial layers 317 and 319 and a pad layer 321 are formed on the entire structure including the cell region CR and the reduced region SR.

[0072] The sacrificial layers 317 and 319 may be formed to include a first sacrificial layer 317 and a second sacrificial layer 319. The first sacrificial layer 317 may be formed on top of the exposed second material layer. For example, the first sacrificial layer 317 may be formed of an oxide layer formed using an oxidation process. The second sacrificial layer 319 may be formed along the upper surface of the entire structure including the first sacrificial layer 317. For example, the second sacrificial layer 310 may be formed of an undoped polysilicon layer.

[0073] The pad layer 321 may be formed along the upper surface of the entire structure including the sacrificial layers 317 and 319. For example, the pad layer 321 may be formed of an oxide layer. For example, the thickness of the pad layer 321 formed on the top of the stacked structure ST may be thicker than the thickness of the pad layer 321 formed on the sidewall of the stacked structure ST.

[0074] refer to Fig. 9 , the sacrificial layers 317 and 319 and the pad layer 321 formed on the sidewalls of the stacked structure ST are removed by performing an etching process. For example, the etching process of the pad layer 321 can be performed using a wet etching process. Because in the wet etching process, the pad layer 321 formed on the sidewalls of the stacked structure ST is thinner than the pad layer 321 formed on the top of the stacked structure ST, the pad layer 321 formed on the sidewalls of the stacked structure ST can be removed in a state where the pad layer 321 remains on the top of the stacked structure ST. Subsequently, the sacrificial layers 317 and 319 exposed when the pad layer 321 is removed are removed by performing a dry etching process. That is, the sacrificial layers 317 and 319 formed on the sidewalls of the stacked structure ST are removed. Therefore, the sacrificial layers 317 and 319 and the pad layer 321 remain only on the top of the second material layer in the reduced region SR.

[0075] refer to Fig.10 , a third interlayer insulating layer 323 is formed on the top of the entire structure including the cell region CR and the reduced region SR. The third interlayer insulating layer 323 may be formed of an oxide layer. Subsequently, a hard mask pattern 325 is formed on the top of the third interlayer insulating layer 323. The hard mask pattern 325 is formed so that the region where the contact hole is formed is open.

[0076] Subsequently, by performing an etching process using the hard mask pattern 325 , a contact hole CH is formed which penetrates the third interlayer insulating layer 323 , the pad layer 321 , the sacrificial layers 319 and 317 , the stacked structure ST, and the first interlayer insulating layer 301 and exposes the lower metal wiring 303 therethrough.

[0077] refer to Fig.11 , the hard mask pattern 325 is removed, and the second material layer exposed through the sidewalls of the contact holes is etched partially, thereby forming a recess A at the sidewalls of each contact hole. The thickness of the etched portion of the second material layer may be thinner than the horizontal width of the sacrificial layers 317 and 319. For example, the end portion of the second material layer overlaps the sacrificial layers 317 and 319. For example, the thickness of the etched portion of the second material layer may be 50 nm to 100 nm.

[0078] refer to Fig.12 , an insulating layer 327 for spacers is formed on the sidewalls of the contact holes. The insulating layer 327 for spacers may be formed to be embedded in the recess formed on the sidewalls of the contact holes. Subsequently, the contact holes may be gap-filled with a polysilicon layer 329 to form a support.

[0079] refer to Fig.13 At least one slit (not shown) penetrating the third interlayer insulating layer 323 and the stacked structure ST is formed in the cell region CR and the reduced region SR, and the sidewall of the stacked structure ST is exposed through the slit. Subsequently, the second material layer exposed by the slit is removed, and a conductive layer 331 for a local line is formed in the region where the second material layer is removed. The conductive layer 331 for a local line can be used as Figure 1 The local line LL shown in .

[0080] refer to Fig.14 , by removing the polysilicon layer for forming a support formed in the contact hole, and etching a portion of the thickness of the insulating layer 327 for the spacer formed on the sidewall of the contact hole to expose the sacrificial layer ( Fig.13 The insulating layer 327 for the spacer remains in the recess at the sidewall of the contact hole to prevent the conductive layer 331 for the local wiring from being exposed through the contact hole.

[0081] Subsequently, the exposed sacrificial layer is removed by performing an etching process. The space B through which the sacrificial layer is removed exposes the upper surface of the end portion of each conductive layer 331 for the partial wiring.

[0082] refer to Fig.15, contact plugs 333 are formed by filling the contact holes with a conductive material. Each contact plug 333 is electrically connected to the corresponding lower metal line 303 on the bottom thereof. Each contact plug 333 is formed to have a protruding portion C in the region where the sacrificial layer is removed. The lower surface of the protruding portion C is electrically connected to the corresponding conductive layer 331 for local lines.

[0083] Fig.16 It is shown Fig.15 3D view of the contact plug shown in FIG.

[0084] The contact plug 333 is formed in a cylindrical shape extending in the vertical direction of the substrate, so that the lower surface of the contact plug 333 is electrically connected to the lower metal line 303 while contacting the lower metal line 303. In addition, a portion of the sidewall of the contact plug 333 may include a protruding portion C protruding in the horizontal direction of the substrate, and the protruding portion C may be provided in a disk shape. A portion of the lower surface of the protruding portion C is electrically connected to the corresponding conductive layer for local wiring ( Fig.15 331) shown in FIG. 1 is in contact with the corresponding conductive layer for local circuits at the same time.

[0085] Fig.17 It is shown that Figure 1 1 is a diagram of an embodiment of a memory system 1000 of a semiconductor memory device 1100 shown in FIG.

[0086] refer to Fig.17 , the memory system 1000 may include a plurality of semiconductor memory devices 1100 configured to store data and a controller 1200 configured to communicate between the semiconductor memory devices 1100 and a host 2000 .

[0087] Each semiconductor memory device 1100 may be the semiconductor memory device described in the above-mentioned embodiments.

[0088] The semiconductor memory device 1100 may be connected to the controller 1200 through a plurality of system channels sCH. For example, a plurality of semiconductor memory devices 1100 may be connected to one system channel sCH, and a plurality of system channels sCH may be connected to the controller 1200.

[0089] The controller 1200 may communicate between the host 2000 and the semiconductor memory device 1100. The controller 1200 may control the semiconductor memory device 1100 in response to a request from the host 2000, or perform a background operation for improving the performance of the memory system 1000 even without a request from the host 2000.

[0090] The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. For example, the request may include a program request capable of controlling a program operation, a read request capable of controlling a read operation, an erase request capable of controlling an erase operation, etc. The host 2000 may communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0091] Fig.18 It is shown that Figure 1 FIG. 1 is a diagram of another embodiment of a memory system of a semiconductor memory device 1100 shown in FIG.

[0092] refer to Fig.18 , the memory system may be implemented using the memory card 3000. The memory card 3000 may include a semiconductor memory device 1100, a controller 1200, and a card interface 7100.

[0093] The controller 1200 may control data exchange between the semiconductor memory device 1100 and the card interface 7100. In some embodiments, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but the present disclosure is not limited thereto.

[0094] The card interface 7100 can interface the data exchange between the host 2000 and the controller 1200 according to the protocol of the host 2000. In some embodiments, the card interface 7100 can support the universal serial bus (USB) protocol and the inter-chip (IC) USB protocol. The card interface 7100 can refer to hardware that can support the protocol used by the host 2000, software embedded in the hardware, or a signal transmission scheme.

[0095] When the memory card 3000 is connected to a host interface of a host 2000 such as a PC, a portable PC, a digital camera, a digital audio player, a mobile phone, console video game hardware, or a digital set-top box, the host interface can perform data communication with the semiconductor memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor of the host 2000.

[0096] According to the present disclosure, a contact plug forming process for connecting a local line of a semiconductor memory device to a peripheral circuit can be improved.

[0097] Although the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents.

[0098] In the above-described embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps do not need to be performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0099] Meanwhile, embodiments of the present disclosure are described in the accompanying drawings and the specification. Although specific terms are used herein, these terms are only used to explain embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many changes are possible within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A semiconductor memory device, comprising: A stacked structure comprising a plurality of conductive layers for local wiring stacked to be spaced apart from each other on a semiconductor substrate, the semiconductor substrate being defined by a cell region and a reduced region, wherein the plurality of conductive layers for local wiring are stacked in a stepped structure in the reduced region; a plurality of contact plugs formed to penetrate the stack structure in the reduced area, the plurality of contact plugs respectively corresponding to the plurality of conductive layers for local circuits; as well as a pad layer formed on each of the protruding portions of the plurality of contact plugs, Each of the plurality of contact plugs includes a protruding portion that protrudes horizontally, and the protruding portion is connected to a corresponding conductive layer for local wiring among the plurality of conductive layers for local wiring. 2 . The semiconductor memory device according to claim 1 , wherein the protruding portion of each of the plurality of contact plugs extends and protrudes to an end portion of the corresponding conductive layer for local wiring. 3 . The semiconductor memory device according to claim 2 , wherein the protruding portion of each of the plurality of contact plugs is connected to an upper surface of the end portion of the corresponding conductive layer for local wiring. 4 . The semiconductor memory device according to claim 2 , wherein a lower surface of the protruding portion of each of the plurality of contact plugs is connected to an upper surface of the end portion of the corresponding conductive layer for local wiring.

5. The semiconductor memory device according to claim 2 , wherein each of the plurality of contact plugs corresponds to a conductive layer for a local wiring, the conductive layer for a local wiring being disposed at an uppermost portion among a plurality of conductive layers for a local wiring penetrated by the contact plug, The protruding portion of each of the plurality of contact plugs is connected to the conductive layer for local wiring disposed at the uppermost portion.

6. The semiconductor memory device according to claim 1, further comprising an insulating layer for spacers formed on side walls of the plurality of contact plugs in a region where the plurality of contact plugs and the plurality of conductive layers for local wirings cross each other. 7 . The semiconductor memory device according to claim 6 , wherein the insulating layer for spacers separates the sidewalls of the plurality of contact plugs from the plurality of conductive layers for local wirings.

8. The semiconductor memory device according to claim 1, further comprising a peripheral circuit structure disposed below the stack structure, The plurality of contact plugs are connected to a plurality of metal lines connected to the peripheral circuit structure.

9. The semiconductor memory device according to claim 8, wherein the peripheral circuit structure includes a row decoder.

10. A semiconductor memory device comprising: A peripheral circuit structure is formed on a semiconductor substrate; a memory cell array formed above the peripheral circuit structure; a plurality of contact plugs penetrating the reduced area of ​​the memory cell array, the plurality of contact plugs being connected to a plurality of metal lines of the peripheral circuit structure; as well as a pad layer surrounding the sidewalls of the plurality of contact plugs respectively, wherein the memory cell array includes a plurality of conductive layers for local wiring stacked in a stepped structure in the shrinking region, wherein each of the plurality of contact plugs comprises a protruding portion protruding horizontally, and the protruding portion is connected to a corresponding conductive layer for local wiring among the plurality of conductive layers for local wiring, and The protruding portion is formed between a pad layer corresponding to the protruding portion in the pad layer and a conductive layer corresponding to the protruding portion in the conductive layer for the local line. 11 . The semiconductor memory device according to claim 10 , wherein the protruding portion of each of the plurality of contact plugs extends and protrudes to an end portion of the corresponding conductive layer for local wiring. 12 . The semiconductor memory device according to claim 11 , wherein a lower surface of the protruding portion of each of the plurality of contact plugs is connected to an upper surface of the end portion of the corresponding conductive layer for local wiring.

13. The semiconductor memory device according to claim 10, further comprising an insulating layer for spacers formed on sidewalls of the plurality of contact plugs in a region where the plurality of contact plugs and the plurality of conductive layers for local wirings cross each other.

14. The semiconductor memory device according to claim 10, wherein the peripheral circuit structure includes a row decoder, The row decoder is connected to the plurality of conductive layers for local wiring through the plurality of metal wirings and the plurality of contact plugs.

15. A method of manufacturing a semiconductor memory device, the method comprising: forming a stack structure including a plurality of first material layers and a plurality of second material layers, the first material layers and the second material layers being alternately stacked in a unit region and a reduced region, wherein the first material layers and the second material layers are stacked in a stepped structure, wherein the second material layers are exposed in the reduced region; forming a sacrificial layer in the reduced area along the upper surface of the stacked structure; forming a cushion layer along the upper surface of the sacrificial layer; By removing the sacrificial layer and the pad layer formed on the sidewall of the stack structure having the stepped structure, the sacrificial layer and the pad layer remain only on the upper surface of the stack structure; forming an interlayer insulating layer on top of the entire structure, and forming a plurality of contact holes penetrating the interlayer insulating layer, the sacrificial layer, and the stacked structure; forming an insulating layer for a spacer on a sidewall of the second material layer exposed through the sidewall of the contact hole; removing the second material layer, and forming a conductive layer for a local word line in a space where the second material layer is removed; removing the sacrificial layer exposed through the sidewall of the contact hole; as well as Contact plugs each having a protruding portion are formed by filling the contact holes each including a space where the sacrificial layer is removed with a conductive material, wherein the pad layer is located on the protruding portion of the contact plug.

16. The method according to claim 15, wherein forming the sacrificial layer comprises: forming a first sacrificial layer including an oxide layer on an upper surface of the second material layer; A second sacrificial layer including an undoped polysilicon layer is formed along a surface of a top of the entire structure including the first sacrificial layer.

17. The method according to claim 15, wherein forming the insulating layer for a spacer comprises: forming a recess at a sidewall of the contact hole by etching the sidewall of the second material layer exposed through the sidewall of the contact hole to a thickness thinner than a horizontal width of the sacrificial layer; forming an insulating layer for a spacer on the sidewalls of the contact holes each including the recess; as well as By performing the etching process, the insulating layer for the spacer remains only in the concave portion. 18 . The method according to claim 15 , wherein when the sacrificial layer exposed through the sidewall of the contact hole is removed, a space where the sacrificial layer is removed exposes an upper surface of an end portion of the conductive layer for a local word line. 19 . The method according to claim 18 , wherein the contact plugs are connected to the upper surfaces of the end portions of the conductive layer for local word lines, respectively. 20 . The method of claim 15 , wherein the contact plug is connected to a peripheral circuit structure disposed at a lower portion of the cell region and the shrink region.

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