Integrated transistor device and method of forming the same

Abstract

In some embodiments, the present disclosure relates to an integrated transistor device and a method for forming the same, the integrated transistor device comprising a first barrier layer arranged above a substrate. In addition, an undoped layer may be arranged above the first barrier layer and have an n-channel device region laterally adjacent to the p-channel device region. The n-channel device region of the undoped layer has a topmost surface, which is higher than the topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further include a second barrier layer above the n-channel device region of the undoped layer. The first gate electrode is arranged above the second barrier layer, and the second gate electrode is arranged above the p-channel device region of the undoped layer. The present disclosure provides a method for preventing the formation of a parasitic channel, thereby producing a reliable integrated transistor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated transistor devices and methods of forming integrated transistor devices. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated chips (ICs) may use many different types of transistor devices depending on the application of the IC. In recent years, the increase in the market for cellular devices and radio frequency (RF) devices has led to a significant increase in the use of high-voltage transistor devices. Therefore, compared to silicon-based semiconductor devices, high electron mobility transistor (HEMT) devices have received increased attention due to higher electron mobility and wide band gap. Such high electron mobility and wide band gap allow for improved performance (e.g., fast switching speed, low noise) and high temperature applications. Summary of the invention

[0003] An integrated transistor device according to an embodiment of the present disclosure includes: a first barrier layer arranged above a substrate; an undoped layer arranged above the first barrier layer, wherein the undoped layer has an n-channel device region laterally adjacent to a p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface, and the topmost surface is higher than the topmost surface of the p-channel device region of the undoped layer; a second barrier layer, above the n-channel device region of the undoped layer; a first gate electrode arranged above the second barrier layer; and a second gate electrode arranged above the p-channel device region of the undoped layer.

[0004] An integrated transistor device according to an embodiment of the present disclosure includes: a first III / V semiconductor layer arranged above a substrate; an undoped binary III / V semiconductor layer arranged above the first III / V semiconductor layer, wherein the undoped binary III / V semiconductor layer has an n-channel device region laterally beside a p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; a second III / V semiconductor layer arranged above the n-channel device region of the undoped binary III / V semiconductor layer; a doped binary III / V source region and a doped binary III / V drain region arranged above the p-channel device region of the undoped binary III / V semiconductor layer; a first gate electrode arranged above the second III / V semiconductor layer; and a second gate electrode arranged above the undoped binary III / V semiconductor layer and between the doped binary III / V source region and the doped binary III / V drain region.

[0005] A method for forming an integrated transistor device according to an embodiment of the present disclosure includes: depositing a first barrier layer over a substrate, wherein the substrate includes an n-channel device region that is laterally adjacent to a p-channel device region and continuously connected to the p-channel device region; depositing an undoped layer over the first barrier layer; depositing a second barrier layer over the undoped layer; performing a first etching process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein a lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than the uppermost surface of the undoped layer on the n-channel device region of the substrate; selectively forming a doped layer over the lower portion of the undoped layer on the p-channel device region of the substrate; forming a first gate electrode arranged over the second barrier layer; and forming a second gate electrode arranged over the lower portion of the undoped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated high electron mobility transistor (HEMT) devices having an n-channel device and a p-channel device on the same substrate are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of integrated HEMT devices having n-channel devices and p-channel devices on the same substrate are shown.

[0009] Figure 3 Cross-sectional views of some embodiments of an integrated HEMT device having a high voltage power device, an n-channel device, and a p-channel device on the same substrate are shown.

[0010] Figures 4 to 20 Cross-sectional views of some embodiments of methods of forming an integrated HEMT device having an n-channel device and a p-channel device on the same substrate are shown.

[0011] Fig.21 Shows the corresponding Figures 4 to 20 Flowcharts of some embodiments of the method.

[0012] [Description of Figure Numbers]

[0013] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000: cross-sectional view;

[0014] 102: substrate;

[0015] 102a: n-channel device region;

[0016] 102b: p-channel device region;

[0017] 104: first barrier layer;

[0018] 106: a first undoped layer;

[0019] 106a: thin sheet;

[0020] 106i: intermediate upper surface;

[0021] 106t: topmost surface;

[0022] 108: second barrier layer;

[0023] 110: n-channel device;

[0024] 112: p-channel device;

[0025] 114: Dielectric structure;

[0026] 116a: a first contact member;

[0027] 116b: second contact member;

[0028] 118: a first gate electrode;

[0029] 120: first doping layer;

[0030] 121: second doping layer;

[0031] 122a: third contact member;

[0032] 122b: fourth contact member;

[0033] 123: third doping layer;

[0034] 124: a second gate electrode;

[0035] 126: Quarantine area;

[0036] 130: first heterojunction;

[0037] 132: Second heterojunction;

[0038] 202: contact hole;

[0039] 302: High voltage power devices;

[0040] 316a: fifth contact member;

[0041] 316b: sixth contact member;

[0042] 318: a third gate electrode;

[0043] 320: buffer stack;

[0044] 322: second buffer layer;

[0045] 324: first buffer layer;

[0046] 330: fourth doping layer;

[0047] 340: The third heterojunction;

[0048] 406: a first undoped material;

[0049] 408: second barrier material;

[0050] 420: doping materials;

[0051] 502: a first mask layer;

[0052] 602: first etching process;

[0053] 620: patterning doping layer;

[0054] 702: a second mask layer;

[0055] 704: Opening;

[0056] 802: selective doping layer;

[0057] 804: Epitaxial growth process;

[0058] 902: a third mask layer;

[0059] 1002: second etching process;

[0060] 1102: Isolation implantation process;

[0061] 1104: fourth mask layer;

[0062] 1106: First opening;

[0063] 1202: dielectric layer;

[0064] 1204: contact opening;

[0065] 1302: conductive layer;

[0066] 1402: a fifth mask layer;

[0067] 1602: additional dielectric layer;

[0068] 1702: first gate opening;

[0069] 1704: second gate opening;

[0070] 1706: dielectric layer;

[0071] 1802: gate layer;

[0072] 2100: Methods;

[0073] 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, 2122: action;

[0074] d1: first distance;

[0075] t1: first thickness;

[0076] t2: second thickness;

[0077] t3: third thickness;

[0078] w1: first width;

[0079] w2: second width;

[0080] w3: third width. DETAILED DESCRIPTION

[0081] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0082] Additionally, for ease of description, spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted likewise accordingly.

[0083] A high electron mobility transistor (HEMT) device includes a heterojunction located at the interface between two materials with different bandgaps and serves as the channel region of the HEMT device. In an enhancement-mode device (e.g., an enhancement-mode field effect transistor (E-FET)), the HEMT device uses a gate-to-source voltage to switch the HEMT device "on" (e.g., to "turn on" the current between the source and the drain). In a depletion-mode device (e.g., a depletion-mode field effect transistor (D-FET)), the HEMT device uses a gate-to-source voltage to switch the device "off" (e.g., to "turn off" the current between the source and the drain).

[0084] For example, in the enhancement mode of an n-channel HEMT device, the conduction band at the heterojunction has a sharp valley that drops below the Fermi level and intersects the Fermi level, thereby forming a two-dimensional electron gas (2DEG) at the heterojunction when a gate-to-source voltage is applied. For example, in the enhancement mode of a p-channel HEMT device, the valence band at the heterojunction exhibits a peak that is above the Fermi level and intersects the Fermi level, thereby forming a two-dimensional hole gas (2DHG) at the heterojunction when a gate-to-source voltage is applied. In some applications, a p-channel HEMT device and an n-channel HEMT device are integrated on the same substrate. However, parasitic 2DEG and 2DHG may form, interfering with the desired 2DEG and 2DHG and degrading device performance.

[0085] In some embodiments of the integrated HEMT device, a first undoped III-V layer may be disposed over a substrate and a barrier layer may be disposed over the first undoped III-V layer. An n-channel device may be disposed on an n-channel device region of a substrate, in part including disposing a second undoped III-V layer over the barrier layer. In an enhancement mode, a desired 2DEG in an n-channel device may be formed between the barrier layer and the first undoped III-V layer. However, an undesired parasitic 2DHG may also be formed between the second undoped III-V layer and the barrier layer. The parasitic 2DHG may interact with the desired 2DEG, assisting electron-hole recombination, and thus reducing the carrier density of the desired 2DEG. In addition, the parasitic 2DHG may cause the sheet resistance of the 2DEG to decrease and may also cause leakage when the device is "off", thereby reducing device performance.

[0086] A p-channel device may be disposed on a p-channel device region laterally lateral to an n-channel device region of a substrate, including, in part, disposing a third undoped III-V layer above a barrier layer. In an enhancement mode, a desired 2DHG in a p-channel device may be formed between the third undoped III-V layer and the barrier layer. However, an undesired parasitic 2DEG may also be formed between the barrier layer and the first undoped III-V layer. The parasitic 2DEG may interact with the desired 2DHG, assisting electron-hole recombination and thereby reducing the carrier density of the desired 2DHG. Additionally, the parasitic 2DEG may cause the sheet resistance of the 2DHG to decrease and may also cause leakage when the device is "off," thereby reducing device performance.

[0087] Various embodiments of the present disclosure provide a method and corresponding structure for an integrated HEMT device that eliminates undesired parasitic channels to produce a reliable integrated HEMT device. In some embodiments, a first barrier layer is formed above a substrate, a first undoped layer is formed above the first barrier layer, a second barrier layer is formed above the first undoped layer, and a first doped layer is formed above the second barrier layer. Selective etching is performed to remove the first doped layer, the second barrier layer, and an upper portion of the first undoped layer on a p-channel device region of the substrate. A second doped layer is grown on a lower portion of the first undoped layer on the p-channel device region of the substrate by an epitaxial growth process. Remaining contacts, gate electrodes, and isolation structures are formed, such that an n-channel device is on an n-channel device region of the substrate, and a p-channel device is on a p-channel device region of the substrate.

[0088] In such embodiments, since the second barrier layer is thin (e.g., less than 30 nanometers), a parasitic 2DHG channel is blocked or prevented from forming in an n-channel device, thereby blocking or preventing the valence band from intersecting the Fermi level at the interface between the first doped layer and the second barrier layer. Since the first barrier layer is above the substrate and directly contacts the substrate (rather than an undoped layer), a parasitic 2DEG channel is blocked or prevented from forming in a p-channel device, and thus a heterojunction is not formed. Thus, the disclosed method of forming an integrated HEMT device blocks or prevents the formation of a parasitic channel, thereby producing a reliable integrated HEMT device without compromising, for example, carrier density, sheet resistance, or on / off gate control.

[0089] Figure 1 A cross-sectional view 100 of some embodiments of an integrated HEMT device including an n-channel device and a p-channel device is shown.

[0090] In some embodiments, the integrated HEMT device in the cross-sectional view 100 includes a first barrier layer 104 disposed above the substrate 102. In some embodiments, the first barrier layer 104 may include a III-V semiconductor material such as, for example, indium aluminum gallium nitride (e.g., InGaN). x Al y Ga 1-x-y N, where x+y=1, and where x can be in the range of 0 to 1). In some embodiments, the substrate 102 can include, for example, silicon, silicon carbide, or sapphire. A first undoped layer 106 can be disposed over the first barrier layer 104. In some embodiments, the first undoped layer 106 can include a binary III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, or indium nitride. In some embodiments, on an n-channel device region 102a of the substrate 102, the first undoped layer 106 has a topmost 104 surface 106t that is higher than an intermediate upper surface 106i of the first undoped layer 106 on a p-channel device region 102b of the substrate 102. In some embodiments, the topmost surface 106t of the first undoped layer 106 can be at a position higher than the intermediate upper surface 106i of the first undoped layer 106 by a first distance d1. For example, in some embodiments, the first distance d1 can be in the range between about 290 nanometers and about 990 nanometers. In some embodiments, the first undoped layer 106 may have different thicknesses due to the p-channel device region 102b using a thinner first undoped layer 106 than the n-channel device region 102a of the substrate 102. In some embodiments, the first undoped layer 106 has a substantially coplanar bottommost surface.

[0091] In some embodiments, the n-channel device 110 can be disposed on the n-channel device region 102a of the substrate 102. The n-channel device 110 can include a second barrier layer 108 above the topmost surface 106t of the first undoped layer 106. In some embodiments, the second barrier layer 108 can include a quaternary III-V semiconductor material such as, for example, indium aluminum gallium nitride (e.g., InGaN). m Al n Ga 1-m-n N, where m+n=1, and where m can be in the range of 0 to 1). Thus, in some embodiments, the first barrier layer 104 can include the same material as the second barrier layer 108 with the same concentration of each element (e.g., x=m and y=n), while in other embodiments, the first barrier layer 104 can include a different concentration of each element than the second barrier layer 108 (e.g., x≠m and y≠n). Thus, in some embodiments, the substrate 102 can include silicon, the first barrier layer 104 can include indium aluminum gallium nitride, the first undoped layer 106 can include indium nitride, and the second barrier layer 108 can include indium aluminum gallium nitride. In some embodiments, the first contact 116a and the second contact 116b can be arranged above the second barrier layer 108 and spaced apart from each other by the first doped layer 120. In some embodiments, the first doped layer 120 can include the same material as the first undoped layer 106; however, the first doped layer 120 also has a doping concentration. Thus, in some embodiments, the first doped layer 120 can include doped indium nitride. In some embodiments, the first doped layer 120 may correspond to a doped binary III / V gate region. A first gate electrode 118 may be disposed over the first doped layer 120 , between the first contact 116 a and the second contact 116 b and surrounded by the dielectric structure 114 .

[0092] In the enhancement mode, due to the difference in the band gap between the first undoped layer 106 and the second barrier layer 108, a two-dimensional electron gas (2DEG) may be formed along the first heterojunction 130 at the interface between the first undoped layer 106 and the second barrier layer 108. In some embodiments, since the second barrier layer 108 is thin enough, a parasitic two-dimensional hole gas (2DHG) is not formed at the interface between the second barrier layer 108 and the first doped layer 120. For example, in some embodiments, the second barrier layer 108 may have a first thickness t1 of less than about 20 nanometers. In other embodiments, the second barrier layer 108 may have a first thickness t1 of less than about 30 nanometers. In some embodiments, the first thickness t1 of the second barrier layer 108 that efficiently prevents the formation of parasitic 2DHG may depend on the concentration of each element in the second barrier layer 108. In addition, in some embodiments, since the first doping layer 120 may be sufficiently thin and / or have a sufficiently low p-type dopant concentration, the parasitic 2DHG may not be formed on the n-channel device region 102a of the substrate 102. For example, in some embodiments, the first doping layer 120 may have a second thickness t2 less than 30 nanometers and / or may include about 10 nanometers. 18 Therefore, in some embodiments, the first thickness t1 of the second barrier layer 108, the concentration of each element in the second barrier layer 108, the second thickness t2 of the first doped layer 120, and / or the dopant concentration of the first doped layer 120 can be designed so that the conduction band is below the Fermi level at the interface between the second barrier layer 108 and the first undoped layer 106 to form a 2DEG without forming a 2DHG. Therefore, the n-channel device 110 can utilize the 2DEG along the first heterojunction 130 without the interference of the parasitic 2DHG.

[0093] In some embodiments, a p-channel device 112 may be disposed on a p-channel device region 102b of the substrate 102. The p-channel device 112 may include a second doped layer 121 disposed above an intermediate upper surface 106i of the first undoped layer 106. A third doped layer 123 may also be disposed above the intermediate upper surface 106i of the first undoped layer 106 and spaced apart from the second doped layer 121 by a second gate electrode 124. In some embodiments, the second doped layer and the third doped layer 123 may correspond to a doped binary III / V source region and a doped binary III / V drain region, respectively, such that the second gate electrode 124 is disposed between the doped binary III / V source region (e.g., the second doped region 121) and the doped binary III / V drain region (e.g., the third doped region 123). In some embodiments, the second gate electrode 124 is spaced apart from the intermediate upper surface 106i of the first undoped layer 106 by a dielectric structure 114. In some embodiments, the third contact 122 a and the fourth contact 122 b may be disposed over the second doping layer 121 and the third doping layer 123 , respectively.

[0094] In the enhancement mode, a two-dimensional hole gas (2DHG) may be formed along the second heterojunction 132 at the interface between the first undoped layer 106 and the first barrier layer 104. In some embodiments, due in part to the first undoped layer 106 on the p-channel device region 102b of the substrate 102 having a thickness in a range of, for example, between about 10 nanometers and about 30 nanometers, the 2DHG is formed, thereby causing the valence band at the second heterojunction 132 to exhibit a peak above the Fermi level and intersecting the Fermi level. In some embodiments, if the first undoped layer 106 on the p-channel device region 102b of the substrate 102 has a thickness greater than 30 nanometers, the 2DHG may not be formed at the second heterojunction 132 in the enhancement mode. In addition, in some embodiments, the 2DHG may be formed along the second heterojunction 132 due in part to the element concentration of the first barrier layer 104. The parasitic 2DEG is not formed in the p-channel device 112 because the first barrier layer 104 does not overlie the undoped layer on the p-channel device region 102b of the substrate 102. Instead, the first undoped layer 106 is above the first barrier layer 104, thereby forming a 2DHG instead of a 2DEG. Therefore, the p-channel device can utilize the 2DHG along the second heterojunction 132 without interference from the parasitic 2DEG.

[0095] Therefore, in some embodiments, the p-channel device 112 and the n-channel device 110 can be integrated on the same substrate 102 without forming parasitic 2DHG and 2DHG. In addition, the isolation region 126 can surround the p-channel device 112 so that the p-channel device 112 is isolated from the n-channel device 110. In some embodiments, the isolation region 126 can extend through the first undoped layer 106 and extend into at least a portion of the first barrier layer 104 so that the isolation region 126 intersects the second heterojunction 132. Therefore, in the enhancement mode, the isolation region 126 prevents the 2DEG along the first heterojunction 130 in the n-channel device 110 from interfering with the 2DHG along the second heterojunction 132 in the p-channel device 112.

[0096] Figure 2 A cross-sectional view 200 of some other embodiments of an integrated HEMT device including an n-channel device and a p-channel device is shown.

[0097] The integrated HEMT device in the cross-sectional view 200 includes contact holes 202 embedded in the dielectric structure 114. Each of the first contact 116a, the first gate electrode 118, the second contact 116b, the second gate electrode 124, the third contact 122a, and the fourth contact 122b can be coupled to one of the contact holes 202. The contact holes 202 can be coupled to a voltage source to control the operation (e.g., "on", "off") of the n-channel device 110 and the p-channel device 112. In some embodiments, up to 20 volts can be applied across the n-channel device 110 and the p-channel device 112 through the contact holes 202. In other embodiments, the voltage bias applied to the n-channel device 110 and the p-channel device 112 can be in a range between, for example, about 1 volt and about 12 volts. In addition, unlike Figure 1 In the cross-sectional view 100, in some embodiments, the first doping layer ( Figure 1 The first doped layer 120 below the first gate electrode 118 is formed so that the first gate electrode 118 directly contacts the dielectric structure 114, wherein the dielectric structure 114 separates the first gate electrode 118 from the second barrier layer 108. Figure 1 In such embodiments where the first doped layer 120 is not gated, the n-channel device 110 may be a depletion mode device, where an applied voltage bias to the first gate electrode 118 causes the n-channel device 110 to become “off”.

[0098] Figure 3 A cross-sectional view 300 of some embodiments of an integrated HEMT device including an n-channel device, a p-channel device, and a high voltage power device is shown.

[0099] The integrated HEMT device in the cross-sectional view 300 includes an n-channel device 110 and a p-channel device 112 integrated over the same substrate 102. Additionally, in some embodiments, a high voltage power device 302 may be disposed over the substrate 102 and laterally adjacent to the n-channel device 110 and the p-channel device 112. In some embodiments, the high voltage power device 302 may be operated using a voltage greater than 100 volts. For example, in some embodiments, the high voltage power device 302 may be operated using a voltage in a range between about 100 volts and about 1000 volts. Thus, in some embodiments, the high voltage power device 302 may be operated using a voltage between 100 and 1000 times greater than a voltage applied to the n-channel device 110 and / or the p-channel device 112.

[0100] In the cross-sectional view 300, the high-voltage power device 302 may be an n-channel enhancement mode device. Therefore, the high-voltage power device 302 may include a fifth contact 316a and a sixth contact 316b disposed above the second barrier layer 108, and in some embodiments, the fourth doped layer 330 separates the fifth contact 316a from the sixth contact 316b. The fourth doped layer 330 may directly contact the second barrier layer 108. In some embodiments, the third gate electrode 318 is disposed above the fourth doped layer 330.

[0101] In some embodiments, to accommodate operating voltages greater than 100 volts, the sixth contact 316b may be spaced apart from the fourth doped layer 330 and / or the third gate electrode 318 by a second width w2 that is greater than a first width w1 between the fifth contact 316a and the fourth doped layer 330 and / or the third gate electrode 318. The fifth contact 316a may correspond to a source region of the high-voltage power device 302, and the sixth contact 316b may correspond to a drain region of the high-voltage power device 302. Similarly, the first contact 116a of the n-channel device 110 may correspond to a source region of the n-channel device 110, and the second contact 116b of the n-channel device 110 may correspond to a drain region of the n-channel device 110. The second contact 116b of the n-channel device 110 may be spaced apart from the first doped layer 120 and / or the first gate electrode 118 by a third width w3. In some embodiments, the second width w2 may be greater than the third width w3 because the high voltage power device 302 utilizes a higher operating voltage compared to the n-channel device 110 .

[0102] Similar to the n-channel device 110, in the high-voltage power device 302, after a sufficient voltage bias is applied to the third gate electrode 318, a 2DEG may be formed at the interface between the second barrier layer 108 and the first undoped layer 106 or at the third heterojunction 340. The isolation region 126 may separate the third heterojunction 340 from the first heterojunction 130 so as to isolate the high-voltage power device 302 from the n-channel device 110. In other embodiments, the high-voltage power device 302 may be adjacent to the p-channel device 112, and therefore, the isolation region 126 may separate the third heterojunction 340 from the second heterojunction 132.

[0103] In some embodiments, a buffer stack 320 may be disposed between the substrate 102 and the first barrier layer 104. The buffer stack 320 may include a second buffer layer 322 above the first buffer layer 324. The first buffer layer 324 and the second buffer layer 322 may each include indium aluminum gallium arsenide. In some embodiments, the first buffer layer 324 and the second buffer layer 322 may include the same concentration of each element, different concentrations of each element, or a combination thereof. The buffer stack 320 may reduce the vertical electric field effects caused by the high-voltage power device 302. The total number of layers in the buffer stack 320 may depend on the operating voltage used to operate the high-voltage power device 302. For example, in some embodiments, if the operating voltage of the high-voltage power device 302 is 500 volts, then a first number of layers may be used in the buffer stack 320, however, if the operating voltage of the high-voltage power device 302 is 100 volts, then a second number of layers less than the first number of layers may be used in the buffer stack 320. Nevertheless, the buffer stack 320 allows the high voltage power device 302 to withstand and maintain its high voltage without interfering with the first heterojunction 130 of the n-channel device 110 and the second heterojunction 132 of the p-channel device 112 , respectively.

[0104] Figures 4 to 20 Cross-sectional views 400 through 2000 illustrate some embodiments of methods of forming an integrated HEMT device including an n-channel device and a p-channel device on the same substrate. Figures 4 to 20 , but it should be understood that Figures 4 to 20 The structures disclosed in are not limited to this method, but rather can stand alone as structures independent of the method.

[0105] like Figure 4As shown in the cross-sectional view 400 of , a substrate 102 is provided. In some embodiments, the substrate 102 includes silicon, sapphire, or silicon carbide. In some embodiments, the substrate 102 may include p-type silicon, which is a widely available substrate and thus reduces the cost of the HEMT device. A first barrier layer 104 may be deposited over the substrate 102. In some embodiments, the first barrier layer 104 may include a quaternary III-V semiconductor material, such as, for example, indium aluminum gallium arsenide. The first barrier layer 104 may have a thickness in a range between about 20 nanometers and about 50 nanometers. A first undoped material 406 may be deposited over the first barrier layer 104 and directly contact the first barrier layer 104. The first undoped material 406 may include a III-V semiconductor material or a III-N semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the first undoped material 406 may have a thickness in a range between about 0.3 micrometers and about 1 micrometer. A second barrier material 408 may be deposited over the first undoped material 406. In some embodiments, the second barrier material 408 may include a quaternary III-V semiconductor material such as, for example, indium aluminum gallium arsenide. In some embodiments, the second barrier material 408 may include each element of indium aluminum gallium arsenide at a different concentration than the first barrier layer 104, while in other embodiments, the second barrier material 408 may include each element of indium aluminum gallium arsenide at the same concentration as the first barrier layer 104. In some embodiments, the second barrier material 408 may have a first thickness t1 in a range between about 10 nanometers and about 30 nanometers. Thus, in some embodiments, the second barrier material 408 may be thinner than the first barrier layer 104. The first thickness t1 may be less than 30 nanometers to prevent parasitic channels from forming in an n-channel device to be formed above the substrate 102 (see Figure 1 n-channel device 110).

[0106] In some embodiments, a doping material 420 may be deposited over the second barrier material 408. The doping material 420 may include the same material as the first undoped material 406, but with a doping concentration. For example, in some embodiments, the doping material 420 may include a p-type III-V semiconductor material such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the doping material 420 is lightly doped (e.g., less than 10 18 dopant / cm3) to prevent a parasitic channel from being formed in an n-channel device to be formed above substrate 102 (see, Figure 1 Similarly, in some embodiments, the doping material 420 may have a second thickness t2 less than 30 nanometers to prevent a parasitic channel from being formed in an n-channel device to be formed above the substrate 102 (see Figure 1In other embodiments, it should be understood that the doping material 420 may be omitted, such as in the case of n-channel devices ( Figure 2 In an embodiment of an n-channel device 110), the n-channel device is a depletion mode device, such as in Figure 2 middle.

[0107] In some embodiments, the first barrier layer 104, the first undoped material 406, the second barrier material 408 and / or the doping material 420 may be deposited by an epitaxial process and / or another form of deposition process (e.g., chemical vapor deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, electron beam / thermal evaporation, etc.).

[0108] like Figure 5 As shown in the cross-sectional view 500 of , the first mask layer 502 may be formed over the n-channel device region 102a of the substrate 102, whereas the p-channel device region 102b of the substrate 102 may remain uncovered. Since the n-channel device region 102a and the p-channel device region 102b are part of the same substrate 102, the n-channel device region 102a of the substrate 102 may be laterally lateral to and continuously connected to the p-channel device region 102b of the substrate 102. In some embodiments, the first mask layer 502 may include a photosensitive material (e.g., photoresist) formed over the doping material 420 by a spin coating process. In such embodiments, the photosensitive material layer is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation may modify the solubility of the exposed regions within the photosensitive material to define soluble regions. Then, the photosensitive material may be subsequently developed to define openings within the photosensitive material by removing the soluble regions. In other embodiments, the first mask layer 502 may include a hard mask layer (eg, a silicon nitride layer, a silicon carbide layer, or the like).

[0109] like Figure 6 As shown in the cross-sectional view 600 of FIG. 1 , a first etching process 602 may be performed to remove the doping material ( Figure 5 The doped material 420) is removed and the first undoped material ( Figure 5The first undoped material 406 of the substrate 102 is formed by etching the upper portion of the first undoped material 406 of the substrate 102. In some embodiments, the first etching process 602 may be a wet etch or a dry etch. After the first etching process 602, on the n-channel device region 102a of the substrate 102, the patterned doped layer 620 is disposed over the second barrier layer 108, the second barrier layer 108 is disposed over the first undoped layer 106, and the first undoped layer 106 is disposed over the first barrier layer 104. On the p-channel device region 102b of the substrate 102, the thin slice 106a of the first undoped layer 106 is disposed over the first barrier layer 104. In some embodiments, the thin slice 106a of the first undoped layer 106 may have a third thickness t3 in a range between about 10 nanometers and about 30 nanometers.

[0110] Therefore, in some embodiments, the first etching process 602 may be controlled to remove the first undoped material ( Figure 5 In some embodiments, the first distance d1 may be, for example, in a range between about 270 nanometers and about 990 nanometers. In some embodiments, since the thin slice 106a is disposed over the p-channel device region 102b of the substrate 102 and laterally surrounds a portion of the first undoped layer 106 disposed over the n-channel device region 102a of the substrate 102 (e.g., the n-channel device region of the first undoped layer 106), the thin slice 106a may correspond to the p-channel device region of the first undoped layer 106.

[0111] The third thickness t3 of the thin slice 106a may allow the p-channel device region 102b of the substrate 102 to form a 2DHG during operation in the enhancement mode. In some embodiments, if the third thickness t3 is too large (e.g., greater than 30 nanometers), the 2DHG may not be formed on the p-channel device region 102b of the substrate 102, and thus the p-channel device region 102b of the substrate 102 will be unreliable. In some embodiments, the first undoped layer 106 on the n-channel device region 102a of the substrate 102 is thicker than the thin slice 106a because the n-channel device region 102a of the substrate 102 relies on the thicker (e.g., greater than 30 nanometers) first undoped layer 106 to form a 2DEG during operation in the enhancement mode.

[0112] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , in some embodiments, the first mask layer ( Figure 5The second mask layer 702 may be formed on the patterned doped layer 620 and the first undoped layer 106. The second mask layer 702 also covers the patterned doped layer 620, the second barrier layer 108, and the sidewalls of the first undoped layer 106. The opening 704 in the second mask layer 702 exposes the first undoped layer 106 on the p-channel device region 102b of the substrate 102. In some embodiments, the first mask layer ( Figure 5 The second mask layer 702 is deposited and patterned using a similar photolithography technique as the first mask layer 502. In some embodiments, the second mask layer 702 may be a hard mask and may be an amorphous material.

[0113] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a selective epitaxial growth process 804 may be performed to selectively deposit a selectively doped layer 802 in the opening ( Figure 7 The selective epitaxial growth process 804 may be an epitaxial process or another form of deposition process (e.g., chemical vapor deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, electron beam / thermal evaporation, etc.). The selective epitaxial growth process 804 may be selective to the first undoped layer 106, so that the selectively doped layer 802 directly contacts the first undoped layer 106, because the first undoped layer 106 may be a crystalline material. The selective epitaxial growth process 804 may prevent the selectively doped layer 802 from being formed on the second mask layer 702, because the second mask layer 702 is an amorphous material.

[0114] In some embodiments, the selectively doped layer 802 includes a p-type binary III-V semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the selectively doped layer 802 may include the same material as the patterned doped layer 620, while in other embodiments, the selectively doped layer 802 may include a different material than the patterned doped layer 620. In some embodiments, the selectively doped layer 802 may be formed to a thickness of less than, for example, about 30 nanometers. In some embodiments, the selectively doped layer 802 is lower than the patterned doped layer 620.

[0115] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , the third mask layer 902 can be formed over portions of the patterned doped layer 620 and the selectively doped layer 802, while other portions of the patterned doped layer 620 and the selectively doped layer 802 remain uncovered. Figure 5The third mask layer 902 is deposited and patterned using a photolithography technique similar to the first mask layer 502).

[0116] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a second etching process 1002 may be performed according to the third mask layer 902. In some embodiments, the second etching process 1002 may be dry etching or wet etching and may be performed on the selectively doped layer ( Fig. 9 The selectively doped layer 802) and the patterned doped layer ( Fig. 9 The patterned doped layer 620 may be selective. Therefore, after the second etching process 1002, the selective doped layer ( Fig. 9 The selectively doped layer 802) and the patterned doped layer ( Fig. 9 A portion of the patterned doped layer 620 is formed, thereby forming a first doped layer 120 on the second barrier layer 108 and forming a second doped layer 121 and a third doped layer 123 on the first undoped layer 106.

[0117] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1100 , a fourth mask layer 1104 may be formed over the first doped layer 120, the second doped layer 121, and the third doped layer 123. The fourth mask layer 1104 may include a first opening 1106. In some embodiments, the first opening 1106 may be a continuous ring shape surrounding the second doped layer 121 and the third doped layer 123 from a top view. An isolation implantation process 1102 may be performed over the fourth mask layer 1104 so that an isolation region 126 is formed within the first opening 1106 in the fourth mask layer 1104. The fourth mask layer 1104 may prevent the isolation implantation process 1102 from affecting other features of the cross-sectional view 1100. In some embodiments, the isolation implantation process 1102 may include implanting iron, chlorine, fluorine, or the like into the first undoped layer 106 not covered by the fourth mask layer 1104. In other embodiments, the isolation implant process 1102 may involve forming a shallow trench isolation (STI) structure such that the isolation region 126 comprises silicon dioxide.

[0118] In some embodiments, the isolation region 126 may also be a continuous ring shape surrounding the second doped layer 121 and the third doped layer 123. In some embodiments, the isolation region 126 may extend from the top surface of the first undoped layer 106 on the p-channel device region 102b of the substrate 102 to the first barrier layer 104. In some embodiments, the isolation region 126 extends through the second heterojunction 132 at the interface between the first undoped layer 106 and the second doped layer 121 and the third doped layer 123 and extends into the first barrier layer 104. Therefore, the isolation region 126 may separate the second heterojunction 132 from the first heterojunction 130 along the interface between the first barrier layer 104 and the first undoped layer 106 to prevent cross interference and / or parasitic channels between the first device on the n-channel device region 102a of the substrate 102 and the second device on the p-channel device region 102b of the substrate 102.

[0119] like Fig.12 As shown in the cross-sectional view 1200 of , a dielectric layer 1202 defining a contact opening 1204 may be formed. The contact opening 1204 may be patterned so that the contact opening 1204 overlies the second barrier layer 108 on either side of the first doped layer 120 and overlies the second doped layer 121 and the third doped layer 123. The dielectric layer 1202 defining the contact opening 1204 may be formed by deposition and photolithography processes. In some embodiments, the dielectric layer 1202 may include, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), or the like.

[0120] like Fig.13 As shown in the cross-sectional view 1300 of , the conductive layer 1302 may be formed above the dielectric layer 1202 and within the contact opening 1204. In some embodiments, the conductive layer 1302 may include, for example, a material that produces an ohmic contact with the second barrier layer 108 and the second doping layer 121 and the third doping layer 123, such as, for example, titanium or aluminum. In other embodiments, the conductive layer 1302 may include, for example, copper, tungsten, or the like. The conductive layer 1302 may be formed by a deposition process (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.).

[0121] like Fig.14As shown in the cross-sectional view 1400 of FIG. 1 , a fifth mask layer 1402 may be formed above the conductive layer 1302. In some embodiments, the fifth mask layer 1402 may have been formed by deposition and photolithography processes to cover the contact openings ( Fig.12 contact opening 1204).

[0122] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a third etching process (for the conductive layer ( Fig.14 The conductive layer 1302) is selective to remove the conductive layer ( Fig.14 In some embodiments, the third etching process may include a wet etchant or a dry etchant. After the third etching process, the remaining conductive layer ( Fig.14 The conductive layer 1302 of FIG. 1 defines the first contact 116a, the second contact 116b, the third contact 122a and the fourth contact 122b. Therefore, in some embodiments, the first contact 116a, the second contact 116b, the third contact 122a and the fourth contact 122b may include the same material.

[0123] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , the fifth mask layer ( Fig.15 The fifth mask layer 1402 is formed, and an additional dielectric layer 1602 is deposited over the dielectric layer 1202. The additional dielectric layer 1602 can be formed in the same manner as the dielectric layer 1202 and also includes the same material as the dielectric layer 1202.

[0124] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , the first gate opening 1702 and the second gate opening 1704 may be formed in a plurality of dielectric layers 1706. The plurality of dielectric layers 1706 include dielectric layers ( Fig.16 The dielectric layer 1202) and the additional dielectric layer ( Fig.16 In some embodiments, a mask layer (not shown) and subsequent etching may be used to remove portions of the plurality of dielectric layers 1706 to define a first gate opening 1702 and a second gate opening 1704. In some embodiments, the first gate opening 1702 may expose the first doped layer 120 on the n-channel device region 102a of the substrate, and the second gate opening 1704 may be disposed between the second doped layer 121 and the third doped layer 123. However, in some embodiments, the second gate opening 1704 may not extend completely through the plurality of dielectric layers 1706. Therefore, in some embodiments, the second gate opening 1704 may have a bottom surface defined by the plurality of dielectric layers 1706.

[0125] like Fig.18As shown in the cross-sectional view 1800 of FIG. 1 , a gate layer 1802 may be deposited over the plurality of dielectric layers 1706 and fill the first gate opening ( Fig.17 The first gate opening 1702 and the second gate opening ( Fig.17 The gate layer 1802 may include a second gate opening 1704. In some embodiments, the gate layer 1802 may include a conductive material such as, for example, titanium nitride, nickel, tungsten, titanium, or platinum. In some embodiments, the gate layer 1802 may form a Schottky contact with the first doped layer 120 and / or the plurality of dielectric layers 1706. However, in other embodiments, the gate layer 1802 is not limited to a material that forms a Schottky contact. The gate layer 1802 may be formed by a deposition process (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.).

[0126] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the gate layer ( Fig.18 The gate layer 1802 of the embodiment of the present invention is used to form a first gate electrode 118 above the first doped layer 120 and a second gate electrode 124 above the plurality of dielectric layers 1706 and between the second doped layer 121 and the third doped layer 123. In some embodiments, the gate layer ( Fig.18 In some embodiments, the first gate electrode 118 and the second gate electrode 124 may have an upper portion that is wider than a lower portion.

[0127] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2 , additional dielectric material may be deposited on multiple dielectric layers ( Fig.19The dielectric layer 1706 of the first heterojunction 130 is formed on the substrate 102 to form a dielectric structure 114 on the substrate 102. Therefore, the dielectric structure 114 can cover the first gate electrode 118 and the second gate electrode 124, so that the n-channel device 110 arranged on the n-channel device region 102a of the substrate 102 is isolated from the p-channel device 112 arranged on the p-channel device region 102b of the substrate 102. In addition, since the second barrier layer 108 is relatively thin (e.g., less than 30 nanometers), during operation, a 2DEG is formed on the n-channel device 110 along the first heterojunction 130, and a 2DHG parasitic channel is not formed on the n-channel device region 102a of the substrate 102. Similarly, since the first barrier layer 104 directly contacts the substrate 102, during operation, a 2DHG is formed on the p-channel device along the second heterojunction 132, and a 2DEG parasitic channel is not formed on the p-channel device region 102b of the substrate 102. By isolating the p-channel device 112 from the n-channel device 110 and by preventing parasitic channels from forming in the p-channel device 112 and the n-channel device, Fig. 20 The integrated HEMT device in the cross-sectional view 2000 is a reliable device with optimal sheet resistance and minimal current leakage along the first heterojunction 130 and the second heterojunction 132 .

[0128] Fig.21 A flow chart illustrating some embodiments of a method 2100 of forming an integrated HEMT device including an n-channel device and a p-channel device on the same substrate.

[0129] Although method 2100 is shown and described as a series of actions or events below, it should be understood that the order of such actions or events shown should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described herein, some actions may occur in different orders and / or simultaneously with other actions or events. In addition, not all of the actions shown may be required to implement one or more aspects or embodiments of the description herein. In addition, one or more of the actions described herein may be performed with one or more separate actions and / or stages.

[0130] At act 2102, a first barrier layer is deposited over a substrate.

[0131] At act 2104 , a first undoped layer is deposited over the first barrier layer.

[0132] At act 2106 , a second barrier layer is deposited over the first undoped layer. Figure 4 Cross-sectional view 400 is shown corresponding to some embodiments of act 2102 , act 2104 , and act 2106 .

[0133] At act 2108 , a first etching process is performed on the p-channel device region of the substrate to remove the second barrier layer and an upper portion of the first undoped layer, wherein a lower portion of the undoped layer remains on the p-channel device region of the substrate. Figure 6 A cross-sectional view 600 is shown corresponding to some embodiments of act 2108 .

[0134] At act 2110 , a doped layer is selectively grown on a lower portion of the first undoped layer. Figure 8 A cross-sectional view 800 corresponding to some embodiments of act 2110 is shown.

[0135] At act 2112, a second etching process is performed to remove a central portion of the doped layer. Fig.10 A cross-sectional view 1000 is shown corresponding to some embodiments of act 2112 .

[0136] At act 2114, an isolation region is formed within the first undoped layer and between the n-channel device region and the p-channel device region of the substrate. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of act 2114 .

[0137] At activity 2116, a first set of contacts is formed over a peripheral portion of the doped layer.

[0138] At act 2118, a second set of contacts is formed on the second barrier layer. Figure 12 to Figure 15 Cross-sectional views 1200 through 1500 are shown corresponding to some embodiments of acts 2116 and 2118 .

[0139] At act 2120, a first gate is formed on the n-channel device region of the substrate and over the second barrier layer.

[0140] At act 2122, a second gate is formed between peripheral portions of the doped layers and over the first undoped layer on the p-channel device region of the substrate. Figure 16 to Figure 19 Cross-sectional views 1600 through 1900 are shown corresponding to some embodiments of acts 2120 and 2122 .

[0141] Therefore, the present disclosure is directed to a new method of fabricating an integrated HEMT device without forming a parasitic channel in order to produce a reliable integrated HEMT device, which includes an n-channel device and a p-channel device on the same substrate.

[0142] Therefore, in some embodiments, the present disclosure relates to an integrated transistor device, comprising: a first barrier layer arranged above a substrate; an undoped layer arranged above the first barrier layer, wherein the undoped layer has an n-channel device region laterally adjacent to the p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface that is higher than the topmost surface of the p-channel device region of the undoped layer; a second barrier layer above the n-channel device region of the undoped layer; a first gate electrode arranged above the second barrier layer; and a second gate electrode arranged above the p-channel device region of the undoped layer.

[0143] In some embodiments, the isolation region is within the undoped layer and between the first gate electrode and the second gate electrode. In some embodiments, the second barrier layer is thinner than the first barrier layer. In some embodiments, the first barrier layer directly contacts the substrate. In some embodiments, a first doped layer and a second doped layer are arranged above the p-channel device region of the undoped layer and directly contact the p-channel device region of the undoped layer, wherein the second gate electrode is between the first doped layer and the second doped layer. In some embodiments, a third doped layer is arranged above the second barrier layer and below the first gate electrode; and a first contact and a second contact are arranged above the second barrier layer, wherein the third doped layer is between the first contact and the second contact. In some embodiments, the second barrier layer has a thickness of less than about 30 nanometers. In some embodiments, a buffer layer is arranged between the first barrier layer and the substrate, wherein the buffer layer includes the same element as the first barrier layer. In some embodiments, a third gate electrode is arranged above the second barrier layer and the n-channel device region of the undoped layer, wherein an additional isolation region is between the third gate electrode and the first gate electrode.

[0144] In other embodiments, the present disclosure relates to an integrated transistor device, comprising: a first III / V semiconductor layer, arranged above a substrate; an undoped binary III / V semiconductor layer, arranged above the first III / V semiconductor layer, wherein the undoped binary III / V semiconductor layer has an n-channel device region laterally lateral to the p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; a second III / V semiconductor layer, arranged above the n-channel device region of the undoped binary III / V semiconductor layer; a doped binary III / V source region and a doped binary III / V drain region, arranged above the p-channel device region of the undoped binary III / V semiconductor layer; a first gate electrode, arranged above the second III / V semiconductor layer; and a second gate electrode, arranged above the undoped binary III / V semiconductor layer and between the doped binary III / V source region and the doped binary III / V drain region.

[0145] In some embodiments, a top surface of the first gate electrode is higher than a top surface of the second gate electrode. In some embodiments, an isolation region is disposed between the first gate electrode and the second gate electrode and extends from a top surface of the p-channel device region of the undoped binary III / V semiconductor layer to the first III / V semiconductor layer. In some embodiments, a doped binary III / V gate region is disposed between the second III / V semiconductor layer and the first gate electrode. In some embodiments, the doped binary III / V gate region has a thickness of less than about 10 18 The doping concentration is p-type dopant / cubic centimeter.

[0146] In yet other embodiments, the present disclosure relates to a method for forming an integrated transistor device, comprising: depositing a first barrier layer over a substrate, wherein the substrate includes an n-channel device region that is laterally adjacent to and continuously connected to a p-channel device region; depositing an undoped layer over the first barrier layer; depositing a second barrier layer over the undoped layer; performing a first etching process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein a lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than an uppermost surface of the undoped layer on the n-channel device region of the substrate; selectively forming a doped layer over the lower portion of the undoped layer on the p-channel device region of the substrate; forming a first gate electrode disposed over the second barrier layer; and forming a second gate electrode disposed over the lower portion of the undoped layer.

[0147] In some embodiments, an isolation process is performed to form an isolation region through the undoped layer and between the first gate electrode and the second gate electrode. In some embodiments, a doped gate region is formed above the second barrier layer on the n-channel device region of the substrate, wherein the doped gate region is between the first gate electrode and the second barrier layer. In some embodiments, the doped gate region has a thickness of less than about 30 nanometers. In some embodiments, a plurality of buffer layers are formed above the substrate and below the first barrier layer, wherein the plurality of buffer layers and the first barrier layer include the same quaternary III / V semiconductor material. In some embodiments, a first set of contacts is formed above the second barrier layer and laterally spaced apart from the first gate electrode; and a second set of contacts is formed above the doped layer on the p-channel device region of the substrate, wherein the second gate electrode is between the second set of contacts.

[0148] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated transistor device comprising: A first barrier layer disposed above the substrate; an undoped layer disposed above the first barrier layer, wherein the undoped layer has an n-channel device region laterally adjacent to the p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface that is higher than a topmost surface of the p-channel device region of the undoped layer; a second barrier layer, above the n-channel device region of the undoped layer; a first gate electrode disposed above the second barrier layer; as well as A second gate electrode is arranged above the p-channel device region of the undoped layer.

2. The integrated transistor device according to claim 1, further comprising: An isolation region is within the undoped layer and between the first gate electrode and the second gate electrode. 3 . The integrated transistor device of claim 1 , wherein the second barrier layer is thinner than the first barrier layer. The integrated transistor device of claim 1 , wherein the first barrier layer directly contacts the substrate.

5. The integrated transistor device according to claim 1, further comprising: A first doped layer and a second doped layer are arranged above the p-channel device region of the undoped layer and directly contact the p-channel device region of the undoped layer, wherein the second gate electrode is between the first doped layer and the second doped layer.

6. The integrated transistor device according to claim 1, further comprising: a third doping layer, arranged above the second barrier layer and below the first gate electrode; as well as A first contact and a second contact are arranged above the second barrier layer, wherein the third doped layer is between the first contact and the second contact.

7. The integrated transistor device of claim 1, wherein the second barrier layer has a thickness less than 30 nanometers.

8. The integrated transistor device according to claim 1, further comprising: A buffer layer is disposed between the first barrier layer and the substrate, wherein the buffer layer includes the same element as the first barrier layer.

9. The integrated transistor device according to claim 8, further comprising: A third gate electrode is disposed above the second barrier layer and the n-channel device region of the undoped layer, wherein an additional isolation region is between the third gate electrode and the first gate electrode.

10. An integrated transistor device comprising: a first III / V semiconductor layer disposed above the substrate; an undoped binary III / V semiconductor layer disposed above the first III / V semiconductor layer, wherein the undoped binary III / V semiconductor layer has an n-channel device region laterally flanking the p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; a second III / V semiconductor layer disposed above the n-channel device region of the undoped binary III / V semiconductor layer; a doped binary III / V source region and a doped binary III / V drain region disposed above the p-channel device region of the undoped binary III / V semiconductor layer; a first gate electrode disposed over the second III / V semiconductor layer; and A second gate electrode is disposed above the undoped binary III / V semiconductor layer and between the doped binary III / V source region and the doped binary III / V drain region. 11 . The integrated transistor device of claim 10 , wherein a top surface of the first gate electrode is higher than a top surface of the second gate electrode. 12 . The integrated transistor device of claim 10 , wherein an isolation region is disposed between the first gate electrode and the second gate electrode and extends from a top surface of the p-channel device region of the undoped binary III / V semiconductor layer to the first III / V semiconductor layer.

13. The integrated transistor device according to claim 10, further comprising: A doped binary III / V gate region is disposed between the second III / V semiconductor layer and the first gate electrode.

14. The integrated transistor device of claim 13, wherein the doped binary III / V gate region has a doping capacity of less than 10 18 The doping concentration is p-type dopant / cubic centimeter.

15. A method of forming an integrated transistor device, comprising: Depositing a first barrier layer over a substrate, wherein the substrate includes an n-channel device region laterally adjacent to and continuously connected to a p-channel device region; depositing an undoped layer over the first barrier layer; depositing a second barrier layer over the undoped layer; performing a first etching process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein the lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than an uppermost surface of the undoped layer on the n-channel device region of the substrate; selectively forming a doped layer over the lower portion of the undoped layer on the p-channel device region of the substrate; forming a first gate electrode disposed above the second barrier layer; as well as A second gate electrode is formed disposed over the lower portion of the undoped layer.

16. The method of forming an integrated transistor device according to claim 15, further comprising: An isolation process is performed to form an isolation region passing through the undoped layer and between the first gate electrode and the second gate electrode.

17. The method of forming an integrated transistor device according to claim 15, further comprising: A doped gate region is formed above the second barrier layer on the n-channel device region of the substrate, wherein the doped gate region is between the first gate electrode and the second barrier layer.

18. The method of forming an integrated transistor device of claim 17, wherein the doped gate region has a thickness of less than 30 nanometers.

19. The method of forming an integrated transistor device according to claim 15, further comprising: A plurality of buffer layers are formed over the substrate and below the first barrier layer, wherein the plurality of buffer layers and the first barrier layer include a same quaternary III / V semiconductor material.

20. The method of forming an integrated transistor device according to claim 15, further comprising: a first set of contacts formed over the second barrier layer and laterally spaced apart from the first gate electrode; as well as A second set of contacts is formed over the doped layer on the p-channel device region of the substrate, wherein the second gate electrode is between the second set of contacts.

21. An integrated transistor device comprising: A first barrier layer disposed above the substrate; an undoped layer disposed above the first barrier layer, wherein the undoped layer has an n-channel device region laterally lateral to the p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; A second barrier layer, arranged above the n-channel device region of the undoped layer; A doped source region and a doped drain region are arranged above the p-channel device region of the undoped layer; a first gate electrode disposed above the second barrier layer; as well as The second gate electrode is arranged above the undoped layer and between the doped source region and the doped drain region.

22. The integrated transistor device of claim 21, wherein a top surface of the first gate electrode is higher than a top surface of the second gate electrode. 23 . The integrated transistor device of claim 21 , wherein an isolation region is disposed between the first gate electrode and the second gate electrode and extends from a top surface of the p-channel device region of the undoped layer to the first barrier layer.

24. The integrated transistor device of claim 21, wherein the first gate electrode is separated from the second barrier layer by a dielectric structure, and wherein the second gate electrode is separated from the undoped layer by the dielectric structure.

25. The integrated transistor device of claim 21, further comprising: The doped gate region is arranged between the first gate electrode and the second barrier layer.

26. The integrated transistor device of claim 25, wherein the doped gate region has a doping capacity of less than 10 18 The doping concentration is p-type dopant / cubic centimeter.

27. An integrated transistor device comprising: A first barrier layer disposed above the substrate; an undoped layer disposed above the first barrier layer, wherein the undoped layer comprises a first portion and a second portion, the first portion having a first thickness being disposed beside the second portion having a second thickness less than the first thickness; a second barrier layer disposed above the first portion of the undoped layer; a first gate electrode disposed above the second barrier layer; as well as A second gate electrode is disposed above the second portion of the undoped layer.

28. The integrated transistor device of claim 27, wherein a dielectric structure separates the first portion of the undoped layer from the second portion of the undoped layer.

29. The integrated transistor device of claim 27, wherein the first portion of the undoped layer corresponds to an n-channel device region, and wherein the second portion of the undoped layer corresponds to a p-channel device region.

30. The integrated transistor device of claim 27, further comprising: a first contact disposed above the second barrier layer; as well as A second contact is arranged above the second barrier layer, wherein a first gate electrode is arranged between the first contact and the second contact.

31. The integrated transistor device of claim 27, further comprising: a first doped layer disposed above the second portion of the undoped layer, and A second doped layer is disposed above the second portion of the undoped layer, wherein the second gate electrode is between the first doped layer and the second doped layer.

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