Method for operating a memory system, method for operating a host, and computing system

Abstract

Methods for operating a memory system, methods for operating a host, and a computing system are disclosed. The memory system includes a memory device, and the method for operating the memory system includes: storing write data and a physical address received from a host in a buffer in response to a write request from the host; performing a write operation on the memory device based on the write data and the physical address; asynchronously providing error occurrence information to the host based on a write error corresponding to the write data occurring; and providing the host with the write data having the write error and information for recovering from the write error.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0123347, filed with the Korean Intellectual Property Office on Oct. 4, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a memory system, a host, and an operation method of the memory system and the host, and more particularly, to a memory system and a host that recover data having a write error and an operation method of the memory system and the host. Background Art

[0003] A memory system may include a general solid state drive (SSD) including a flash translation layer (FTL) or an open channel SSD not including the FTL. The open channel SSD may not support an address mapping function that maps a logical address to a physical address of a storage device, and thus may allow a host to handle a write error occurring therein. Summary of the Invention

[0004] A memory system, a host, and an operation method of the memory system and the host are provided, in which the memory system generates information for recovering data having a write error, and the host performs recovery based on the generated information, thereby improving reliability and efficiency.

[0005] According to an embodiment, a method of operating a memory system including a memory device includes: storing write data and a physical address received from a host in a buffer in response to a write request of the host; performing a write operation on the memory device based on the write data and the physical address; asynchronously providing error occurrence information to the host based on a write error corresponding to the write data occurring; and providing the host with the write data having the write error and information for recovering from the write error.

[0006] According to an embodiment, a method of operating a host configured to control a memory system includes: sending a first write request to the memory system based on write data and a physical address; asynchronously obtaining error occurrence information about a write error corresponding to the write data occurring in the memory system from the memory system; obtaining the write data having the write error and information for recovering from the write error from the memory system; recovering the write data having the write error based on the write data having the write error and the information for recovering from the write error; and sending a second write request to the memory system based on the recovered write data.

[0007] According to an embodiment, a computing system includes: a memory system including memory devices; and a host configured to send a write request to the memory system based on write data and a physical address, wherein the memory system is configured in response to the host's write request to: store the received write data and physical address from the host in a buffer of the memory system; perform a write operation on the memory devices based on the write data and the physical address; asynchronously provide error occurrence information to the host based on a write error corresponding to the write data occurring; and provide the host with the write data having the write error and information for recovering from the write error, and wherein the host is configured to: recover the write data having the write error based on the write data having the write error and the information for recovering from the write error; and send a second write request to the memory system based on the recovered write data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a computing system according to an embodiment;

[0010] Figure 2 is a block diagram showing an example of a Figure 1 computing system according to an embodiment;

[0011] Figure 3 is a block diagram of a memory system according to an embodiment;

[0012] Figure 4 is a diagram showing a memory controller according to an embodiment;

[0013] Figure 5 is a flowchart of an operation method of a memory system according to an embodiment;

[0014] Figure 6 is a diagram showing an example of information for recovering from a write error according to an embodiment;

[0015] Figure 7 is a flowchart of a recovery method of a host according to an embodiment;

[0016] Figure 8 is a flowchart of a recovery method of a host when multiple write errors occur according to an embodiment;

[0017] Figure 9 is a flowchart of a recovery method of a host when multiple write errors occur according to another embodiment;

[0018] Figure 10 is a flowchart of a recovery operation of a host using metadata according to an embodiment;

[0019] Figure 11 is a conceptual diagram showing various operations of a host and a memory system associated with recovering from a write error in a computing system according to an exemplary embodiment;

[0020] Figure 12 is a block diagram of a computing system including a host memory buffer (HMB) according to an embodiment;

[0021] Figure 13 is a block diagram of a computing system including a controller memory buffer (CMB) according to an embodiment;

[0022] Figure 14 is a block diagram of a computing system using a host-aware performance booster (HPB) according to an embodiment; and

[0023] Figure 15 is a flowchart of a recovery method of a computing system using an HPB according to an embodiment. DETAILED DESCRIPTION

[0024] Figure 1 is a block diagram of an example of a computing system according to an embodiment.

[0025] Referring to Figure 1 , the computing system 1000 may include a memory system 100 and a host 200. The computing system 1000 may be various types of systems in which a memory system 100 storing data is installed. For example, the computing system 1000 may correspond to various types of systems such as a computer, a netbook, a network tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a navigation device, a digital camera, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a virtual reality (VR) device, an augmented reality (AR) device, and the like.

[0026] The memory system 100 may include a memory controller 110 and a memory device 120. The memory system 100 may include one or more storage media. For example, the memory system 100 may include one or more solid state drives (SSDs). Additionally, the memory system 100 may include one or more open-channel SSDs. Here, an open-channel SSD may refer to an SSD that does not include a flash translation layer (FTL). An open-channel SSD may not include an FTL capable of mapping logical addresses provided by the host 200 to physical addresses of the memory device 120, and thus may not directly manage addresses. Accordingly, an open-channel SSD may receive physical addresses rather than logical addresses from the host 200 to perform write / read / erase operations, etc. Additionally, even if an error occurs in the memory device 120, the open-channel SSD may not randomly store the recovered data at another address, and thus may perform a recovery operation through the host 200. According to an embodiment, an open-channel SSD may include mapping information defining a relationship between logical addresses provided by the host 200 and physical addresses of the memory device 120. However, an open-channel SSD may not directly manage addresses by using the mapping information.

[0027] The host 200 may provide an access request for data to the memory system 100. For example, the host 200 may provide a write request or a read request for data to the memory system 100, and the memory system 100 may write data to the memory device 120 or read data from the memory device 120 based on the access request of the host 200 and provide the data to the host 200. Additionally, based on an erase request of the host 200 for data, the memory system 100 may perform an erase operation on the data in a region indicated by the host 200.

[0028] When the memory system 100 is a normal SSD, the host 200 may generally provide an access request to the memory system 100 based on logical addresses. However, when the memory system 100 is an open-channel SSD or the host 200 includes mapping information defining a relationship between logical addresses and physical addresses of the memory device 120, the host 200 may provide an access request to the memory system 100 based on the physical addresses of the memory system 100. For example, the host 200 may determine physical addresses by using the mapping information and provide an access request to the memory system 100 based on the determined physical addresses. Additionally, the memory system 100 may perform a write operation, a read operation, or an erase operation based on the physical addresses received from the host 200.

[0029] The host 200 may include a recovery module 210. The recovery module 210 may be implemented in various types included in the host 200. For example, the recovery module 210 may be hardware (HW), such as a circuit, etc., for performing various types of processing associated with the recovery of data with errors. In an embodiment, the recovery module 210 may be software (SW) including a program, and a processing unit in the host 200 may execute the recovery module 210 loaded into an operation memory to perform various types of processing associated with the recovery of data with errors. Additionally, the recovery module 210 may be a combination of HW and SW.

[0030] The recovery module 210 may support the function of recovering data with errors. As an example, when the memory system 100 detects an error during the process of writing data DATA in response to an access request from the host 200 and sends the written data DATA with a write error and recovery information Info_RCV to the host 200, the recovery module 210 may perform the recovery of the data with errors based on the written data DATA with a write error and the recovery information Info_RCV.

[0031] For example, the host 200 may provide a write request based on a physical address (or a logical address according to an embodiment) determined by using mapping information of the memory system 100 and the write data. The memory system 100 may store the write data and the physical address (or the logical address according to an embodiment) received from the host 200 in a buffer in response to the write request. Additionally, the memory system 100 may perform a write operation on the memory device 120 based on the write data and the physical address (or the logical address according to an embodiment). When a write error occurs during this process, the memory system 100 may notify the host 200 of the occurrence of the write error by providing error occurrence information about the write error to the host 200 in an asynchronous mode. Here, the asynchronous mode may refer to a mode in which the memory system 100 performs a specific operation without a request from the host 200 when a preset event is detected. In addition, the memory system 100 may provide the host 200 with the written data DATA with a write error and the recovery information Info_RCV. Additionally, the recovery module 210 may recover the write data by using the written data DATA with a write error and the recovery information Info_RCV obtained from the memory system 100. Furthermore, the host 200 may generate a new write request based on the write data recovered by the recovery module 210 and provide the write request to the memory system 100.

[0032] According to the above embodiments, even if the memory system 100 is a general SSD that can independently perform recovery from write errors, the memory system 100 can use the host 200 having many operation resources when performing the recovery operation. Therefore, when many other operations are performed in the memory system 100, performance improvement of the memory system 100 can be achieved.

[0033] In addition, even if the memory system 100 is an open-channel SSD that can indirectly manage addresses, randomly store the recovered data at another address, and independently perform recovery from write errors, the memory system 100 can perform the recovery operation through the recovery module 210 of the host 200 that manages the mapping information of the memory system 100. In addition, since the memory system 100 rather than the host 200 generates information for recovery from write errors, the utilization rate of the resources of the host 200 can be increased. Hereinafter, more detailed operations of the memory system 100 as an open-channel SSD will be described.

[0034] Figure 2 is a block diagram showing Figure 1 an example of an embodiment of a computing system.

[0035] Referring to Figure 1 and Figure 2 , the memory system 100 may be an open-channel SSD and may include a buffer 111, and the host 200 may include an FTL 220 and a host buffer 230.

[0036] The FTL 220 of the host 200 may manage the write / read / erase operations of the memory system 100 by using the mapping information of the memory system 100. In addition, the FTL 220 may perform an address mapping function and a garbage collection function of mapping the logical addresses used by the host 200 to the physical addresses of the memory device 120.

[0037] According to an embodiment, a recovery module may be included in the FTL 220. In addition, the FTL 220 may recover from errors occurring in the memory system 100 by using the recovery module while managing the write / read / erase operations of the memory system 100.

[0038] The FTL 220 may be SW, such as firmware, an operating system, or an application driven by a processing unit. In an embodiment, the FTL 220 may be HW, such as a circuit, for performing various types of processing associated with the management of the memory system 100. In an embodiment, the FTL 220 may be a combination of HW and SW.

[0039] The host 200 may convert a logical address into a physical address of the memory device 120 through the FTL 220, and send a write command CMD, write data DATA, and a physical address ADDR to the memory system 100.

[0040] Here, the host 200 may allocate a host buffer 230 to store the write data DATA and the physical address ADDR sent to the memory system 100. The host buffer 230 may temporarily store the write data DATA and the physical address ADDR during the access of the host 200 to the memory system 100.

[0041] In addition, the memory controller 110 may store the received write data DATA and the physical address ADDR in the buffer 111. The buffer 111 may temporarily store the write data DATA and the physical address ADDR received from the host 200 during the execution of the write operation. Further, when the storage of the write data DATA and the physical address ADDR in the buffer 111 is completed, the memory controller 110 may send a response signal RSP to the host 200. Additionally, when the host 200 receives the response signal RSP from the memory system 100, the write data DATA and the physical address ADDR corresponding to the response signal RSP may be released from the host buffer 230.

[0042] Before performing a write operation based on the write data DATA and the physical address ADDR stored in the buffer 111, the memory controller 110 may generate recovery information Info_RCV to prepare for possible subsequent errors. For example, the memory controller 110 may generate an error correction code (ECC) parity based on the received write data DATA, or may generate a recovery parity for multiple write data DATA in the recovery unit according to a redundant array of inexpensive disks (RAID) scheme. The recovery information Info_RCV is not limited to the above examples, and thus, various types of information may be generated.

[0043] In addition, the memory controller 110 may write the write data DATA and the generated parity information to the memory device 120. For example, the memory controller 110 may write the write data DATA and the generated ECC parity and / or recovery parity in the same area or different areas of the memory device 120. Further, the memory controller 110 may generate a directory including physical address information of the area in which the generated parity is stored. Additionally, according to an embodiment, the memory controller 110 may share the generated directory with the host 200.

[0044] In addition, the memory controller 110 may check whether a write error has occurred. For example, the memory controller 110 may program the write data DATA and the generated parity, and perform a program verification to check whether a write error has occurred. In an embodiment, the memory controller 110 may check whether a write error has occurred by randomly generating a read command for reading the write data DATA and checking for error bits in the read data. The method for checking whether a write error has occurred is not limited to the above examples.

[0045] In addition, when a write error occurs, the memory controller 110 may send asynchronous event information (AEI) to the host. Here, the AEI may refer to information that notifies of an error occurring in the memory system 100 in an asynchronous mode. For example, the AEI may include the physical address of the write data DATA having the write error.

[0046] In addition, the memory controller 110 may read the write data DATA having the write error and the information for recovery Info_RCV from the buffer 111 or the memory device 120. Here, the information for recovery Info_RCV may include the ECC parity and / or the recovery parity of the write data DATA having the write error, and may also include the normal data in which the write error has occurred in the recovery unit. An example of this will be described in detail later with reference to Figure 6 In addition, the information for recovery Info_RCV may include metadata. The metadata may include various information for managing the memory system 100. For example, the metadata may include mapping information that defines the relationship between the logical address and the physical address of the memory device 120, physical block information indicating information on pages included in each physical block of the memory device 120, attribute information indicating the validity or invalidity of data, a directory indicating the physical address of the mapping information, physical block information, or parity information stored in the memory device 120, etc. The information for recovery Info_RCV is not limited to the above examples.

[0047] The host 200 may send a request signal REQ for requesting information associated with the error to the memory controller 110. For example, when obtaining the AEI from the memory controller 110, the host 200 may send a request signal REQ for requesting information associated with the error to the memory controller 110. In addition, the memory controller 110 may provide the pre-read write data DATA and the information for recovery Info_RCV to the host 200.

[0048] After receiving a request signal REQ from the host 200, the memory controller 110 may perform a read operation to read the write data DATA and the recovery information Info_RCV. Here, the request signal REQ may be a signal that requests only the information associated with an error. In this case, when the request signal REQ is received, the memory controller 110 may read the write data DATA from the buffer 111 and check the physical address of the recovery information Info_RCV based on the directory information to read the recovery information Info_RCV from the memory device 120. In an embodiment, the request signal REQ may include the physical address of the recovery information Info_RCV. In this case, the memory controller 110 may read the write data DATA from the buffer 111 and read the recovery information Info_RCV from the memory device 120 based on the physical address within the request signal REQ.

[0049] The memory controller 110 may provide the write data DATA and the recovery information Info_RCV when providing the AEI, regardless of whether the request signal REQ is received from the host 200.

[0050] In addition, the host 200 may perform recovery of the write data having a write error through the FTL 220 and the recovery module. For example, the host 200 may recover the write data DATA by using the write data DATA having a write error and the recovery information Info_RCV, determine a new physical address by using the mapping information of the memory system 100, generate a write request based on the new physical address and the recovered write data DATA, and provide the write request to the memory system 100.

[0051] According to the above embodiment, when the response signal RSP is received, the host 200 may release the write data DATA and the physical address ADDR from the host buffer 230, thereby terminating the synchronization associated with the write operation between the host 200 and the memory system 100. The actual write operation of the memory system 100 may be performed separately from the host 200. In addition, when a write error occurs during the actual write operation, the memory system 100 may notify the host 200 of the occurrence of the write error in an asynchronous mode, thereby recovering the write error. Therefore, since the host 200 may not need to allocate the write data DATA and the physical address ADDR to the host buffer 230 until the write operation of the memory system 100 is substantially completed, the utilization rate of the host buffer 230 may be improved. In addition, at the same time, the write error occurring in the memory system 100 may still be recovered by the host 200.

[0052] Figure 3 is a block diagram of a memory system according to an embodiment.

[0053] Referring to Figure 3 , the memory system 100 may include a memory controller 110 and a memory device 120. The memory controller 110 may include a buffer 111 and an error correction module 112, and the memory device 120 may include a memory cell array 121, a voltage generator 122, and a control logic 123.

[0054] The memory controller 110 may control the memory device 120 to write data to the memory device 120, or read or erase the data stored in the memory device 120, in response to a write / read request from the host HOST. Specifically, the memory controller 110 may control write, read, or erase operations with respect to the memory device 120 by providing an address ADDR, a command CMD, or a control signal CTRL to the memory device 120. In addition, data DATA to be written to the memory device 120 and data DATA read from the memory device 120 may be transmitted and received between the memory controller 110 and the memory device 120.

[0055] In addition, according to an embodiment, the memory controller 110 may store received write data and a physical address in the buffer 111 in response to a write request from the host HOST. In addition, the memory controller 110 may perform a write operation on the memory device 120 based on the write data and the physical address stored in the buffer 111. In addition, when the write operation is completed, the memory controller 110 may delete the write data and the physical address stored in the buffer 111. When the write operation fails, the memory controller 110 may retain the write data and the physical address stored in the buffer 111 without deleting them. Before performing the write operation, the memory controller 110 may generate information for recovery by using the error correction module 112 to prepare for possible errors that may occur subsequently. The error correction module 112 may perform ECC encoding based on the write data received from the host HOST. For example, the error correction module 112 may perform an exclusive OR (XOR) operation on the write data to generate an ECC parity check, and send the write data and the generated ECC parity check to the memory device 120.

[0056] In addition, the error correction module 112 may detect error bits in the data received from the memory device 120, and perform an ECC operation to correct the detected error bits. The error correction module 112 may determine whether the number of error bits detected in the received data exceeds the error correction capability of the error correction module 112. When the number of detected error bits exceeds the error correction capability, the error correction module 112 may determine that a read error has occurred.

[0057] In an embodiment, the error correction module 112 may generate a recovery parity for multiple pieces of write data DATA in a recovery unit according to a RAID scheme. In addition, the error correction module 112 may generate an ECC parity for the generated recovery parity. Additionally, the error correction module 112 may send the generated recovery parity or the ECC parity of the recovery parity to the memory device 120. An example of this will be described in detail later with reference to Figure 6 an example that details this.

[0058] The error correction module 112 has been described above as generating an ECC parity or generating a recovery parity according to a RAID scheme. However, the error correction module 112 may include an ECC module that generates an ECC parity and / or a RAID module that generates a recovery parity according to a RAID scheme.

[0059] The memory device 120 may be a non-volatile memory device. The memory cell array 121 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the embodiment is not limited thereto, and the plurality of memory cells included in the memory cell array 121 may be resistive memory cells such as resistive random access memory (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0060] The memory cell array 121 may include a plurality of blocks. In addition, each of the plurality of blocks may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells. In the memory cell array 121, an erase operation of data may be performed in units of blocks, and write and read operations of data may be performed in units of pages. For example, the memory device 120 may perform an erase operation in units of blocks and perform write and read operations in units of pages with reference to an address ADDR provided by the memory controller 110.

[0061] The voltage generator 122 may generate various types of voltages for performing the above-described write / read / erase operations. For example, a write operation of data may be performed by using an incremental step pulse program (ISPP), and the voltage generator 122 may generate a plurality of voltages for the ISPP and provide the plurality of voltages to the memory cell array 121. In addition, the voltage generator 122 may generate a read voltage for a read operation of data and provide the read voltage to the memory cell array 121. Additionally, the voltage generator 122 may generate an erase voltage having a high voltage level for an erase operation and provide the erase voltage to the memory cell array 121.

[0062] The control logic 123 may control the overall operation of the memory device 120 associated with memory operations. For example, the control logic 123 may control the voltage generator 122, and the voltage generator 122 may change the levels of various types of generated voltages under the control of the control logic 123. In addition, the threshold voltage distribution of the memory cells in the memory cell array 121 may be adjusted according to the voltages generated by the voltage generator 122.

[0063] Figure 4 is a diagram showing an example of a memory controller according to an embodiment.

[0064] Referring Figure 3 and Figure 4 , the memory controller 110 may include a buffer 111, an error correction module 112, a processor 113, a host interface 114, and a memory interface 115 that can communicate with each other via a bus 116. The buffer 111 and the error correction module 112 may be substantially the same as those described above with reference to Figure 3 Therefore, redundant descriptions thereof will be omitted.

[0065] The buffer 111 may operate under the control of the processor 113 and may be multiple. The buffer 111 may be a volatile memory such as a dynamic RAM (DRAM) or a static RAM (SRAM), or may be a non-volatile memory such as a PRAM or a flash memory. According to an embodiment, the buffer 111 may temporarily store write data and physical addresses received from the host HOST. The buffer 111 is Figure 4 shown and described as being included in the memory controller 110, but the buffer 111 may be an element separate from the memory controller 110.

[0066] In addition, the memory system 100 according to an embodiment may further include a memory. The memory may be a volatile memory or a non-volatile memory like the buffer 111 and may be used as an operating memory, a buffer memory, a cache memory, etc.

[0067] The error correction module 112 may be HW. In an embodiment, when a HW accelerator is included in the memory controller 110, the HW accelerator may include the error correction module 112 as an accelerator dedicated to XOR operations. The HW accelerator may be various types of accelerators such as a field programmable gate array (FPGA), a massively parallel processor array (MPPA), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a neural processing unit (NPU), a tensor processing unit (TPU), a multi-processor system on chip (MPSoC), etc. However, the embodiment is not limited thereto, and the error correction module 112 may be firmware or SW and may be loaded into the buffer 111 or the memory.

[0068] The processor 113 may include a central processing unit, a microprocessor, etc., and may control the overall operation of the memory controller 110 by executing instructions stored in the buffer 111 or the memory.

[0069] The host interface 114 may provide a physical connection between the host HOST and the memory system 100. For example, the host interface 114 may include various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Compact Flash (CF) card interface, High-Speed Non-Volatile Memory (NVMe), etc.

[0070] In addition, the host interface 114 may send various types of information to the host 200 in an asynchronous mode under the control of the processor 113. For example, the host interface 114 may send various types of information to the host 200 by generating an interrupt in a preset area of the host 200, and the interrupt may be implemented in various ways such as MSI, MSI-X, pin-based, Advanced Error Reporting (AER), etc.

[0071] According to an embodiment, the host interface 114 may receive a write request from the host 200 and send a response signal corresponding to the write request to the host 200. In addition, the host interface 114 may send error occurrence information to the host 200 in an asynchronous mode. For example, the host interface 114 may send an AEI notifying of a write error to the host 200. In addition, the host interface 114 may receive a request signal for requesting information about an error from the host 200 and send the written data with the write error and information for recovery to the host 200. Additionally, the host interface 114 may receive a write request for recovering from the write error from the host 200.

[0072] The memory interface 115 may provide a channel between the memory controller 110 and the memory device 120. For example, commands CMD, addresses ADDR, data DATA, etc. may be sent and received between the memory controller 110 and the memory device 120 through the memory interface 115.

[0073] Figure 5 is a flowchart of an example of an operation method of a memory system according to an embodiment.

[0074] In an embodiment, the term "write data" may correspond to "user data" or "metadata" or any other type of data. Further, the method of operation according to this embodiment may be performed in Figure 1 or Figure 2 the memory system 100. The description above with reference to Figures 1 to 4 may also be applied to this embodiment.

[0075] In operation S11, the memory system may store write data and a physical address received from a host in a buffer in response to a write request from the host. For example, when a write command is received from the host, the memory system may store the received write data and physical address in an area of the buffer allocated for the write operation. Further, the memory system may send a response signal to the host.

[0076] In operation S12, the memory system may perform a write operation based on the write data and the physical address. For example, the memory system may write the write data to an area of the memory device corresponding to the physical address stored in the buffer.

[0077] Before performing the write operation, the memory system may generate information for recovery. For example, the memory system may generate ECC parity by XOR operation based on the received write data, or may generate recovery parity for multiple write data in a recovery unit according to a RAID scheme. The information for recovery is not limited to the above examples, and various types of information may be generated. Further, the memory system may write the write data and the generated parity information. Additionally, the memory system may update metadata such as mapping information, attribute information, etc.

[0078] In operation S13, when a write error occurs, the memory system may provide error occurrence information to the host in an asynchronous mode. For example, when a write error occurs, the memory system may send an AEI, and the AEI may include the physical address of the write data having the write error.

[0079] In operation S14, the memory system may provide the write data having the write error and the information for recovery to the host. For example, the memory system may first read the information for recovering from the write error from the memory device to temporarily store the information in the buffer, and when a request signal is received from the host, the memory system may provide the write data having the write error and the information for recovery stored in the buffer to the host.

[0080] In an embodiment, when a request signal is received from a host, the memory system may read write data with a write error and information for recovery to provide the host with the write data with the write error and the information for recovery. Here, when the physical address of the information for recovery is included in the request signal received from the host, the memory system may read the information for recovery based on the included physical address. In an embodiment, even if the physical address is not received from the host, the memory system may check and read the physical address of the information for recovery with reference to directory information or the like.

[0081] Here, the information for recovery may include the ECC parity of the write data with the write error and / or the recovery parity, and may also include the normal data in which the write error has occurred within the recovery unit. In addition, the information for recovery may also include metadata.

[0082] In addition, when another write request is provided by the host, the memory system may perform a write operation in response to the another write request. Here, the another write request provided by the host may be a request for recovering the data with the write error and rewriting the recovered data to the memory system again.

[0083] Figure 6 is a diagram showing an example of information for recovery according to an embodiment.

[0084] Referring to Figures 1 to 6 , the memory system 100 may receive multiple pieces of write data and multiple physical addresses from the host 200. In addition, the memory system 100 may write the received multiple pieces of write data and the received multiple physical addresses to the memory device 120. Before performing the write operation, the memory system 100 or an error correction module 112 such as Figure 3 may generate information for recovery to prepare for possible errors that may occur subsequently. The operation of generating the information for recovery may be performed by various methods.

[0085] For example, the memory system 100 may perform an XOR operation on the write data DATA to generate ECC parity. Referring to Figure 6 , the memory system 100 may perform an XOR operation on each of the multiple pieces of write data DATA1 to DATA3 to generate corresponding ECC parity. In addition, the memory system 100 may write the ECC parity generated as the information for recovery to the memory device 120 in combination with the write data DATA.

[0086] In addition, the memory system 100 may generate recovery parity for multiple pieces of write data DATA in the recovery unit according to the RAID scheme. Referring to Figure 6, an XOR operation may be performed on multiple pieces of write data DATA1 to DATA3 in the recovery unit to generate a recovery parity. When the memory system 100 generates both an ECC parity and a recovery parity according to a RAID scheme, an ECC parity for the recovery parity may further be generated.

[0087] In addition, the memory system 100 may write the recovery parity generated as information for recovery to the memory device 120. Here, the area where the recovery parity is stored may be different from the area where multiple pieces of write data are stored. Also, when there are multiple pieces of write data in multiple recovery units, the areas where the respective recovery parities of the multiple recovery units are stored may be the same as or different from each other, and this may be determined according to the level of the RAID applied. For example, in the case of RAID4, the recovery parity of each recovery unit may be stored in the same block in the memory device 120, and in the case of RAID5, the recovery parity of each recovery unit may be stored in different blocks in the memory device 120.

[0088] As Figure 6 shown, a write error may occur in the write data DATA2. Since the write data DATA2 is not written to the memory device 120 due to the write error, the memory system 100 may read the write data DATA2 with the write error from the buffer 111 and read the information for recovering the write data DATA2 from the memory device 120. In addition, the memory system 100 may provide the host with the write data DATA2 with the write error and the information for recovery. The information for recovering the write data DATA2 may include the ECC parity of the write data DATA2. In addition, when recovery is performed according to a RAID scheme, the information for recovery may further include the recovery parity of the write data DATA2 and the normal data (e.g., write data DATA1 and DATA3) among the multiple pieces of write data (e.g., DATA1 to DATA3) in the recovery unit to which the write data DATA2 belongs. Also, the information for recovering the write data DATA2 may include mapping information of metadata, and when the write data DATA2 with the write error belongs to the user data area, the write data DATA2 may further include attribute information of the metadata indicating whether the write data DATA2 is valid.

[0089] The host 200 may perform recovery of the write data DATA2 based on the write data DATA2 obtained from the memory system 100 and the information for recovering the write data DATA2. For example, the host 200 may correct the bits with errors based on the write data DATA2 with a write error and the ECC parity. In addition, the host 200 may recover the data with a write error based on the recovery parity and multiple pieces of normal data in the recovery unit. Additionally, the host 200 may further consider metadata to perform the recovery, and the method of performing the recovery by the host 200 is not limited to the above examples.

[0090] With respect to Figure 6 The memory system 100 is shown and described as providing the host 200 with write data DATA2 having a write error. However, the memory system 100 may also not provide the host 200 with write data DATA2 having a write error, but instead provide only the information for recovery to the host. For example, when the memory system 100 generates only recovery parity according to the RAID scheme, the host 200 may recover the write data DATA2 based only on the write data DATA1 and DATA3 that are normal data corresponding to the recovery parity and the write data DATA2 having a write error in the recovery unit.

[0091] Figure 7 is a flowchart of an example of a recovery method of a host according to an embodiment.

[0092] The operation method according to this embodiment may be performed in Figure 1 or Figure 2 the host 200. Hereinafter, Figure 7 the operations shown in Figure 7 at least some of the operations shown may correspond to operations performed in a recovery module in the host.

[0093] In operation S21, the host may send a write request to the memory system based on the write data and the physical address. For example, the host may provide a write request based on the physical address and the write data by using the mapping information of the memory system. In addition, when the host receives a response signal to the provided write request from the memory system, the host may release the write data and the address information corresponding to the write request from a buffer in the host. Thus, the host may improve the utilization rate of the buffer.

[0094] In operation S22, the host may obtain error occurrence information from the memory system in an asynchronous mode. For example, the host may obtain the AEI from the memory system, and the AEI may include the physical address of the write data having a write error.

[0095] In operation S23, the host can obtain the write data with a write error and the information for recovering from the write error from the memory system. For example, when obtaining an AEI, the host can send a signal requesting information associated with the error to the memory system in response to the AEI. In addition, the host can obtain the write data with a write error and the information for recovery from the memory system.

[0096] In an embodiment, when obtaining an AEI, the host can check the operating state of the host and send a request signal when entering the idle state Idle, or send a request signal for requesting information associated with multiple errors when obtaining a preset number of AEIs to obtain the information.

[0097] In an embodiment, the host can check the physical address of the information for recovery based on the physical address of the write data with a write error included in the AEI and the directory information of the memory system, and send a request signal with the checked physical address to the memory system to obtain the information. The method for the host to obtain the write data with a write error and the information for recovery is not limited to the above examples.

[0098] In operation S24, the host can recover the write data with a write error based on the write data with a write error and the information for recovery. Here, the information for recovery can include at least one of the ECC parity of the write data with a write error, the recovery parity, the normal data where the write error occurs in the recovery unit, and the metadata. In addition, the metadata can include mapping information, and when the write data with a write error belongs to the user data area, the metadata can further include attribute information indicating whether the corresponding write data is valid.

[0099] In operation S25, the host can send a second write request to the memory system based on the recovered write data. For example, the host can determine a new physical address by using the mapping information of the memory system, generate a second write request based on the new physical address and the recovered write data, and provide the second write request to the memory system. Additionally, when receiving a response signal to the second write request from the memory system, the host can update the mapping information of the memory system.

[0100] Figure 8 is a flowchart of an example of a recovery method of the host when multiple write errors occur according to an embodiment.

[0101] Figure 8 is a flowchart of an example of a recovery method of the host according to an embodiment. When the host provides multiple write requests and the memory system performs multiple write operations, multiple write errors may occur. Hereinafter, a recovery method of the host when multiple write errors occur will be described. In the description Figure 8When the operations shown in Figure 7 are performed, the detailed description of the operations identical to those in

[0102] In operation S31, the host can obtain multiple error occurrence messages from the memory system. For example, the host can obtain multiple AEIs. In operation S32, the host can input the multiple error occurrence messages into a first-in first-out memory (FIFO) according to the obtained order. For example, the host can input the multiple obtained AEIs into the FIFO in the host according to the obtained order. In an embodiment, the host can input the physical addresses included in the multiple AEIs into the FIFO in the host according to the obtained order. In operation S33, the host can obtain multiple write data with multiple write errors and multiple pieces of information for recovering from the multiple write errors from the memory system.

[0103] In operation S34, the host can respectively recover the multiple write data with write errors according to the input order of the multiple error occurrence messages in the FIFO, and provide a new write request to the memory system. For example, the host can perform the recovery by using the AEI first input into the FIFO or the write data corresponding to the physical address and the information for recovery. In addition, the host can generate a new write request based on the recovered write data and the new physical address, and provide the new write request to the memory system. In addition, the host can repeat the above operations for the write errors input into the FIFO in the following order.

[0104] Figure 9 is a flowchart of an example of a recovery method of the host when multiple write errors occur according to an embodiment.

[0105] Figure 9 is a flowchart of an example of a recovery method of the host according to an embodiment. Hereinafter, another recovery method of the host when multiple write errors occur will be described. When describing Figure 9 the operations shown in Figure 7 and Figure 8 are performed, the detailed description of the operations identical to those in

[0106] In operation S41, the host can obtain multiple error occurrence messages from the memory system. For example, the host can obtain multiple AEIs.

[0107] In operation S42, the host can determine the priority based on the physical addresses included in the multiple error occurrence messages. For example, the host can determine in which area of the storage region of the memory system each of the multiple errors occurs based on the physical addresses included in the multiple AEIs. For example, the host can check whether the multiple errors occur in the user data area or the metadata area of the memory system. In addition, the host can determine the priority based on the area where the error occurs. For example, the host can determine to recover first from the errors occurring in the metadata area. The method for the host to determine the priority based on the physical address is not limited to this.

[0108] In operation S43, the host can obtain multiple pieces of write data each having multiple write errors from the memory system, and multiple pieces of information respectively for recovering from the multiple write errors. In operation S44, the host can recover the multiple pieces of write data having write errors respectively according to the determined priority, and provide a new write request to the memory system. For example, the host can perform the recovery by using the write data corresponding to the errors occurring in the metadata area among the multiple errors and the information for recovery. In addition, the host can generate a new write request based on the recovered write data and the new physical address, and provide the new write request to the memory system. In addition, the host can repeat the above operations for the errors occurring in the user data area.

[0109] With respect to Figure 8 and Figure 9 The host is shown and described as determining the priority based on the order of obtaining the multiple error occurrence messages or the physical addresses included in the multiple error occurrence messages. However, the host can also determine the priority based on the information for recovery.

[0110] Figure 10 is a flowchart showing an example of the recovery operation of the host using metadata according to an embodiment.

[0111] Figure 10 is a flowchart showing an example of the recovery method of the host according to an embodiment. In the embodiment, some of the write data having write errors may not need to be recovered. Hereinafter, the method for the host to determine whether the write data having write errors needs to be recovered will be described. For example, when describing Figure 10 the operations shown, the detailed description of the operations the same as those in Figure 7 will be omitted.

[0112] In operation S51, the host may obtain write data with a write error and information for recovering from the write error from the memory system. In operation S52, the host may check metadata among the information for recovery. For example, the host may check attribute information indicating whether the write data with the write error is valid among various types of information for recovery obtained.

[0113] In operation S53, the host may check whether the write data is valid based on the metadata. When the write data is valid, in operation S54, the host may recover the write data with the write error. In operation S55, the host may send a write request to the memory system based on the recovered write data. When the write data is invalid, in operation S56, the host may determine not to continue recovering the write data with the write error.

[0114] According to the above embodiment, although a write error occurs, the host can be prevented from recovering write data that is invalid for any reason, thereby reducing unnecessary operations of the host.

[0115] Relative to Figure 10 The host is shown and described as obtaining all information for recovering from a write error and checking the metadata. However, the host may first obtain only the metadata of the write data with the write error from the memory system to check whether the write data is valid. For example, the host may first check the metadata of the write data with the write error. If the validity of the write data is confirmed, the host may obtain the ECC parity and / or recovery parity of the write data with the write error from the memory system to perform recovery. However, if the validity of the write data is not confirmed, the host may not obtain further information from the memory system and may not perform a recovery operation.

[0116] Figure 11 is a conceptual diagram showing an example of each operation of a host and a memory system associated with recovering from a write error in a computing system according to an exemplary embodiment.

[0117] The operation method according to this embodiment can be executed in Figure 1 or Figure 2 of the computing system 1000. The above description regarding Figures 1 to 10 can also be applied to this embodiment. The host 200 may include an asynchronous error sender 240 and a write error processor 250, and the asynchronous error sender 240 and / or the write error processor 250 may form part of the recovery module of the host 200. The asynchronous error sender 240 and the write error processor 250 may be HW, may be SW, or may be a combination of HW and SW.

[0118] At operation ①, the memory system 100 may send error occurrence information to the asynchronous error sender 240 of the host 200 in an asynchronous mode. For example, when a write error occurs, the memory system 100 may send error occurrence information or, for example, AEI to the asynchronous error sender 240 of the host 200. Here, the error occurrence information may include an error type indicating that the generated error corresponds to a write error and a physical address of the data having the error.

[0119] In addition, the asynchronous error sender 240 may determine the type of error that occurred in the memory system 100 based on the error occurrence information. Additionally, at operation ②, when the error that occurred in the memory system 100 is a write error, the asynchronous error sender 240 may send the error occurrence information to the write error processor 250 that performs recovery from the write error. According to an embodiment, when the host 200 includes a separate processor such as a read error processor, the asynchronous error sender 240 may send the error occurrence information to the processor corresponding to the error type.

[0120] Furthermore, at operation ③, the write error processor 250 may register the error occurrence information received from the asynchronous error sender 240 in the error handling waiting list 251. When multiple error occurrence messages are sent, the write error processor 250 may register the multiple error occurrence messages in the error handling waiting list 251 according to the order of transmission, or may determine priorities based on the physical addresses of the multiple error occurrence messages to register the multiple error occurrence messages in the error handling waiting list 251.

[0121] In addition, at operation ④, the write error processor 250 may obtain the error occurrence information from the error handling waiting list 251. For example, when a signal indicating that information for recovery is ready is received from the memory system 100, the write error processor 250 may obtain the error occurrence information from the error handling waiting list 251. In an embodiment, the write error processor 250 may obtain the error occurrence information from the error handling waiting list 251 at the time point of performing recovery (e.g., at the time point when the host 200 enters an idle state).

[0122] At operation ⑤, the write error processor 250 may obtain metadata and information for its recovery from the memory system 100 to perform recovery. For example, when the data having a write error is metadata, the write error processor 250 may obtain the metadata having the write error, the ECC parity of the metadata, and / or the recovery parity from the memory system 100 to recover the metadata. In addition, even when the data having a write error is user data, the write error processor 250 may obtain the metadata, the ECC parity of the metadata, and / or the recovery parity. Additionally, the write error processor 250 may recover the user data by using the obtained information.

[0123] At operation ⑥, the write error handler 250 can obtain user data and information for its recovery from the memory system 100 to perform recovery. For example, the write error handler 250 can obtain user data with a write error, the ECC parity of the user data, and / or recovery parity from the memory system 100 to recover the user data. Here, the write error handler 250 can recover the user data by using the previously obtained metadata or the like. For example, the write error handler 250 can check the validity information of the user data included in the metadata and perform recovery when the user data is valid. In an embodiment, the recovery operations ⑤ and ⑥ of the write error handler 250 for the metadata and the user data can be performed sequentially as described above, or can be performed simultaneously.

[0124] In addition, at operation ⑦, the write error handler 250 can determine a new physical address by using the mapping information of the memory system 100, generate a write request based on the new physical address and the recovered write data, and provide the write request to the memory system 100.

[0125] With respect to Figure 11 The host 200 is shown and described as including an error handling wait list 251. However, when the host 200 is capable of simultaneously handling the recovery from multiple write errors, the host 200 can perform recovery without including the error handling wait list 251.

[0126] Figure 12 is a block diagram of a computing system including a host memory buffer (HMB) according to an embodiment.

[0127] Figure 12 A computing system according to an embodiment is shown. Referring to Figure 12 , the computing system 1000' can include a memory system 100' and a host 200'. In addition, the memory system 100' can include a memory controller 110 and a memory device 120, and the host 200' can include an FTL 220 and an HMB 260.

[0128] The HMB 260 can be a buffer memory present in the host 200' and can be the memory to which access to the memory system 100' is allocated. The memory system 100' can directly access and use the HMB 260. The memory system 100' can directly store various types of information associated with write errors occurring in the memory system 100' in the HMB 260. For example, when a write error occurs, the memory system 100' can generate an AEI, store the AEI in the HMB 260, read the write data and the information for recovery, and store the write data and the information in the HMB 260.

[0129] In addition, the host 200' can access the HMB 260 to obtain the AEI, the write data, and the information for recovery. For example, the host 200' can access the HMB 260 at a preset time interval to check for the presence of an AEI, and when it is detected that a write error has occurred in the memory system 100', the host 200' obtains the remaining write data and the information for recovery from the HMB 260 to perform a recovery operation. In an embodiment, when the memory system 100' stores various types of information associated with a write error in the HMB 260 and then sends a return signal indicating the completion of storage to the host 200', the host 200' can directly access the HMB 260 to obtain various types of information associated with the write error and perform a recovery operation.

[0130] Figure 13 is a block diagram of a computing system including a controller memory buffer (CMB) according to an embodiment.

[0131] Figure 13 illustrates a computing system according to a modifiable embodiment. Referring to Figure 13 , the computing system 1000” can include a memory system 100” and a host 200”. In addition, the memory system 100” can include a memory controller 110 and a memory device 120, and the host 200” can include an FTL 220. Additionally, the memory controller 110 can include a CMB 117.

[0132] The CMB 117 can be a buffer memory present in the memory controller 110 and is the memory to which access to the host 200” is allocated. The host 200” can directly access and use the CMB 117. The memory system 100” can store various types of information associated with write errors occurring in the memory system 100” in the CMB 117. For example, when a write error occurs, the memory system 100” can generate an AEI to store the AEI in the CMB 117, and read the write data and the information for recovery to store the write data and the information in the CMB 117.

[0133] In addition, the host 200” can access the CMB 117 to obtain AEI, write data, and information for recovery. For example, the host 200” can access the CMB 117 at a preset time interval to check for the presence of AEI, and when a write error is detected in the memory system 100”, the host 200” obtains the remaining write data and information for recovery from the CMB 117 to perform a recovery operation. In an embodiment, when the memory system 100” can store various types of information associated with the write error in the CMB 117 and then send a return signal indicating the completion of storage to the host 200”, the host 200” can directly access the CMB 117 to obtain various types of information associated with the write error and perform a recovery operation.

[0134] Figure 14 is a block diagram of a computing system using a host-aware performance booster (HPB) according to an embodiment.

[0135] Figure 14 illustrates a computing system according to a modifiable embodiment. Referring to Figure 14 , the computing system 1000”' can include a memory system 100”' and a host 200”'.

[0136] The memory system 100”' can include a memory controller 110 and a memory device 120, and the memory controller 110 can include an FTL 118. In other words, the memory system 100”' can perform an address mapping function through the FTL 118, so that it can correspond to a common SSD.

[0137] Figure 14 The host 200”' applies the HPB scheme and, unlike the Figure 2 host 200, does not include an FTL. Therefore, since the host 200”' can not perform an address mapping function, the host 200”' can not directly determine a physical address to store write data and can send a write request based on a logical address. In other words, the host 200”' can include mapping information 270 of the memory system 100”'. Therefore, the host 200”' can check the physical address corresponding to the logical address based on the mapping information and send a read request based on the checked physical address.

[0138] Hereinafter, a method of a computing system using HPB will be described in detail.

[0139] Figure 15 is a flowchart of a recovery method of a computing system using HPB according to an embodiment.

[0140] The operating method according to this embodiment can be in Figure 14Execute in the computing system 1000. In operation S105, the host 200 can send a write request to the memory system 100. For example, the host 200 can send a write command CMD, write data DATA, and a logical address ADDR. In operation S110, the memory system 100 can store the received write data and logical address in the buffer of the memory system 100.

[0141] In operation S115, the memory system 100 can provide a response signal RSP to the host 200. In operation S120, the host 200 can release the write data and logical address from the host memory. For example, the host 200 can release the write data and logical address corresponding to the response signal among multiple write data and multiple logical addresses stored in the host memory.

[0142] In operation S125, the memory system 100 can generate ECC parity and / or recovery parity based on the write data. In operation S130, the memory system 100 can perform a write operation on the generated parity and write data. For example, the memory system 100 can check the physical address corresponding to the logical address ADDR and perform a write operation in the area corresponding to the physical address.

[0143] In operation S135, when a write error occurs, the memory system 100 can provide an AEI to the host 200. In operation S140, the host 200 can determine whether the error that occurred in the memory system 100 is a write error based on the obtained error occurrence information.

[0144] In operation S145, the memory system 100 can read the write data with the write error and the information for recovery. In operation S150, the host 200 can request information about the error from the memory system 100.

[0145] In an embodiment, the order of operations S145 and S150 can be changed. For example, the host 200 can provide a request signal REQ to the memory system 100, and then the memory system 100 can read the write data with the write error and the information for recovery in response to the request signal REQ. Here, the host 200 can check the physical address of the information for recovery by using the directory information of the memory system 100, and the request signal REQ can include the physical address of the information for recovery. In addition, the memory system 100 can read the write data with the write error from the buffer and read the information for recovery from the memory device 120 based on the physical address included in the request signal REQ.

[0146] In operation S155, the memory system 100''' may provide write data DATA and recovery information Info_RCV to the host 200'''. In operation S160, the host 200''' may recover the write data having a write error. In operation S165, the host 200''' may send a second write request to the memory system 100'''. For example, the host 200''' may send a write command CMD2, the recovered write data DATA2, and a new physical address ADDR2. Further, when receiving a response signal to the second write request from the memory system 100''', the host 200''' may update the mapping information of the memory system 100'''.

[0147] As is conventional in the field of the inventive concept, embodiments are described and illustrated in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, etc.) that may be formed using semiconductor-based manufacturing technology or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, they may be programmed with software (e.g., microcode) to perform the various functions discussed herein, and they may be driven optionally by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Further, without departing from the scope of the inventive concept, each block, unit, and / or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0148] The above embodiments are all exemplary, and thus, the inventive concept is not limited to these embodiments and may be implemented in various other forms. Although the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A method of operating a memory system, the memory system including a memory device, the method comprising: In response to a write request from a host, storing write data and a physical address received from the host in a buffer; Performing a write operation on the memory device based on the write data and the physical address; Asynchronously providing error occurrence information to the host based on a write error corresponding to the write data; And Providing the host with the write data having the write error and information for recovering from the write error, and wherein the error occurrence information is registered by the host in an error handling wait list included in the host.

2. The method according to claim 1, wherein, The step of performing the write operation includes: Generating at least one parity check based on the write data, the at least one parity check including at least one of an error correction code parity check of the write data and a recovery parity check of a plurality of write data in a recovery unit corresponding to the write data; and Writing the write data and the generated at least one parity check.

3. The method according to claim 2, wherein The information for recovering from the write error includes at least one of the at least one parity check, normal data included in the recovery unit, and management information of the memory system.

4. The method according to claim 1, wherein Based on a write error occurring in a data area, the information for recovering from the write error includes metadata corresponding to the write data having the write error.

5. The method according to claim 1, wherein Based on a request for information for recovering from a write error received from the host, providing the host with the write data having the write error and the information for recovering from the write error.

6. The method according to claim 1, wherein, The error occurrence information includes the physical address of the write data having the write error.

7. The method according to claim 1, wherein, The step of providing the host with the write data having the write error and the information for recovering from the write error includes: storing the write data having the write error and the information for recovering from the write error in one of a controller memory buffer included in the memory system and a host memory buffer included in the host.

8. The method according to claim 7, the method further comprising providing a return signal to the host based on the storage.

9. A method of operating a host, the host being configured to control a memory system, the method comprising: Based on write data and a physical address, sending a first write request to the memory system; Asynchronously obtaining error occurrence information about a write error corresponding to the write data occurring in the memory system from the memory system; Obtaining from the memory system the write data having the write error and the information for recovering from the write error; Recovering the write data having the write error based on the write data having the write error and the information for recovering from the write error; And Based on the recovered write data, sending a second write request to the memory system, and The method further comprises: registering the error occurrence information in an error handling wait list included in the host, and obtaining the error occurrence information from the error handling wait list.

10. The method according to claim 9, wherein, The error occurrence information includes the physical address of the write data having the write error.

11. The method according to claim 10, wherein the method further comprises: Based on a plurality of error occurrence information being obtained, the host determines a recovery priority based on the physical addresses included in the plurality of error occurrence information, The step of obtaining write data with write errors and information for recovering from the write errors includes: obtaining multiple pieces of write data with multiple write errors and multiple pieces of information for recovering from the multiple write errors from a memory system, and The step of recovering write data with write errors includes: recovering the multiple pieces of write data with the multiple write errors based on the multiple pieces of information for recovering from the multiple write errors according to a recovery priority.

12. The method according to claim 10, wherein the method further comprises: Based on obtaining multiple pieces of error occurrence information, a host determines a recovery priority based on the obtaining order of the multiple pieces of error occurrence information. The step of obtaining write data with write errors and information for recovering from the write errors includes: obtaining multiple pieces of write data with multiple write errors and multiple pieces of information for recovering from the multiple write errors from a memory system, and The step of recovering write data with write errors includes: recovering the multiple pieces of write data with the multiple write errors based on the multiple pieces of information for recovering from the multiple write errors according to a recovery priority.

13. The method according to claim 9, wherein The information for recovering from a write error includes at least one of an error correction code parity check of write data with a write error, a recovery parity check, normal data in a recovery unit corresponding to the write error, and management information of the memory system.

14. The method according to claim 9, wherein, Based on a write error occurring in a data area, the information for recovering from the write error includes metadata corresponding to the write data with the write error.

15. The method according to claim 14, wherein, The step of recovering write data with write errors includes: determining, by a host, whether to recover write data with a write error based on metadata; and recovering, by the host, the write data with the write error based on the determined result.

16. The method according to claim 15, wherein, The step of determining whether to recover write data with a write error includes: determining whether to recover write data with a write error by using validity information included in the metadata.

17. The method according to claim 9, wherein, The step of obtaining write data with write errors and information for recovering from the write errors includes: accessing a controller memory buffer included in the memory system or accessing a host memory buffer included in the host.

18. The method according to claim 9, wherein The step of sending a second write request to the memory system includes: determining a new physical address based on mapping information of the memory system; and sending a second write request to the memory system based on the new physical address and the recovered write data.

19. A computing system, the computing system comprising: a memory system including a memory device; and a host configured to send a write request to the memory system based on write data and a physical address, wherein the memory system is configured in response to a write request of the host to: store the write data and the physical address received from the host in a buffer of the memory system, perform a write operation on the memory device based on the write data and the physical address, asynchronously provide error occurrence information to the host based on a write error corresponding to the write data, and Provide write data with a write error and information for recovering from the write error to a host, and wherein the host is configured to: Recover the write data with the write error based on the write data with the write error and the information for recovering from the write error, and Send a second write request to the memory system based on the recovered write data, and wherein the host is further configured to: register error occurrence information in an error handling wait list included in the host, and obtain the error occurrence information from the error handling wait list.

20. The computing system according to claim 19, wherein, The memory system is configured to send a response signal to the host based on storing the write data and the physical address in a buffer of the memory system, and wherein the host is further configured to: Allocate multiple write data and multiple physical addresses to a buffer of the host, and Release the write data and the physical address corresponding to the response signal from the buffer of the host based on receiving the response signal from the memory system.

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