Apparatus and method for handling cache maintenance operations

Abstract

Apparatus and methods are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element can be arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requester elements. A given requester element can be arranged to detect when a write request needs to be issued prior to a cache maintenance operation request so as to cause a write operation to be performed for a data item within the specified range of memory addresses, and in that case to generate a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request. A recipient completer element receiving the combined write and cache maintenance operation request can then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the processing of cache maintenance operations, and can provide reduced bandwidth utilisation.

Description

TECHNICAL FIELD

[0001] The present technology relates to apparatuses and methods for processing cache maintenance operations. BACKGROUND

[0002] An apparatus can comprise a plurality of elements, each of which is able to issue requests to access data, which requests typically specify a memory address to identify where that data is stored or is to be stored within a memory. To improve access times, it is known to provide a cache hierarchy comprising a plurality of levels of cache for storing cache copies of data associated with addresses in the memory. Some of the caches in the cache hierarchy can be local caches associated with a particular element, while others can be shared caches accessible to a plurality of elements.

[0003] It is often the case that data written by one element needs to be visible to at least one other element within the apparatus. One way in which this is sought to be achieved is using cache maintenance operations, which can for example be used to evict data that has been written into a cache but is more up to date than the data held in the memory, so that the written data is subsequently pushed down to a lower level in the cache hierarchy. By passing a cache maintenance operation request onto one or more levels of cache in the cache hierarchy, this can be used to push previously written data to a desired point of visibility within the apparatus. The cache maintenance operation can typically specify a range of memory addresses to which the operation is to be performed, and the determined point of visibility can depend on the range of memory addresses of interest, and the particular element that needs to have visibility of that data.

[0004] However, there can be a considerable latency involved in processing cache maintenance operations for pushing written data to a desired point of visibility. In particular, each time it is determined that there is a pending write to an address within the specified address range of the cache maintenance operation when processing the cache maintenance operation, or that data in a cache undergoing the cache maintenance operation needs to be written out to a lower level of the cache hierarchy or memory, then according to known techniques, further processing of the cache maintenance operation needs to wait until the earlier write operation has completed, before the cache maintenance operation can then continue.

[0005] It is desirable to reduce the latency associated with the processing of cache maintenance operations. SUMMARY

[0006] In one example arrangement there is provided an apparatus comprising: a plurality of requestor elements for issuing requests; at least one completer element for processing requests; a cache hierarchy comprising a plurality of levels of cache for storing cached copies of data associated with addresses in a memory; wherein: a given requestor element of the plurality of requestor elements is arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor elements of the plurality of requestor elements; the given requestor element, in response to detecting a need to issue a write request prior to the cache maintenance operation request so as to cause a write operation to be performed on a data item within the specified range of memory addresses, generates a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request; wherein a recipient completer element of the at least one completer element that receives the combined write and cache maintenance operation request is arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete.

[0007] In another example arrangement there is provided a method of processing cache maintenance operations within an apparatus, comprising: providing a plurality of requestor elements for issuing requests, at least one completer element for processing requests, and a cache hierarchy comprising a plurality of levels of cache for storing cached copies of data associated with addresses in a memory; arranging a given requestor element to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor elements of the plurality of requestor elements; in response to detecting a need to issue a write request prior to the cache maintenance operation request so as to cause a write operation to be performed on a data item within the specified range of memory addresses, generating at the given requestor element a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request; and causing a recipient completer element of the at least one completer element that receives the combined write and cache maintenance operation request to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete.

[0008] In a further example arrangement, there is provided an apparatus comprising: a plurality of requestor element devices for issuing requests; at least one completer element device for processing said requests; a cache hierarchy comprising a plurality of levels of cache devices for storing cached copies of data associated with addresses in a memory; wherein: a given requestor element device of said plurality of requestor element devices is arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of said cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor element devices of said plurality of requestor element devices; the given requestor element device, in response to detecting a need to issue a write request prior to said cache maintenance operation request so as to cause a write operation to be performed on a data item within said specified range of memory addresses, is arranged to generate a combined write and cache maintenance operation request to occur in place of said write request and a subsequent cache maintenance operation request; wherein a recipient completer element device of said at least one completer element device that receives said combined write and cache maintenance operation request is arranged to initiate processing of the cache maintenance operation required by said combined write and cache maintenance operation request without waiting for said write operation to complete. BRIEF DESCRIPTION OF DRAWINGS

[0009] The technology will be further described, by way of illustration only, with reference to examples thereof illustrated in the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an apparatus according to one example implementation;

[0011] Figure 2 is a timing diagram illustrating various signals passing between a requestor element and a completer element during processing of a combined write and cache maintenance operation request according to one example implementation;

[0012] Figure 3 is a timing diagram illustrating a sequence of signals that can pass between a master device, an interconnect and a slave device according to a first example scenario, but in which a combined write and cache maintenance operation request of the kind described herein is not used, whereas Figure 4 is an equivalent timing diagram for the same example scenario, but in which a combined write and cache maintenance operation request of the kind described herein is used;

[0013] Figure 5 is a timing diagram illustrating a sequence of signals that can pass between a master device, an interconnect and a slave device according to a second example scenario, but in which a combined write and cache maintenance operation request of the kind described herein is not used, whereas Figure 6is a simultaneous timing diagram of the same example scenario, but in which the combined write and cache maintenance operation request described herein is used;

[0014] Figure 7 is a table illustrating various cases in which the combined write and cache maintenance operation request described herein can be used in one or both of the communication between a master device and an interconnect and between an interconnect and a slave device, according to one example implementation;

[0015] Figure 8 is a flowchart illustrating a process performed in one example implementation; and

[0016] Figure 9 is a flowchart illustrating steps performed in order to determine whether a condition exists for creating a combined write and cache maintenance operation request, according to a particular implementation. DETAILED DESCRIPTION

[0017] According to the techniques described herein, there is provided an apparatus having a plurality of requester elements which can issue requests, and at least one completer element for processing such requests. The requester elements can take a variety of forms, depending on the implementation. They can for example take the form of a master device issuing access requests to a memory, or indeed an intermediate element at an intermediate location within the apparatus, for example within an interconnect for providing a connection between a number of master devices and one or more slave devices. Such an intermediate element can act both as a completer element to process requests from master devices, and as a requester element to issue requests to other downstream elements within the system (downstream elements being elements closer to the memory than the requester element in question). Similarly, the completer elements can take a variety of forms. They can for example be a slave device for processing access requests issued from upstream elements, an example of such a slave device being a memory controller for controlling access to a memory. However, as noted above, the completer elements can also be intermediate elements within the apparatus, for example present within an interconnect for providing a connection between one or more master devices and one or more slave devices.

[0018] The apparatus also provides a cache hierarchy comprising a plurality of levels of cache for storing cached copies of data associated with addresses in the memory.

[0019] One or more of the requestor elements can be able to issue cache maintenance operation (CMO) requests that specify a memory address range and are used to cause a data block associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make the data block visible to one or more other requestor elements of the plurality of requestor elements. The determined visibility point can depend on the memory type of the memory specified by the memory address range and the understanding of the requestor elements that need to have visibility of the data within the memory address range. While in principle the determined visibility point can be specified directly by the cache maintenance operation request, in one example implementation the visibility point is determined based on system knowledge about the memory type and the requestor elements that need to have visibility of the data, and thus the determined visibility point can vary for different cache maintenance operation requests.

[0020] While the memory address range specified by the cache maintenance operation request can vary depending on the implementation, it may, for example, be a memory address range sufficient to identify as much data as a cache line to be stored within a cache line of the cache. Thus, execution of the cache maintenance operation for a particular cache can involve performing a lookup to determine whether the data block identified by the memory address range is stored within the cache, and if so, performing the cache maintenance operation for the identified cache line. This may, for example, cause any data in the cache line that is more up to date than a copy held in the memory to be evicted from the cache. Often, in such a situation, the cache line of data is evicted and thus will be propagated up the cache hierarchy to a lower level or to the memory. During the eviction process, a clean copy of the data can be retained in the cache, or a copy of the data can not be left in the cache (e.g. by invalidating the cache line). The term "evict" will be used herein to cover the situation where data in a given level of cache is pushed from the given level of cache to a lower level in the cache hierarchy or to the memory, whether or not a clean copy is retained in the cache.

[0021] The cache maintenance operation request itself can then be propagated so that the same cache maintenance operation can be performed in any further intermediate levels of the cache until the determined visibility point is reached. The determined visibility point can itself be a level of cache, or can be a location within the system beyond the final level of cache in the cache hierarchy, such as a buffer within the memory controller or indeed the memory itself.

[0022] According to the techniques described herein, a given requestor element that is able to issue such cache maintenance operation requests can be arranged to detect when a write request needs to be issued prior to a cache maintenance operation request in order to cause a write operation to be performed on a data item within a specified memory address range, and in such a case can be arranged to generate a combined write and cache maintenance operation request to issue in place of the write request and the subsequent cache maintenance operation request. There are various scenarios in which it can be determined that it is necessary to initiate a write operation first, before a cache maintenance operation request can be issued. Typically, this forces a write request to be issued and then the issuance of the cache maintenance operation request to be deferred until a completion signal is received for the write request. However, according to the techniques described herein, this potential latency impact on the processing of cache maintenance operations is mitigated by allowing a given requestor element to generate a combined write and cache maintenance operation request, and thus there is no delay in issuing the cache maintenance operation request.

[0023] Depending on the conditions that give rise to the need to perform a write operation, the data item to be written can be a subset of the data in the specified memory address range for the cache maintenance operation, or all of the data in the specified memory address range.

[0024] The recipient completer element that receives the combined write and cache maintenance operation request can be arranged to initiate the processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. In particular, the recipient completer element can be arranged so that it can start processing the required cache maintenance operation on the identified cache lines of the local cache of the recipient completer element while the write operation is still in progress. For example, the recipient completer element can initiate the performance of the required cache maintenance operation on the identified cache lines of the local cache of the recipient completer element before the write data associated with the write operation has been received and processed by the completer element. Indeed, the recipient completer element can be able to undertake all the necessary actions in respect of the local cache lines that are subject to the cache maintenance operation, and the subsequent processing of the write data is constrained to ensure that the write data is not written into the cache lines that are subject to the cache maintenance operation in a manner that is inconsistent with the cache maintenance operation. The cache maintenance operation completion response can thus effectively be issued before the data associated with the write operation has been processed by the recipient completer element. Similarly, the recipient completer element can issue a write completion response for the write operation before it has received the write data, and in particular can issue the write completion response as soon as it has established that any risk checks required to ensure that subsequently received requests specifying the same address as the address associated with the write operation will be arranged to access the write data associated with the write operation.

[0025] Thus, it has been found that the processing of the write and cache maintenance operation requests can generally be performed in parallel, and often the case is that the completion signal for the write operation and the completion signal for the cache maintenance operation can be issued in time relatively close to each other. In any case, since the recipient completer element can initiate processing of the cache maintenance operation without having to wait for the write operation to complete, this avoids the requirement to serialize the requests at the requester element, and in particular avoids the need for the requester element to postpone issuing the cache maintenance operation request until the write completion signal is received. Thus, even if there is some delay required at the recipient completer element before the completion signal for the cache maintenance operation can be issued, this will be a significantly reduced latency compared to the case where the cache maintenance operation request is not issued by the requester element until the preceding write operation has completed.

[0026] As a further benefit, the use of the combined write and cache maintenance operation request reduces the bandwidth utilization in the path provided between the requester element and the completer element, since a single request signal can be issued rather than two separate requests at two different points in time. This can also result in a further bandwidth utilization benefit in processing the response signals issued for the write operation and the cache maintenance operation, since these two operations can be processed in parallel. In particular, it can be possible not only to combine certain response signals issued for the write operation and / or certain response signals issued for the cache maintenance operation, but in fact in some cases it can be possible to combine certain response signals issued for the write operation and the cache maintenance operation, thus resulting in a combined write and CMO response.

[0027] It should also be noted that the use of the combined write and cache maintenance operation request still enables the underlying characteristics of the write operation and the cache maintenance operation to be preserved, since the recipient completer element can still process the write operation and the cache maintenance operation in the standard manner, but by the use of the techniques described herein the execution of the cache maintenance operation can be initiated much more quickly than would otherwise be possible if separate serialized requests issued by the requester element were used.

[0028] In one example implementation, the recipient completer element is arranged to issue a completion signal in processing a request specifying a memory address to indicate that the recipient completer element has taken sufficient steps to ensure that the results of the operations required by the request will be observed by at least a subset of the plurality of requestor elements that issue subsequent requests to the recipient completer element specifying the memory address. The recipient completer element is arranged to issue a write completion signal and a separate cache maintenance operation completion signal to a given requestor element to enable the given requestor element to independently assess the progress of the write operation and cache maintenance operation required by the combined write and cache maintenance operation request. In some instances, the results of the operations required by the request can need to be observed by all requestor elements, but in other instances, not all requestor elements can need to observe the results of the operations, and in these instances, the completion signal can be issued when it can be guaranteed that the results of the operations will be observed by the required requestor elements.

[0029] Since the combined write and cache maintenance operation request effectively specifies the execution of two separate operations via a single request, the recipient completer element can be arranged to issue separate write completion signals and cache maintenance operation completion signals in response to the single combined request. However, it should be noted that in some instances it can be possible to combine the two different completion signals, provided that the combined completion signal can be specified in such a way that it will be understood by a given requestor element to indicate both the completion of the write and the completion of the cache maintenance operation. This can be useful, for example, in situations where the write completion and cache maintenance operation completion both occur at substantially the same time, and so a reduction in bandwidth can be achieved by combining the completion signals without imparting any perceptible delay in issuing either completion signal to the requestor element.

[0030] In one example implementation, the combined write and cache maintenance operation request will have an associated transaction identifier and this transaction identifier is used in the responses returned to the given requestor element to enable the requestor element to match the responses to the initiated request. Thus, in such an implementation, both the write completion signal and the separate cache maintenance operation completion signal can be arranged to use the same transaction identifier as specified in the combined write and cache maintenance operation request.

[0031] In one example implementation, the recipient completer element can be arranged to issue a plurality of signals during the processing of the combined write and cache maintenance operation request. While in some instances it can be that all of these signals are issued to the same upstream element, this can not always be the case, and indeed it can be that certain signals must be issued to a different upstream element than others. In one example implementation, the combined write and cache maintenance operation request can provide a target indication field for determining the target element for each signal.

[0032] As an example, in one implementation the target indication field can indicate when the source element from which the recipient completer element is to obtain the data item associated with the write operation is a different element to the given requester element that generated the combined write and cache maintenance operation request, and in that case the recipient completer element can be arranged to issue a data pull signal directly to that different element to trigger that different element to send the data item to the recipient completer element.

[0033] By providing such a mechanism, this can provide support for direct write transfer within the apparatus when using combined write and cache maintenance operation requests. As a specific example, the given requester element can be a node within an interconnect and the recipient completer element can be a slave node. However, the write data that can be associated with the write operation can still be present at an upstream master device, i.e. upstream of the node that forms the given requester element within the interconnect. In such an instance, the target indication field can be used to indicate to the slave device that it can obtain the write data directly from the master device, and in that instance the slave device can issue a data pull signal directly to the master device. This can result in an improvement in performance by reducing the time taken to obtain the write data from the master device.

[0034] In one example implementation, the different element is the element that issued the initial combined write and cache maintenance operation request to the given requester element, and processing of the initial combined write and cache maintenance operation request by the given requester element results in the given requester element issuing the combined write and cache maintenance operation request to the recipient completer element.

[0035] However, it can not always be the case that the recipient completer element is to be allowed to obtain data directly from the different element that issued the initial combined write and cache maintenance operation request. For example, it can be the case that for at least one class of write operation the apparatus is arranged to prohibit obtaining the data item directly from that different element, and when the combined write and cache maintenance operation request relates to such a write operation the target indication field is set to identify that the data item is to be obtained from the given requester element. Thus, the target indication field can be used to directly control from where the recipient completer element is to obtain the write data.

[0036] However, the target indication field can also be used for other purposes. For example, the target indication field can indicate when the target element of a first signal issued by the recipient completer element during processing of a write operation is different from the target element of a second signal issued by the recipient completer element during processing of a cache maintenance operation. In particular, when processing a request in a standard form that specifies only a single operation associated, it can be predetermined where a response signal needs to be sent. However, a combined write and cache maintenance operation request specifies both a write operation and a separate cache maintenance operation, and it can be that the target of at least one of the response signals issued when the write operation is performed is different from the target of at least one of the response signals issued when the cache maintenance operation is processed. By using the target indication field, this makes it possible for this difference to be identified, enabling the recipient completer element to determine the appropriate target for the various signals it generates during processing of the combined write and cache maintenance operation request.

[0037] As previously mentioned, the determined point of visibility can vary depending on the memory region being accessed and the requester element that needs to have visibility of the data. The cache maintenance operation can also be used to identify that the data should be pushed to a point of persistence within the system, i.e. to identify that the determined point of visibility is a point of persistence. A point of persistence (PoP) is a point at which it is guaranteed that data is retained even if power is removed from the system. In some instances, the point of persistence can be provided with a backup power supply, such that in the event of a loss of power to the system, the backup power supply provides sufficient power for the data stored at the point of persistence to be migrated to non-volatile memory. This can in some instances allow for some level of caching to form the point of persistence, or a write buffer within the memory controller to form the point of persistence. Sometimes, the point of persistence can be specified as a deep point of persistence, which is a point of persistence that will ensure retention of data even if the backup power fails. One example of a deep point of persistence would be non-volatile memory itself.

[0038] When the cache maintenance operation is used to push data to a point of persistence, it can be the case that a persistence signal needs to be issued to identify when a block of data associated with a specified memory address range has reached the point of persistence. This will typically occur at some time after a completion signal has been issued for the cache maintenance operation.

[0039] When attempting to implement such cache maintenance operations that push data to a persistence point and thus where the determined visibility point therein is the persistence point, certain signals that are issued when handling a write operation can need to be issued to a different element than certain signals that are issued when handling a cache maintenance operation. For example, a first signal can be a data pull signal issued by a recipient completer element to attempt to obtain a data item, and a second signal can be a persistence signal issued to identify that a data block associated with a specified memory address range has reached a persistence point, and the targets of these first and second signals can be different. As an example, when a request from a master device is received by a node within an interconnect, which then propagates the request to a slave device, the element from which write data will be obtained can be different than the element to which a persistence signal should be sent. Purely as a specific example, write data can need to be obtained from a node within an interconnect, but the persistence signal should be sent directly back to the original master device. The reverse situation can also apply.

[0040] In one example implementation, at least when handling one of a write operation and a cache maintenance operation, a recipient completer element is arranged to combine a plurality of signals into a single combined signal when the plurality of signals are to be issued to the same target element. Thus, one or more signals generated when handling a write operation can be combined, and similarly one or more signals generated when performing a cache maintenance operation can be combined. As another example, a signal generated when handling a write operation can be combined with a signal generated when handling a cache maintenance operation, thus resulting in a combined write and CMO response signal. By combining signals when possible, this can result in a reduction in bandwidth usage in signal paths within the apparatus, which in turn can increase overall throughput.

[0041] There are various different scenarios that can occur that make it appropriate for a given requester device to determine to issue a combined write and cache maintenance operation request rather than separate write and subsequent cache maintenance operation requests. As one example, a cache maintenance operation request can identify a cache maintenance operation that is also performed by a given requester element for a given level of cache associated with the requester element, and the given requester element can be arranged to detect a need to issue a write request prior to the cache maintenance operation request when the performance of the cache maintenance operation for the given level of cache requires evicting a data item from the given level of cache. Thus, the local performance of the cache maintenance operation itself can cause a situation in which write data needs to be evicted, and thus a need exists for a write request. However, in such instances, by issuing a combined write and cache maintenance operation request latency impacts can be significantly reduced, avoiding the need to serialize the cache maintenance operation request after the write request, and in particular avoiding the need for the given requester element to delay issuance of the cache maintenance operation request until a completion signal is received for the write request.

[0042] As another example, a given requestor element can include a buffer to hold pending write requests from the given requestor element prior to issuance of these pending write requests, and the given requestor element can be arranged to detect a need to issue a write request prior to a cache maintenance operation request when the pending write requests in the buffer are directed to addresses within a specified memory address range targeted by the cache maintenance operation request. Prior to use of the techniques described herein, it would typically be necessary for the pending write requests to be issued first, and the given requestor element would then wait to receive a completion signal for the write operation before the given requestor element can then issue the cache maintenance operation request. However, when the techniques described herein are used, this delay is avoided, as a combined write and cache maintenance operation request can be issued, allowing the recipient completor device to begin processing of the cache maintenance operation without having to wait for the write operation to complete.

[0043] As another example, when a given requestor element detects a need to write a data item to a persistent point, the given requestor element can be arranged to issue a combined write and cache maintenance operation request, such that execution of the cache maintenance operation will cause the data item to be pushed to the persistent point. In particular, when it is determined that it is necessary to write a data item to a persistent point, it is typically not possible for the write request itself to specify that the data needs to be written to the persistent point, but rather a separate cache maintenance operation needs to be performed to achieve this effect. However, when the techniques described herein are used, it is not necessary to defer issuance of the cache maintenance operation request until a completion signal is received for the write, but rather a combined write and cache maintenance operation request can be issued directly from the given requestor element.

[0044] As previously noted, requestor elements and completor elements can take a variety of forms. In one example implementation, a given requestor element is a master device for generating transactions that are processed by an interconnect circuit, which includes a recipient completor element that receives combined write and cache maintenance operation requests issued by the master device.

[0045] In another example implementation, a given requestor element is an intermediate element within an interconnect circuit that acts both as a completor element to perform cache maintenance operations in response to requests from an upstream element, and as a given requestor element to issue combined write and cache maintenance operation requests to a downstream completor element.

[0046] In such an implementation, the request from the upstream element can take a variety of forms. For example, the request can specify only performance of a cache maintenance operation. Alternatively, however, the request from the upstream element can also take the form of a combined write and cache maintenance operation request.

[0047] In one example implementation, when processing a combined write and cache maintenance operation request, the recipient completer element determines whether the cache maintenance operation also needs to be performed by downstream elements in response to determining that the data item needs to be propagated to the downstream elements. In particular, while the write data can need to be propagated to the downstream elements, it can not be necessary to perform the cache maintenance operation beyond the current recipient completer element. For example, the current recipient completer element can be associated with a final level cache in the cache hierarchy, and by performing the cache maintenance operation for that final cache level, it can be determined that the cache maintenance operation does not need to be propagated to downstream elements. However, when the cache maintenance operation specifies a persistence point that is beyond the final level of the cache hierarchy, it can still be necessary to issue the cache maintenance operation to downstream elements.

[0048] As another example, even if the cache maintenance operation is not attempting to push data to a persistence point, in some situations it can be necessary for one of the requestor elements to have visibility of the data to be a requestor element that does not utilize the cache hierarchy, and thus for example can have a path directly to the memory controller beyond the cache hierarchy. In this situation, it can again be necessary to push the cache maintenance operation to the final level of the cache hierarchy in order to ensure that the data reaches the required point of visibility, in this case the memory controller.

[0049] In one example implementation, when it is determined that the cache maintenance operation also needs to be performed by downstream elements, the recipient completer element is arranged to either issue a further combined write and cache maintenance operation request to the downstream elements, or to issue a write request to the downstream elements followed by a subsequent cache maintenance operation request to the downstream elements. Thus, elements in the system that receive a combined write and cache maintenance operation request and determine that both the write and cache maintenance operation need to be propagated to downstream elements have the possibility of either maintaining the combined write and cache maintenance operation request for that onward request to the downstream elements, or splitting the request so that separate write and cache maintenance operation requests are issued to the downstream elements.

[0050] Specific examples will now be described with reference to the accompanying drawings.

[0051] Figure 1is a block diagram of an apparatus according to one example implementation. The apparatus includes a plurality of master devices 10, 20, 30, which are coupled to a slave device 55 via an interconnect 40. The slave device is coupled in this example to a main memory 60. The slave device can take a variety of forms, but for example can be a memory controller. It will be appreciated that a typical system can include more master devices, and indeed can include multiple slave devices. One or more levels of cache can be provided within certain master devices, and indeed one or more levels of cache can be provided within the interconnect. In addition, in some implementations, a certain level of cache can be present outside of the interconnect, for example associated with the slave device.

[0052] In the example shown, the master devices 10, 20 are assumed to be fully coherent master devices, whose caches 15, 25 are coherent with caches at a lower level of the cache hierarchy, for example a system cache 50 provided within the interconnect 40. To maintain this coherence, a cache coherence circuit 45 is provided, which can employ a cache coherence protocol in order to attempt to ensure that each of the fully coherent master devices 10, 20 has a coherent view of data cached within the cache hierarchy. It will be appreciated that a variety of different cache coherence protocols can be used, and the cache coherence circuit can employ a variety of mechanisms to attempt to maintain coherence. For example, the cache coherence circuit 45 can employ a snoop-based cache coherence mechanism, whereby in response to a request from one of the coherent master devices 10, 20, it can issue a snoop request to one or more of the other fully coherent master devices 10, 20 in order to determine whether these other coherent master devices have a cached copy of the data that the requesting coherent master device is attempting to access. Although a fully coherent master device can itself have more than one level of cache, for simplicity, Figure 1 A single level of cache is shown in the example, and thus the fully coherent master device 10 has an associated local cache 15 and the fully coherent master device 20 has a local cache 25. At a lower level in the cache hierarchy, a system cache 50 is provided within the interconnect 40, and the cache coherence circuit 45 ensures coherence between the contents of the various caches 15, 25, 50, such that each fully coherent master device has a coherent view of the data.

[0053] It should be noted that not all master devices need to be fully coherent master devices, and an input / output (I / O) coherent master device 30 is shown as an example. Such an I / O coherent master device can or can not have a local cache, for example Figure 1The cache 35 shown is an example, but if it does have a cache, the contents of cache 35 are not kept consistent by cache coordinating circuitry 45 in the interconnect, and therefore, for example, cache 35 will not be the object of any listening requests from cache coordinating circuitry 45. If data generated by I / O coordinating master 30 is made visible to other devices within the system, software executing on I / O coordinating master 30 will need to write that data out of coordinating master 30, which may, for example, result in a write operation to main memory 60.

[0054] I / O consistency master devices can be used to... Figure 1 The device shown is coupled to an upstream network or upstream component 70. As a specific example, the I / O consistency master 30 could be used to... Figure 1 The device shown is connected to the PCIe interface of the PCIe network that forms the upstream network 70.

[0055] like Figure 1 As shown, when considering a pair of components within the device, the component closer to the memory can be referred to as the downstream component and the component further away from the memory can be referred to as the upstream component. Therefore, the cache coherence circuit 45 is a downstream component when compared with the master devices 10, 20, 30, but an upstream component when considered with respect to the slave device 55.

[0056] During operation, it may be necessary to make certain data items generated by components within the device visible to other components that can request access to that data. To facilitate this, it may be necessary to push the data through the cache hierarchy to a determined visibility point within the device. The determined visibility point may vary depending on the memory region associated with the data of interest and / or the component that requires visibility of that data. For example, the visibility point may be a consistency point or serialization point within the system, which may be, for example, at cache consistency circuitry 45 and the associated system cache 50. While system cache level 50 may provide an appropriate downstream visibility point if all requesting devices that require visibility of the data can access the system cache, it may be necessary for the visibility point to be located further downstream within the device, such as at slave device level 55, if any master device that requires visibility of the data does not use the system cache. This could be, for example, a situation where I / O consistency master device 30 needs visibility of the data of interest but does not access system cache 50, instead bypassing the system cache and accessing main memory 60 directly via slave device 55. The slave device may include some kind of local buffer where write data can be stored before being written to main memory, and in this instance, those write buffers within slave device 55 can be considered as visible points to which write data needs to be pushed.

[0057] There are also instances in which write data needs to be written to a persistent point within the device, so that it can be guaranteed that the data will not be lost if power is removed from the system. While non-volatile memory would be an example of a persistent point, sometimes components further upstream can be arranged to provide a persistent point. For example, a write buffer within the slave device 55 can be provided with backup power sufficient to ensure that in the event of a loss of main power from the system, the backup power will allow any data in the write buffer to be written out to the main memory 60. Similarly, in some instances, the system cache 50 can be provided with such backup power sufficient to ensure that any contents of the system cache can be written out to memory in the event of a power failure. In some instances, a distinction is made between a persistent point and a deep persistent point, a deep persistent point being a persistent point that can ensure data is retained even in the event of a backup power failure. An example of a deep persistent point would be non-volatile memory itself.

[0058] A persistent point can thus be seen as a specific example of a desired visible point, and there will be a variety of situations in which it is necessary for write data to be pushed to a desired visible point. Typically, it is not possible to use the write operation itself to ensure that data is written to a particular visible point within the system. For example, data issued by a master device can be cached within a cache level in the cache hierarchy at a level higher than the level associated with the required visible point. Thus, it is known to use a cache maintenance operation as a mechanism for pushing data to a desired downstream visible point. The cache maintenance operation can be performed for a particular cache level, and then, if that cache level is upstream of the desired visible point, the request to perform the cache maintenance operation can be continued to propagate through the cache hierarchy until the performance of the cache maintenance operation has caused the data to reach the desired visible point. In the case where the desired visible point is a particular level in the cache hierarchy, then it is not necessary to perform the cache maintenance operation beyond that level in the cache hierarchy. However, as noted previously, in some instances, one or more master devices that need to have visibility of the data can not have access to the cache hierarchy, and if this is the case, the cache maintenance operation can need to be continued to propagate beyond the lowest level of the cache hierarchy in order to ensure that the data of interest is pushed to the required visible point. It can also be the case, for example, if the cache maintenance operation is used to push data to a persistent point, where the persistent point is beyond the lowest level in the cache hierarchy.

[0059] If, in performing such a cache maintenance operation (CMO), an in-progress write operation is encountered, or the performance of the cache maintenance operation in a particular cache results in a need to evict data from that cache and thus a need to issue a write request from that cache, then normally the forward propagation of the cache maintenance operation request is necessary to pause at that point until the preceding write request has been processed. In particular, it is normally necessary to wait to receive a completion response regarding the earlier write request before continuing to propagate the cache maintenance operation request to downstream components. This, however, introduces a significant latency problem in the processing of the cache maintenance operation. According to the techniques described herein, this latency problem is mitigated by allowing a requester element within the system to detect a situation in which a write request needs to be issued prior to a cache maintenance operation request, and in that instance to generate a combined write and cache maintenance operation request that can be issued to a recipient completer element within the system for processing. The recipient completer element is then able to initiate processing of the cache maintenance operation without having to wait for the write operation to complete. This can significantly reduce latency when compared to prior art that requires the write operation to be completed prior to the cache maintenance operation request being issued. In addition, by enabling a single request signal to be issued rather than two separate request signals, this approach can reduce bandwidth usage within the system.

[0060] Figure 2 is a timing diagram illustrating the processing of a combined write and CMO request according to one example implementation. As shown, a requester element 100 can wish to communicate with a completer element 105. The requester element can take a variety of forms and thus, for example, can be a master device 10, 20, 30, or some intermediate node between a master device and a slave device, such as a node containing cache coherency circuitry 45. Similarly, the completer element can take a variety of forms and thus, for example, can be a slave device 55, or can be an intermediate node, such as cache coherency circuitry 45.

[0061] As Figure 2As shown by bubble 110, at some point in time, the requester element makes a decision to combine the write request and the CMO request into a single write and CMO request that is propagated to the completer element 105, as indicated by line 115. The completer element 105 then detects the need to perform the write operation and also to perform the CMO operation, and can initiate processing of both operations. While processing the write operation, once the completer element 105 determines that it has sufficient buffer space to receive the write data, it can issue a data pull request 120 to the requester element 100, which then causes the write data to be issued from the requester element to the completer element, as indicated by line 130. In addition, once the completer element has established any required risk checks that will ensure that subsequent requests issued by the requester element to access the same memory address associated with the write operation will be handled by the completer element such that the requester element will access the write data (i.e., the write data that will be provided through path 130), the completer element can issue a write completion signal as indicated by line 125 to identify to the requester element that the write operation is considered to be complete. The requester element 100 needs to wait to receive the write completion signal before it is in a state to issue subsequent requests to the same address.

[0062] As Figure 2 As indicated in the middle, if desired, the data pull and the write completion signal can be combined into a single response signal that is issued from the completer element 105 to the requester element 105, thereby reducing bandwidth usage by avoiding the need to send two separate signals. This can be appropriate, for example, in cases where the completer element has buffer space available to receive the write data at the same time that it has also taken the necessary steps to ensure that the write data will be observable by subsequent requests issued to that completer element specifying the same address.

[0063] While handling the write operation, the completer element 105 can also begin to handle the CMO. Execution of the CMO can involve performing a lookup in any local cache of the completer element to determine whether the data associated with the CMO request is already cached in the local cache and then taking any necessary action with respect to the cache line containing that data in order to implement cache maintenance operations. In much the same way as the write operation is executed, it can also involve setting up an address risk check to ensure that the data of interest will be observable to any subsequent requests issued to the completer element by a requester element that will have visibility of that data. Typically, a CMO request can identify a range of memory addresses that can be a block of data stored within a single cache line, and so a lookup based on that memory address range information can be used to identify whether there is a cache line within the cache that stores the data of interest. The associated write operation can involve a particular portion of that data in that cache line, or can itself involve the entire cache line. It will be seen therefore that the address risk check that needs to be set up in order to issue a write completion signal can be substantially the same as the address risk check that needs to be set up in order to issue a completion signal for a CMO, and so in some instances the completion signal for the CMO can be able to be issued immediately adjacent to the completion signal for the write, e.g. Figure 2 the CMO completion signal indicated by line 135. Indeed, in some instances the CMO completion signal can be able to be issued before the write completion signal, e.g. because the write completion signal can be formatted and sent later.

[0064] However, it is necessary to issue an indication of both the completion of the CMO and the completion of the write operation, as they are substantially two separate operations identified by a single write and CMO request.

[0065] The write and CMO requests passed over path 115 will typically specify a transaction ID, and that transaction ID will be included in the write completion signal on path 125 and the CMO completion signal on path 135 to enable the requester element to match the completion signals to the original request.

[0066] From Figure 2 It will be noted that the CMO completion signal can be issued before the write data is received by the completer element, and the handling of the CMO can begin before the write operation is completed. This gives rise to a significant reduction in latency in the handling of the CMO when compared to the previous scheme in which the write completion signal would have to be received before the CMO request could be issued from the requester element.

[0067] As previously mentioned, the requestor element 100 will need to wait to receive the write completion signal 125 before sending any subsequent requests to the same address. However, the requestor element can or can not need to also wait for the CMO completion request before issuing such subsequent requests to the same address. In some cases, this can not be necessary, and once the write completion signal 125 is received, the requestor element can be able to issue subsequent requests to the same address without waiting to receive the CMO completion signal 135. However, if the CMO is executed as a mechanism for a barrier, then the system can be arranged such that any later requests will not be issued until the CMO completion signal is received. Thus, in general terms, the sending of a subsequent request without waiting for the CMO completion signal depends on the memory properties of the target memory, the architecture implementation, and / or whether there is a barrier following the CMO, or whether the CMO is used as part of a process to complete a barrier sequence at the master device.

[0068] As previously mentioned, in some instances the CMO can be used to push data to a persistence point. In such instances, the CMO request can take the form of a persistent CMO request, and the combined write and CMO request 115 will identify whether the CMO is a persistent CMO or a normal CMO. In the case that the CMO is a persistent CMO, then as indicated by the dashed line 140, the completer element 105 can be arranged to send a persistence signal back to the requestor element once it has confirmed that the data subject to the CMO has been pushed to the persistence point. If desired, the persistence signal can be combined with the CMO completion signal. It will be appreciated that the persistence signal will need to be issued at some point after the write data is received, as this write data will need to be written at the persistence point. The persistence point can be at the completer element 105, or in some instances can be at a component downstream of the completer element 105, in which case there can be a longer delay between the completer element receiving the write data and the completer element issuing the persistence signal on the path 140. However, in some implementations, only a single persistence signal will be issued, and this will be issued from the completer element associated with the persistence point, rather than being routed back through any intervening elements.

[0069] Whilst Figure 2The illustration illustrates the possibility of combining certain write response signals and / or combining certain CMO response signals. However, it should also be noted that by using combined write and CMO request signals, the completer element can process both write operations and CMO in substantially parallel. This allows for the combination of certain write responses with certain CMO responses, resulting in combined write and CMO response signals that can further reduce bandwidth utilization. Therefore, purely as an example, a single combined signal can be generated to indicate write completion and CMO completion (combined write completion and CMO completion signal), write completion, data pull, and CMO completion can be combined into a single signal (combined write completion, data pull, and CMO completion signal), data pull and CMO completion can be combined into a single signal (combined data pull and CMO completion signal), or a continuous signal can be combined with any of the above combinations.

[0070] As previously referenced Figure 1 The system may not consist of only a single requester element and a single completer element, as the request may need to be propagated through multiple elements within the system. Figure 3 The illustration depicts a first example scenario where a request needs to be passed from master device 200 to interconnect 205, and then forwarded to slave device 210. Figure 3 In the example shown, it is assumed that the techniques described in this article are not used, and therefore there is no ability to send combined write and CMO requests.

[0071] In this first example, assume the master device is executing software and at some point executes an instruction to perform a CMO within its local cache. During the execution of the CMO in the local cache, this causes a cache line to be evicted from the cache, and therefore a write request needs to be issued. Thus, a write request is issued as indicated by line 215. The issuance of this write request causes a delay in issuing CMO requests to downstream interconnects, because the master device needs to wait for the write operation to complete before it can issue a CMO request.

[0072] In this example, it is assumed that a combined data pull and completion signal is issued by interconnect 205, as indicated by line 220. In response to the data pull, write data can then be issued to the interconnect, as indicated by line 225, and in response to the completion signal, the master device can now issue a CMO request to push the data to the slave device. It should be noted that, as previously stated, the CMO request itself may not specify where the data needs to be pushed; instead, system information can be used to determine the type of memory region associated with the data, and the requesting element that needs visibility of the data, and this will determine the visibility point to which the data needs to be pushed. However, in this example, it is assumed that the visibility point is the slave device 210.

[0073] exist Figure 3 In the illustrated example, it is assumed that the data is allocated in a cache provided by the interconnect, for example...Figure 1 The system shown, and hence the interconnect, does not issue a write request to the slave 210 at this point in time, or write data.

[0074] However, upon receipt of the CMO request, the interconnect performs a cache maintenance operation in its associated cache, and assume that the performance of this cache maintenance operation causes the eviction of a relevant cache line from the interconnect cache, i.e. the cache line comprising the data that was just written into the cache. As a result, a write request is issued to the slave, as indicated by line 235. This issuance of the write request effectively prevents the ability to issue a CMO request to a downstream slave, as the interconnect needs to wait for the completion of the write operation before it can issue the CMO request.

[0075] Similarly, assume that a combined data pull and completion signal is sent from the slave to the interconnect, as indicated by line 240, which enables the write data to be issued to the slave, as indicated by line 245, and the CMO request to be subsequently issued to the slave, as indicated by line 250.

[0076] The CMO operation will then be processed by the slave, and when the slave has taken the necessary steps, a completion signal can be issued, as indicated by line 255, to indicate that the CMO operation has completed. Once the completion signal has been received by the interconnect, the completion signal can also be sent from the interconnect 205 to the master 200 to indicate the completion of the CMO request issued from the master to the interconnect over line 230.

[0077] In the case where the CMO is a persistent CMO, the slave can be arranged to issue a persistence signal when the data has been written to the persistent point, and in one example implementation this persistence signal can be sent directly back to the master 200, as indicated by line 265.

[0078] If the slave determines that the particular region of memory that the CMO request is directed to is not part of a persistent memory device, the slave can be arranged to send a persistence response without waiting for the data. This is because the persistence response has no functional meaning, but can be required to complete the CMO protocol flow. In this case, the slave can include an indication of the non-existence of the persistent memory in the persistence response.

[0079] From Figure 3 It will be appreciated that there is a delay in both the communication from the master to the interconnect and the communication from the interconnect to the slave, in which the CMO request is issued whilst waiting for the completion of a preceding write operation.

[0080] Figure 4The same example is illustrated, but in a situation where both the master and the interconnect device can issue combined write and CMO requests. Thus, again it is assumed that the master is executing an instruction that causes a CMO to be executed in its local cache, and this again causes data to be evicted from the cache, thus necessitating the issuance of a write request. However, rather than issuing the write request prior to the CMO request, the master 200 decides to issue a combined write and CMO request, as indicated by line 300. The CMO request is to cause the data to be pushed to the desired visibility point, and again it is assumed that the desired visibility point is the slave device 210. When the interconnect 205 receives the combined write and CMO request, it can determine by reference to the system information mentioned earlier that the data of interest needs to be pushed to the slave device, and thus knows at that point that the data will need to be written out to the slave device. Thus, it can issue a combined write and CMO request directly to the slave device 210, as indicated by line 305. This second write and CMO request can include a target indication field, which can be used to identify where various responses that the slave device will issue in processing both the write operation and the CMO should be sent. In particular, it can not be that all response signals need to be sent to the same element. As a specific example related to Figure 4 If the CMO is a persistent CMO, it can be that the persistent signal can be sent back directly to the master 200, but in this example it is assumed that the data pull request needs to be sent back to the interconnect, and not directly to the master.

[0081] Since the interconnect 205 has set the target indication field in this way, it knows that it needs to get the write data itself, and thus can send a data pull request back to the master. In the example shown, the data pull request is again combined with a completion signal, as indicated by line 310, but in this example the completion signal needs to specify that it is a write completion signal, so that the master can distinguish between completion of the write and completion of the CMO.

[0082] In response to the data pull request by line 310, the master 200 can then issue the write data, as indicated by line 315.

[0083] Similarly, at the slave device, the slave device can perform the necessary steps to complete the write operation, and once buffer space is available, it can send a data pull request and a write completion signal back to the interconnect. Again, in this example it is assumed that the two signals are combined into a single data pull and write completion response, as indicated by line 320. Once the data pull request has been received from the slave device 210, and the write data has been received from the master 200, the interconnect 205 can issue the write data to the slave device, as indicated by line 325.

[0084] In addition, as mentioned earlier with respect to Figure 2The slave device 210 can begin processing the CMO upon receiving a combined write and CMO request, without waiting for the write to complete. Thus, as previously discussed... Figure 3 Compared to the previous example, the CMO completion signal can be issued much earlier, such as... Figure 4 As indicated by line 330. Upon receiving a CMO completion signal from the slave device, interconnect 205 can also propagate the CMO completion signal back to the master device, as indicated by line 335. (See earlier reference...) Figure 2 As also discussed, if the CMO is a persistent CMO, a persistent response can be sent back to the master device once the slave device determines that data has been written to the persistent point, as indicated by line 340. However, if the CMO specified by the combined write and CMO request is not a persistent CMO, then a persistent signal will not be required.

[0085] According to Figure 3 and Figure 4 A comparison will make it clear that the use of combined writes and CMO requests can significantly reduce latency when processing CMO operations within such a system. Furthermore, the use of combined writes and CMO requests can significantly reduce bandwidth usage in the signal paths between the master and the interconnect, as well as between the interconnect and the slave devices, thus improving throughput within the system.

[0086] Figure 5 and Figure 6 Another example scenario is illustrated, again initially without combined write and CMO requests, and then with combined write and CMO requests. However, in this example, a scenario is considered where direct write transfers from the master to the slave are allowed. As in the earlier example, it is assumed that the master executes an instruction to perform a CMO in its local cache, causing a cache line to be evicted from that local cache. This causes a write request to be issued, such as... Figure 5 As shown by line 400. In this example, since direct transfer from the master to the slave is permitted, the write request is propagated directly from interconnect 205 to the slave, as shown by line 405. In one example implementation, once the necessary risk checks have been performed as described above, completion of the write can be signaled from the interconnect, as indicated by dashed line 410. However, in an alternative implementation, the completion signal can instead be sent directly from the slave to the master, as indicated by line 415.

[0087] In this implementation, since the write data can be obtained directly from the master device by the slave device, a direct data pull request to the master device is issued by the slave device, as indicated by line 415. This can optionally be combined with a completion signal if the slave device provides a completion signal to the master device, rather than the interconnect 205 providing a completion signal to the master device.

[0088] However, in addition, a completion signal also needs to be sent to the interconnect so that the interconnect knows that the slave has completed the write operation, as indicated by line 420.

[0089] In response to receipt of the data pull request, the master 200 sends a write data directly to the slave, as indicated by line 425. In addition, upon receiving the completion signal regarding the write, the master can then send a CMO request to the interconnect, as indicated by line 430.

[0090] Upon receipt of the CMO request, and once the completion signal has been received from the slave indicating that the slave has completed the write operation, then the interconnect 205 can propagate the CMO request on to the slave, as indicated by line 435.

[0091] Once the CMO has been executed by the slave, a completion signal can be sent back to the interconnect, as indicated by line 440. The interconnect can then send a completion signal back to the master 200, as indicated by line 445, to indicate that the CMO request sent by the master is now complete. As before, if the CMO specifies a persistent CMO, a persistent response can be sent from the slave to the master to identify that the data in the identified cache line has been written to the persistence point.

[0092] Figure 6 is an equal time sequence diagram, but illustrates an example using a combined write and CMO request. Thus, when execution of a CMO in the local cache causes eviction of a cache line, the master 200 decides to send a combined write and CMO request, as indicated by line 500. As with the earlier examples discussed with reference to Figure 4 As with the earlier examples discussed with reference to Figure 4 As also discussed, the combined write and CMO request sent by the interconnect can include a target indication field to provide certain information that can be used by the slave to determine where certain responses generated by the slave should be sent. In this example, the target indication field can be used to identify that direct write transfer is supported, and thus a direct data pull request can be sent to the master 200. The target indication field can also be used to distinguish the target of signals that can be sent when processing the write operation and signals that can be sent when processing the CMO, as the target of these signals can be different depending on whether the write operation is being executed or the CMO is being executed.

[0093] As Figure 6As shown in the example, once the slave has determined that it has buffer space to receive the write data, it sends a data pull request directly back to the master as indicated by line 515. If the slave, rather than the interconnect, also signals the write completion, the slave can send the write completion directly back to the master, and if desired, this write completion can be combined with the data pull signal (as per the example shown in Figure 6

[0094] The slave can perform the cache maintenance operation without waiting for the write operation to complete, and once the slave has taken the necessary steps for the cache maintenance operation, it can send a CMO completion signal back to the interconnect as indicated by line 530.

[0095] The master is arranged to respond to the data pull signal by issuing the write data directly to the slave as indicated by line 525.

[0096] Once the interconnect signals receive the CMO completion signal from the slave, it can send the CMO completion signal back to the master as indicated by line 535.

[0097] As with the other examples, in the case where the CMO is a persistent CMO, a persistence signal can be sent directly from the slave back to the master, where the persistence signal is issued once the slave determines that the write data has been written to the desired persistence point. In the example shown, it is assumed that the slave is the persistence point, and so there is a relatively short delay between receiving the write data and being able to issue the persistence signal. However, if the persistence point is beyond the slave, and so the write data needs to be propagated by the slave to a downstream element, the slave will not be able to issue the persistence signal until it has received confirmation from the downstream element that the data has been written to the persistence point, and so there will be more delay between the slave receiving the write data and the slave being able to issue the persistence signal in this case. Figure 6

[0098] According to a comparison of Figure 5 and Figure 6 it will be seen that by using a combined write and CMO request, a significant reduction in latency can be achieved. In addition, by supporting direct write transfer for the write operation, further performance benefits can be achieved by avoiding the need to route certain signals via intermediate nodes, and instead allowing a single hop data transfer from the master to the slave.

[0099] Figure 7 ​​is a table illustrating various ways in which a combined write and CMO request can be used when considering the communication from the master to the interconnect and the subsequent communication from the interconnect to the slave. Case 1 is shown as used earlier in the discussion Figure 4 and Figure 6 where the master sends a combined write and CMO request to the interconnect and the interconnect also sends a combined write and CMO request to the slave. Cases 2 and 3 illustrate scenarios where the master issues a combined write and CMO request to the interconnect but the interconnect does not issue a combined write and CMO request to the slave. In particular, according to case 2, the interconnect can separate the write request and the CMO request and therefore does not issue a combined write and CMO request. In case 3, the interconnect can decide that it is not necessary to propagate the CMO beyond the interconnect since it is determined that the data will reach the desired visibility point without any need to perform downstream cache maintenance operations. In this instance, it can only issue a write request to the downstream slave.

[0100] Case 4 illustrates another example where a standard CMO request is issued from the master to the interconnect, i.e. where there is no need to send a write request from the master to the interconnect. However, when processing the CMO at the interconnect, the interconnect can determine that it is necessary to issue a write request prior to the CMO request, e.g. because the execution of the CMO at the interconnect causes the cache line to be evicted from the interconnect's cache. In this instance, it can choose to issue a combined write and CMO request from the interconnect to the slave in order to reduce the latency in processing the downstream CMO request.

[0101] As Figure 7 another example not shown in the above table, it is possible that a combined write and CMO request is issued from the master to the interconnect but the interconnect determines that it is not necessary to send any further requests downstream. For example, the interconnect can be able to cache the data in its local cache and this local cache can represent the desired visibility point. Therefore, there is no need to propagate a write operation or a CMO downstream.

[0102] Figure 8is a flowchart illustrating a sequence of steps performed by an apparatus described herein according to one example implementation. At step 600, the requester element determines whether a condition is detected that indicates a write operation and a CMO to the same address are required. If not, normal processing is performed at step 605. However, if the condition is detected at step 600, at step 610 the requester element issues a combined write and CMO request to the recipient element. At step 615, the recipient element processes the write operation and the CMO as separate operations, but can initiate processing of the CMO without waiting for the write operation to complete. The CMO can thus be completed before the write data has been received / processed by the recipient element. In addition, the CMO can be completed before a completion signal is issued for the write operation, provided that the recipient element has established appropriate risk checks to ensure that when the write data is subsequently written, it will not be allocated to the recipient's local cache in a manner that conflicts with the execution of cache maintenance operations.

[0103] The condition can be detected at step 600 for a variety of reasons. Figure 9 is a flowchart illustrating a series of checks that can be performed in order to determine whether the condition exists. At step 650, it is determined whether execution of the CMO in the requester element's local cache causes eviction of a cache line. If so, and the CMO needs to be propagated downstream from the requester element, then the process can proceed to step 665, where the combined condition is determined to exist and thus the requester element can issue a combined write and CMO request.

[0104] If the "NO" path is followed from step 650, it can be determined whether the CMO specifies a memory address for which there is a pending write in the requester element's write buffer. In this condition, it will be necessary to flush the pending write from the buffer in order to send the write request downstream, and again the process can proceed to step 665, where the combined condition is determined to exist.

[0105] If the "NO" path is followed from step 655, at step 660 it can be determined whether the write operation requires data to be pushed to a persistence point. In this latter case, there can be no pending cache maintenance operation, but when it is determined that write data needs to be written to a persistence point, typically the write request itself cannot cause this to happen and a persistence CMO request needs to follow the write request in order for the data to be pushed to the persistence point. In this case, again the process can proceed to step 665, where the combined condition is determined to exist.

[0106] If none of the checks performed at steps 650, 655, 660 result in the combined condition being detected, then the process proceeds to step 670, where the combined condition is determined not to exist, and as Figure 8Normal processing is performed as indicated by step 605.

[0107] The techniques described herein can be used in a variety of different systems. As one specific example use case, the combined write and CMO requests described herein can be used in systems using the Advanced Microcontroller Bus Architecture (AMBA) developed by Arm Limited of Cambridge, United Kingdom, and in particular in systems using the AMBA 5CHI (Coherent Hub Interface) architecture specification. The various types of write operations and cache maintenance operations described in that architecture can be candidates for processing with the combined write and CMO request mechanisms described herein. For example, the techniques can be employed in association with certain CopyBack write operations (caches normally generated write operations) such as WriteBack and WriteClean operations, as well as certain NonCopyBack write operations such as WriteNoSnp and WriteUnique operations. Such write operations can be allowed to be the subject of the combined write and CMO requests of a variety of CMOs, such as CleanShared (persistent) CMOs (where all cache copies are required to be clean (i.e., clean to non-dirty state) and dirty data is written back to memory (or PoP)), as well as CleanInvalid CMOs (where all cache copies are invalidated and dirty data is required to be written back to memory) in some instances.

[0108] The techniques described herein enable a significant reduction in latency of CMO completion by avoiding the need to serialize CMO requests after a write request, and also enable a reduction in bandwidth utilization by enabling the combination of two requests into a single request.

[0109] In this application, the word "configured" is used to mean that an element of a device has a configuration able to perform a defined operation. In this context, a "configuration" refers to a hardware or software arrangement or interconnection that is able to perform the defined operation. For example, a device can have specific hardware able to provide the defined operation, or a processor or other processing device can be programmed to perform the defined operation. "Configured" does not imply that a device element needs to be changed in any way in order to provide the defined operation.

[0110] While the illustrative embodiments of the application have been described with reference to the accompanying drawings detailed description, it is to be understood that the application is not limited to those precise embodiments, and that various changes, additions and modifications can be made without departing from the scope and spirit of the application as defined in the appended claims. For example, features of one claim can be combined with features of another claim while not departing from the scope or spirit of the application.

Claims

1. An apparatus comprising: a plurality of requestor elements to issue requests; at least one completer element to process said requests; a cache hierarchy comprising a plurality of levels of cache to store cached copies of data associated with addresses in a memory; wherein: a given requestor element of said plurality of requestor elements is arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of said cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor elements of said plurality of requestor elements; said given requestor element, in response to detecting a need to issue a write request to cause a write operation to be performed on a data item within the specified range of memory addresses prior to said cache maintenance operation request, generates a combined write and cache maintenance operation request to be issued in place of said write request and the subsequent cache maintenance operation request; wherein a recipient completer element of said at least one completer element that receives said combined write and cache maintenance operation request is arranged to initiate processing of the cache maintenance operation required by said combined write and cache maintenance operation request without waiting for said write operation to complete.

2. The apparatus of claim 1, wherein: said recipient completer element is arranged to issue a completion signal when processing a request specifying a memory address to indicate that said recipient completer element has taken sufficient steps to ensure that the outcome of the operation required by the request will be observed by at least a subset of said plurality of requestor elements that issue subsequent requests specifying that memory address to said recipient completer element; and said recipient completer element is arranged to issue a write completion signal and a separate cache maintenance operation completion signal to said given requestor element to enable said given requestor element to assess the progress of the write operation and the cache maintenance operation required by said combined write and cache maintenance operation request independently.

3. The apparatus of claim 2, wherein, both said write completion signal and said separate cache maintenance operation completion signal use the same transaction identifier specified in said combined write and cache maintenance operation request.

4. The apparatus of claim 1, wherein: said recipient completer element is arranged to issue a plurality of signals during processing of said combined write and cache maintenance operation request; and said combined write and cache maintenance operation request provides a target indication field for determining a target element for each of said signals.

5. The apparatus of claim 4, wherein, said target indication field indicates when a source element from which said recipient completer element is to obtain a data item associated with said write operation is a different element to said given requestor element that generated said combined write and cache maintenance operation request, and in the case that said source element is a different element to said given requestor element, said recipient completer element is arranged to issue a data pull signal directly to said different element to trigger said different element to send said data item to said recipient completer element.

6. The apparatus of claim 5, wherein, The different element is an element that issues an initial combined write and cache maintenance operation request to the given requestor element, and processing of the initial combined write and cache maintenance operation request by the given requestor element results in the given requestor element issuing the combined write and cache maintenance operation request to the recipient completer element.

7. The apparatus of claim 6, wherein, For at least one type of write operation, the apparatus is arranged to inhibit obtaining the data item directly from the different element, and when the combined write and cache maintenance operation request relates to the at least one type of write operation, the target indication field is set to identify that the data item is to be obtained from the given requestor element.

8. The apparatus of claim 4, wherein, The target indication field indicates when the target element of a first signal issued by the recipient completer element during processing of the write operation is different to the target element of a second signal issued by the recipient completer element during processing of the cache maintenance operation.

9. The apparatus of claim 8, wherein, The determined point of visibility is a persistence point, the first signal is a data pull signal issued by the recipient completer element in an attempt to obtain the data item, and the second signal is a persistence signal issued to identify that a data block associated with the specified memory address range has reached the persistence point.

10. The apparatus of claim 4, wherein, At least when processing one of the write operation and the cache maintenance operation, the recipient completer element is arranged to combine a plurality of signals into a single combined signal when the plurality of signals are to be issued to the same target element.

11. The apparatus of claim 10, wherein, The recipient completer element is arranged to include at least one signal associated with the write operation and at least one signal associated with the cache maintenance operation into the single combined signal.

12. The apparatus of claim 1, wherein: The cache maintenance operation request identifies a cache maintenance operation also performed by the given requestor element for a given level of cache associated with the requestor element, and the given requestor element is arranged to detect a need to issue a write request prior to the cache maintenance operation request when performance of the cache maintenance operation for the given level of cache requires eviction of the data item from the given level of cache.

13. The apparatus of claim 1, wherein, The given requestor element includes a buffer to hold pending write requests from the given requestor element prior to issuance of the pending write requests, and the given requestor element is arranged to detect a need to issue a write request prior to the cache maintenance operation request when pending write requests in the buffer are directed to addresses within the specified memory address range of the cache maintenance operation request.

14. The apparatus of claim 1, wherein, When the given requestor element detects a need to write the data item to a persistence point, the given requestor element is arranged to issue the combined write and cache maintenance operation request such that performance of the cache maintenance operation will cause the data item to be pushed to the persistence point.

15. The apparatus of claim 1, wherein, The given requestor element is a master device for generating transactions for processing by an interconnect circuit, the interconnect circuit including the recipient completer element that receives the combined write and cache maintenance operation request issued by the master device.

16. The apparatus of claim 1, wherein, The given requestor element is an intermediate element within the interconnect circuit that acts both as a completer element to perform the cache maintenance operation in response to a request from an upstream element and as the given requestor element to issue the combined write and cache maintenance operation request to a downstream completer element.

17. The apparatus of claim 16, wherein, The request from the upstream element also takes the form of the combined write and cache maintenance operation request.

18. The apparatus of claim 1, wherein, When processing the combined write and cache maintenance operation request, the recipient completer element determines whether the cache maintenance operation also needs to be performed by a downstream element in response to determining that the data item needs to be propagated to the downstream element.

19. The apparatus of claim 18, wherein, On determining that the cache maintenance operation also needs to be performed by the downstream element, the recipient completer element is arranged to issue one of: a further combined write and cache maintenance operation request to the downstream element; a write request to the downstream element followed by a subsequent cache maintenance operation request to the downstream element.

20. A method of processing cache maintenance operations within an apparatus, comprising: providing a plurality of requestor elements to issue requests, at least one completer element to process the requests, and a cache hierarchy comprising a plurality of levels of cache to store cached copies of data associated with addresses in a memory; arranging a given requestor element to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor elements of the plurality of requestor elements; in response to detecting a need to issue a write request prior to the cache maintenance operation request so as to cause a write operation to be performed on a data item within the specified range of memory addresses, generating at the given requestor element a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request; and causing a recipient completer element of the at least one completer element that receives the combined write and cache maintenance operation request to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete.

21. An apparatus, comprising: a plurality of requestor element means for issuing requests; at least one completer element means for processing the requests; a cache hierarchy comprising a plurality of levels of cache means for storing cached copies of data associated with addresses in a memory; wherein: a given requestor element means of the plurality of requestor element means is arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requestor element means of the plurality of requestor element means; said given requestor element device being responsive to detecting a need to cause a write operation to be performed on a data item within the specified range of memory addresses to issue a write request prior to the cache maintenance operation request, to generate a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request; wherein a recipient completer element device among the at least one completer element device that receives the combined write and cache maintenance operation request is arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete.

Images