Display device

Abstract

The present invention relates to a display device. The display device comprises data lines extending in a first direction, scan lines extending in a second direction crossing the first direction, a wiring extending in the second direction, and a bridge for electrically connecting the wiring to the data lines, wherein the wiring comprises a branch protruding from the wiring in the first direction, and the bridge overlaps the branch of the wiring and the data lines.

Description

Technical Field

[0001] An exemplary embodiment relates to a display device. Background Technology

[0002] With the rapid development of display devices for visually representing various electrical signal information, a variety of display devices with excellent characteristics such as thinness, light weight, and low power consumption have been introduced. Furthermore, recently, physical buttons have been removed from the front of display devices, thereby reducing the dead zone of the display device and increasing the area occupied by the display area. Summary of the Invention

[0003] An exemplary embodiment includes a display device in which dead zones are reduced and data signals can be stably transmitted to pixels.

[0004] The technical problems to be solved by the present invention are not limited to those described above, and those skilled in the art will understand other technical problems from the following description.

[0005] Additional features of the invention will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the exemplary embodiments proposed in this invention.

[0006] An exemplary embodiment of the display device includes: a data line extending in a first direction; a scan line extending in a second direction intersecting the first direction; a wiring extending in the second direction, the wiring including a branch protruding from the wiring in the first direction; and a bridge portion for electrically connecting the wiring to the data line, wherein the bridge portion overlaps with the branch of the wiring and the data line.

[0007] In an exemplary embodiment, the bridge portion may include: a first bridge electrode disposed on the lower layer of the data line and at least partially overlapping the data line, and electrically connected to the data line; and a second bridge electrode disposed on the same layer as the data line and at least partially overlapping the branch of the wiring and the first bridge electrode, and electrically connected to the branch of the wiring and the first bridge electrode.

[0008] In an exemplary embodiment, the display device may further include: an inorganic insulating layer between the first bridge electrode and the data line; and an organic insulating layer between the data line and the wiring.

[0009] In an exemplary embodiment, the display device may further include power lines arranged parallel to data lines, and include a first power line and a second power line spaced apart from each other.

[0010] In an exemplary embodiment, the bridge portion may be arranged in the gap between the first power line and the second power line.

[0011] In an exemplary embodiment, power lines may be arranged on the same layer as data lines.

[0012] In an exemplary embodiment, the display device may further include a conductive pattern that electrically connects the first power line to the second power line.

[0013] In an exemplary embodiment, the conductive pattern may be arranged in the same layer as the wiring.

[0014] An exemplary embodiment of the display device includes: a data line extending in a first direction; a scan line extending in a second direction intersecting the first direction; wiring extending parallel to the data line or scan line and including branches protruding in a direction perpendicular to the extension direction; and a bridge portion overlapping a portion of the wiring.

[0015] In an exemplary embodiment, the display device may further include power lines arranged parallel to data lines, and include a first power line and a second power line spaced apart from each other.

[0016] In an exemplary embodiment, the bridge portion may be arranged in the gap between the first power line and the second power line.

[0017] In an exemplary embodiment, power lines may be arranged on the same layer as data lines.

[0018] In an exemplary embodiment, the display device may further include a conductive pattern that electrically connects the first power line to the second power line.

[0019] In an exemplary embodiment, the conductive pattern may be arranged in the same layer as the wiring.

[0020] In an exemplary embodiment, the bridge portion may include: a first bridge electrode disposed on the lower layer of the data line and at least partially overlapping the data line, and insulated from the data line; and a second bridge electrode disposed on the same layer as the data line and at least partially overlapping the first bridge electrode and the wiring, and electrically connected to the first bridge electrode and the wiring.

[0021] In an exemplary embodiment, the display device may further include: an inorganic insulating layer between the first bridge electrode and the data line; and an organic insulating layer between the data line and the wiring.

[0022] In an exemplary embodiment, the display device may include a bridge electrode arranged in the same layer as the data line and at least partially overlapping the wiring, and electrically connected to the wiring.

[0023] In an exemplary embodiment, the display device may further include: an inorganic insulating layer; and an organic insulating layer on the inorganic insulating layer between the wiring and the data line.

[0024] In an exemplary embodiment, the inorganic insulating layer may include at least one of a hole overlapping the data line and a hole overlapping the bridge electrode.

[0025] In an exemplary embodiment, the bridge portion may overlap with a branch protruding from a wiring extending parallel to the scan line or with a wiring extending parallel to the data line. Attached Figure Description

[0026] The above and other features and advantages of exemplary embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 This is a schematic plan view of an exemplary embodiment of the display panel;

[0028] Figure 2 yes Figure 1 A schematic conceptual diagram of region A;

[0029] Figure 3 yes Figure 2 A partially enlarged plan view of region A';

[0030] Figure 4A and Figure 4B This is an equivalent circuit diagram of an exemplary embodiment of a pixel disposed in a display panel;

[0031] Figure 5 This is a partial cross-sectional view of the display panel;

[0032] Figures 6 to 8 This is a schematic plan view of an exemplary embodiment of the first wiring;

[0033] Figure 9 This is a schematic plan view of an exemplary embodiment of the fourth wiring;

[0034] Figure 10A and Figure 10B They are Figure 8 Enlarged plan view and cross-sectional view of the contact portion;

[0035] Figure 11 It's a diagram. Figure 10A and Figure 10B Comparative example diagram of the structure of the contact portion;

[0036] Figure 12 This is a diagram illustrating an exemplary embodiment of the first wiring for each pixel region;

[0037] Figures 13AA to 13AB , Figures 13BA to 13BB , Figures 13CA to 13CB , Figures 13DA to 13DB These are magnified planar and cross-sectional views of the bridge portion in the second pixel region;

[0038] Figure 14 This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the first pixel region;

[0039] Figure 15 It is along Figure 14 Cross-sectional view of the pixel circuit intercepted by lines III-III' and IV-IV';

[0040] Figures 16A to 16E It's a layer-by-layer diagram. Figure 14 A schematic plan view of the components;

[0041] Figure 17 This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the first pixel region;

[0042] Figure 18 It is along Figure 17 Cross-sectional view of the pixel circuit intercepted by lines III-III' and IV-IV';

[0043] Figure 19 This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the second pixel region;

[0044] Figure 20 and Figure 21 It is along Figure 19 A cross-sectional view of the pixel circuit cut by lines V-V' and VI-VI';

[0045] Figure 22 This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the second pixel region;

[0046] Figure 23 It is along Figure 22 Cross-sectional views of the pixel circuits intercepted by lines VII-VII' and VIII-VIII'; and

[0047] Figure 24 This is a schematic plan view of another exemplary embodiment of the display panel. Detailed Implementation

[0048] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, exemplary embodiments are described below only by reference to the accompanying drawings to explain the innovative features described. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the invention, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] In the following description, although terms such as "first," "second," etc., may be used to describe individual elements, these elements are not necessarily limited to these terms. The terms above are used only to distinguish one element from another.

[0050] In the following description, expressions used in the singular form include those used in the plural form, unless they have a distinctly different meaning in the context.

[0051] In the following description, it should be understood that terms such as “comprising,” “having,” and “including” are intended to indicate the presence of features, figures, steps, actions, elements, components, or combinations thereof disclosed in the specification, and are not intended to exclude the possibility that one or more other features, figures, steps, actions, elements, components, or combinations thereof may be present or added.

[0052] In the following description, it should be understood that when an element such as a layer, film, region, or plate is referred to as being “on” another element, the element may be directly on the other element, or an intermediate element may be present on it.

[0053] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily illustrated for ease of explanation, the following exemplary embodiments are not limited thereto.

[0054] The expression "A and / or B" means only A, only B, or both A and B. Conversely, the expression "at least one of A and B" means only A, only B, or both A and B.

[0055] In the following exemplary embodiments, when wiring “extends along a first direction or a second direction”, it may mean that the wiring extends not only in a linear shape but also in a zigzag or curved shape along the first or second direction.

[0056] In the following exemplary embodiments, "plan view of an object" refers to "a view of an object seen from above," and "section view of an object" refers to "a view of an object cut vertically and viewed from the side." In the following exemplary embodiments, when elements "overlap," it can mean that the elements overlap in both the "plan view" and the "section view."

[0057] Hereinafter, the invention will be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention, in which the same reference numerals denote the same or corresponding elements.

[0058] Figure 1 This is a schematic plan view of an exemplary embodiment of the display panel 10. Figure 2 yes Figure 1 A schematic conceptual diagram of region A, and Figure 3 yes Figure 2 A magnified plan view of region A'.

[0059] Reference Figure 1 In an exemplary embodiment, the display device may include a display panel 10 comprising a substrate 100. The display panel 10 may include a display area and a peripheral area disposed outside the display area. The substrate 100 may include a display area DA and a peripheral area PA corresponding to the display area and peripheral area of ​​the display panel 10, respectively.

[0060] The edges of the display area DA can have an overall shape similar to a rectangle or a square. For example... Figure 1 and Figure 2 As shown, the first corner CN1 of the edge of the display area DA can have a rounded shape. Specifically, the display area DA may include a first edge E1 and a second edge E2 facing each other, and a third edge E3 and a fourth edge E4 disposed between the first edge E1 and the second edge E2 and facing each other. The pad area PADA is adjacent to the fourth edge E4 among the first edge E1 to the fourth edge E4. In this case, the rounded first corner CN1 connects the first edge E1 to the fourth edge E4. Similar to the first corner CN1, the second corner CN2 of the edge of the display area DA can also have a rounded shape. The second corner CN2 connects the second edge E2 to the fourth edge E4. Furthermore, other portions of the edge of the display area DA can have a rounded shape.

[0061] The peripheral region PA may surround the display region DA. The peripheral region PA, which does not have pixels PX, may include pad regions PADA for electrically attaching various electronic devices or printed circuit boards, and voltage lines for supplying power to drive display elements may be provided in the peripheral region PA. Multiple pads may be provided in the pad regions PADA and may be electrically connected to data drivers. In an exemplary embodiment, the data driver supplying data signals may be provided, for example, on the film of the pads electrically connected to the pad regions PADA using a chip-on-film (“COF”) method. In another exemplary embodiment, the data driver may be directly disposed on the substrate 100, for example, using a chip-on-glass (“COG”) method or a chip-on-plastic (“COP”) method.

[0062] Figure 1 This is a plan view illustrating the state of substrate 100 during the manufacturing process of a display device. To reduce the size of the peripheral area PA, which is perceived by the user in the final display device or an electronic device including the display device, such as a smartphone, a portion of substrate 100 may be bent.

[0063] like Figure 2 As shown, the peripheral region PA may include a curved region BA, and the curved region BA may be disposed between the pad region PADA and the display region DA. In this case, the substrate 100 may be bent in the curved region BA, and at least a portion of the pad region PADA may overlap with the display region DA. The bending direction is set such that the pad region PADA does not cover the display region DA and is disposed behind the display region DA. Therefore, the user recognizes that the display region DA occupies most of the display device.

[0064] Figure 3 A portion of the first corner CN1 is illustrated. When a user observes the display device or electronic device including the illustrated exemplary embodiment in a normal usage environment, the user recognizes that the display device or electronic device has a circular shape, i.e., a curved shape. However, in an environment where the first corner CN1 is magnified and thus wiring with a width of several micrometers or tens of micrometers can be observed, such as... Figure 3 As shown, the first corner CN1 can have a linear shape that bends several times along a first direction D1 and a second direction D2 intersecting the first direction D1. Even when the first corner CN1 is magnified and the first corner CN1 is as shown... Figure 3When the shape shown has a linear shape with multiple bends, the user can recognize that the first corner CN1 has a circular shape, i.e., a curved shape, in a normal use environment. Therefore, when each of the first corner CN1 and the second corner CN2 has a circular shape, it can include the case where each of the first corner CN1 and the second corner CN2 has a substantially circular shape, and the case where each of the first corner CN1 and the second corner CN2 has a linear shape with multiple bends.

[0065] Multiple pixels PX and signal lines for applying electrical signals to the multiple pixels PX can be set in the display area DA.

[0066] Each of the plurality of pixels PX may include a display element and pixel circuitry for driving the display element. In an exemplary embodiment, the display element may be an organic light-emitting diode, and the pixel circuitry may include, for example, a plurality of transistors and capacitors.

[0067] Signal lines used to apply electrical signals to multiple pixels PX may include multiple scan lines SL, multiple data lines DL, etc. Each of the multiple data lines DL may extend along a first direction D1, and each of the multiple scan lines SL may extend along a second direction D2. The multiple scan lines SL may be arranged in multiple rows and can transmit scan signals to pixels PX, and the multiple data lines DL may be arranged in multiple columns and can transmit data signals to pixels PX. Each of the multiple pixels PX may be connected to at least one corresponding scan line SL and a corresponding data line DL. The data lines DL may be as follows: Figure 3 The diagram includes a first data line DL1 and a second data line DL2. The first data line DL1 can be a data line connected to the first wiring 200 described below. The second data line DL2 can be a data line other than the first data line DL1.

[0068] Furthermore, a first wiring 200 for transmitting electrical signals from the pad area PADA to the signal line connected to the pixel PX can be provided in the display area DA. In an exemplary embodiment, the first wiring 200 may, for example, be connected to a first data line DL1 and can transmit data signals from the pad area PADA to the first data line DL1. The first wiring 200 may be provided in a different layer than the scan line SL and data line DL of the pixel PX.

[0069] The first wiring 200 arranged to the left of the virtual center line CL that substantially passes through the center of the display panel 10 along the second direction D2, and the first wiring 200 arranged to the right of the center line CL, can be substantially symmetrical to each other with respect to the center line CL.

[0070] Each of the first wirings 200 may include a first portion 200a extending along a first direction D1 and a second portion 200b extending along a second direction D2. The first portion 200a and the second portion 200b may be integral with each other. The first portion 200a may extend along the first direction D1 from the fourth edge E4 facing the pad region PADA, away from the pad region PADA. The second portion 200b may be bent at the first portion 200a and may extend along the second direction D2 toward either the first edge E1 or the second edge E2. The first portion 200a may be close to the centerline CL.

[0071] The display area DA can be divided into multiple areas depending on whether the first wiring 200 is provided. In an exemplary embodiment, the display area DA may include a first area S1 where the first wiring 200 is provided and a second area S2 other than the first area S1. The second area S2 may be an area where the first wiring 200 is not provided.

[0072] The first region S1 can be divided into multiple sub-regions along the extension direction of the first wiring 200. In an exemplary embodiment, for example, the first region S1 may include a first sub-region SS1 that provides a first portion 200a of the first wiring 200 and a second sub-region SS2 that provides a second portion 200b. The first sub-region SS1 and the second sub-region SS2 located to the right of the center line CL and the first sub-region SS1 and the second sub-region SS2 located to the left of the center line CL can be substantially symmetrical to each other.

[0073] The second region S2 may include at least one third sub-region SS3 facing the first sub-region SS1 of the first region S1 (the second sub-region SS2 of the first region S1 is between the first sub-region SS1 and the third sub-region SS3) and a fourth sub-region SS4 above the second sub-region SS2.

[0074] Reference Figure 3 Each of the first wirings 200 has a first portion 200a that may be parallel to the second data line DL2 and may partially overlap or be adjacent to the second data line DL2. The first portion 200a of each of the first wirings 200 may extend parallel to the second data line DL2 disposed in one of a plurality of columns. The second portion 200b of each of the first wirings 200 may be parallel to the scan line SL and may partially overlap or be adjacent to the scan line SL. The second portion 200b of each of the first wirings 200 may extend parallel to the scan line SL disposed in one of a plurality of rows.

[0075] like Figure 3 As shown, the second wiring 203 and the third wiring 205 can be further disposed in the peripheral area PA.

[0076] One end of each of the first wirings 200 can be connected to the first data line DL1, and the other end of each of the first wirings 200 can be connected to the second wiring 203. The second portion 200b of the first wiring 200 can be electrically connected to the first data line DL1 at the contact portion CNT.

[0077] One end of the second wiring 203 can be connected to the other end of the first wiring 200, and the other end of the second wiring 203 can be connected to the pads of the pad area PADA. In an exemplary embodiment, the second wiring 203 may be a portion of the first portion 200a of the first wiring 200 extending into the peripheral area PA. In another exemplary embodiment, the second wiring 203, as a discrete wiring disposed on a different layer from the first wiring 200, may be electrically connected in the peripheral area PA to the first portion 200a of the first wiring 200.

[0078] One end of the third wiring 205 can be connected to the second data line DL2, and the other end of the third wiring 205 can be connected to the pads of the pad area PADA. In an exemplary embodiment, the third wiring 205 may be a portion of the second data line DL2 extending into the peripheral area PA. In another exemplary embodiment, the third wiring 205, as a discrete wiring disposed on a different layer from the second data line DL2, may be electrically connected to the second data line DL2 in the peripheral area PA.

[0079] Figure 4A and Figure 4B This is an equivalent circuit diagram of an exemplary embodiment of a pixel disposed in the display panel 10.

[0080] Reference Figure 4A A pixel PX includes a pixel circuit PC and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel PX can emit light, such as red, green, blue, or white light, from the OLED. The first transistor T1 and the second transistor T2 may be implemented as thin-film transistors.

[0081] A second transistor T2, acting as a switching transistor, can be connected to the scan line SL and the data line DL, and can transmit the data signal input from the data line DL to the first transistor T1 according to the switching voltage input from the scan line SL. A capacitor Cst can be connected to the second transistor T2 and the power voltage line PL, and can store a voltage corresponding to the difference between the voltage corresponding to the data signal received from the second transistor T2 and the first power voltage ELVDD supplied to the power voltage line PL. The power voltage line PL can be spaced apart from the scan line SL or the data line DL and parallel to the scan line SL or the data line DL.

[0082] The first transistor T1, acting as the driving transistor, can be connected to the power voltage line PL and the capacitor Cst, and can control the driving current flowing through the organic light-emitting diode (OLED) from the power voltage line PL in response to the value of the voltage stored in the capacitor Cst. The OLED may include a pixel electrode and a counter electrode, and the counter electrode can receive a second power voltage ELVSS. The OLED receives a driving current I from the first transistor T1. oled It emits light to display images.

[0083] Figure 4A The illustration shows a pixel circuit PC comprising two transistors and one capacitor. In another exemplary embodiment, the number of transistors and the number of capacitors can be modified in various ways depending on the design of the pixel circuit PC.

[0084] Reference Figure 4B Each pixel PX is connected to a signal line (first scan line SL1, second scan line SL2, transmit control line ECL, and data line DL), an initialization voltage line VIL, and a power voltage line PL. In another exemplary embodiment, at least one of the signal lines (first scan line SL1, second scan line SL2, transmit control line ECL, and data line DL), the initialization voltage line VIL, and / or the power voltage line PL may be shared by adjacent pixels.

[0085] The signal lines include a first scan line SL1 for transmitting a first scan signal GW, a second scan line SL2 for transmitting a second scan signal GI, a transmit control line ECL for transmitting a transmit control signal EM, and a data line DL that crosses the first scan line SL1 and transmits a data signal DATA. The second scan line SL2 can be connected to the first scan line SL1 in the next or previous row, and the second scan signal GI can be the first scan signal GW in the next or previous row.

[0086] The power voltage line PL transmits the first power voltage ELVDD to the first transistor T1, and the initialization voltage line VIL transmits the initialization voltage VINT for initializing the first transistor T1 and the organic light-emitting diode OLED to the pixel PX.

[0087] The first scan line SL1, the second scan line SL2, the transmit control line ECL, and the initialization voltage line VIL can extend along the second direction D2 and can be spaced apart from each other in each row. The data line DL and the power voltage line PL can extend along the first direction D1 and can be spaced apart from each other in each column.

[0088] The pixel circuit PC of pixel PX may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. The first transistor T1 to the seventh transistor T7 may be implemented as thin-film transistors.

[0089] The first transistor T1 is connected to the power voltage line PL via the fifth transistor T5, and is electrically connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1, acting as the driving transistor, receives the data signal DATA according to the switching operation of the second transistor T2 to drive the current I. oled It is supplied to organic light-emitting diodes (OLEDs).

[0090] The second transistor T2 is connected to the first scan line SL1 and the data line DL, and is turned on according to the first scan signal GW received through the first scan line SL1 to perform a switching operation to send the data signal DATA sent to the data line DL to node N.

[0091] The third transistor T3 is connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The third transistor T3 is turned on according to the first scan signal GW received through the first scan line SL1 to connect the first transistor T1.

[0092] The fourth transistor T4 is turned on according to the second scan signal GI received through the second scan line SL2 to initialize the gate voltage of the first transistor T1 by sending the initialization voltage VINT from the initialization voltage line VIL to the gate electrode of the first transistor T1.

[0093] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the transmit control signal EM received through the transmit control line ECL, so as to form a current path and drive the current I. oled Current can flow from the power voltage line PL to the organic light-emitting diode (OLED) through this current path.

[0094] The seventh transistor T7 is turned on according to the second scan signal GI received via the second scan line SL2 to initialize the organic light-emitting diode OLED by sending the initialization voltage VINT from the initialization voltage line VIL to the organic light-emitting diode OLED. In another exemplary embodiment, the seventh transistor T7 may be omitted.

[0095] Figure 4B The illustration shows a fourth transistor T4 and a seventh transistor T7 connected to a second scan line SL2. In another exemplary embodiment, the fourth transistor T4 may be connected to the second scan line SL2, and the seventh transistor T7 may be connected to a discrete wiring and driven according to a signal transmitted to the wiring.

[0096] The capacitor Cst can be connected to the gate electrode of the first transistor T1 and the power voltage line PL, and can store and maintain a voltage corresponding to the difference between the voltages at its two ends, thereby maintaining the voltage applied to the gate electrode of the first transistor T1.

[0097] An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode, and the counter electrode may receive a second electrical voltage ELVSS. The OLED may receive a drive current I from a first transistor T1. oled It also emits light to display images.

[0098] Figure 5 This is a partial cross-sectional view of an exemplary embodiment of the display panel 10. Figure 5 The illustration shows the stacking relationship between the components included in a pixel arranged in the display area of ​​the substrate 100 and the wiring connected to the pixel.

[0099] Substrate 100 may comprise any of a variety of materials such as glass, metal, or plastic. In an exemplary embodiment, substrate 100 may be a flexible substrate and may include, for example, a polymer resin such as polyethersulfone (“PES”), polyacrylate, polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyaryl compound (“PAR”), polyimide (“PI”), polycarbonate (“PC”), or cellulose acetate propionate (“CAP”). Substrate 100 may have a multilayer structure comprising a layer containing the aforementioned polymer resin and an inorganic layer (not shown). Buffer layer 110 may be disposed on substrate 100.

[0100] The buffer layer 110 may have a single-layer or multi-layer structure comprising an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. A barrier layer (not shown) for preventing external air ingress may be further provided between the substrate 100 and the buffer layer 110. In another exemplary embodiment, the buffer layer 110 may be omitted.

[0101] A thin-film transistor (TFT) can be disposed on the buffer layer 110. The TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0102] The semiconductor layer Act may include amorphous silicon, polycrystalline silicon, or organic semiconductor materials. The semiconductor layer Act may include a source region, a drain region, and a channel region between the source and drain regions. A first insulating layer 111 may be disposed on the semiconductor layer Act.

[0103] The gate electrode GE can have a single-layer or multi-layer structure comprising at least one material selected from materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), taking into account adhesion to adjacent layers, surface flatness of layers to be stacked on top, and processing performance. A second insulating layer 112 can be disposed on the gate electrode GE.

[0104] The source electrode SE and drain electrode DE can have a single-layer or multi-layer structure comprising at least one material selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The source electrode SE and drain electrode DE can be electrically connected to the source and drain regions of the semiconductor layer Act, respectively, through contact holes defined in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0105] The capacitor Cst includes a lower electrode LE and an upper electrode UE that overlap each other, with a second insulating layer 112 between the lower electrode LE and the upper electrode UE. The capacitor Cst can be overlapped with a thin-film transistor (TFT). Figure 5 The illustration shows that the gate electrode GE of the thin-film transistor TFT is the lower electrode LE of the capacitor Cst. In another exemplary embodiment, the capacitor Cst may not overlap with the thin-film transistor TFT, and the lower electrode LE of the capacitor Cst may be a separate element from the gate electrode GE of the thin-film transistor TFT. The upper electrode UE of the capacitor Cst may have a single-layer or multi-layer structure comprising at least one material selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The capacitor Cst may be covered by a third insulating layer 113.

[0106] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0107] Various conductive layers may be further disposed on the third insulating layer 113. In an exemplary embodiment, the data line DL and the power voltage line PL may, for example, be disposed on the third insulating layer 113, i.e., in the same layer as the source electrode SE and the drain electrode DE. Each of the data line DL and the power voltage line PL may include Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. In an exemplary embodiment, each of the data line DL and the power voltage line PL may have a multi-layer structure including Ti / Al / Ti.

[0108] The fourth insulating layer 114 can be provided on the data line DL and the power line PL.

[0109] The first wiring 200 may be disposed on the fourth insulating layer 114. The first wiring 200 may have a single-layer or multi-layer structure including at least one of Mo, Al, Cu, Ti and their alloys. In an exemplary embodiment, the first wiring 200 may have a multi-layer structure including Ti / Al / Ti.

[0110] The connection member 150 for electrically connecting a thin-film transistor (TFT) to an organic light-emitting diode (OLED) may be further disposed on a fourth insulating layer 114. The connection member 150 may have a single-layer or multi-layer structure comprising at least one of Mo, Al, Cu, Ti, and alloys thereof. In an exemplary embodiment, the connection member 150 may have a multi-layer structure comprising Ti / Al / Ti.

[0111] The fifth insulating layer 115 may be disposed on the first wiring 200 and the connecting member 150.

[0112] Each of the fourth insulating layer 114 and the fifth insulating layer 115, which serves as a planarization insulating layer, may be an organic insulating layer. Each of the fourth insulating layer 114 and the fifth insulating layer 115 may include an organic insulating material, such as a general-purpose polymer (e.g., polymethyl methacrylate (“PMMA” or polystyrene (“PS”)), a polymer derivative having phenolic groups, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. In an exemplary embodiment, each of the fourth insulating layer 114 and the fifth insulating layer 115 may include polyimide (“PI”).

[0113] An organic light-emitting diode (OLED) as a display element can be disposed on a fifth insulating layer 115. An OLED may include a pixel electrode (PE), an intermediate layer (EL), and a counter electrode (CE).

[0114] The pixel electrode PE may be disposed on the fifth insulating layer 115 and may include a conductive oxide, such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (“ZnO”), indium oxide (“In2O3”), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). In another exemplary embodiment, the pixel electrode PE may include a reflective film comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or combinations thereof. In another exemplary embodiment, the pixel electrode PE may further include a film comprising ITO, IZO, ZnO, or In2O3 above / below the reflective film. The pixel electrode PE may be electrically connected to the source electrode SE or drain electrode DE of the thin-film transistor TFT via a connection member 150 on the fourth insulating layer 114.

[0115] A sixth insulating layer 116 may be disposed on the fifth insulating layer 115. The sixth insulating layer 116 may serve as a pixel defining layer by defining an opening, or opening OP, corresponding to each pixel, through which a portion of the pixel electrode PE is exposed. The sixth insulating layer 116 may include organic materials such as acrylic resin, benzocyclobutene (“BCB”), PI, or hexamethyldisiloxane (“HMDSO”). In an alternative exemplary embodiment, the sixth insulating layer 116 may include the above-mentioned inorganic materials.

[0116] An intermediate layer EL may be disposed on the pixel electrode PE exposed by the opening OP of the sixth insulating layer 116. The intermediate layer EL includes an emitting layer. The emitting layer may include a polymeric organic material or a low molecular weight organic material that emits light of a predetermined color. In an exemplary embodiment, the emitting layer may be, for example, a red emitting layer, a green emitting layer, or a blue emitting layer. In an alternative exemplary embodiment, the emitting layer may have a multilayer structure in which red, green, and blue emitting layers are stacked to emit white light, or it may have a single-layer structure including red, green, and blue emitting materials. In an exemplary embodiment, the intermediate layer EL may include a first functional layer disposed below the emitting layer and / or a second functional layer disposed above the emitting layer. The first functional layer and / or the second functional layer may include layers integrally disposed above the plurality of pixel electrodes PE, or may include layers patterned to correspond respectively to each of the plurality of pixel electrodes PE.

[0117] The first functional layer may have a single-layer or multi-layer structure. In an exemplary embodiment, when the first functional layer comprises a polymer material, the first functional layer, as a hole transport layer (“HTL”) having a single-layer structure, may, for example, comprise poly(3,4-ethylenedioxythiophene) (“PEDOT”) or polyaniline (“PANI”). When the first functional layer comprises a low molecular weight material, the first functional layer may comprise a hole injection layer (“HIL”) and an HTL.

[0118] In another exemplary embodiment, the second functional layer may be omitted. In an exemplary embodiment, when each of the first functional layer and the emitter layer comprises a polymer material, a second functional layer is preferably provided to improve the characteristics of the organic light-emitting diode (OLED). The second functional layer may have a single-layer or multi-layer structure. The second functional layer may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”).

[0119] The counter electrode CE faces the pixel electrode PE, and the intermediate layer EL lies between the counter electrode CE and the pixel electrode PE. The counter electrode CE may include a conductive material with a low work function. In an exemplary embodiment, the counter electrode CE may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. In an alternative exemplary embodiment, the counter electrode CE may further include a layer comprising ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the above materials. The counter electrode CE may be disposed on the intermediate layer EL and the sixth insulating layer 116. The counter electrode CE may be a common electrode for multiple organic light-emitting diodes (OLEDs) integrated into the display area DA and facing multiple pixel electrodes PE.

[0120] Figures 6 to 8 This is a schematic plan view of an exemplary embodiment of the first wiring 200. Figure 6 yes Figure 1 A magnified plan view of region B. Figure 7 yes Figure 1 A magnified plan view of region C, and Figure 8 yes Figure 3 A magnified plan view of region D. Figure 9 This is a schematic plan view of an exemplary embodiment of the fourth wiring 300.

[0121] Despite Figure 6 and Figure 7 The diagram illustrates a first wiring 200 positioned to the left of the center line CL; the same description applies to a first wiring 200 positioned to the right of the center line CL. Figures 6 to 9 In the diagram, the pixel region CA, where pixels are arranged, is defined by a dashed line.

[0122] Reference Figure 6 In the first sub-region SS1, the first portion 200a of the first wiring 200 may extend in a direction parallel to the first direction D1, and the first portion 200a may include a first branch 211 protruding in the second direction D2.

[0123] The first branch 211 may protrude symmetrically from the first portion 200a of the first wiring 200. That is, the first branch 211 may protrude in two directions along the second direction D2 from the first portion 200a of the first wiring 200 extending along the first direction D1. Furthermore, in the first sub-region SS1, a pair of first branches 211 protruding from two adjacent first portions 200a toward each other in the first portions 200a arranged parallel to each other may be arranged on the same line. To prevent short circuits between the first wirings 200, the ends of the first branches 211 extending from two adjacent first portions 200a toward each other may be spaced apart to define a gap. In the first sub-region SS1, the first portions 200a and the first branches 211 may be arranged in a predetermined pattern in the pixel region CA.

[0124] Reference Figure 7 In the second sub-region SS2, the second portion 200b of the first wiring 200 may extend in a direction parallel to the second direction D2, and the second portion 200b may include a second branch 221 protruding in the first direction D1.

[0125] The second branch 221 may protrude from the second portion 200b around the second portion 200b of the first wiring 200. That is, the second branch 221 may protrude from the second portion 200b of the first wiring 200 extending along the second direction D2 in two directions along the first direction D1. Furthermore, in the second sub-region SS2, a pair of second branches 221 protruding from two adjacent second portions 200b toward each other may be arranged on the same line. To prevent short circuits between the first wiring 200s, the ends of the second branches 221 extending from two adjacent second portions 200b toward each other may be spaced apart to define a gap. In the second sub-region SS2, the second portion 200b and the second branch 221 may be arranged in a predetermined pattern in the pixel region CA.

[0126] Reference Figure 8 The second portion 200b of the first wiring 200 can be electrically connected to the first data line DL1 by the first bridge portion 180 at the contact portion CNT. The contact portion CNT can be located in the boundary between the second sub-region SS2 of the first region S1 and the third sub-region SS3 of the second region S2.

[0127] In the second region S2, the fourth wiring 300 may be disposed on the same layer as the first wiring 200. The fourth wiring 300 may include the same material as the first wiring 200. Figure 8 The diagram illustrates the fourth wiring 300 located in the third sub-region SS3 of the second region S2. (See diagram for reference.) Figure 9 As shown, the fourth wiring 300 can also be set in the fourth sub-region SS4 of the second region S2. Figure 9 yes Figure 1 The enlarged plan view of region E, which is the fourth sub-region SS4 of the second region S2.

[0128] Reference Figure 8 and Figure 9 The fourth wiring 300 may be spaced apart from the first wiring 200 and may be electrically isolated. The fourth wiring 300 may include a plurality of first portions 300a extending along a first direction D1 and spaced apart from each other, and a plurality of second portions 300b extending along a second direction D2, intersecting with the first portions 300a and spaced apart from each other. The fourth wiring 300 may have a grid structure, wherein the plurality of first portions 300a and the plurality of second portions 300b are connected to each other. In the second region S2, the fourth wiring 300 may be arranged in a predetermined pattern in the pixel region CA. Since the second region S2 includes the fourth wiring 300, the first region S1 and the second region S2 where the first wiring 200 is disposed can be effectively prevented from being distinguishably seen. The fourth wiring 300 disposed in the third sub-region SS3 and the fourth wiring 300 disposed in the fourth sub-region SS4 may be partially physically and / or electrically connected to each other in an exemplary embodiment, and may also be separated from each other in another exemplary embodiment.

[0129] like Figures 6 to 9 As shown, in each pixel region CA, multiple conductive patterns can be further disposed in the same layer as the first wiring 200 and the fourth wiring 300. The conductive patterns may include first patterns 230. Each of the first patterns 230 can serve as a shielding electrode to prevent signal interference between pixel circuits disposed on the lower layer of the first pattern 230 and pixel electrodes disposed on the upper layer of the first pattern 230 in the pixel region CA. The first pattern 230 can be electrically connected to the power voltage line PL connected to the pixel PX and can receive a first power voltage ELVDD. The conductive patterns may further include second patterns 240. Each of the second patterns 240 can serve as a bridge electrode to connect pixel circuits disposed on the lower layer of the second pattern 240 to pixel electrodes disposed on the upper layer of the second pattern 240 in the pixel region CA. In an exemplary embodiment, the second pattern 240 may be, for example, a... Figure 5 An exemplary embodiment of the connecting member 150 shown.

[0130] like Figures 6 to 7 As shown, in the pixel region CA of the first region S1, that is, the pixel region CA where the first wiring 200 is arranged, the first pattern 230 can be physically and electrically separated from the first wiring 200. Conversely, as Figure 8 and Figure 9As shown, in the pixel region CA of the second region S2, the first pattern 230 can be electrically connected to the fourth wiring 300 by the bridge portion 250. In an exemplary embodiment, the fourth wiring 300, the first pattern 230, and the bridge portion 250 disposed in the pixel region CA of the second region S2 can be integrated. The fourth wiring 300 disposed in the pixel region CA of the second region S2 can receive the first power voltage ELVDD by being electrically connected to the first pattern 230 of the power voltage line PL. Since the first pattern 230 and the second pattern 240 are included in the first region S1 and the second region S2, pattern density can be ensured, thereby providing advantages in the manufacturing process.

[0131] Figure 8 and Figure 9 An exemplary embodiment of a grid structure is illustrated, showing the first portion 300a and the second portion 300b of a fourth wiring 300 disposed in the second region S2 connected to each other. However, in another exemplary embodiment, similar to... Figure 7 The second portion 200b of the first wiring 200 shown, and the second portion 300b of the fourth wiring 300 can extend along the second direction D2, can be spaced apart from each other, and can include branches protruding from the second portion 300b along the first direction D1.

[0132] Figure 10A and Figure 10B They are Figure 8 Enlarged plan view and cross-sectional view of the CNT contact portion. Figure 11 It's a diagram. Figure 10A and Figure 10B Comparative example diagram of CNT structure in the contact portion. Figure 10A It is a plan view of the contact part of CNT, and Figure 10B This is a cross-sectional view of the contact portion CNT taken along line I-I'.

[0133] In the following text, for ease of explanation, the pixel region CA in the first region S1 where the first wiring 200 contacts the first data line DL1 is referred to as the first pixel region CA1 (see reference). Figure 12 The other pixel region CA is referred to as the second pixel region CA2 (see reference). Figure 12 The pixel region CA of the second region S2 is called the third pixel region CA3 (see reference). Figure 12 ).

[0134] Reference Figure 10A and Figure 10BIn the first pixel region CA1, the first wiring 200 can be electrically connected to the first data line DL1 by a first bridge portion 180. The first bridge portion 180 can electrically connect a second branch 221 of the first wiring 200 to the first data line DL1. The first bridge portion 180 may include at least two conductive patterns on different layers to electrically connect the second branch 221 of the first wiring 200 to the first data line DL1. The first bridge portion 180 may include a first bridge electrode 181 and a second bridge electrode 183. The first wiring 200 and the first data line DL1 can be electrically connected without direct contact with each other, but rather by a dual-bridge structure using the first bridge electrode 181 and the second bridge electrode 183.

[0135] Referring to the plan and cross-sectional views, the first bridge electrode 181 can be arranged on the insulating layer IL1, and the second bridge electrode 183 can be arranged on the insulating layer IL2 above the insulating layer IL1. The first data line DL1 can be arranged on the insulating layer IL2, and the first wiring 200, i.e., the second branch 221 of the first wiring 200, can be arranged on the insulating layer IL3 above the insulating layer IL2. The first data line DL1 can at least partially overlap with the first bridge electrode 181 and can contact the first bridge electrode 181 through the contact hole 51 of the insulating layer IL2. The second bridge electrode 183 can at least partially overlap with the first bridge electrode 181 and can contact the first bridge electrode 181 through the contact hole 52 of the insulating layer IL2. The second branch 221 of the first wiring 200 can at least partially overlap with the second bridge electrode 183 and can contact the second bridge electrode 183 through the contact hole 53 of the insulating layer IL3. Figure 10A and Figure 10B In the present embodiment, the contact hole 52 of insulating layer IL2 does not overlap with the contact hole 53 of insulating layer IL3. However, in another exemplary embodiment, the contact hole 52 of insulating layer IL2 may overlap with the contact hole 53 of insulating layer IL3. Insulating layer IL4, as a planarization layer, may be used to cover the first wiring 200. Insulating layers IL1 and IL2 may be inorganic insulating layers, and insulating layers IL3 and IL4 may be organic insulating layers.

[0136] In an exemplary embodiment, the first bridge electrode 181 can be coupled with... Figure 5 The gate electrode GE of the thin-film transistor TFT shown is arranged in the same layer. The first bridge electrode 181 may include the same material as the gate electrode GE. In this case, the insulating layer IL1 may be... Figure 5 The first insulating layer 111 shown, and the insulating layer IL2 may have Figure 5 The structure shown depicts a stacked second insulating layer 112 and a third insulating layer 113. In another exemplary embodiment, the first bridge electrode 181 can be coupled with... Figure 5The upper electrode UE of the capacitor Cst shown is arranged in the same layer. The first bridge electrode 181 may include the same material as the upper electrode UE. In this case, the insulating layer IL1 may be... Figure 5 The second insulating layer 112 shown, and the insulating layer IL2 can be Figure 5 The third insulating layer 113 shown in the figure.

[0137] The second bridge electrode 183 can be disposed in the same layer as the first data line DL1. The second bridge electrode 183 can include the same material as the first data line DL1. The insulating layer IL3 can be... Figure 5 The fourth insulating layer 114 shown, and the insulating layer IL4 can be Figure 5 The fifth insulating layer 115 is shown in the figure.

[0138] Reference Figure 11 In the comparative example diagram, a first conductive layer ML1 is disposed between inorganic insulating layers 101 and 102, and a second conductive layer ML2 is disposed on the inorganic insulating layer 102 covering the first conductive layer ML1. An organic insulating layer 103 is disposed on the second conductive layer ML2, and a third conductive layer ML3 is disposed on the organic insulating layer 103. An organic insulating layer 104 is disposed on the third conductive layer ML3. The organic insulating layers 103 and 104, serving as planarization layers, are relatively thicker than the inorganic insulating layers 101 and 102. When the organic insulating layer 103 is in contact with and overlaps the second conductive layer ML2 and the third conductive layer ML3 between them, the third conductive layer ML3 is not planarized. Therefore, the metallic reflection characteristics X1 and X2 of the third conductive layer ML3 to external light change according to its position, making the area where the second conductive layer ML2 and the third conductive layer ML3 are in contact visible to the user.

[0139] In an exemplary embodiment, such as Figure 8 As shown, the contact portion CNT where the first data line DL1 and the first wiring 200 are electrically connected, with the organic insulating layer disposed between them, can be provided only in the first pixel region CA1 within the entire pixel region CA. In this case, as... Figure 10A and Figure 10BAs shown, in the first pixel region CA1, the first wiring 200 and the first data line DL1 are electrically connected by the first bridge portion 180 at the lower layer of the organic insulating layers IL3 and IL4, and the first wiring 200 does not overlap with the first data line DL1. Therefore, in the first pixel region CA1, the portions where the first data line DL1 and the first bridge electrode 181 of the first bridge portion 180 are electrically connected and overlap each other can be planarized by the organic insulating layers 113 and 114. That is, in the exemplary embodiment, in the first pixel region CA1, the first wiring 200 does not directly contact the first data line DL1 by overlapping the first wiring 200 with the first data line DL1, and therefore, in the first region S1, it is possible to prevent the first pixel region CA1 with the contact portion CNT and the second pixel region CA2 without the contact portion CNT from being distinguishably seen.

[0140] Figure 12 This is a diagram illustrating an exemplary embodiment of the first wiring 200 for each pixel region. Figures 13AA to 13DB These are enlarged planar and cross-sectional views of the bridge portion of the second pixel region CA2. Figure 13AA , Figure 13BA , Figure 13CA and Figure 13DA It is a plan view of the bridge section, and Figure 13AB , Figure 13BB , Figure 13CB and Figure 13DB It is a cross-sectional view of the bridge section taken along line II-II'.

[0141] Reference Figure 12 In each of the first pixel regions CA1, the first wiring 200 can be electrically connected to the first data line DL1 at the contact portion by the first bridge portion 180. The structure of the contact portion is as shown in the reference. Figure 10A and Figure 10B The structures described are identical and therefore omitted.

[0142] In each of the second pixel regions CA2, the second bridge portion 190 may be arranged at a position corresponding to the position of the first bridge portion 180 in the first pixel region CA1. In each of the second pixel regions CA2, the second bridge portion 190 disposed between the first wiring 200 and the first data line DL1 or the second data line DL2 does not electrically connect the first wiring 200 to the first data line DL1 or the second data line DL2. Although the second bridge portion 190 may not necessarily be arranged in the third pixel region CA3, in the exemplary embodiment, the second bridge portion 190 may be arranged in the third pixel region CA3.

[0143] In an exemplary embodiment, such as Figure 13AA and Figure 13ABAs shown, the second bridge portion 190 may include a third bridge electrode 191 and a fourth bridge electrode 193. Referring to the plan view and cross-sectional view, the third bridge electrode 191 may be arranged on the insulating layer IL1, and the fourth bridge electrode 193 may be arranged on the insulating layer IL2 on the insulating layer IL1. The first wiring 200, namely the second branch 221 and the first portion 200a of the first wiring 200, may be arranged on the insulating layer IL3 on the insulating layer IL2. Figures 13AA to 13DB The data line DL can be either the first data line DL1 or the second data line DL2. The data line DL at least partially overlaps with the third bridge electrode 191, but does not contact the third bridge electrode 191. The fourth bridge electrode 193 can at least partially overlap with the third bridge electrode 191 and can contact the third bridge electrode 191 through the contact hole 55 of the insulating layer IL2. The second branch 221 or the first portion 200a of the first wiring 200 can at least partially overlap with the fourth bridge electrode 193 and can contact the fourth bridge electrode 193 through the contact hole 56 of the insulating layer IL3. Figure 13AA and Figure 13AB In one embodiment, the contact hole 55 of the insulating layer IL2 does not overlap with the contact hole 56 of the insulating layer IL3. However, in another exemplary embodiment, the contact hole 55 of the insulating layer IL2 may overlap with the contact hole 56 of the insulating layer IL3. The first wiring 200 may be covered by the insulating layer IL4, which serves as a planarization layer.

[0144] In an exemplary embodiment, the third bridge electrode 191 may be arranged in the same layer as the first bridge electrode 181. That is, the third bridge electrode 191 may be arranged in the same layer as the first bridge electrode 181. Figure 5 The gate electrode GE of the thin-film transistor TFT shown is arranged in the same layer. The third bridge electrode 191 may include the same material as the gate electrode GE. In this case, the insulating layer IL1 may be... Figure 5 The first insulating layer 111 shown, and the insulating layer IL2 may have Figure 5 The structure shown depicts a stacked second insulating layer 112 and a third insulating layer 113. In another exemplary embodiment, the third bridge electrode 191 can be coupled with... Figure 5 The upper electrode UE of the capacitor Cst shown is arranged in the same layer. The third bridge electrode 191 may include the same material as the upper electrode UE. In this case, the insulating layer IL1 may be... Figure 5 The second insulating layer 112 shown, and the insulating layer IL2 can be Figure 5 The third insulating layer 113 shown.

[0145] The fourth bridge electrode 193 can be disposed in the same layer as the second bridge electrode 183. The fourth bridge electrode 193 can comprise the same material as the second bridge electrode 183. The insulating layer IL3 can be... Figure 5 The fourth insulating layer 114 shown, and the fourth insulating layer IL4 can be Figure 5 The fifth insulating layer 115 shown.

[0146] In another exemplary embodiment, such as Figures 13BA to 13DB As shown, in the second pixel region CA2, the second bridge portion 190 may include only the fourth bridge electrode 193. Referring to the plan view and cross-sectional view, the second branch 221 or the first portion 200a of the first wiring 200 may at least partially overlap with the fourth bridge electrode 193 and may contact the fourth bridge electrode 193 via the contact hole 56 of the insulating layer IL3. The first wiring 200 may be covered with an insulating layer IL4 as a planarization layer. In this case, in the second pixel region CA2, at least one of the contact hole 57 overlapping with the data line DL and the contact hole 55 overlapping with the fourth bridge electrode 193 may be defined in the insulating layer IL2. Figure 13CA and Figure 13CB As shown, the contact hole 52 (refer to) that defines the insulating layer IL2 in the first pixel region CA1 can be connected to the contact hole 52 (refer to the contact hole 52). Figure 10A and Figure 10B The process simultaneously defines a contact hole 55 in the insulating layer IL2 within the second pixel region CA2. The fourth bridge electrode 193 can fill the contact hole 55. In an alternative exemplary embodiment, such as... Figure 13DA and Figure 13DB As shown, contact holes 51 and 52 (refer to) can be used with the insulating layer IL2 defined in the first pixel region CA1. Figure 10A and Figure 10B The process simultaneously defines contact holes 55 and 57 in the insulating layer IL2 within the second pixel region CA2. The data line DL can fill contact hole 57, and the fourth bridge electrode 193 can fill contact hole 55.

[0147] exist Figures 13AA to 13DB The second bridge portion 190 is applied to the second pixel region CA2. Figure 12 In an exemplary embodiment, the first wiring 200 can be electrically connected to the second bridge electrode 183 below the first wiring 200 in each first pixel region CA1 through the contact hole 53 of the insulating layer IL3, and can be electrically connected to the fourth bridge electrode 193 below the first wiring 200 in each second pixel region CA2 through the contact hole 56 of the insulating layer IL3. That is, a portion of the first wiring 200 can also be electrically connected to the bridge electrode below the first wiring 200 in the first pixel region CA1 and the second pixel region CA2. Therefore, it is possible to prevent the first pixel region CA1 and the second pixel region CA2 from being distinguishably seen.

[0148] Figure 14This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the first pixel region. Figure 15 It is along Figure 14 A cross-sectional view of the pixel circuits cut by lines III-III' and IV-IV'. Figures 16A to 16E It's a layer-by-layer diagram. Figure 14 A schematic plan view of the components. Figure 17 This is a schematic plan view illustrating the positions of pixel circuits and wiring arranged in a first pixel region according to another exemplary embodiment, and Figure 18 It is along Figure 17 A cross-sectional view of the pixel circuits cut by lines III-III' and IV-IV'.

[0149] Figure 14 It can correspond to Figure 4B The image shows a planar view of the pixels. Figure 4B The first transistor T1 to the seventh transistor T7 shown can be implemented as thin-film transistors.

[0150] Reference Figure 14 and Figure 15 In the first pixel region CA1, the first wiring 200 can be electrically connected to the data line 171. The data line 171 can be the first data line DL1. A first bridge portion 180 for electrically connecting the second branch 221 to the data line 171 can be arranged between the data line 171 and the second branch 221 protruding from the second portion 200b of the first wiring 200. (The rest of the text will omit the repetition of the previous sentence.) Figure 5 Detailed description of the same components as those shown.

[0151] The semiconductor layer Act can be disposed on the buffer layer 110 on the substrate 100. The semiconductor layer Act can be bent into various shapes. Figure 16A As shown, the semiconductor layer Act may include the channel region 131a of the first transistor T1, the channel region 131b of the second transistor T2, the channel regions 131c1 and 131c2 of the third transistor T3, the channel regions 131d1 and 131d2 of the fourth transistor T4, the channel region 131e of the fifth transistor T5, the channel region 131f of the sixth transistor T6, and the channel region 131g of the seventh transistor T7. That is, each channel region of the first transistor T1 to the seventh transistor T7 may be a portion of the semiconductor layer Act. The channel region 131a of the first transistor T1 may be provided to be long by having a curve, thereby widening the driving range of the gate voltage applied to the gate electrode. The channel region 131a of the first transistor T1 may have various shapes in various exemplary embodiments, for example... "S", "M", "W", etc. The channel region 131g of the seventh transistor T7 can be a portion of the semiconductor layer Act extending from the previous row. That is, Figure 14 The seventh transistor T7 can be the seventh transistor T7 of the pixel in the previous row.

[0152] The semiconductor layer Act of the first transistor T1 to the seventh transistor T7 can be respectively included in the source region and drain region on both sides of the channel region. For example... Figure 16A As shown, the semiconductor layer Act may include the source region 176a and drain region 177a of the first transistor T1, the source region 176b and drain region 177b of the second transistor T2, the source region 176c and drain region 177c of the third transistor T3, the source region 176d and drain region 177d of the fourth transistor T4, the source region 176e and drain region 177e of the fifth transistor T5, the source region 176f and drain region 177f of the sixth transistor T6, and the source region 176g and drain region 177g of the seventh transistor T7. In some cases, the source region or drain region can be interpreted as the source electrode or drain electrode of the transistor. That is, for example, the source electrode and drain electrode of the first transistor T1 may correspond to the source electrode and drain electrode of the transistor T7, respectively. Figure 16A The semiconductor layer Act shown has a source region 176a and a drain region 177a near the channel region 131a, which are doped with impurities. In some exemplary embodiments, the positions of the source and drain regions can be changed. A first insulating layer 111 can be disposed on the semiconductor layer Act.

[0153] like Figure 16B As shown, the gate electrode 125a of the first transistor T1, the gate electrode 125b of the second transistor T2, the gate electrode 125c of the third transistor T3 including gate electrodes 125c1 and 125c2, the gate electrode 125d of the fourth transistor T4 including gate electrodes 125d1 and 125d2, the gate electrode 125e of the fifth transistor T5, the gate electrode 125f of the sixth transistor T6, and the gate electrode 125g of the seventh transistor T7 can be disposed on the first insulating layer 111. Furthermore, on the first insulating layer 111, the first scan line 121, the second scan line 122, and the emission control line 123 can comprise the same material and be disposed on the same layer as the gate electrodes of the first transistor T1 to the seventh transistor T7, and can be arranged to extend along the second direction D2. The gate electrode 125a of the first transistor T1 can be used as the lower electrode 125a of the capacitor Cst.

[0154] The gate electrode 125b of the second transistor T2 and the gate electrodes 125c1 and 125c2 of the third transistor T3 can be the portion of the first scan line 121 that intersects with the semiconductor layer Act, or the portion protruding from the first scan line 121. The gate electrodes 125d1 and 125d2 of the fourth transistor T4 and the gate electrode 125g of the seventh transistor T7 can be the portion of the second scan line 122 that intersects with the semiconductor layer Act, or the portion protruding from the second scan line 122. The gate electrode 125e of the fifth transistor T5 and the gate electrode 125f of the sixth transistor T6 can be the portion of the emitter control line 123 that intersects with the semiconductor layer Act, or the portion protruding from the emitter control line 123. The gate electrode 125a of the first transistor T1 can be island-shaped.

[0155] The gate electrodes of the first transistor T1 to the seventh transistor T7 may have a single-layer or multi-layer structure comprising at least one material selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and Cu.

[0156] The first bridge electrode 181 may be further disposed on the first insulating layer 111. The first bridge electrode 181 may include the same material as the gate electrode of the first transistor T1 to the seventh transistor T7.

[0157] The second insulating layer 112 can be disposed on the gate electrode of the first transistor T1 to the seventh transistor T7 and the first bridge electrode 181.

[0158] like Figure 16C As shown, the upper electrode 127 of capacitor Cst can be disposed on the second insulating layer 112. An opening 27 can be defined within the upper electrode 127 of capacitor Cst. A node electrode 174 allows the lower electrode 125a of capacitor Cst to be electrically connected to the drain region 177c of the third transistor T3. The upper electrode 127 of capacitor Cst can have a single-layer or multi-layer structure comprising at least one material selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

[0159] The initialization voltage line 124 can be disposed in the same layer as the upper electrode 127 of the capacitor Cst on the second insulating layer 112. The initialization voltage line 124 can comprise the same material as the upper electrode 127 of the capacitor Cst. The initialization voltage line 124 can extend along the second direction D2.

[0160] The third insulating layer 113 can be arranged on the upper electrode 127 of the capacitor Cst and the initialization voltage line 124.

[0161] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0162] like Figure 16D As shown, data line 171 and power voltage line 172 can be arranged on the third insulating layer 113. Data line 171 can be connected to the source region 176b of the second transistor T2 through contact holes 164 defined in each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Data line 171 can be connected to the first bridge electrode 181 through contact holes 51 defined in each of the second insulating layer 112 and the third insulating layer 113. The power voltage line 172 extending along the first direction D1 may include a first voltage line 172a and a second voltage line 172b spaced apart from each other. The second voltage line 172b of power voltage line 172 can be connected to the source region 176e of the fifth transistor T5 through contact holes 165 defined in each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The second voltage line 172b of power voltage line 172 can be connected to the upper electrode 127 of capacitor Cst through contact holes 168 defined in the third insulating layer 113. The second bridge electrode 183 of the first bridge portion 180 can be disposed in the gap between the first voltage line 172a and the second voltage line 172b. The second bridge electrode 183 can be connected to the first bridge electrode 181 through a contact hole 52 defined in each of the second insulating layer 112 and the third insulating layer 113.

[0163] Each of the data line 171, the power voltage line 172, and the second bridge electrode 183 may include Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. In an exemplary embodiment, the data line 171, the power voltage line 172, and the second bridge electrode 183 may have a multi-layer structure including Ti / Al / Ti.

[0164] Various conductive layers may be further disposed on the third insulating layer 113. In an exemplary embodiment, node electrode 174 and connecting members 173 and 175 may, for example, be provided on the third insulating layer 113. One end of node electrode 174 may be connected to the drain region 177c of the third transistor T3 and the drain region 177d of the fourth transistor T4 through contact holes 166 defined in each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113, and the other end of node electrode 174 may be connected to the gate electrode 125a of the first transistor T1 through contact holes 167 defined in each of the second insulating layer 112 and the third insulating layer 113. In this case, the other end of node electrode 174 may be connected to the gate electrode 125a of the first transistor T1 through an opening 27 defined in the upper electrode 127 of capacitor Cst. One end of the connecting member 173 can be connected to the initialization voltage line 124 through a contact hole 161 defined in the third insulating layer 113, and the other end of the connecting member 173 can be connected to the source region 176d of the fourth transistor T4 through a contact hole 162 defined in each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The connecting member 175 can be connected to the drain region 177f of the sixth transistor T6 through a contact hole 163 defined in each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0165] The fourth insulating layer 114 can be arranged on the data line 171 and the power line 172. For example... Figure 16E As shown, the first wiring 200 can be arranged on the fourth insulating layer 114. Figure 16E The diagram illustrates the second portion 200b and the second branch 221 of the first wiring 200. The second branch 221 of the first wiring 200 can be connected to the second bridge electrode 183 through the contact hole 53 of the fourth insulating layer 114. Therefore, the first wiring 200 can be electrically connected to the data line 171 through the first bridge electrode 181 and the second bridge electrode 183.

[0166] The first pattern 230 and the second pattern 240 can be further arranged on the fourth insulating layer 114. The first pattern 230 can be connected to the first voltage line 172a of the power voltage line 172 through the contact hole 58 of the fourth insulating layer 114. The first pattern 230 can be connected to the second voltage line 172b of the power voltage line 172 through the contact hole 59 of the fourth insulating layer 114. The first voltage line 172a and the second voltage line 172b, which are spaced apart from each other, can be electrically connected to each other by the first pattern 230. Since the second voltage line 172b is connected to the upper electrode 127 of the capacitor Cst extending along the second direction D2, the power voltage line 172 can have a grid structure. The second pattern 240 can be connected to the connecting member 175 through the contact hole 54 of the fourth insulating layer 114. The second pattern 240 can be connected to the pixel electrode PE through the contact hole of the fifth insulating layer 115. That is, the thin film transistor and the pixel electrode PE can be electrically connected to each other by the connecting member 175 and the second pattern 240. The second pattern 240 can be used as Figure 5 The connecting member 150 shown is shown.

[0167] Each of the first wiring 200, the first pattern 230, and the second pattern 240 may include Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. In an exemplary embodiment, the first wiring 200, the first pattern 230, and the second pattern 240 may have a multi-layer structure including Ti / Al / Ti.

[0168] Each of the fourth insulating layer 114 and the fifth insulating layer 115, which serve as planarization insulating layers, can be an organic insulating layer. For example... Figure 5 As shown, an organic light-emitting diode (OLED) as a display element can be arranged on the fifth insulating layer 115.

[0169] exist Figure 14 and Figure 15 In the first bridge portion 180, the first bridge electrode 181 may include the same material as the gate electrode of the transistor and is disposed in the same layer as the gate electrode of the transistor. In another exemplary embodiment, as shown... Figure 17 and Figure 18 As shown, the first bridge electrode 181 can be disposed in the same layer as the upper electrode 127 of the capacitor Cst on the second insulating layer 112. The first bridge electrode 181 can be made of the same material as the upper electrode 127 of the capacitor Cst. The data line 171 can be connected to the first bridge electrode 181 through a contact hole 51 defined in the third insulating layer 113. The second bridge electrode 183 can be connected to the first bridge electrode 181 through a contact hole 52 defined in the third insulating layer 113.

[0170] Figure 19This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in the second pixel region. Figure 20 and Figure 21 It is along Figure 19 The image shows a cross-sectional view of the pixel circuit captured by lines V-V' and VI-VI'. The following text primarily describes the relationship between... Figure 14 Different components. Figure 19 The illustration shows the second pixel region CA2 of the first portion 200a of the second wiring 200.

[0171] Reference Figure 19 and Figure 20 The second bridge portion 190 can be arranged in the second pixel region CA2 at a position corresponding to the arrangement of the first bridge portion 180 in the first pixel region CA1. The second bridge portion 190 may include a third bridge electrode 191 and a fourth bridge electrode 193. Data line 171 may be a second data line DL2. The third bridge electrode 191 may be arranged on the first insulating layer 111. The third bridge electrode 191 may include the same material as the gate electrode of the first transistor T1 to the seventh transistor T7. Data line 171 may be arranged on the third insulating layer 113 and may at least partially overlap with the third bridge electrode 191. The fourth bridge electrode 193 of the second bridge portion 190 may be arranged in the gap between the first voltage line 172a and the second voltage line 172b spaced apart from each other in the power voltage line 172. The fourth bridge electrode 193 may at least partially overlap with the third bridge electrode 191 and may be connected to the third bridge electrode 191 through a contact hole 55 defined in each of the second insulating layer 112 and the third insulating layer 113. The first wiring 200 can be set on the fourth insulating layer 114. Figure 19 The diagram illustrates a first portion 200a and a first branch 211 of the first wiring 200. The first portion 200a of the first wiring 200 can be connected to the fourth bridge electrode 193 through the contact hole 56 of the fourth insulating layer 114.

[0172] exist Figure 19 and Figure 20 In the second bridge portion 190, the third bridge portion electrode 191 may include the same material as the gate electrode of the transistor and is disposed in the same layer as the gate electrode of the transistor. In another exemplary embodiment, as shown... Figure 21 As shown, the third bridge electrode 191 can be disposed in the same layer as the upper electrode 127 of the capacitor Cst on the second insulating layer 112. The third bridge electrode 191 can be made of the same material as the upper electrode 127 of the capacitor Cst. The fourth bridge electrode 193 can be connected to the third bridge electrode 191 through a contact hole 55 defined in the third insulating layer 113.

[0173] Figure 22This is a schematic plan view illustrating the location of pixel circuits and wiring arranged in a second pixel region according to another exemplary embodiment. Figure 23 It is along Figure 22 Cross-sectional views of the pixel circuits intercepted by lines VII-VII' and VIII-VIII'. The following mainly describes the... Figure 19 Different components. Figure 22 The illustration shows the second pixel region CA2 of the first portion 200a of the first wiring 200.

[0174] Reference Figure 22 and Figure 23 The second bridge portion 190 can be arranged in the second pixel region CA2 to correspond to the position of the first bridge portion 180 arranged in the first pixel region CA1. The second bridge portion 190 may only include the fourth bridge electrode 193. The data line 171 may be the second data line DL2. The fourth bridge electrode 193 of the second bridge portion 190 may be arranged in the gap between the first voltage line 172a and the second voltage line 172b that are spaced apart from each other in the power voltage line 172. The first wiring 200 may be disposed on the fourth insulating layer 114. Figure 22 The diagram illustrates a first portion 200a and a first branch 211 of the first wiring 200. The first portion 200a of the first wiring 200 can be connected to the fourth bridge electrode 193 through the contact hole 56 of the fourth insulating layer 114.

[0175] In another exemplary embodiment, such as Figure 13CA and Figure 13CB As shown, the contact hole 52 that defines the third insulating layer 113 in the first pixel region CA1 (see reference) Figure 15 and Figure 18 The process simultaneously defines a contact hole 55 in the third insulating layer 113 within the second pixel region CA2. A fourth bridge electrode 193 may fill the contact hole 55. In an alternative exemplary embodiment, such as... Figure 13DA and Figure 13DB As shown, contact holes 51 and 52 (refer to) can define the third insulating layer 113 in the first pixel region CA1. Figure 15 and Figure 18 The process simultaneously defines contact holes 55 and 57 in the third insulating layer 113 within the second pixel region CA2. Data line 171 can fill contact hole 57, and the fourth bridge electrode 193 can fill contact hole 55.

[0176] Figure 19 and Figure 22 The second bridge portion 190 can also be applied to the second pixel region CA2 of the second portion 200b of the first wiring 200.

[0177] Figure 24This is a schematic plan view of an exemplary embodiment of a display panel 10' according to another exemplary embodiment.

[0178] Figure 24 The display panel 10' shown may include a display area and a peripheral area disposed outside the display area. The display panel 10' may include a substrate 100', and the substrate 100' may include a display area DA and a peripheral area PA corresponding to the display area and peripheral area of ​​the display panel 10', respectively.

[0179] exist Figure 24 In the display panel 10' shown, the pad region PADA is adjacent to the second edge E2 from the first edge E1 to the fourth edge E4. Since the bending region is disposed between the pad region PADA and the display region DA, when the substrate 100' is bent, at least a portion of the pad region PADA can overlap with the display region DA.

[0180] Multiple pixels PX and signal lines for applying electrical signals to the multiple pixels PX can be disposed in a display area DA. The signal lines may include multiple scan lines SL and multiple data lines DL. Each of the multiple data lines DL may extend along a first direction D1, and each of the multiple scan lines SL may extend along a second direction D2. A first wiring 200' for transmitting electrical signals applied from the pad area PADA to the signal lines connected to the pixels PX can be disposed in the display area DA. In an exemplary embodiment, for example, the first wiring 200' may be connected to the data lines DL, and data signals supplied from the pad area PADA may be transmitted to the data lines DL. Each of the first wirings 200' may be electrically connected to the corresponding data line DL at a contact portion CNT'. The first wiring 200' may extend along a second direction D2 parallel to the scan lines SL. The first wiring 200' may be disposed in a different layer than the scan lines SL and data lines DL of the pixels PX. Although not shown, a second wiring connected to the first wiring 200' may be further provided between the display area DA and the pad area PADA. The second wiring may be a portion of the first wiring 200' extending into the peripheral area PA, or it may be a discrete wiring disposed on a different layer than the first wiring 200'.

[0181] Each of the first wirings 200' may include a first portion 200a' extending along a second direction D2 between the contact portion CNT' and the second edge E2, and a second portion 200b' extending along the second direction D2 between the contact portion CNT' and the first edge E1. The lengths of the first portion 200a' and the second portion 200b' may vary depending on the location of the data line DL connecting the first wirings 200'. When the data line DL is closer to the first edge E1, the first portion 200a' of the first wiring 200' may be longer and the second portion 200b' may be shorter.

[0182] The display area DA may include a first area S1' where the first wiring 200' is set, and a second area S2' outside the first area S1'. The second areas S2' may face each other, with the first area S1' between the second areas S2'. The arrangement of pixel circuits and wiring in the pixel area of ​​the first area S1', the pixel area where the contact portion CNT' is set, and other pixel areas can be referenced as an example. Figure 1 The arrangement of pixel circuits and wiring provided in the first pixel region CA1 and the second pixel region CA2 of the display panel 10 is the same. The arrangement of pixel circuits and wiring provided in the pixel region of the second region S2' can be the same as that described in the example. Figure 1 The display panel 10 provides the same arrangement of pixel circuits and wiring in the third pixel region CA3.

[0183] In an exemplary embodiment of the present invention, since the connection wiring for transmitting data signals to the data line is provided in the display area, the dead zone of the display device can be reduced. Furthermore, since the reflective properties are the same or similar across the entire display area, the area where the connection wiring is provided can be prevented from being clearly seen. However, the scope of the present invention is not limited to these effects.

[0184] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features within each exemplary embodiment should generally be regarded as other similar features that may be used in other exemplary embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail can be made without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: Data cable extending in the first direction; A scan line extending along a second direction that intersects the first direction; A wiring extending along the second direction, the wiring including branches protruding from the wiring along the first direction; as well as Connect the wiring to the bridge portion of the data cable. The bridge portion overlaps with the branch of the wiring and the data line. The bridge portion includes: A first bridge electrode is disposed on the lower layer of the data line and at least partially overlaps with the data line, and is electrically connected to the data line; and The second bridge electrode is disposed in the same layer as the data line and at least partially overlaps with the branch of the wiring and the first bridge electrode, and is electrically connected to the branch of the wiring and the first bridge electrode. The display device further includes: An inorganic insulating layer between the first bridge electrode and the data line; and An organic insulating layer between the data line and the wiring.

2. The display device according to claim 1, further comprising power lines arranged parallel to the data lines, and including a first power line and a second power line spaced apart from each other.

3. The display device according to claim 2, wherein, The bridge section is arranged in the gap between the first power line and the second power line.

4. The display device according to claim 2, wherein, The power lines and the data lines are arranged on the same layer.

5. The display device according to claim 2, further comprising a conductive pattern that electrically connects the first power line to the second power line.

6. The display device according to claim 5, wherein, The conductive pattern and the wiring are arranged in the same layer.

7. A display device, comprising: Data cable extending in the first direction; A scan line extending along a second direction that intersects the first direction; The wiring extends parallel to the data line or the scan line and includes branches protruding in a direction perpendicular to the extension direction of the wiring. as well as A bridge portion that overlaps with a portion of the wiring. The bridge portion includes: A first bridge electrode is disposed on the lower layer of the data line and at least partially overlaps with the data line, and is insulated from the data line; and The second bridge electrode is disposed in the same layer as the data line and at least partially overlaps with the first bridge electrode and the wiring, and is electrically connected to the first bridge electrode and the wiring. The display device further includes: An inorganic insulating layer between the first bridge electrode and the data line; and An organic insulating layer between the data line and the wiring.

8. The display device according to claim 7, further comprising power lines arranged parallel to the data lines, and including a first power line and a second power line spaced apart from each other.

9. The display device according to claim 8, wherein, The bridge section is arranged in the gap between the first power line and the second power line.

10. The display device according to claim 8, wherein, The power lines and the data lines are arranged on the same layer.

11. The display device of claim 8, further comprising a conductive pattern electrically connecting the first power line to the second power line.

12. The display device according to claim 11, wherein, The conductive pattern and the wiring are arranged in the same layer.

13. The display device according to claim 7, in, The wiring includes a first portion extending along the first direction and a second portion extending along the second direction, and the branch includes a first branch protruding from the first portion of the wiring along the second direction and a second branch protruding from the second portion of the wiring along the first direction. The second bridge electrode overlaps with the second branch of the second portion of the wiring or with the first portion of the wiring.

14. A display device, comprising: Data cable extending in the first direction; A scan line extending along a second direction that intersects the first direction; The wiring extends parallel to the data line or the scan line and includes branches protruding in a direction perpendicular to the extension direction of the wiring. as well as A bridge portion that overlaps with a portion of the wiring. The bridge portion includes bridge electrodes, which are arranged in the same layer as the data line and at least partially overlap with the wiring, and are electrically connected to the wiring. The display device further includes: Inorganic insulating layer; and An organic insulating layer on top of the inorganic insulating layer, The bridge electrode is disposed between the inorganic insulating layer and the organic insulating layer, and The inorganic insulating layer includes at least one of a hole overlapping the data line and a hole overlapping the bridge electrode.

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