A lateral conduction GaN hybrid pn Schottky power diode and its preparation method

Abstract

The invention discloses a lateral conduction GaN hybrid pn Schottky power diode and a preparation method thereof. The diode comprises a substrate layer, a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer which are arranged in sequence from bottom to top, wherein a GaN channel layer is arranged on a portion of the upper surface of the GaN epitaxial layer not covered by the p-GaN buried layer, and the GaN channel layer also covers a portion of the upper surface of the p-GaN buried layer; a barrier layer is arranged on the upper surface of the GaN channel layer; a p-GaN cap layer and an ohmic contact electrode are arranged on both sides of the upper surface of the barrier layer, respectively, and the p-GaN cap layer is located above the p-GaN buried layer; and a Schottky electrode is arranged on the upper surface of the p-GaN cap layer and on a portion of the upper surface of the p-GaN buried layer not covered by the GaN channel layer. Based on the groove anode structure that reduces the on-state voltage of the Schottky diode, the present invention uses a p-GaN buried layer to form a parallel pn junction diode, thereby improving the surge current resistance and reducing the on-state resistance of the device, and at the same time uses a p-GaN cap layer to improve the reverse withstand voltage capability.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic devices, and in particular relates to a lateral conduction GaN hybrid pn Schottky power diode and a preparation method thereof. Background Art

[0002] AlGaN / GaN-based diodes are very promising for use in power switching devices due to their high electron mobility, high critical breakdown electric field, and high saturated electron velocity caused by two-dimensional electron gas (2DEG). Typically, power rectifier diodes trade off between two conflicting characteristics, namely high off-state withstand voltage and low forward loss. Conventional planar AlGaN / GaN Schottky Barrier Diodes (SBDs) typically exhibit a high forward conduction voltage, which results in considerable conduction losses. The forward conduction voltage can be effectively reduced by selecting an anode metal with a lower work function, but this will increase the reverse off-state leakage current.

[0003] Recent studies have shown that AlGaN / GaN-based groove-structured anode Schottky barrier diodes can effectively balance the on-state voltage and off-state withstand voltage, but the sharp corners at the bottom of the grooves increase the risk of electric field concentration and early breakdown under high reverse bias. In addition, when current overshoot or oscillation occurs, power devices usually withstand high surge currents, while conventional Schottky diodes have relatively weak surge current resistance, so it is necessary to design some new device structures. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a lateral conduction GaN hybrid pn Schottky power diode and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] One aspect of the present invention provides a lateral conduction GaN hybrid pn Schottky power diode, comprising a substrate layer, a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer arranged in sequence from bottom to top, wherein:

[0006] A GaN channel layer is provided on a portion of the upper surface of the GaN epitaxial layer that is not covered by the p-GaN buried layer, and the GaN channel layer also covers a portion of the upper surface of the p-GaN buried layer;

[0007] A barrier layer is provided on the upper surface of the GaN channel layer;

[0008] A p-GaN capping layer and an ohmic contact electrode are respectively arranged on both sides of the upper surface of the barrier layer, and the p-GaN capping layer is located above the p-GaN buried layer;

[0009] The upper surface of the p-GaN cap layer and the portion of the upper surface of the p-GaN buried layer not covered by the GaN channel layer are provided with Schottky electrodes.

[0010] In one embodiment of the present invention, the Schottky electrode has an L-shaped cross-section, including a transverse portion and a longitudinal portion, wherein the transverse portion covers the upper surface of the p-GaN cap layer, the longitudinal portion is located on the upper surface of the p-GaN buried layer, and the inner side wall of the longitudinal portion contacts the side wall of the GaN channel layer, the side wall of the barrier layer and the side wall of the p-GaN cap layer in sequence from bottom to top.

[0011] In one embodiment of the present invention, the Schottky electrode forms an ohmic contact with the p-GaN buried layer and the p-GaN cap layer; the Schottky electrode forms a Schottky contact with the GaN channel layer and the barrier layer.

[0012] In one embodiment of the present invention, the substrate layer is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate or a GaN self-supporting substrate, and the stress buffer layer is any one of AlN, AlGaN or GaN or a combination thereof.

[0013] In one embodiment of the present invention, the p-GaN buried layer is a Mg-doped GaN material with a hole concentration of 10 14 -10 20 cm -3 .

[0014] In one embodiment of the present invention, the p-GaN capping layer is a Mg-doped GaN material with a hole concentration of 10 14 -10 20 cm -3 .

[0015] In one embodiment of the present invention, the material of the Schottky electrode is Pt, Ni or titanium nitride.

[0016] Another aspect of the present invention provides a method for preparing a lateral conduction GaN hybrid pn Schottky power diode, which is used to prepare the lateral conduction GaN hybrid pn Schottky power diode described in any one of the above embodiments, and the preparation method comprises:

[0017] S1: growing a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer in sequence on the substrate layer;

[0018] S2: performing selective area etching on the p-GaN buried layer to expose at least a portion of the GaN epitaxial layer;

[0019] S3: growing a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer in sequence on the upper surfaces of the GaN epitaxial layer and the p-GaN buried layer;

[0020] S4: performing selective area etching on the p-GaN cap layer to expose at least a portion of the AlGaN barrier layer;

[0021] S5: growing an ohmic contact electrode on the upper surface of the AlGaN barrier layer;

[0022] S6: etching downward from the upper surface edge of the p-GaN cap layer to the upper surface of the p-GaN buried layer to expose at least a portion of the p-GaN buried layer to form a recessed anode region;

[0023] S7: Depositing metal on the upper surface of the p-GaN cap layer and in the recessed anode region to form a Schottky electrode.

[0024] In one embodiment of the present invention, the S2 includes:

[0025] The p-GaN buried layer is selectively etched using a photoresist or a silicon oxide mask to expose at least a portion of the GaN epitaxial layer.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The lateral conduction type GaN hybrid pn Schottky power diode of this embodiment deposits metal electrodes on the upper surface of the p-GaN cap layer and in the groove anode region. Since the metal electrode and the two-dimensional electron gas channel on the side wall of the groove form a Schottky contact with a low barrier height, this part is turned on first at a lower forward voltage, thereby reducing the turn-on voltage of the entire diode. The metal electrode and the p-GaN buried layer and the p-GaN cap layer on the surface form an ohmic contact. When the forward voltage is further increased, the p-GaN cap layer and the AlGaN / GaN and the p-GaN buried layer and the GaN channel layer The pn junction is turned on. Compared with traditional Schottky diodes, PN diodes have better avalanche breakdown strength under surge current. Therefore, due to the introduction of these two layers of p-GaN, the device forms a composite structure of a Schottky diode and a pn junction diode, which improves the surge current resistance and greatly reduces the on-resistance of the device. In the reverse voltage state, the pn junction formed by the p-GaN cap layer and the AlGaN / GaN is reverse biased to deplete the two-dimensional electron gas channel, and at the same time, the electric field edge gathering phenomenon at the bottom of the groove is shielded, which can further enhance the reverse breakdown characteristics. The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1It is a schematic structural diagram of a lateral conduction GaN hybrid pn Schottky power diode provided by an embodiment of the present invention;

[0029] Figure 2 It is a flow chart of a method for preparing a lateral conduction GaN hybrid pn Schottky power diode provided by an embodiment of the present invention;

[0030] Figure 3a to Figure 3g It is a schematic diagram of the preparation process of a lateral conduction GaN hybrid pn Schottky power diode provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a lateral conduction GaN hybrid pn Schottky power diode and a preparation method thereof proposed in accordance with the present invention are described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0032] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0033] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0034] Embodiment 1

[0035] See also Figure 1 , Figure 1It is a structural schematic diagram of a lateral conduction GaN hybrid pn Schottky power diode provided by an embodiment of the present invention. The power diode includes a substrate layer 1, a stress buffer layer 2, a GaN epitaxial layer 3 and a p-GaN buried layer 4 arranged in sequence from bottom to top, wherein a GaN channel layer 5 is provided on the portion of the upper surface of the GaN epitaxial layer 3 not covered by the p-GaN buried layer 4, and the GaN channel layer 5 also covers a portion of the upper surface of the p-GaN buried layer 4; a barrier layer 6 is provided on the upper surface of the GaN channel layer 5; a p-GaN cap layer 7 and an ohmic contact electrode 8 are respectively provided on both sides of the upper surface of the barrier layer 6, and the p-GaN cap layer 7 is located above the p-GaN buried layer 4; a Schottky electrode 9 is provided on the upper surface of the p-GaN cap layer 7 and the portion of the upper surface of the p-GaN buried layer 4 not covered by the GaN channel layer 5.

[0036] In this embodiment, the Schottky electrode 9 has an L-shaped cross-section, including a transverse portion 91 and a longitudinal portion 92, wherein the transverse portion 91 covers the upper surface of the p-GaN cap layer 7, and the longitudinal portion 92 is located on the upper surface of the p-GaN buried layer 4, and the inner side wall of the longitudinal portion 92 contacts the side wall of the GaN channel layer 5, the side wall of the barrier layer 6 and the side wall of the p-GaN cap layer 7 from bottom to top, wherein the Schottky electrode 9 forms an ohmic contact with the p-GaN buried layer 4 and the p-GaN cap layer 7; the Schottky electrode 9 forms a Schottky contact with the GaN channel layer 5 and the barrier layer 6.

[0037] Further, the substrate layer 1 is any one of Si substrate, sapphire substrate, silicon carbide substrate or GaN self-supporting substrate, the stress buffer layer 2 is any one of AlN, AlGaN or GaN or a combination thereof, and the thickness of the stress buffer layer 2 is 10nm-100μm.

[0038] Preferably, the GaN epitaxial layer 3 is an unintentionally doped GaN epitaxial layer with a thickness of 100nm-100μm; the p-GaN buried layer 4 is a Mg-doped GaN material with a thickness of 100nm-10μm and a hole concentration of 10 14 -10 20 cm -3 The GaN channel layer 5 is an unintentionally doped GaN epitaxial layer with a thickness of 100nm-100μm; the barrier layer 6 has a thickness of 6nm-30nm, and the aluminum component concentration can be varied below 30%; the p-GaN cap layer 7 is a Mg-doped GaN material with a thickness of 100nm-10μm and a hole concentration of 10 14 -10 20 cm -3 .

[0039] In this embodiment, the material of the barrier layer 6 is one of AlInN, InGaN, AlInGaN, AlN or any combination of them; the material of the ohmic contact electrode 8 is Ti / Al / Ni / Au alloy, Ti / Al / Ti / Au alloy, Ti / Al / Mo / Au alloy or Ti / Al / Ti / TiN alloy; the material of the Schottky electrode 9 is Pt, Ni or titanium nitride with good thermal stability.

[0040] In traditional devices, the p-GaN buried layer is mainly used to improve the reverse withstand voltage and will damage the conduction characteristics to a certain extent, and is not used to improve the surge current resistance. In the lateral conduction GaN hybrid pn Schottky power diode of this embodiment, metal electrodes are deposited on the upper surface of the p-GaN cap layer and in the groove anode area. Since the metal electrode and the two-dimensional electron gas channel on the side wall of the groove form a Schottky contact with a low barrier height, this part is turned on first at a lower forward voltage, thereby reducing the conduction voltage of the entire diode. The metal electrode and the p-GaN buried layer and the p-GaN cap layer on the surface form an ohmic contact. When the forward voltage is further increased, the p-GaN cap layer and AlGaN / GaN and the p-GaN buried layer and GaN channel layer The pn junction is turned on. Compared with traditional Schottky diodes, PN diodes have better avalanche breakdown strength under surge currents. Therefore, due to the introduction of these two layers of p-GaN, the device forms a composite structure of Schottky diode and pn junction diode, which improves the surge current resistance and greatly reduces the on-resistance of the device. In the reverse voltage state, the pn junction formed by the p-GaN cap layer and AlGaN / GaN is reverse biased to deplete the two-dimensional electron gas channel, and at the same time, it will shield the electric field edge gathering phenomenon at the bottom of the groove, which can further enhance the reverse breakdown characteristics.

[0041] Embodiment 2

[0042] Based on the above embodiments, this embodiment provides a method for preparing a lateral conduction GaN hybrid pn Schottky power diode, which is used to prepare the lateral conduction GaN hybrid pn Schottky power diode described in Embodiment 1. Figure 2 , Figure 3a to Figure 3g , Figure 2 It is a flow chart of a method for preparing a lateral conduction GaN hybrid pn Schottky power diode provided by an embodiment of the present invention; Figure 3a to Figure 3g It is a schematic diagram of the preparation process of a lateral conduction GaN hybrid pn Schottky power diode provided in an embodiment of the present invention.

[0043] The preparation method of this embodiment includes:

[0044] S1: A stress buffer layer 2, a GaN epitaxial layer 3 and a p-GaN buried layer 4 are sequentially grown on a substrate layer 1, such as Figure 3a shown.

[0045] In this embodiment, the substrate layer 1 is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate or a GaN self-supporting substrate. In other embodiments, the substrate layer 1 may also be a multi-layer epitaxial substrate with different components.

[0046] The stress buffer layer 2 is any one of AlN, AlGaN or GaN or a combination thereof, and the thickness of the stress buffer layer 2 is 10 nm-100 μm.

[0047] The GaN epitaxial layer 3 is an unintentionally doped GaN epitaxial layer with a thickness of 100nm-100μm; the p-GaN buried layer 4 is a Mg-doped GaN material with a thickness of 100nm-10μm and a hole concentration of 10 14 -10 20 cm -3 .

[0048] In this embodiment, the stress buffer layer 2, the GaN epitaxial layer 3, and the p-GaN buried layer 4 can all be grown by metal organic chemical vapor deposition or molecular beam epitaxy. In other embodiments, the p-GaN buried layer 4 can also be grown by ion implantation.

[0049] In other embodiments, the GaN template material with the p-GaN buried layer may be directly obtained for subsequent preparation.

[0050] S2: selectively etching the p-GaN buried layer 4 to expose at least a portion of the GaN epitaxial layer 3, such as Figure 3b shown.

[0051] The p-GaN buried layer 4 is etched in a selected area using a photoresist or silicon oxide mask 10 to achieve patterning. Specifically, in this embodiment, a spinner is used to spin the photoresist on the upper surface of the p-GaN buried layer 4, and then the device sample is placed in a photolithography machine to expose the photoresist in the area to be etched; finally, the device sample after exposure is placed in a developer to remove the photoresist in the area to be etched; for the sample after photolithography, the p-GaN buried layer 4 is dry-etched to the surface of the GaN epitaxial layer 3 using an ICP process; finally, the sample after etching is placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution in turn for cleaning to remove the remaining photoresist.

[0052] S3: A GaN channel layer 5, an AlGaN barrier layer 6 and a p-GaN cap layer 7 are sequentially grown on the upper surfaces of the GaN epitaxial layer 3 and the p-GaN buried layer 4. Figure 3c shown.

[0053] The GaN channel layer 5 is an unintentionally doped GaN epitaxial layer with a thickness of 100nm-100μm; the barrier layer 6 has a thickness of 6-30nm, and the aluminum component concentration can be varied below 30%; the p-GaN cap layer 7 is a Mg-doped GaN material with a thickness of 100nm-10μm and a hole concentration of 10 14 -10 20 cm -3 .

[0054] In this embodiment, the GaN channel layer 5, the AlGaN barrier layer 6 and the p-GaN cap layer 7 can all be grown by metal organic chemical vapor deposition or molecular beam epitaxy. In other embodiments, the p-GaN cap layer 7 can also be grown by ion implantation.

[0055] S4: performing selective area etching on the p-GaN cap layer 7 to expose at least a portion of the AlGaN barrier layer 6;

[0056] The p-GaN capping layer 7 is etched in a selected area using a photoresist 10 or a silicon oxide mask to achieve patterning. Specifically, in this embodiment, a spinner is used to spin the photoresist on the upper surface of the p-GaN capping layer 7, and then the device sample is placed in a photolithography machine to expose the photoresist in the area to be etched; finally, the device sample after exposure is placed in a developer to remove the photoresist in the area to be etched; for the sample after photolithography, the p-GaN capping layer 7 is dry-etched to the surface of the AlGaN barrier layer 6 using an ICP process; finally, the sample after etching is placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution in turn for cleaning to remove the remaining photoresist.

[0057] S5: growing an ohmic contact electrode 8 on the upper surface of the AlGaN barrier layer 6, such as Figure 3e shown.

[0058] In this embodiment, the material of the ohmic contact electrode 8 is Ti / Al / Ni / Au alloy, Ti / Al / Ti / Au alloy, Ti / Al / Mo / Au alloy or Ti / Al / Ti / TiN alloy.

[0059] The ohmic contact electrode 8 can be prepared by magnetron sputtering, electron beam evaporation or thermal evaporation.

[0060] S6: Etching from the upper surface edge of the p-GaN cap layer 7 downward to the upper surface of the p-GaN buried layer 4 to expose at least a portion of the p-GaN buried layer 4 to form a recessed anode region, such as Figure 3f shown.

[0061] In this embodiment, the recessed anode region may be etched using inductively coupled plasma etching, reactive ion etching or ion milling.

[0062] S7: Depositing metal on the upper surface of the p-GaN cap layer 7 and in the groove anode region to form a Schottky electrode 9, such as Figure 3g shown.

[0063] Preferably, the Schottky electrode 9 can be prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, etc. The material of the Schottky electrode 9 is Pt, Ni or titanium nitride with good thermal stability.

[0064] The Schottky electrode 9 of this embodiment has an L-shaped cross-section, including a transverse portion 91 and a longitudinal portion 92, wherein the transverse portion 91 covers the upper surface of the p-GaN cap layer 7, and the longitudinal portion 92 is located on the upper surface of the p-GaN buried layer 4, and the inner side wall of the longitudinal portion 92 contacts the side wall of the GaN channel layer 5, the side wall of the barrier layer 6 and the side wall of the p-GaN cap layer 7 from bottom to top, so that the Schottky electrode 9 forms an ohmic contact with the p-GaN buried layer 4 and the p-GaN cap layer 7, and the Schottky electrode 9 forms a Schottky contact with the GaN channel layer 5 and the barrier layer 6.

[0065] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A lateral conduction GaN hybrid pn Schottky power diode, characterized in that: It comprises a substrate layer (1), a stress buffer layer (2), a GaN epitaxial layer (3) and a p-GaN buried layer (4) which are arranged in sequence from bottom to top, wherein: A GaN channel layer (5) is provided on a portion of the upper surface of the GaN epitaxial layer (3) not covered by the p-GaN buried layer (4), and the GaN channel layer (5) also covers a portion of the upper surface of the p-GaN buried layer (4); A barrier layer (6) is provided on the upper surface of the GaN channel layer (5); A p-GaN cap layer (7) and an ohmic contact electrode (8) are respectively arranged on both sides of the upper surface of the barrier layer (6), and the p-GaN cap layer (7) is located above the p-GaN buried layer (4); The upper surface of the p-GaN cap layer (7) and the portion of the upper surface of the p-GaN buried layer (4) not covered by the GaN channel layer (5) are provided with a Schottky electrode (9); The p-GaN buried layer (4) is made of Mg-doped GaN material with a hole concentration of 10 14 -10 20 cm -3 .

2. The lateral conduction GaN hybrid pn Schottky power diode according to claim 1, characterized in that: The Schottky electrode (9) has an L-shaped cross section, comprising a transverse portion (91) and a longitudinal portion (92), wherein the transverse portion (91) covers the upper surface of the p-GaN cap layer (7), the longitudinal portion (92) is located on the upper surface of the p-GaN buried layer (4), and the inner side wall of the longitudinal portion (92) contacts the side wall of the GaN channel layer (5), the side wall of the barrier layer (6), and the side wall of the p-GaN cap layer (7) in sequence from bottom to top.

3. The lateral conduction GaN hybrid pn Schottky power diode according to claim 2, characterized in that: The Schottky electrode (9) forms an ohmic contact with the p-GaN buried layer (4) and the p-GaN cap layer (7); and the Schottky electrode (9) forms a Schottky contact with the GaN channel layer (5) and the barrier layer (6).

4. The lateral conduction GaN hybrid pn Schottky power diode according to claim 1, characterized in that: The substrate layer (1) is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate or a GaN self-supporting substrate, and the stress buffer layer (2) is any one of AlN, AlGaN or GaN or a combination thereof.

5. The lateral conduction GaN hybrid pn Schottky power diode according to claim 1, characterized in that: The p-GaN capping layer (7) is made of Mg-doped GaN material with a hole concentration of 10 14 -10 20 cm -3 .

6. The lateral conduction GaN hybrid pn Schottky power diode according to claim 1, characterized in that: The material of the Schottky electrode (9) is Pt, Ni or titanium nitride.

7. A method for preparing a lateral conduction GaN hybrid pn Schottky power diode, characterized in that: For preparing a lateral conduction GaN hybrid pn Schottky power diode according to any one of claims 1 to 6, the preparation method comprising: S1: growing a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer in sequence on the substrate layer; S2: performing selective area etching on the p-GaN buried layer to expose at least a portion of the GaN epitaxial layer; S3: sequentially growing a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer on the upper surfaces of the GaN epitaxial layer and the p-GaN buried layer; S4: performing selective area etching on the p-GaN cap layer to expose at least a portion of the AlGaN barrier layer; S5: growing an ohmic contact electrode on the upper surface of the AlGaN barrier layer; S6: etching downward from the upper surface edge of the p-GaN cap layer to the upper surface of the p-GaN buried layer to expose at least a portion of the p-GaN buried layer to form a recessed anode region; S7: Depositing metal on the upper surface of the p-GaN cap layer and in the recessed anode region to form a Schottky electrode.

8. The method for preparing a lateral conduction GaN hybrid pn Schottky power diode according to claim 7, characterized in that: The S2 includes: The p-GaN buried layer is selectively etched using a photoresist or a silicon oxide mask to expose at least a portion of the GaN epitaxial layer.

Images