High-speed low-dark-current three-step structure avalanche photodetector and preparation method thereof

Abstract

The invention relates to a high-speed low-dark-current three-step structure avalanche photodetector and a preparation method thereof, and belongs to the technical field of semiconductor devices. Comprising an intrinsic InP substrate, an N-type InAlAs ohmic contact layer, an intrinsic InAlAs transition layer, an N-type InAlAs charge layer, an intrinsic InAlAs multiplication layer, a P-type InAlAs charge layer, an intrinsic InAlGaAs transition layer, an intrinsic InGaAs absorption layer, a gradient-doped P-type InGaAs absorption layer and a P-type InAlAs ohmic contact layer which are stacked from bottom to top. The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are both of a step structure so as to form a three-stage step structure of the photoelectric detector. According to the invention, through growing the SiNx antireflection film with the refractive index of 1.85 and the thickness of 210 nm on the light incident surface, the reflectivity of incident light can be less than 1%. For an optical signal with the wavelength of 1550 nm, the single light absorption quantum efficiency can reach 0.45.

Description

Technical Field

[0001] The invention relates to the field of semiconductor devices, and in particular to a high-speed, low dark current avalanche photodetector with a three-step structure. Background Art

[0002] With the increasing demand for information transmission, there are higher requirements for the transmission speed and distance of optical communication. As an important receiving device in optical communication, semiconductor photodetectors play a vital role. The main indicators for evaluating the performance of photodetectors include 3dB bandwidth, dark current, responsivity and quantum efficiency.

[0003] Compared with PIN photodetectors, avalanche photodetectors (APDs) can improve the sensitivity of receivers without amplifiers due to their internal gain of photocurrent. Therefore, they are increasingly used in optical communications.

[0004] Commonly used high-speed avalanche photodetectors use a separated absorption charge multiplication structure. In order to increase the device response speed, the depletion region length needs to be reduced to reduce the carrier transit time, but the reduction in the absorption region thickness will lead to a decrease in responsiveness. In addition, in order to reduce the impact ionization time required for APD to obtain the same gain, the multiplication layer thickness should be reduced. However, when the multiplication layer thickness is reduced, the electric field strength required to induce impact ionization will increase, which will increase the tunneling current in the multiplication region. Due to the high electric field strength at the edge of the multiplication region, the requirements for the passivation layer are higher. When the passivation effect is not good, leakage current and edge breakdown are easily introduced, reducing the reliability of the device. Therefore, in order to obtain a high-speed, low dark current avalanche photodetector, it is necessary not only to solve the contradiction between bandwidth and responsiveness and dark current, but also to use materials with better density and electrical insulation as the passivation layer. Summary of the invention

[0005] In view of this, the purpose of the present invention is to overcome the shortcomings and deficiencies of the prior art, optimize the epitaxy, structure and preparation process of the avalanche photodetector, and provide a three-step structure avalanche photodetector with high speed and low dark current, thereby obtaining a high-speed, low dark current avalanche photodetector.

[0006] The present invention adopts the following technical solutions to achieve the above technical effects:

[0007] A high-speed, low-dark-current three-step-structure avalanche photodetector, comprising an intrinsic InP substrate 1, an N-type InAlAs ohmic contact layer 2, an intrinsic InAlAs transition layer 3, an N-type InAlAs charge layer 4, an intrinsic InAlAs multiplication layer 5, a P-type InAlAs charge layer 6, an intrinsic InAlGaAs transition layer 7, an intrinsic InGaAs absorption layer 8, a gradient-doped P-type InGaAs absorption layer 9 and a P-type InAlAs ohmic contact layer 10 stacked from bottom to top;

[0008] The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are both step structures to form a three-level step structure of the photodetector;

[0009] A passivation layer 14 is provided on the upper surface of the P-type InAlAs ohmic contact layer 10; the P electrode passes through the passivation layer 14 and contacts the upper surface of the P-type InAlAs ohmic contact layer 10;

[0010] The passivation layer 14 sequentially covers the side surface of the P-type InAlAs ohmic contact layer 10, the side surface of the gradient-doped P-type InGaAs absorption layer 9, the side surface and step surface of the intrinsic InGaAs absorption layer 8, the side surface of the intrinsic InAlGaAs transition layer 7, the side surface of the P-type InAlAs charge layer 6, the side surface of the intrinsic InAlAs multiplication layer 5, the side surface of the N-type InAlAs charge layer 4, the side surface of the intrinsic InAlAs transition layer 3, and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer 2 from the upper surface of the P-type InAlAs ohmic contact layer 10;

[0011] The N-electrode 12 passes through the passivation layer 14 and contacts the step surface of the N-type InAlAs ohmic contact layer 2 .

[0012] Furthermore, the P electrode is a circular ring structure.

[0013] Furthermore, the area surrounded by the P electrode serves as an incident window.

[0014] Furthermore, the N-electrode 12 is an N-electrode window.

[0015] A method for preparing a high-speed, low-dark-current three-step-structure avalanche photodetector is provided, and the specific process is as follows:

[0016] Step 1, using an epitaxial growth process to grow an epitaxial structure of an avalanche photodetector on an intrinsic InP substrate 1;

[0017] Step 2, using a photolithography process, photolithography a P electrode pattern on the top surface of the epitaxial structure, leaving an incident window 13, and sputtering a P electrode with a glue; then, using a lift-off process to prepare a P electrode 11;

[0018] Step 3, using a photolithography process to photolithograph a first-level step pattern on the epitaxial structure; using a wet etching process to etch the epitaxial structure portion of the first-level step from top to bottom until the intrinsic InGaAs absorption region stops, forming a first-level step structure 15;

[0019] Step 4, using a photolithography process to photolithograph a second-level step pattern on the epitaxial structure, wherein the radius of the second-level step pattern is larger than that of the first-level step structure; using a wet etching process, continuing to etch until the N-type InAlAs ohmic contact layer 2 stops, thereby preparing a second-level step structure 16;

[0020] Step 5, using a photolithography process to photoetch a third-level step pattern on the front side of the epitaxial substrate; using a wet etching process, etching into the epitaxial substrate and stopping to form a third-level step structure; the depth of etching into the epitaxial substrate should be greater than 0.3 μm to form a good electrical isolation; wherein, a phosphoric acid etching solution is used to etch the N-type InAlAs ohmic contact layer 2, and a bromine water etching solution is used to etch the InP epitaxial substrate;

[0021] Step 6: Using plasma enhanced chemical vapor deposition process, grow 100nm SiO2 and 210nm thick SiN with a refractive index of 1.85 on the epitaxial structure. x Thin film, passivation layer 14, SiN x At the same time, the antireflection film used as the incident window 13 has a growth temperature between 200°C and 300°C;

[0022] Step 7, using photolithography to pattern the N electrode window 18 and the P electrode window on the epitaxial structure; using wet etching to etch away the SiO2 and SiN at the electrode window. x , forming N-electrode and P-electrode windows;

[0023] Step 8, using a photolithography process, re-etching the N electrode window; sputtering Au / Ge / Ni / Au with glue, and then peeling off the N electrode 12;

[0024] Step 9, using a photolithography process, photolithography N electrode lead and P electrode lead windows are formed on the epitaxial structure; Ti / Au is sputtered with a resin, and then the N electrode lead 19 and the P electrode lead 20 are peeled off;

[0025] Step 10, using a rapid annealing alloy process at a temperature of 390° C. for 40 seconds to form a good ohmic contact between the semiconductor device and the metal;

[0026] Step 11, thinning and polishing the back side of the epitaxial structure;

[0027] Step 12, cleaving the epitaxial wafer and dividing it into independent devices.

[0028] Furthermore, the etching solution used in step 3 and step 4 is phosphoric acid etching solution; and the etching solution selected in step 7 is BOE etching solution.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] 1. The use of partially doped InGaAs absorption regions solves the contradiction between APD bandwidth and responsivity. The partially doped absorption region design can minimize the transit time required by carriers in the absorption region by adjusting the ratio of the p-type doped absorption region and the intrinsic absorption region while keeping the total absorption layer thickness unchanged, that is, the corresponding quantum efficiency unchanged, thereby improving the device bandwidth. The absorption region is designed to be a 0.3μm P-type gradient doped region and a 0.3μm intrinsic region, with a total thickness of 0.6μm. And by growing a 210nm thick SiN with a refractive index of 1.85 on the light incident surface x The anti-reflection film can reduce the reflectivity of incident light to less than 1%. For a light signal with a wavelength of 1550nm, the quantum efficiency of single light absorption can reach 0.45.

[0031] 2. The SAGCMCT structure can reduce the device capacitance while ensuring that the original carrier transit time remains unchanged, thereby increasing the APD bandwidth. Since the impact ionization coefficient of electrons in InAlAs materials is greater than that of holes, in order to reduce excess noise, the photogenerated electrons are injected into the multiplication region to induce avalanche multiplication. The multiplied electrons generated by impact ionization drift toward the N-type charge layer and transition layer, while the multiplied holes drift toward the P-type charge layer, transition layer and absorption layer; while keeping the original absorption layer, transition layer, P-type charge layer and multiplication layer thickness unchanged, a 0.3μm thick transition layer and a 70nm thick N-type charge layer are used to make the multiplied electron transit time less than the multiplied holes, so that the total carrier transit time remains unchanged. In addition, the newly added N-type charge and transition layer can increase the thickness of the depletion region, thereby reducing the device capacitance and increasing the bandwidth.

[0032] 3. Using 0.12μm thick InAlAs material as the multiplication layer can improve the APD bandwidth while reducing the generation of tunneling current. The thinner the multiplication layer, the shorter the time required for impact ionization when obtaining the same gain, thereby improving the APD bandwidth, but the tunneling current in the multiplication region will also increase. Using 0.12μm thick InAlAs as the multiplication layer can reduce the impact ionization time while limiting the tunneling dark current before breakdown to less than 0.5μA.

[0033] 4. Use PECVD process to grow SiO2 and SiN x As a double passivation layer, it is different from the traditional one that only uses SiO2 and SiN xCompared with a single-layer passivation layer, the APD table edge leakage current can be effectively reduced. The dark current of the prepared APD at 0.9 times the breakdown voltage is less than 10nA, which is much lower than the same type of high-speed avalanche photodetector.

[0034] 5. By using a three-step structure, the electric field strength at the edge of the multiplication region is reduced. When the central electric field strength of the multiplication layer is 770 kV / cm, the electric field strength at the edge of the multiplication layer is reduced to below 650 kV / cm, which greatly reduces the edge leakage current, inhibits the occurrence of edge breakdown, and improves the reliability of the APD.

[0035] The three-step structure SAGCMCT-APD prepared by the above technical solution greatly reduces the dark current while improving the device bandwidth, making the APD achieve excellent performance. The 3dB bandwidth is about 20GHz at 5 times the gain, and the dark current is 6.7nA at 0.9 times the breakdown voltage. The device is expected to be used in 25Gbps high-speed and high-sensitivity optical communication receivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a cross-sectional schematic diagram of a high-speed, low dark current three-step structure avalanche photodetector chip.

[0037] Figure 2 This is a schematic diagram of the structure of the N stage in the APD chip ( Figure 1 ).

[0038] Figure 3 This is a schematic diagram of the front structure of the APD chip.

[0039] In the figure: 1. Intrinsic InP substrate; 2. N-type InAlAs ohmic contact layer; 3. Intrinsic InAlAs transition layer; 4. N-type InAlAs charge layer; 5. Intrinsic InAlAs multiplication layer; 6. P-type InAlAs charge layer; 7. Intrinsic InAlGaAs transition layer; 8. Intrinsic InGaAs absorption layer; 9. Gradient-doped P-type InGaAs absorption layer; 10. P-type InAlAs ohmic contact layer; 11. P electrode, which is a circular ring structure; 12. N electrode; 13. Incident window; 14. Passivation layer. 11. P electrode, which is a circular ring structure; 13. Incident window; 15. First step; 16. Second step; 17. Third step, i.e., N platform; 18. N electrode window. 13. Incident window; 15. First step; 16. Second step; 17. Third step, i.e., N platform; 19. N electrode lead; 20. P electrode lead. DETAILED DESCRIPTION

[0040] Below, the present invention is further described in conjunction with the accompanying drawings.

[0041] The various performances of high-speed, low dark current avalanche photodetectors are mutually restricted. The following problems need to be solved:

[0042] The contradiction between bandwidth and responsivity at unit gain. To improve the responsivity of an avalanche photodetector at unit gain, the thickness of the intrinsic absorption layer is usually increased. However, when the intrinsic absorption region is completely depleted, the carrier transit time is prolonged, affecting the 3dB bandwidth of the device.

[0043] The contradiction between bandwidth and dark current. The impact ionization time of photogenerated carriers in the multiplication region increases with the increase of gain. At high gain, the impact ionization time will gradually become the main factor limiting the 3dB bandwidth of the device. For the same semiconductor material, the thinner the multiplication layer thickness, the smaller the impact ionization time when the same gain is obtained, but the higher the electric field strength required for impact ionization, the greater the tunneling dark current.

[0044] High-speed APD can improve bandwidth by reducing the active area and thus reducing device capacitance, so a mesa structure is often used. However, in the commonly used mesa structure, the leakage current caused by defects and impurities at the edge of the multiplication layer will increase with the increase of the electric field strength, and it is also easy to produce edge breakdown, reducing device reliability. Therefore, it is crucial to reduce the electric field strength at the edge of the multiplication layer of the mesa structure device, grow a dense and electrically insulating passivation layer.

[0045] The purpose of the present invention is to overcome the shortcomings and deficiencies of the prior art and optimize the epitaxy, structure and preparation process of the avalanche photodetector, so as to obtain a high-speed, low dark current avalanche photodetector.

[0046] First, in order to solve the contradiction between bandwidth and responsivity under unity gain, a partially doped InGaAs absorption region is used, including a 0.3μm thick P-type doped absorption region and a 0.3μm thick intrinsic absorption region. The P-type doped absorption region uses three layers with a thickness of 0.1μm and doping concentrations of 2.0×10 18 cm -3 , 1.4×10 18 cm -3 8.0×10 17 cm -3 In addition, a 210 nm thick SiN layer with a refractive index of 1.85 was grown on the light incident window. x As anti-reflection film.

[0047] Furthermore, in order to improve the bandwidth of APD, a new n-type charge layer and an intrinsic transition layer are added to the epitaxy of APD on the basis of the separated absorption, transition, charge, and multiplication structure, that is, a separated absorption, transition, charge (P-type doping), multiplication, charge (N-type doping), and transition structure (SAGCMCT) is adopted. The transition layer adopts a composition-gradient intrinsic In with a thickness of 30nm.0.53 Ga 0.35 Al 0.12 As、In 0.53 Ga 0.23 Al 0.24 As and In 0.52 Ga 0.12 Al 0.36 Materials: Both charge layers are 70nm thick InAlAs material, and the P-type charge layer doping concentration is 5.7×10 17 cm -3 , the doping concentration of the N-type charge layer is 5.0×10 17 cm -3 ; The transition layer uses 0.3μm intrinsic InAlAs material.

[0048] Furthermore, in order to resolve the contradiction between bandwidth and dark current, we use 0.12μm intrinsic InAlAs as the multiplication layer. Since the InAlAs material is lattice-matched with the InGaAs absorption material required for the optical communication band, the increase in dark current caused by lattice mismatch can be reduced; compared with InP, the impact ionization rate k of InAlAs is smaller, which can reduce the excess noise of APD.

[0049] Furthermore, in order to reduce the edge leakage current of the APD table, 100nm SiO2 and 210nm thick SiN were grown on the surface of the APD chip using plasma enhanced chemical vapor deposition (PECVD) technology. x The growth temperature is between 200℃-300℃ to provide better electrical insulation.

[0050] Furthermore, in order to reduce the electric field strength at the edge of the multiplication layer, a three-step APD is used. The first step is etched to the intrinsic absorption layer, which can limit the active area of ​​the device; the second step is etched to the n-ohm contact layer, which can reduce the electric field strength on the surface of the multiplication layer; the third step is etched into the insulating substrate, which plays a role in electrical isolation.

[0051] The cross-sectional structure of the high-speed, low dark current three-step structure avalanche photodetector chip in this embodiment is as follows: Figure 1 As shown; this embodiment includes an intrinsic InP substrate 1, an N-type InAlAs ohmic contact layer 2, an intrinsic InAlAs transition layer 3, an N-type InAlAs charge layer 4, an intrinsic InAlAs multiplication layer 5, a P-type InAlAs charge layer 6, an intrinsic InAlGaAs transition layer 7, an intrinsic InGaAs absorption layer 8, a gradient-doped P-type InGaAs absorption layer 9 and a P-type InAlAs ohmic contact layer 10 stacked from bottom to top;

[0052] The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are both step structures to form a three-level step structure of the photodetector;

[0053] A passivation layer 14 is provided on the upper surface of the P-type InAlAs ohmic contact layer 10; the P electrode passes through the passivation layer 14 and contacts the upper surface of the P-type InAlAs ohmic contact layer 10;

[0054] The passivation layer 14 sequentially covers the side surface of the P-type InAlAs ohmic contact layer 10, the side surface of the gradient-doped P-type InGaAs absorption layer 9, the side surface and step surface of the intrinsic InGaAs absorption layer 8, the side surface of the intrinsic InAlGaAs transition layer 7, the side surface of the P-type InAlAs charge layer 6, the side surface of the intrinsic InAlAs multiplication layer 5, the side surface of the N-type InAlAs charge layer 4, the side surface of the intrinsic InAlAs transition layer 3, and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer 2 from the upper surface of the P-type InAlAs ohmic contact layer 10;

[0055] The N-electrode 12 passes through the passivation layer 14 and contacts the step surface of the N-type InAlAs ohmic contact layer 2 .

[0056] The P electrode is a ring structure. The area surrounded by the P electrode serves as an incident window. The N electrode 12 is an N electrode window.

[0057] The specific preparation method of the detector chip comprises the following steps:

[0058] 1) An epitaxial growth process is used to grow an epitaxial structure 2-10 of an avalanche photodetector on an intrinsic InP substrate 1; wherein the transition layer 3 is 0.3 μm, the multiplication layer 5 is 0.12 μm, and the intrinsic absorption layer 8 and the gradient-doped P-type absorption layer 9 are both 0.3 μm.

[0059] 2) Using photolithography technology, a P electrode pattern is patterned on the front side of the epitaxial layer. The P electrode is a circular ring structure with an incident window 13. The P electrode is sputtered with a glue and the material is Ti / Au. The P electrode 11 is prepared by a lift-off process.

[0060] 3) Using photolithography, photolithography the first step pattern on the epitaxial front side; using wet etching, etching the epitaxial material outside the first step until it stops at the center of the intrinsic InGaAs absorption region 8, forming the first step 15, and using phosphoric acid etching solution as the etching solution.

[0061] 4) Using photolithography, a second step pattern is formed on the front side of the epitaxial growth, and the radius of the pattern is slightly larger than that of the first step. Using wet etching, the etching stops at the N-type InAlAs ohmic contact layer 2 to prepare the second step 16, and phosphoric acid etching solution is used as the etching solution.

[0062] 5) A photolithography process is used to photolithograph a third step pattern on the front side of the epitaxial layer; a wet etching process is used to etch into the epitaxial substrate 1 and stop, forming a third step, namely, N platform 17. The depth of etching into the epitaxial substrate 1 should be greater than 0.3 μm to form a good electrical isolation; wherein, phosphoric acid etching solution is used to etch the N-type InAlAs ohmic contact layer 2, and bromine water etching solution is used to etch the InP epitaxial substrate 1.

[0063] 6) Using plasma enhanced chemical vapor deposition process, 100nm SiO2 and 210nm thick SiN with a refractive index of 1.85 are grown on the epitaxial front. x Thin film, passivation layer 14, SiN x At the same time, the antireflection film used as the incident window 13 has a growth temperature between 200°C and 300°C.

[0064] 7) Using photolithography, pattern the N electrode window 18 and the P electrode window on the epitaxial front; using wet etching to etch away the SiO2 and SiN at the electrode window. x , forming N electrode and P electrode windows; BOE etching solution is selected as the etching solution.

[0065] 8) Re-etch the N electrode window using a photolithography process; sputter Au / Ge / Ni / Au with glue, and then peel off the N electrode 12.

[0066] 9) Using photolithography, photolithography is performed to form N-electrode lead and P-electrode lead windows on the front side of the epitaxial growth; Ti / Au is sputtered with a resin, and then the N-electrode lead 19 and the P-electrode lead 20 are peeled off.

[0067] 10) Rapid annealing alloy process is used at a temperature of 390°C for 40 seconds to form a good ohmic contact between the semiconductor device and the metal.

[0068] 11) Thinning and polishing the back side of the epitaxial layer.

[0069] 12) Cleave the epitaxial wafer and separate it into independent devices.

[0070] At this point, the preparation of a high-speed, low dark current three-step structure avalanche photodetector has been completed.

[0071] The present invention adopts a partially doped absorption region, a 0.12 μm InAlAs multiplication region, and SiO2 and SiN grown by PECVD. x The SAGCMCT-APD with a three-step structure prepared by using double passivation layers not only improves the device bandwidth, but also greatly reduces the dark current, enabling the APD to obtain excellent performance.

[0072] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-speed, low-dark-current three-step-structure avalanche photodetector, characterized in that: The invention comprises an intrinsic InP substrate (1), an N-type InAlAs ohmic contact layer (2), an intrinsic InAlAs transition layer (3), an N-type InAlAs charge layer (4), an intrinsic InAlAs multiplication layer (5), a P-type InAlAs charge layer (6), an intrinsic InAlGaAs transition layer (7), an intrinsic InGaAs absorption layer (8), a gradient-doped P-type InGaAs absorption layer (9) and a P-type InAlAs ohmic contact layer (10) stacked from bottom to top; The intrinsic InGaAs absorption layer (8) and the N-type InAlAs ohmic contact layer (2) are both step structures to form a three-level step structure of the photodetector; A passivation layer (14) is provided on the upper surface of the P-type InAlAs ohmic contact layer (10); the P electrode passes through the passivation layer (14) and contacts the upper surface of the P-type InAlAs ohmic contact layer (10); The passivation layer (14) sequentially covers, from the upper surface of the P-type InAlAs ohmic contact layer (10), the side surface of the P-type InAlAs ohmic contact layer (10), the side surface of the gradient-doped P-type InGaAs absorption layer (9), the side surface and step surface of the intrinsic InGaAs absorption layer (8), the side surface of the intrinsic InAlGaAs transition layer (7), the side surface of the P-type InAlAs charge layer (6), the side surface of the intrinsic InAlAs multiplication layer (5), the side surface of the N-type InAlAs charge layer (4), the side surface of the intrinsic InAlAs transition layer (3), and the side surface and step surface above the step surface of the N-type InAlAs ohmic contact layer (2); The N electrode (12) passes through the passivation layer (14) and contacts the step surface of the N-type InAlAs ohmic contact layer (2).

2. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The P electrode is a circular ring structure.

3. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 2, characterized in that: The area surrounded by the P electrode serves as an incident window.

4. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The N electrode (12) is an N electrode window.

5. The high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 1, characterized in that: The N-type InAlAs ohmic contact layer comprises a stacked and integrally designed step upper portion and a step lower portion; the horizontal cross-sections of the step upper portion and the step lower portion both comprise a semicircle and a rectangle; the long side of the rectangle coincides with the diameter of the semicircle; the step surface of the N-type InAlAs ohmic contact layer (2) is a portion of the upper surface of the step lower portion; The cross section of the intrinsic InGaAs absorption layer is circular.

6. A method for preparing a high-speed, low-dark-current, three-step-structured avalanche photodetector, for preparing the high-speed, low-dark-current, three-step-structured avalanche photodetector as claimed in any one of claims 1 to 5, wherein the specific process is as follows: Step 1, using an epitaxial growth process to grow an epitaxial structure of an avalanche photodetector on an intrinsic InP substrate (1); Step 2, using a photolithography process to photolithograph a P electrode pattern on the top surface of the epitaxial structure, leaving an incident window (13), and sputtering the P electrode with glue; then, using a lift-off process to prepare the P electrode (11); Step 3, using a photolithography process to photolithograph a first-level step pattern on the epitaxial structure; using a wet etching process to etch the epitaxial structure portion of the first-level step from top to bottom until the intrinsic InGaAs absorption region stops, forming a first-level step structure (15); Step 4, using a photolithography process to photolithograph a second-level step pattern on the epitaxial structure, wherein the radius of the second-level step pattern is larger than that of the first-level step structure; using a wet etching process to continue etching until the N-type InAlAs ohmic contact layer (2) is reached, thereby preparing a second-level step structure (16); Step 5, using a photolithography process to photoetch a third-level step pattern on the front side of the epitaxial substrate; using a wet etching process, etching into the epitaxial substrate and stopping to form a third-level step structure; the depth of etching into the epitaxial substrate should be greater than 0.3 μm to form good electrical isolation; wherein, Phosphoric acid etching solution is used to etch the N-type InAlAs ohmic contact layer (2), and bromine water etching solution is used to etch the InP epitaxial substrate; Step 6: Using plasma enhanced chemical vapor deposition process, grow 100nm SiO2 and 210nm thick SiN with a refractive index of 1.85 on the epitaxial structure. x Thin film, passivation layer (14), SiN x At the same time, the antireflection film used as the incident window (13) has a growth temperature between 200°C and 300°C; Step 7, using photolithography to pattern the N electrode window 18 and the P electrode window on the epitaxial structure; using wet etching to etch away the SiO2 and SiN at the electrode window. x , forming N-electrode and P-electrode windows; Step 8, using a photolithography process to re-photolithograph the N electrode window; sputtering Au / Ge / Ni / Au with glue, and then peeling off the N electrode (12); Step 9, using a photolithography process to photolithographically form N-electrode lead and P-electrode lead windows on the epitaxial structure; sputtering Ti / Au with glue, and then peeling off the N-electrode lead (19) and the P-electrode lead (20); Step 10, using a rapid annealing alloy process at a temperature of 390° C. for 40 seconds to form a good ohmic contact between the semiconductor device and the metal; Step 11, thinning and polishing the back side of the epitaxial structure; Step 12, cleaving the epitaxial wafer and dividing it into independent devices.

7. The method for preparing a high-speed, low-dark-current three-step-structure avalanche photodetector according to claim 5, characterized in that: The etching solution used in step 3 and step 4 is phosphoric acid etching solution; the etching solution selected in step 7 is BOE etching solution.

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