Butt-joint epitaxial growth ridge waveguide laser chip and manufacturing method thereof

Abstract

The invention discloses a butt-joint epitaxial growth ridge waveguide laser chip and a manufacturing method thereof, and belongs to the technical field of lasers, and the manufacturing method comprises the following steps: manufacturing a ridge waveguide structure on an epitaxial wafer subjected to butt-joint growth, coating a layer of photoresist adhesive and two layers of photoresist on the ridge waveguide structure, forming a window at a convex ridge of the overlay ridge waveguide structure, and forming the butt-joint epitaxial growth ridge waveguide laser chip. The window covers an area above the passive area and a part of the active area, exposing and developing the epitaxial wafer in the window, removing a part of photoresist, etching and removing the residual photoresist in the window to expose the ohmic contact layer, corroding and removing the ohmic contact layer in the window, and removing all the photoresist on the surface of the epitaxial wafer. The length of the ohmic contact layer is controlled through double-layer adhesive photoetching and wet etching, and the ohmic contact layer above the active region is further etched, so that diffusion of current to the passive waveguide direction is effectively inhibited, the threshold current of the chip is reduced, the heating value of the passive waveguide region is reduced, and the reliability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of laser technology, and in particular to a butt-jointed epitaxially grown ridge waveguide laser chip and a manufacturing method thereof. Background Art

[0002] As a common method for epitaxial growth of semiconductor lasers, butt-joint growth is essentially an etching and re-growth process. The materials in different regions are completed through their own relatively independent growth processes, so it is very convenient to optimize the materials and structures of each functional area. At present, many relatively mature butt-joint epitaxial growth processes have different growth methods, materials, thickness and other parameters, but their overall structure is still similar. A layer of heavily doped InGaAs / InGaAsP will grow on the surface of the epitaxial wafer as an ohmic contact layer. Due to the high doping concentration of the ohmic contact layer, it contains more carriers, so the conductivity is better than that of undoped InP and InGaAs intrinsic semiconductor materials. When the chip is powered on, the current enters the active area through the metal electrode, ohmic contact layer, and InP cladding in turn, so that carriers are produced and recombinated in the active area, generating photons. Compared with the InP cladding, the ohmic contact layer has a higher carrier concentration and a smaller resistance, so after the current is injected, it will be preferentially conducted laterally in the ohmic contact layer and then injected into the InP below.

[0003] The epitaxial wafers produced by docking are divided into an active waveguide area containing a quantum well structure and a passive waveguide area without a quantum well structure, referred to as the active area and the passive area. The active area can realize the recombination of electrons and holes and generate photons, while the carriers in the passive area hardly generate photons, but release energy in the form of heat energy, which will reduce the electro-optical conversion efficiency of the chip and cause the chip to generate more heat. For this reason, in the process of making chips, it is necessary to avoid injecting current into the passive area as much as possible, but to limit it to the active area to generate photons. Therefore, when making laser chips in the industry, the ohmic contact layer above the passive area is removed.

[0004] However, it is difficult to accurately control the corrosion length of the isolation area using traditional manufacturing methods. If the corrosion length is too deep, it will affect the current injection efficiency. If the corrosion length is too short, the current will still be injected into the passive area, making it difficult to ensure the production quality of the chip. The present invention proposes a new solution to the above problems. Summary of the invention

[0005] In order to overcome at least one of the above disadvantages, the present invention provides a butt-jointed epitaxially grown ridge waveguide laser chip and a method for manufacturing the same. The purpose of the present invention can be achieved by adopting the following technical solutions:

[0006] A first aspect of the present invention provides a method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip, comprising:

[0007] A ridge waveguide structure is fabricated on the butt-grown epitaxial wafer, and a layer of photoresist adhesive and two layers of photoresist are coated on the surface of the ridge waveguide structure;

[0008] A window is opened at the ridge of the ridge waveguide structure by using an overlay method, the window covers the passive area and the upper area of ​​part of the active area, the epitaxial wafer in the window is exposed and developed, and the upper photoresist and part of the lower photoresist are removed;

[0009] The remaining photoresist in the window is removed by gas etching to expose the ohmic contact layer, and the ohmic contact layer in the window is removed by etching with an etching liquid to remove all the photoresist on the surface of the epitaxial wafer.

[0010] In one embodiment, the manufacturing method comprises:

[0011] Fabricating a ridge waveguide structure on the butted-grown epitaxial wafer to form a first wafer;

[0012] A layer of photoresist adhesive is coated on the surface of the first wafer and then baked to form a second wafer;

[0013] Coating a first layer of photoresist on the surface of the second wafer and then baking to form a third wafer;

[0014] Coating a second layer of photoresist on the surface of the third wafer and then baking to form a fourth wafer;

[0015] The fourth wafer is subjected to overlay processing, and then exposed, developed, and baked for finalization, and the photoresist of a preset thickness in the window is removed by a developer to form a fifth wafer;

[0016] Performing a gas etching process on the fifth wafer to remove the remaining photoresist in the window by etching, thereby forming a sixth wafer;

[0017] The sixth wafer is placed in a sulfuric acid solution for etching to remove the ohmic contact layer in the window, and the etching solution on the surface of the wafer is cleaned to form a seventh wafer;

[0018] The photoresist on the surface of the seventh wafer is removed, and a passivation layer is grown, a metal electrode is made, and a thinning process is performed to form a chip.

[0019] In one possible implementation, the first wafer includes an InP substrate and an epitaxial wafer formed on the InP substrate, a ridge waveguide structure is formed on an upper surface of the epitaxial wafer, and an ohmic contact layer is provided on a surface of the ridge waveguide structure;

[0020] A passive region, an active region, and a passive region that are butted against each other are sequentially formed along the length direction of the ridge waveguide structure. The active region and the passive region are both located within the edge projection region of the plane where the ridge waveguide structure is located.

[0021] In one possible implementation, the fourth wafer is overlaid to open the window at the ridge, the passive area is located within the edge projection area of ​​the plane where the window is located, a portion of the active area is located within the edge projection area of ​​the plane where the window is located, and the boundary line between the passive area and the active area is located within the edge projection area of ​​the plane where the window is located.

[0022] In one possible implementation, the window is formed by overlaying the fourth wafer using a photomask of a preset size.

[0023] In one possible implementation, the fifth wafer is placed in a plasma gas etching machine, and oxygen plasma etching is performed for a period of time to remove the photoresist of a preset thickness in the window. The preset thickness is greater than the thickness of the second layer of photoresist and less than the sum of the thickness of the first layer of photoresist and the thickness of the second layer of photoresist.

[0024] In one possible implementation, the sixth wafer is placed in a sulfuric acid solution and etched for a preset time to remove the ohmic contact layer in the window.

[0025] In one embodiment, the sulfuric acid solution includes sulfuric acid solution, hydrogen peroxide solution and water.

[0026] In one possible implementation manner, the etching length of the ohmic contact layer above the active area is proportional to the maximum operating current of the chip.

[0027] According to a second aspect of the present invention, there is provided a butt-jointed epitaxially grown ridge waveguide laser chip, comprising an InP substrate and an epitaxial wafer formed on the InP substrate, wherein a ridge waveguide structure is provided on the upper surface of the InP substrate, and a butt-jointed passive region-active region-passive region is sequentially formed on the InP substrate along the length direction of the ridge waveguide structure, wherein the active region and the passive region are both located within the edge projection region of the plane where the ridge waveguide structure is located, and wherein two windows are relatively arranged at the ridge of the ridge waveguide structure, wherein the passive region and a part of the active region are located within the edge projection region of the plane where the windows are located, and wherein the InP substrate outside the window region is sequentially provided with an ohmic contact layer, a photoresist adhesion layer, a first photoresist layer, and a second photoresist layer from bottom to top.

[0028] Beneficial technical effects of the present invention: According to the content of the present disclosure, the method for manufacturing the butt-jointed epitaxially grown ridge waveguide laser controls the length of the ohmic contact layer through double-layer photolithography and wet etching, and further etches the ohmic contact layer above the active area, effectively inhibiting the diffusion of current in the passive waveguide direction, reducing the generation and recombination of carriers in the passive waveguide area, and improving the current utilization efficiency. The current can enter the quantum well more to generate photons, reducing the threshold current of the chip, and designing the etching length according to the maximum current when the chip is actually used, reducing the free carrier absorption loss in the passive waveguide area, reducing the threshold current of the laser, reducing the heat generation in the passive waveguide area, and improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In the accompanying drawings, the following are given by way of example and not limitation:

[0030] Figure 1 A three-dimensional structural cross-sectional view of a single chip on a first wafer is shown;

[0031] Figure 2 showing a front view of a second wafer;

[0032] Figure 3 shows a front view of a third wafer coated with a layer of photoresist;

[0033] Figure 4 shows a front view of a fourth wafer coated with two layers of photoresist;

[0034] Figure 5 shows a front view of a fifth wafer;

[0035] Figure 6 shows a top view of a fifth wafer;

[0036] Figure 7 shows a three-dimensional structural cross-sectional view of a fifth wafer;

[0037] Figure 8 shows a front view of a sixth wafer;

[0038] Fig. 9 shows a three-dimensional structural cross-sectional view of the seventh wafer;

[0039] Fig.10 A side view of a common docking structure is shown.

[0040] In the figure:

[0041] 1. InP substrate; 2. Ridge waveguide structure; 3. Ohmic contact layer; 4. Passive region; 5. Active region; 6. Photoresist adhesion layer; 7. First photoresist layer; 8. Second photoresist layer; 9. Window;

[0042] 11. Docking to produce InP cladding; 12. Normal growth of InP cladding; 51. Normal growth of active area waveguide layer; 52. Quantum well region. DETAILED DESCRIPTION

[0043] In the following detailed disclosure, these embodiments are fully described with reference to the accompanying drawings. In order to make the technical scheme of the present invention more clear and specific to those skilled in the art, the implementation methods described below are not limited to this. The present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings.

[0044] In the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise clearly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by terms such as “upper”, “lower”, “left”, “right”, “front” and “back” are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, cannot be understood as a limitation on the present invention.

[0046] Traditional butt-jointed epitaxial structures such as Fig.10 As shown, an active region 5 and a passive region 4 are formed on an InP substrate 1, wherein the active region 5 includes a quantum well region 52 and a normally grown active region waveguide layer 51 wrapped around the outside of the quantum well region 52, a normally grown InP cladding 12 is arranged above the active region 5, a butt-grown InP cladding 11 is arranged above the passive region 4, and a heavily doped InGaAs / InGaAsP ohmic contact layer 3 is arranged above the normally grown InP cladding 12 and the butt-grown InP cladding 11. The butt-grown epitaxial wafer includes an active region 5 containing a quantum well structure and a passive region 4 without a quantum well structure. In order to avoid injecting current into the passive region 4 as much as possible, the ohmic contact layer 3 above the passive region 4 is removed when manufacturing a laser chip, i.e., the isolation region is removed. However, the etching length is difficult to control, and it is difficult to ensure the production quality of the chip.

[0047] The first aspect of the present invention, as Figure 1-Figure 9As shown, a method for manufacturing a butt-epitaxially grown ridge waveguide laser chip is provided, comprising manufacturing a ridge waveguide structure 2 on a butt-grown epitaxial wafer, coating a layer of photoresist adhesive and two layers of photoresist on the surface of the ridge waveguide structure 2; using an overlay method to open a window 9 at the ridge of the ridge waveguide structure 2, the window 9 covers the passive area 4 and the upper area of ​​a part of the active area 5, exposing and developing the epitaxial wafer in the window 9, and removing the upper photoresist and part of the lower photoresist; using a gas etching method to remove the remaining photoresist in the window 9 to expose the ohmic contact layer 3, using an etching solution to remove the ohmic contact layer 3 in the window 9, and removing all the photoresist on the surface of the epitaxial wafer.

[0048] The method for manufacturing a docked epitaxially grown ridge waveguide laser provided in this embodiment controls the length of the ohmic contact layer 3 through double-layer photolithography and wet etching, ensures that the isolation area is cleanly etched, and further etches the ohmic contact layer 3 above the active area 5, effectively suppressing the diffusion of current in the passive waveguide direction, reducing the generation and recombination of carriers in the passive waveguide area, and improving the current utilization efficiency. The current can enter the quantum well more to generate photons, reducing the threshold current of the chip. The etching length is designed according to the maximum current when the chip is actually used, reducing the free carrier absorption loss in the passive waveguide area, reducing the threshold current of the laser, reducing the heat generation in the passive waveguide area, and improving the reliability of the chip.

[0049] In one possible implementation, the manufacturing method includes: making a ridge waveguide structure 2 on a butt-grown epitaxial wafer to form a first wafer; coating a layer of photoresist adhesive on the surface of the first wafer and then baking it to form a second wafer; coating the first layer of photoresist on the surface of the second wafer and then baking it to form a third wafer; coating the second layer of photoresist on the surface of the third wafer and then baking it to form a fourth wafer; performing overlay processing on the fourth wafer, exposing and developing it and then baking it to form a fifth wafer; performing a developer solution on the fifth wafer to remove the photoresist of a preset thickness in the window 9 by gas etching to form a sixth wafer; placing the sixth wafer in a sulfuric acid solution to corrode and remove the ohmic contact layer 3 in the window 9, and cleaning the etching solution on the surface of the wafer to form a seventh wafer; removing the photoresist on the surface of the seventh wafer, growing a passivation layer, making a metal electrode, and performing a thinning process to form a chip.

[0050] like Figure 1 -like Fig. 9 As shown, the method for manufacturing the butt-jointed epitaxially grown ridge waveguide laser provided in this embodiment specifically comprises the following steps:

[0051] S1, manufacturing a ridge waveguide structure 2 on a butt-grown epitaxial wafer, which is a first wafer;

[0052] S2, coating a layer of photoresist adhesive on the surface of the first wafer, and then baking and shaping it to form a second wafer;

[0053] S3, coating a first layer of photoresist on the surface of the second wafer, and then baking and finalizing the first layer to form a third wafer;

[0054] S4, coating a second layer of photoresist on the surface of the third wafer, and then baking and finalizing the layer to form a fourth wafer;

[0055] S5, using a photomask of designed size to overlay the fourth wafer, exposing it for an appropriate time, developing it with a developer, and baking it to form a fifth wafer;

[0056] S6, placing the fifth wafer into a plasma gas etching machine, using oxygen plasma etching for an appropriate time to remove a certain thickness of photoresist on the surface, forming a sixth wafer. At this time, the exposed area on the wafer has been completely exposed, and the other parts are partially covered with photoresist;

[0057] S7, placing the sixth wafer in a sulfuric acid solution for etching for 1 to 2 minutes, wherein the specific etching time is determined by the thickness of the ohmic contact layer 3 during epitaxial growth, and then cleaning the etching solution on the surface of the wafer to obtain a seventh wafer;

[0058] S8. After all the photoresist on the wafer surface is removed, normal passivation layer growth, metal electrode production, thinning and other operations are performed to complete the subsequent chip production steps.

[0059] The method for manufacturing the butt-jointed epitaxially grown ridge waveguide laser provided in this embodiment etches and removes a specific length of the ohmic contact layer 3 above the active area 5. Compared with only etching the isolation area above the passive area 4, it effectively suppresses the diffusion of current in the passive waveguide direction, reduces the generation and recombination of carriers in the passive waveguide area, and improves the current utilization efficiency.

[0060] Among them, the method for manufacturing the butt-jointed epitaxially grown ridge waveguide laser provided in this embodiment etches away a certain length of the ohmic contact layer 3 above the active area 5, and adopts a method combining coating of a double layer of photoresist, development and gas etching to obtain a photolithography pattern. The accuracy of the developed pattern is controlled by coating a double layer of resist and using a photoresist of a designed size, thereby ensuring the accuracy of the etching length of the isolation area.

[0061] It is understandable that similar methods, such as two layers of positive photoresist with different brands and types, different exposure times, different development times, and different gas compositions, concentrations and times used in dry etching, all fall within the scope of protection of this patent.

[0062] In one possible implementation, Figure 1As shown, the first wafer includes an InP substrate 1 and an epitaxial wafer formed on the InP substrate 1, a ridge waveguide structure 2 is formed on the upper surface of the epitaxial wafer, and an ohmic contact layer 3 is provided on the surface of the ridge waveguide structure 2; along the length direction of the ridge waveguide structure 2, a butt-jointed passive region 4-active region 5-passive region 4 are sequentially formed, and the active region 5 and the passive region 4 are both located in the edge projection area of ​​the plane where the ridge waveguide structure 2 is located.

[0063] Among them, the InP substrate 1, as the basis of the semiconductor laser chip, has good optical and electrical properties. The epitaxial wafer is a material layer grown on the InP substrate 1, which is usually formed by epitaxial growth technology. The epitaxial wafer can contain different doping concentrations and layer structures to meet the performance requirements of the laser chip.

[0064] Among them, the ridge waveguide structure 2 is formed on the upper surface of the epitaxial wafer. The ridge waveguide structure 2 has low main mode cutoff frequency, wide bandwidth and low impedance characteristics, and is suitable for making high-performance laser chips; the ohmic contact layer 3 is arranged on the surface of the ridge waveguide structure 2 to achieve good electrical contact. The ohmic contact layer 3 is usually selected from materials with low resistivity and high stability to ensure the effective transmission of electrical signals.

[0065] Among them, the three regions formed in sequence along the length direction of the ridge waveguide structure 2 are the passive region 4-active region 5-passive region 4. The active region 5 is the region where photons are generated in the laser chip, and the passive region 4 is used to realize functions such as transmission and coupling of photons. Both the passive region 4 and the active region 5 are located in the edge projection region of the plane where the ridge waveguide structure 2 is located, so as to utilize the guiding effect of the ridge waveguide on the light wave to enhance the interaction between the light and the active region 5, which helps to ensure the effective confinement and transmission of photons and can improve the performance and stability of the laser chip.

[0066] In one possible implementation, Figure 4 and Figure 5 As shown, the fourth wafer is overlaid to form a window 9 at the ridge, the passive area 4 is located in the edge projection area of ​​the plane where the window 9 is located, a portion of the active area 5 is located in the edge projection area of ​​the plane where the window 9 is located, and the boundary line between the passive area 4 and the active area 5 is located in the edge projection area of ​​the plane where the window 9 is located.

[0067] Among them, a window 9 is opened at the ridge by overetching so that the subsequent process can accurately align the position of window 9. Window 9 covers the entire area above the passive area 4, that is, window 9 covers the isolation area. Window 9 also covers a part of the area above the active area 5. Part of the photoresist can be removed by overetching the window 9 area.

[0068] The window 9 is formed by overlaying the fourth wafer with a photomask of a preset size.

[0069] It is understandable that the photoresist is a mask, and the design pattern on the photoresist is accurately transferred to the photoresist on the surface of the wafer, and then a specific window 9 structure is formed on the wafer through subsequent processing steps. The photoresist and the wafer are precisely aligned. After the alignment is completed, a photolithography machine is used for exposure. The light passes through the pattern on the photoresist and irradiates the photoresist on the surface of the wafer. After exposure, a development process is required to remove the unexposed part of the photoresist, leaving a pattern corresponding to the photoresist pattern for baking and finalization, which can ensure the accuracy of the corrosion length of the isolation area.

[0070] In one possible implementation, Figure 5-Figure 7 As shown, the fifth wafer is placed in a plasma gas etching machine, and oxygen plasma etching is performed for a period of time to remove the photoresist of a preset thickness in the window 9. The preset thickness is greater than the thickness of the second photoresist layer and less than the sum of the thickness of the first photoresist layer and the second photoresist layer.

[0071] Among them, the photoresist on the wafer includes multiple layers. The second layer of photoresist and a part of the first layer of photoresist are removed first. When etching is performed using a plasma gas etching machine, oxygen plasma will chemically react with the photoresist and gradually remove it.

[0072] The etching depth, that is, the thickness of the removed photoresist, can be precisely adjusted by controlling parameters such as etching time, flow rate and pressure of the plasma gas.

[0073] In one possible implementation, Figure 8 and Fig. 9 As shown, the sixth wafer is placed in a sulfuric acid solution for etching for a preset time to remove the ohmic contact layer 3 in the window 9 through etching.

[0074] The ohmic contact layer 3 is a thin layer used to form a good electrical contact with the metal electrode, and has a low contact resistance and good thermal stability. However, in order to avoid injecting current into the passive area 4 as much as possible, the ohmic contact layer 3 above the passive area 4 and the ohmic contact layer 3 above the end of the active area 5 are removed.

[0075] Among them, by placing the six wafers in a sulfuric acid solution, the sulfuric acid solution can chemically react with the ohmic contact layer 3, gradually corroding and removing it, and the corrosion speed and depth can be precisely adjusted by controlling parameters such as the concentration, temperature and corrosion time of the etching solution.

[0076] Among them, sulfuric acid solution usually refers to a solution system containing sulfuric acid as the main component, but is not necessarily limited to only sulfuric acid. It can also include a solution of hydrogen peroxide and water. The sulfuric acid solution can contain a variety of other components. The selection of these components depends on specific application requirements, such as corrosion, cleaning, etching and other process steps.

[0077] Among them, sulfuric acid is the main component of sulfuric acid solution. It has multiple chemical properties such as strong corrosiveness and strong oxidizing properties. It can be used to remove pollutants on the surface of materials and corrode specific material layers. Adding hydrogen peroxide can enhance its oxidizing or cleaning ability. Hydrogen peroxide can show stronger oxidizing properties under acidic conditions, which helps to remove organic pollutants or perform more efficient cleaning. Water, as a solvent in sulfuric acid solution, is used to dilute sulfuric acid and other additives for use under specific process conditions. The water content can affect the concentration and activity of the solution.

[0078] It is understandable that, depending on application requirements, the sulfuric acid solution may also contain other additives, such as corrosion inhibitors, surfactants, stabilizers, etc., to improve the performance of the solution or protect the treated material.

[0079] In one possible implementation, the etching length of the ohmic contact layer 3 above the active region 5 is proportional to the maximum operating current of the chip.

[0080] Among them, the ohmic contact layer 3 provides a low-resistance contact between the metal and the semiconductor in the semiconductor laser, thereby allowing current to be effectively injected into the active area 5. The corrosion length usually refers to the partial length of the ohmic contact layer 3 removed in a specific process step. The corrosion length of the ohmic contact layer 3 affects the contact resistance and current injection efficiency. The corrosion length of the ohmic contact layer 3 above the active area 5 is proportional to the maximum operating current of the chip.

[0081] Among them, the longer the corrosion length of the ohmic contact layer 3 above the active area 5, the less the current diffuses toward the passive waveguide direction, the less carriers are generated and recombined in the passive waveguide region, and the current can enter the quantum well to generate photons more, thereby reducing the threshold current of the chip and increasing the maximum operating current of the chip; the shorter the corrosion length of the ohmic contact layer 3 above the active area 5, the more the current diffuses toward the passive waveguide direction, the more carriers are generated and recombined in the passive waveguide region, and the current can enter the quantum well to generate photons less, thereby increasing the threshold current of the chip and reducing the maximum operating current of the chip.

[0082] It is understandable that the etching length of the ohmic contact layer 3 above the active area 5 can be designed according to the maximum operating current required by the chip to meet the needs of different operating currents.

[0083] In specific implementation, for example, for a chip with a maximum operating current of 80 mA, the etching length of the ohmic contact layer 3 above the active area 5 is about 2 to 3 um. If the maximum operating current is 240 mA, the etching length of the ohmic contact layer 3 above the active area 5 is 7 to 9 um.

[0084] According to a second aspect of the present invention, a butt-jointed epitaxially grown ridge waveguide laser chip is provided, comprising an InP substrate 1 and an epitaxial wafer formed on the InP substrate 1, a ridge waveguide structure 2 is provided on the upper surface of the InP substrate 1, and a butt-jointed passive region 4-active region 5-passive region 4 are sequentially formed on the InP substrate 1 along the length direction of the ridge waveguide structure 2, the active region 5 and the passive region 4 are both located within the edge projection region of the plane where the ridge waveguide structure 2 is located, two windows 9 are relatively arranged at the ridge of the ridge waveguide structure 2, the passive region 4 and a part of the active region 5 are located within the edge projection region of the plane where the windows 9 are located, and the InP substrate 1 outside the window 9 region is sequentially provided with an ohmic contact layer 3, a photoresist adhesion layer 6, a first photoresist layer 7 and a second photoresist layer 8 from bottom to top.

[0085] The ridge waveguide laser chip is based on the InP substrate 1, on which an epitaxial wafer is formed, which constitutes the main part of the laser chip. The upper surface of the InP substrate 1 is provided with a ridge waveguide structure 2, which is helpful for light conduction and mode control. The InP substrate 1 is divided into a structure of passive area 4-active area 5-passive area 4. The active area 5 is the main area for laser generation, while the passive area 4 plays an auxiliary and isolation role.

[0086] Among them, in the layers from bottom to top of the InP substrate 1, an ohmic contact layer 3, a photoresist adhesion layer 6, a first photoresist layer 7, and a second photoresist layer 8 are sequentially arranged. By removing the ohmic contact layer 3, the photoresist adhesion layer 6, the first photoresist layer 7, and the second photoresist layer 8 in the window 9, the ohmic contact layer 3, the photoresist adhesion layer 6, the first photoresist layer 7, and the second photoresist layer 8 in the passive region 4 and the upper region of the end of the active region 5 are all removed, which optimizes current injection and reduces energy loss, ensures that more current can be effectively injected into the active region 5, and reduces diffusion to the passive region 4. By removing these layers, the current can flow more concentratedly to the active region 5 when injected, thereby improving the efficiency of generating photons in the quantum well, reducing the free carrier absorption loss in the passive waveguide region, reducing the threshold current of the laser, reducing the heat generation in the passive waveguide region, and improving the reliability of the chip.

[0087] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0088] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0089] In view of the above detailed description, these and other changes can be made to these embodiments, and this written description includes the best mode embodiments to disclose the present invention. The scope of the patent obtained by the present invention is defined by the claims, which are not limited by the present disclosure, and the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field within the scope disclosed by the present invention, according to the technical solution and its conception of the present invention, is equivalent to or changes, and all are within the protection scope of the present invention.

Claims

1. A method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip, characterized in that: include: A ridge waveguide structure is fabricated on the butt-grown epitaxial wafer, and a layer of photoresist adhesive and two layers of photoresist are coated on the surface of the ridge waveguide structure; A window is opened at the ridge of the ridge waveguide structure by using an overlay method, the window covers the passive area and the upper area of ​​part of the active area, the epitaxial wafer in the window is exposed and developed, and the upper photoresist and part of the lower photoresist are removed; The remaining photoresist in the window is removed by gas etching to expose the ohmic contact layer, and the ohmic contact layer in the window is removed by etching with an etching liquid to remove all the photoresist on the surface of the epitaxial wafer.

2. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 1, characterized in that: include: Fabricating a ridge waveguide structure on the butted-grown epitaxial wafer to form a first wafer; A layer of photoresist adhesive is coated on the surface of the first wafer and then baked to form a second wafer; Coating a first layer of photoresist on the surface of the second wafer and then baking to form a third wafer; Coating a second layer of photoresist on the surface of the third wafer and then baking to form a fourth wafer; The fourth wafer is subjected to overlay processing, and then exposed, developed, and baked for finalization, and the photoresist of a preset thickness in the window is removed by a developer to form a fifth wafer; Performing a gas etching process on the fifth wafer to remove the remaining photoresist in the window by etching, thereby forming a sixth wafer; The sixth wafer is placed in a sulfuric acid solution for etching to remove the ohmic contact layer in the window, and the etching solution on the surface of the wafer is cleaned to form a seventh wafer; The photoresist on the surface of the seventh wafer is removed, and a passivation layer is grown, a metal electrode is made, and a thinning process is performed to form a chip.

3. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 2, characterized in that: The first wafer includes an InP substrate and an epitaxial wafer formed on the InP substrate, a ridge waveguide structure is formed on the upper surface of the epitaxial wafer, and an ohmic contact layer is provided on the surface of the ridge waveguide structure; A passive region, an active region, and a passive region that are butted against each other are sequentially formed along the length direction of the ridge waveguide structure. The active region and the passive region are both located within the edge projection region of the plane where the ridge waveguide structure is located.

4. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 3, characterized in that: The fourth wafer is overlaid to open the window at the ridge, the passive area is located in the edge projection area of ​​the plane where the window is located, a part of the active area is located in the edge projection area of ​​the plane where the window is located, and the boundary line between the passive area and the active area is located in the edge projection area of ​​the plane where the window is located.

5. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 2, characterized in that: The window is formed by overlaying the fourth wafer using a photomask of a preset size.

6. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 2, characterized in that: The fifth wafer is placed in a plasma gas etching machine, and the photoresist of a preset thickness in the window is removed by oxygen plasma etching for a period of time. The preset thickness is greater than the thickness of the second photoresist layer and less than the sum of the thickness of the first photoresist layer and the second photoresist layer.

7. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 2, characterized in that: The sixth wafer is placed in a sulfuric acid solution for etching for a preset time to remove the ohmic contact layer in the window.

8. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 7, characterized in that: The sulfuric acid solution includes sulfuric acid solution, hydrogen peroxide solution and water.

9. The method for manufacturing a butt-jointed epitaxially grown ridge waveguide laser chip according to claim 1 or 2, characterized in that: The etching length of the ohmic contact layer above the active area is proportional to the maximum operating current of the chip.

10. A butt-jointed epitaxially grown ridge waveguide laser chip, characterized in that: The invention comprises an InP substrate and an epitaxial wafer formed on the InP substrate, wherein a ridge waveguide structure is arranged on the upper surface of the InP substrate, and a butted passive region-active region-passive region are sequentially formed on the InP substrate along the length direction of the ridge waveguide structure, wherein the active region and the passive region are both located within the edge projection region of the plane where the ridge waveguide structure is located, and two windows are relatively arranged at the ridge of the ridge waveguide structure, wherein the passive region and a part of the active region are located within the edge projection region of the plane where the windows are located, and wherein the InP substrate outside the window region is sequentially provided with an ohmic contact layer, a photoresist adhesion layer, a first photoresist layer, and a second photoresist layer from bottom to top.

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